[agd5f:drm-next 113/305] checkpatch: WARNING: adding a line without newline at end of file

[agd5f:drm-next 113/305] checkpatch: WARNING: adding a line without newline at end of file

[kernel test robot]

:::::: 
:::::: Manual check reason: "checkpatch"
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
TO: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
CC: Alex Deucher <alexander.deucher@amd.com>
INFO skip CC for checkpatch warnings

tree:   https://gitlab.freedesktop.org/agd5f/linux.git drm-next
head:   86f2ec2265358fb1d7b76c7ffb86af6e04118388
commit: ea629e5cf252dc07656e49cb4ebe240b40475795 [113/305] drm/amd/display: Add dcn35 register header files
:::::: branch date: 13 hours ago
:::::: commit date: 13 days ago
reproduce: (https://download.01.org/0day-ci/archive/20230912/202309121858.ExL1UMYo-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202309121858.ExL1UMYo-lkp@intel.com/

# many are suggestions rather than must-fix

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#20: 
new file mode 100644

WARNING: line length of 112 exceeds 100 columns
#53: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:29:
+#define regGLOBAL_CAPABILITIES                                                                          0x4b7000

WARNING: line length of 105 exceeds 100 columns
#54: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:30:
+#define regGLOBAL_CAPABILITIES_BASE_IDX                                                                 3

WARNING: line length of 112 exceeds 100 columns
#55: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:31:
+#define regMINOR_VERSION                                                                                0x4b7000

WARNING: line length of 105 exceeds 100 columns
#56: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:32:
+#define regMINOR_VERSION_BASE_IDX                                                                       3

WARNING: line length of 112 exceeds 100 columns
#57: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:33:
+#define regMAJOR_VERSION                                                                                0x4b7000

WARNING: line length of 105 exceeds 100 columns
#58: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:34:
+#define regMAJOR_VERSION_BASE_IDX                                                                       3

WARNING: line length of 112 exceeds 100 columns
#59: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:35:
+#define regOUTPUT_PAYLOAD_CAPABILITY                                                                    0x4b7001

WARNING: line length of 105 exceeds 100 columns
#60: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:36:
+#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                           3

WARNING: line length of 112 exceeds 100 columns
#61: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:37:
+#define regINPUT_PAYLOAD_CAPABILITY                                                                     0x4b7001

WARNING: line length of 105 exceeds 100 columns
#62: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:38:
+#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                            3

WARNING: line length of 112 exceeds 100 columns
#63: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:39:
+#define regGLOBAL_CONTROL                                                                               0x4b7002

WARNING: line length of 105 exceeds 100 columns
#64: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:40:
+#define regGLOBAL_CONTROL_BASE_IDX                                                                      3

WARNING: line length of 112 exceeds 100 columns
#65: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:41:
+#define regWAKE_ENABLE                                                                                  0x4b7003

WARNING: line length of 105 exceeds 100 columns
#66: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:42:
+#define regWAKE_ENABLE_BASE_IDX                                                                         3

WARNING: line length of 112 exceeds 100 columns
#67: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:43:
+#define regSTATE_CHANGE_STATUS                                                                          0x4b7003

WARNING: line length of 105 exceeds 100 columns
#68: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:44:
+#define regSTATE_CHANGE_STATUS_BASE_IDX                                                                 3

WARNING: line length of 112 exceeds 100 columns
#69: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:45:
+#define regGLOBAL_STATUS                                                                                0x4b7004

WARNING: line length of 105 exceeds 100 columns
#70: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:46:
+#define regGLOBAL_STATUS_BASE_IDX                                                                       3

WARNING: line length of 112 exceeds 100 columns
#71: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:47:
+#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY                                                             0x4b7006

WARNING: line length of 105 exceeds 100 columns
#72: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:48:
+#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                    3

WARNING: line length of 112 exceeds 100 columns
#73: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:49:
+#define regINPUT_STREAM_PAYLOAD_CAPABILITY                                                              0x4b7006

WARNING: line length of 105 exceeds 100 columns
#74: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:50:
+#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                     3

WARNING: line length of 112 exceeds 100 columns
#75: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:51:
+#define regINTERRUPT_CONTROL                                                                            0x4b7008

WARNING: line length of 105 exceeds 100 columns
#76: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:52:
+#define regINTERRUPT_CONTROL_BASE_IDX                                                                   3

WARNING: line length of 112 exceeds 100 columns
#77: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:53:
+#define regINTERRUPT_STATUS                                                                             0x4b7009

WARNING: line length of 105 exceeds 100 columns
#78: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:54:
+#define regINTERRUPT_STATUS_BASE_IDX                                                                    3

WARNING: line length of 112 exceeds 100 columns
#79: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:55:
+#define regWALL_CLOCK_COUNTER                                                                           0x4b700c

WARNING: line length of 105 exceeds 100 columns
#80: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:56:
+#define regWALL_CLOCK_COUNTER_BASE_IDX                                                                  3

WARNING: line length of 112 exceeds 100 columns
#81: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:57:
+#define regSTREAM_SYNCHRONIZATION                                                                       0x4b700e

WARNING: line length of 105 exceeds 100 columns
#82: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:58:
+#define regSTREAM_SYNCHRONIZATION_BASE_IDX                                                              3

WARNING: line length of 112 exceeds 100 columns
#83: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:59:
+#define regCORB_LOWER_BASE_ADDRESS                                                                      0x4b7010

WARNING: line length of 105 exceeds 100 columns
#84: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:60:
+#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX                                                             3

WARNING: line length of 112 exceeds 100 columns
#85: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:61:
+#define regCORB_UPPER_BASE_ADDRESS                                                                      0x4b7011

WARNING: line length of 105 exceeds 100 columns
#86: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:62:
+#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX                                                             3

WARNING: line length of 112 exceeds 100 columns
#87: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:63:
+#define regAZCONTROLLER0_CORB_WRITE_POINTER                                                             0x4b7012

WARNING: line length of 105 exceeds 100 columns
#88: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:64:
+#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX                                                    3

WARNING: line length of 112 exceeds 100 columns
#89: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:65:
+#define regAZCONTROLLER0_CORB_READ_POINTER                                                              0x4b7012

WARNING: line length of 105 exceeds 100 columns
#90: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:66:
+#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX                                                     3

WARNING: line length of 112 exceeds 100 columns
#91: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:67:
+#define regAZCONTROLLER0_CORB_CONTROL                                                                   0x4b7013

WARNING: line length of 105 exceeds 100 columns
#92: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:68:
+#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX                                                          3

WARNING: line length of 112 exceeds 100 columns
#93: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:69:
+#define regAZCONTROLLER0_CORB_STATUS                                                                    0x4b7013

WARNING: line length of 105 exceeds 100 columns
#94: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:70:
+#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX                                                           3

WARNING: line length of 112 exceeds 100 columns
#95: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:71:
+#define regAZCONTROLLER0_CORB_SIZE                                                                      0x4b7013

WARNING: line length of 105 exceeds 100 columns
#96: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:72:
+#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX                                                             3

WARNING: line length of 112 exceeds 100 columns
#97: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:73:
+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS                                                        0x4b7014

WARNING: line length of 105 exceeds 100 columns
#98: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:74:
+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               3

WARNING: line length of 112 exceeds 100 columns
#99: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:75:
+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS                                                        0x4b7015

WARNING: line length of 105 exceeds 100 columns
#100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:76:
+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               3

WARNING: line length of 112 exceeds 100 columns
#101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:77:
+#define regAZCONTROLLER0_RIRB_WRITE_POINTER                                                             0x4b7016

WARNING: line length of 105 exceeds 100 columns
#102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:78:
+#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX                                                    3

WARNING: line length of 112 exceeds 100 columns
#103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:79:
+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT                                                       0x4b7016

WARNING: line length of 105 exceeds 100 columns
#104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:80:
+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              3

WARNING: line length of 112 exceeds 100 columns
#105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:81:
+#define regAZCONTROLLER0_RIRB_CONTROL                                                                   0x4b7017

WARNING: line length of 105 exceeds 100 columns
#106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:82:
+#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX                                                          3

WARNING: line length of 112 exceeds 100 columns
#107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:83:
+#define regAZCONTROLLER0_RIRB_STATUS                                                                    0x4b7017

WARNING: line length of 105 exceeds 100 columns
#108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:84:
+#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX                                                           3

WARNING: line length of 112 exceeds 100 columns
#109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:85:
+#define regAZCONTROLLER0_RIRB_SIZE                                                                      0x4b7017

WARNING: line length of 105 exceeds 100 columns
#110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:86:
+#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX                                                             3

WARNING: line length of 112 exceeds 100 columns
#111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:87:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x4b7018

WARNING: line length of 105 exceeds 100 columns
#112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:88:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    3

WARNING: line length of 112 exceeds 100 columns
#113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:89:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x4b7018

WARNING: line length of 105 exceeds 100 columns
#114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:90:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               3

WARNING: line length of 112 exceeds 100 columns
#115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:91:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x4b7018

WARNING: line length of 105 exceeds 100 columns
#116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:92:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              3

WARNING: line length of 112 exceeds 100 columns
#117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:93:
+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x4b7019

WARNING: line length of 105 exceeds 100 columns
#118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:94:
+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    3

WARNING: line length of 112 exceeds 100 columns
#119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:95:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS                                                       0x4b701a

WARNING: line length of 105 exceeds 100 columns
#120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:96:
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              3

WARNING: line length of 112 exceeds 100 columns
#121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:97:
+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x4b701c

WARNING: line length of 105 exceeds 100 columns
#122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:98:
+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       3

WARNING: line length of 112 exceeds 100 columns
#123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:99:
+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x4b701d

WARNING: line length of 105 exceeds 100 columns
#124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:100:
+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       3

WARNING: line length of 112 exceeds 100 columns
#125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:101:
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS                                                       0x4b780c

WARNING: line length of 105 exceeds 100 columns
#126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:102:
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              3

WARNING: line length of 109 exceeds 100 columns
#130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:106:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000

WARNING: line length of 109 exceeds 100 columns
#131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:107:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001

WARNING: line length of 109 exceeds 100 columns
#132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:108:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002

WARNING: line length of 109 exceeds 100 columns
#133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:109:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003

WARNING: line length of 109 exceeds 100 columns
#134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:110:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004

WARNING: line length of 109 exceeds 100 columns
#135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:111:
+#define ixSINK_DESCRIPTION0                                                                            0x0005

WARNING: line length of 109 exceeds 100 columns
#136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:112:
+#define ixSINK_DESCRIPTION1                                                                            0x0006

WARNING: line length of 109 exceeds 100 columns
#137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:113:
+#define ixSINK_DESCRIPTION2                                                                            0x0007

WARNING: line length of 109 exceeds 100 columns
#138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:114:
+#define ixSINK_DESCRIPTION3                                                                            0x0008

WARNING: line length of 109 exceeds 100 columns
#139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:115:
+#define ixSINK_DESCRIPTION4                                                                            0x0009

WARNING: line length of 109 exceeds 100 columns
#140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:116:
+#define ixSINK_DESCRIPTION5                                                                            0x000a

WARNING: line length of 109 exceeds 100 columns
#141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:117:
+#define ixSINK_DESCRIPTION6                                                                            0x000b

WARNING: line length of 109 exceeds 100 columns
#142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:118:
+#define ixSINK_DESCRIPTION7                                                                            0x000c

WARNING: line length of 109 exceeds 100 columns
#143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:119:
+#define ixSINK_DESCRIPTION8                                                                            0x000d

WARNING: line length of 109 exceeds 100 columns
#144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:120:
+#define ixSINK_DESCRIPTION9                                                                            0x000e

WARNING: line length of 109 exceeds 100 columns
#145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:121:
+#define ixSINK_DESCRIPTION10                                                                           0x000f

WARNING: line length of 109 exceeds 100 columns
#146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:122:
+#define ixSINK_DESCRIPTION11                                                                           0x0010

WARNING: line length of 109 exceeds 100 columns
#147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:123:
+#define ixSINK_DESCRIPTION12                                                                           0x0011

WARNING: line length of 109 exceeds 100 columns
#148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:124:
+#define ixSINK_DESCRIPTION13                                                                           0x0012

WARNING: line length of 109 exceeds 100 columns
#149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:125:
+#define ixSINK_DESCRIPTION14                                                                           0x0013

WARNING: line length of 109 exceeds 100 columns
#150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:126:
+#define ixSINK_DESCRIPTION15                                                                           0x0014

WARNING: line length of 109 exceeds 100 columns
#151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:127:
+#define ixSINK_DESCRIPTION16                                                                           0x0015

WARNING: line length of 109 exceeds 100 columns
#152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:128:
+#define ixSINK_DESCRIPTION17                                                                           0x0016

WARNING: line length of 109 exceeds 100 columns
#157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:133:
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000

WARNING: line length of 109 exceeds 100 columns
#158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:134:
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:135:
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:136:
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003

WARNING: line length of 109 exceeds 100 columns
#161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:137:
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004

WARNING: line length of 109 exceeds 100 columns
#162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:138:
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005

WARNING: line length of 109 exceeds 100 columns
#163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:139:
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006

WARNING: line length of 109 exceeds 100 columns
#164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:140:
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007

WARNING: line length of 109 exceeds 100 columns
#169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:145:
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000

WARNING: line length of 109 exceeds 100 columns
#170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:146:
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:147:
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:148:
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003

WARNING: line length of 109 exceeds 100 columns
#173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:149:
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004

WARNING: line length of 109 exceeds 100 columns
#174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:150:
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005

WARNING: line length of 109 exceeds 100 columns
#175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:151:
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006

WARNING: line length of 109 exceeds 100 columns
#176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:152:
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007

WARNING: line length of 109 exceeds 100 columns
#181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:157:
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:158:
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001

WARNING: line length of 109 exceeds 100 columns
#183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:159:
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002

WARNING: line length of 109 exceeds 100 columns
#184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:160:
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003

WARNING: line length of 109 exceeds 100 columns
#185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:161:
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004

WARNING: line length of 109 exceeds 100 columns
#186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:162:
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005

WARNING: line length of 109 exceeds 100 columns
#187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:163:
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006

WARNING: line length of 109 exceeds 100 columns
#188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:164:
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007

WARNING: line length of 109 exceeds 100 columns
#193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:169:
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:170:
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001

WARNING: line length of 109 exceeds 100 columns
#195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:171:
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002

WARNING: line length of 109 exceeds 100 columns
#196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:172:
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003

WARNING: line length of 109 exceeds 100 columns
#197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:173:
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004

WARNING: line length of 109 exceeds 100 columns
#198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:174:
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005

WARNING: line length of 109 exceeds 100 columns
#199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:175:
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006

WARNING: line length of 109 exceeds 100 columns
#200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:176:
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007

WARNING: line length of 109 exceeds 100 columns
#205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:181:
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:182:
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:183:
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:184:
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:185:
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:190:
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:191:
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:192:
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:193:
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:194:
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:199:
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:200:
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:201:
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:202:
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:203:
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:208:
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:209:
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:210:
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:211:
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:212:
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:217:
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:218:
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:219:
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:220:
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:221:
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:226:
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:227:
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:228:
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:229:
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:230:
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:235:
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:236:
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:237:
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:238:
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:239:
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:244:
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:245:
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:246:
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:247:
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:248:
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:253:
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:254:
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:255:
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:256:
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:257:
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:262:
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000

WARNING: line length of 109 exceeds 100 columns
#287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:263:
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001

WARNING: line length of 109 exceeds 100 columns
#288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:264:
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002

WARNING: line length of 109 exceeds 100 columns
#289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:265:
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003

WARNING: line length of 109 exceeds 100 columns
#290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:266:
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004

WARNING: line length of 109 exceeds 100 columns
#295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:271:
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000

WARNING: line length of 109 exceeds 100 columns
#296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:272:
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001

WARNING: line length of 109 exceeds 100 columns
#297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:273:
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002

WARNING: line length of 109 exceeds 100 columns
#298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:274:
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003

WARNING: line length of 109 exceeds 100 columns
#299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:275:
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004

WARNING: line length of 109 exceeds 100 columns
#304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:280:
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000

WARNING: line length of 109 exceeds 100 columns
#305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:281:
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001

WARNING: line length of 109 exceeds 100 columns
#306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:282:
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002

WARNING: line length of 109 exceeds 100 columns
#307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:283:
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003

WARNING: line length of 109 exceeds 100 columns
#308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:284:
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004

WARNING: line length of 109 exceeds 100 columns
#313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:289:
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000

WARNING: line length of 109 exceeds 100 columns
#314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:290:
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001

WARNING: line length of 109 exceeds 100 columns
#315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:291:
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002

WARNING: line length of 109 exceeds 100 columns
#316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:292:
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003

WARNING: line length of 109 exceeds 100 columns
#317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:293:
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004

WARNING: line length of 109 exceeds 100 columns
#322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:298:
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000

WARNING: line length of 109 exceeds 100 columns
#323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:299:
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001

WARNING: line length of 109 exceeds 100 columns
#324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:300:
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002

WARNING: line length of 109 exceeds 100 columns
#325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:301:
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003

WARNING: line length of 109 exceeds 100 columns
#326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:302:
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004

WARNING: line length of 109 exceeds 100 columns
#331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:307:
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000

WARNING: line length of 109 exceeds 100 columns
#332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:308:
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001

WARNING: line length of 109 exceeds 100 columns
#333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:309:
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002

WARNING: line length of 109 exceeds 100 columns
#334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:310:
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003

WARNING: line length of 109 exceeds 100 columns
#335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:311:
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004

WARNING: line length of 109 exceeds 100 columns
#340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:316:
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000

WARNING: line length of 109 exceeds 100 columns
#341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:317:
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001

WARNING: line length of 109 exceeds 100 columns
#342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:318:
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002

WARNING: line length of 109 exceeds 100 columns
#343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:319:
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003

WARNING: line length of 109 exceeds 100 columns
#344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:320:
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004

WARNING: line length of 109 exceeds 100 columns
#349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:325:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:326:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:327:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:328:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:329:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:330:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:331:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:332:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:333:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:334:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:335:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:336:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:337:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:338:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:339:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:340:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:341:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:342:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:343:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:344:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:345:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:346:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:347:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:348:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:349:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:350:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:351:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:352:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:353:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:354:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:355:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:356:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:357:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:358:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:359:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:360:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:361:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:362:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:363:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:364:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:365:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:366:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:367:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:368:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:369:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:370:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:371:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:372:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:373:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:374:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:375:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:376:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:377:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:378:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:379:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:380:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:381:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:382:
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:383:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:384:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:385:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:386:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:387:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:388:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:389:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:390:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:391:
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:392:
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:393:
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:394:
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:395:
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:396:
+#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:401:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:402:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:403:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:404:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:405:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:406:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:407:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:408:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:409:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:410:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:411:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:412:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:413:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:414:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:415:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:416:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:417:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:418:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:419:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:420:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:421:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:422:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:423:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:424:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:425:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:426:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:427:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:428:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:429:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:430:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:431:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:432:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:433:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:434:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:435:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:436:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:437:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:438:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:439:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:440:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:441:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:442:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:443:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:444:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:445:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:446:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:447:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:448:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:449:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:450:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:451:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:452:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:453:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:454:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:455:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:456:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:457:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:458:
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:459:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:460:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:461:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:462:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:463:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:464:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:465:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:466:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:467:
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:468:
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:469:
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:470:
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:471:
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:472:
+#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:477:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:478:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:479:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:480:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:481:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:482:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:483:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:484:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:485:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:486:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:487:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:488:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:489:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:490:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:491:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:492:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:493:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:494:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:495:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:496:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:497:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:498:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:499:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:500:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:501:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:502:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:503:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:504:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:505:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:506:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:507:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:508:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:509:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:510:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:511:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:512:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:513:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:514:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:515:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:516:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:517:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:518:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:519:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:520:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:521:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:522:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:523:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:524:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:525:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:526:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:527:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:528:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:529:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:530:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:531:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:532:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:533:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:534:
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:535:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:536:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:537:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:538:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:539:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:540:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:541:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:542:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:543:
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:544:
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:545:
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:546:
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:547:
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:548:
+#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:553:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:554:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:555:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:556:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:557:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:558:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:559:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:560:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:561:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:562:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:563:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:564:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:565:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:566:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:567:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:568:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:569:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:570:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:571:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:572:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:573:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:574:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:575:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:576:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:577:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:578:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:579:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:580:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:581:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:582:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:583:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:584:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:585:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:586:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:587:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:588:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:589:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:590:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:591:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:592:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:593:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:594:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:595:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:596:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:597:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:598:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:599:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:600:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:601:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:602:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:603:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:604:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:605:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:606:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:607:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:608:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:609:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:610:
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:611:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:612:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:613:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:614:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:615:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:616:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:617:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:618:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:619:
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:620:
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:621:
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:622:
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:623:
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:624:
+#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:629:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:630:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:631:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:632:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:633:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:634:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:635:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:636:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:637:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:638:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:639:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:640:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:641:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:642:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:643:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:644:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:645:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:646:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:647:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:648:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:649:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:650:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:651:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:652:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:653:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:654:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:655:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:656:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:657:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:658:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:659:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:660:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:661:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:662:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:663:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:664:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:665:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:666:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:667:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:668:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:669:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:670:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:671:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:672:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:673:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:674:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:675:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:676:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:677:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:678:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:679:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:680:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:681:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:682:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:683:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:684:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:685:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:686:
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:687:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:688:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:689:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:690:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:691:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:692:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:693:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:694:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:695:
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:696:
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:697:
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:698:
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:699:
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:700:
+#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:705:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:706:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:707:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:708:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:709:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:710:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:711:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:712:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:713:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:714:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:715:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:716:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:717:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:718:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:719:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:720:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:721:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:722:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:723:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:724:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:725:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:726:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:727:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:728:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:729:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:730:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:731:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:732:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:733:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:734:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:735:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:736:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:737:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:738:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:739:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:740:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:741:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:742:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:743:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:744:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:745:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:746:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:747:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:748:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:749:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:750:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:751:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:752:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:753:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:754:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:755:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:756:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:757:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:758:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:759:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:760:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:761:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:762:
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:763:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:764:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:765:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:766:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:767:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:768:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:769:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:770:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:771:
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:772:
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:773:
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:774:
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:775:
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:776:
+#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:781:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:782:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:783:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:784:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:785:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:786:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:787:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:788:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:789:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:790:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:791:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:792:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:793:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:794:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:795:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:796:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:797:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:798:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:799:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:800:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:801:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:802:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:803:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:804:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:805:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:806:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:807:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:808:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:809:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:810:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:811:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:812:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:813:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:814:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:815:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:816:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:817:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:818:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:819:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:820:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:821:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:822:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:823:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:824:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:825:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:826:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:827:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:828:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:829:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:830:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:831:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:832:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:833:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:834:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:835:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:836:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:837:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:838:
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:839:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:840:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:841:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:842:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:843:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:844:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:845:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:846:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:847:
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:848:
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:849:
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:850:
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:851:
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:852:
+#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:857:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001

WARNING: line length of 109 exceeds 100 columns
#882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:858:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002

WARNING: line length of 109 exceeds 100 columns
#883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:859:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003

WARNING: line length of 109 exceeds 100 columns
#884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:860:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004

WARNING: line length of 109 exceeds 100 columns
#885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:861:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005

WARNING: line length of 109 exceeds 100 columns
#886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:862:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006

WARNING: line length of 109 exceeds 100 columns
#887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:863:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007

WARNING: line length of 109 exceeds 100 columns
#888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:864:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008

WARNING: line length of 109 exceeds 100 columns
#889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:865:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009

WARNING: line length of 109 exceeds 100 columns
#890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:866:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c

WARNING: line length of 109 exceeds 100 columns
#891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:867:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d

WARNING: line length of 109 exceeds 100 columns
#892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:868:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e

WARNING: line length of 109 exceeds 100 columns
#893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:869:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020

WARNING: line length of 109 exceeds 100 columns
#894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:870:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021

WARNING: line length of 109 exceeds 100 columns
#895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:871:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022

WARNING: line length of 109 exceeds 100 columns
#896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:872:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023

WARNING: line length of 109 exceeds 100 columns
#897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:873:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024

WARNING: line length of 109 exceeds 100 columns
#898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:874:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025

WARNING: line length of 109 exceeds 100 columns
#899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:875:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028

WARNING: line length of 109 exceeds 100 columns
#900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:876:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029

WARNING: line length of 109 exceeds 100 columns
#901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:877:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a

WARNING: line length of 109 exceeds 100 columns
#902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:878:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b

WARNING: line length of 109 exceeds 100 columns
#903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:879:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c

WARNING: line length of 109 exceeds 100 columns
#904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:880:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d

WARNING: line length of 109 exceeds 100 columns
#905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:881:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e

WARNING: line length of 109 exceeds 100 columns
#906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:882:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f

WARNING: line length of 109 exceeds 100 columns
#907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:883:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030

WARNING: line length of 109 exceeds 100 columns
#908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:884:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031

WARNING: line length of 109 exceeds 100 columns
#909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:885:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032

WARNING: line length of 109 exceeds 100 columns
#910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:886:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033

WARNING: line length of 109 exceeds 100 columns
#911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:887:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034

WARNING: line length of 109 exceeds 100 columns
#912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:888:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035

WARNING: line length of 109 exceeds 100 columns
#913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:889:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036

WARNING: line length of 109 exceeds 100 columns
#914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:890:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037

WARNING: line length of 109 exceeds 100 columns
#915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:891:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038

WARNING: line length of 109 exceeds 100 columns
#916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:892:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a

WARNING: line length of 109 exceeds 100 columns
#917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:893:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b

WARNING: line length of 109 exceeds 100 columns
#918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:894:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c

WARNING: line length of 109 exceeds 100 columns
#919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:895:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d

WARNING: line length of 109 exceeds 100 columns
#920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:896:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e

WARNING: line length of 109 exceeds 100 columns
#921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:897:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f

WARNING: line length of 109 exceeds 100 columns
#922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:898:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040

WARNING: line length of 109 exceeds 100 columns
#923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:899:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041

WARNING: line length of 109 exceeds 100 columns
#924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:900:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042

WARNING: line length of 109 exceeds 100 columns
#925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:901:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054

WARNING: line length of 109 exceeds 100 columns
#926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:902:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055

WARNING: line length of 109 exceeds 100 columns
#927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:903:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056

WARNING: line length of 109 exceeds 100 columns
#928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:904:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057

WARNING: line length of 109 exceeds 100 columns
#929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:905:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058

WARNING: line length of 109 exceeds 100 columns
#930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:906:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059

WARNING: line length of 109 exceeds 100 columns
#931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:907:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a

WARNING: line length of 109 exceeds 100 columns
#932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:908:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b

WARNING: line length of 109 exceeds 100 columns
#933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:909:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c

WARNING: line length of 109 exceeds 100 columns
#934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:910:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d

WARNING: line length of 109 exceeds 100 columns
#935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:911:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e

WARNING: line length of 109 exceeds 100 columns
#936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:912:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f

WARNING: line length of 109 exceeds 100 columns
#937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:913:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060

WARNING: line length of 109 exceeds 100 columns
#938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:914:
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061

WARNING: line length of 109 exceeds 100 columns
#939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:915:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062

WARNING: line length of 109 exceeds 100 columns
#940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:916:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063

WARNING: line length of 109 exceeds 100 columns
#941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:917:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064

WARNING: line length of 109 exceeds 100 columns
#942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:918:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065

WARNING: line length of 109 exceeds 100 columns
#943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:919:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066

WARNING: line length of 109 exceeds 100 columns
#944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:920:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067

WARNING: line length of 109 exceeds 100 columns
#945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:921:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068

WARNING: line length of 109 exceeds 100 columns
#946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:922:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069

WARNING: line length of 109 exceeds 100 columns
#947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:923:
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a

WARNING: line length of 109 exceeds 100 columns
#948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:924:
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b

WARNING: line length of 109 exceeds 100 columns
#949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:925:
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c

WARNING: line length of 109 exceeds 100 columns
#950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:926:
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d

WARNING: line length of 109 exceeds 100 columns
#951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:927:
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e

WARNING: line length of 109 exceeds 100 columns
#952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:928:
+#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070

WARNING: line length of 109 exceeds 100 columns
#957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:933:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:934:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:935:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:936:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:937:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:938:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:939:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:940:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:941:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:942:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:943:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:944:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:945:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:946:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:947:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:948:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:949:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:950:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:951:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:952:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:953:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:954:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:955:
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:960:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:961:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:962:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:963:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:964:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:965:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:966:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:967:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:968:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:969:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:970:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:971:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:972:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:973:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:974:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:975:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#1000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:976:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#1001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:977:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#1002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:978:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#1003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:979:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#1004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:980:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#1005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:981:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#1006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:982:
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#1011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:987:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#1012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:988:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#1013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:989:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#1014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:990:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#1015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:991:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#1016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:992:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#1017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:993:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#1018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:994:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#1019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:995:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#1020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:996:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#1021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:997:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#1022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:998:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#1023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:999:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#1024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1000:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#1025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1001:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#1026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1002:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#1027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1003:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#1028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1004:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#1029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1005:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#1030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1006:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#1031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1007:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#1032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1008:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#1033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1009:
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#1038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1014:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#1039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1015:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#1040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1016:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#1041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1017:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#1042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1018:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#1043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1019:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#1044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1020:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#1045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1021:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#1046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1022:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#1047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1023:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#1048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1024:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#1049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1025:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#1050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1026:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#1051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1027:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#1052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1028:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#1053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1029:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#1054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1030:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#1055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1031:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#1056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1032:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#1057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1033:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#1058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1034:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#1059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1035:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#1060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1036:
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#1065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1041:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#1066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1042:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#1067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1043:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#1068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1044:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#1069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1045:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#1070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1046:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#1071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1047:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#1072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1048:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#1073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1049:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#1074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1050:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#1075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1051:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#1076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1052:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#1077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1053:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#1078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1054:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#1079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1055:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#1080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1056:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#1081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1057:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#1082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1058:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#1083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1059:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#1084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1060:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#1085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1061:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#1086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1062:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#1087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1063:
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#1092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1068:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#1093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1069:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#1094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1070:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#1095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1071:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#1096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1072:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#1097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1073:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#1098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1074:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#1099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1075:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#1100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1076:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#1101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1077:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#1102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1078:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#1103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1079:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#1104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1080:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#1105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1081:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#1106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1082:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#1107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1083:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#1108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1084:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#1109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1085:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#1110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1086:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#1111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1087:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#1112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1088:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#1113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1089:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#1114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1090:
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#1119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1095:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#1120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1096:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#1121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1097:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#1122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1098:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#1123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1099:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#1124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1100:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#1125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1101:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#1126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1102:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#1127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1103:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#1128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1104:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#1129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1105:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#1130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1106:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#1131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1107:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#1132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1108:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#1133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1109:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#1134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1110:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#1135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1111:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#1136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1112:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#1137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1113:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#1138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1114:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#1139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1115:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#1140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1116:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#1141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1117:
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#1146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1122:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001

WARNING: line length of 109 exceeds 100 columns
#1147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1123:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002

WARNING: line length of 109 exceeds 100 columns
#1148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1124:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003

WARNING: line length of 109 exceeds 100 columns
#1149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1125:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004

WARNING: line length of 109 exceeds 100 columns
#1150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1126:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005

WARNING: line length of 109 exceeds 100 columns
#1151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1127:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006

WARNING: line length of 109 exceeds 100 columns
#1152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1128:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020

WARNING: line length of 109 exceeds 100 columns
#1153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1129:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021

WARNING: line length of 109 exceeds 100 columns
#1154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1130:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022

WARNING: line length of 109 exceeds 100 columns
#1155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1131:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023

WARNING: line length of 109 exceeds 100 columns
#1156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1132:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024

WARNING: line length of 109 exceeds 100 columns
#1157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1133:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036

WARNING: line length of 109 exceeds 100 columns
#1158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1134:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037

WARNING: line length of 109 exceeds 100 columns
#1159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1135:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038

WARNING: line length of 109 exceeds 100 columns
#1160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1136:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053

WARNING: line length of 109 exceeds 100 columns
#1161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1137:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054

WARNING: line length of 109 exceeds 100 columns
#1162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1138:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055

WARNING: line length of 109 exceeds 100 columns
#1163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1139:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056

WARNING: line length of 109 exceeds 100 columns
#1164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1140:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064

WARNING: line length of 109 exceeds 100 columns
#1165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1141:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065

WARNING: line length of 109 exceeds 100 columns
#1166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1142:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066

WARNING: line length of 109 exceeds 100 columns
#1167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1143:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067

WARNING: line length of 109 exceeds 100 columns
#1168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1144:
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068

WARNING: line length of 109 exceeds 100 columns
#1173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1149:
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001

WARNING: line length of 109 exceeds 100 columns
#1174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1150:
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002

WARNING: line length of 109 exceeds 100 columns
#1175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1151:
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003

WARNING: line length of 109 exceeds 100 columns
#1176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1152:
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004

WARNING: line length of 109 exceeds 100 columns
#1177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1153:
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005

WARNING: line length of 109 exceeds 100 columns
#1178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1154:
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006

WARNING: line length of 109 exceeds 100 columns
#1179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1155:
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007

WARNING: line length of 109 exceeds 100 columns
#1180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1156:
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008

WARNING: line length of 109 exceeds 100 columns
#1181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1157:
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009

WARNING: line length of 109 exceeds 100 columns
#1182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1158:
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a

WARNING: line length of 109 exceeds 100 columns
#1183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1159:
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b

WARNING: line length of 109 exceeds 100 columns
#1184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1160:
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c

WARNING: line length of 109 exceeds 100 columns
#1185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1161:
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d

WARNING: line length of 109 exceeds 100 columns
#1186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1162:
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e

WARNING: line length of 112 exceeds 100 columns
#1190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1166:
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x4b7018

WARNING: line length of 105 exceeds 100 columns
#1191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1167:
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      3

WARNING: line length of 112 exceeds 100 columns
#1192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1168:
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x4b7018

WARNING: line length of 105 exceeds 100 columns
#1193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1169:
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     3

WARNING: line length of 112 exceeds 100 columns
#1198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1174:
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x4b7018

WARNING: line length of 105 exceeds 100 columns
#1199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1175:
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  3

WARNING: line length of 112 exceeds 100 columns
#1200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1176:
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x4b7018

WARNING: line length of 105 exceeds 100 columns
#1201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1177:
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 3

WARNING: line length of 110 exceeds 100 columns
#1206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1182:
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040

WARNING: line length of 105 exceeds 100 columns
#1207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1183:
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1

WARNING: line length of 110 exceeds 100 columns
#1208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1184:
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041

WARNING: line length of 105 exceeds 100 columns
#1209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1185:
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1

WARNING: line length of 110 exceeds 100 columns
#1210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1186:
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042

WARNING: line length of 105 exceeds 100 columns
#1211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1187:
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1

WARNING: line length of 110 exceeds 100 columns
#1212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1188:
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043

WARNING: line length of 105 exceeds 100 columns
#1213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1189:
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1

WARNING: line length of 110 exceeds 100 columns
#1214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1190:
+#define regDP_DTO_DBUF_EN                                                                               0x0044

WARNING: line length of 105 exceeds 100 columns
#1215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1191:
+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1

WARNING: line length of 110 exceeds 100 columns
#1216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1192:
+#define regDSCCLK3_DTO_PARAM                                                                            0x0045

WARNING: line length of 105 exceeds 100 columns
#1217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1193:
+#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1194:
+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048

WARNING: line length of 105 exceeds 100 columns
#1219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1195:
+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1

WARNING: line length of 110 exceeds 100 columns
#1220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1196:
+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049

WARNING: line length of 105 exceeds 100 columns
#1221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1197:
+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1

WARNING: line length of 110 exceeds 100 columns
#1222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1198:
+#define regDPSTREAMCLK_CNTL                                                                             0x004a

WARNING: line length of 105 exceeds 100 columns
#1223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1199:
+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1

WARNING: line length of 110 exceeds 100 columns
#1224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1200:
+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b

WARNING: line length of 105 exceeds 100 columns
#1225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1201:
+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1

WARNING: line length of 110 exceeds 100 columns
#1226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1202:
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c

WARNING: line length of 105 exceeds 100 columns
#1227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1203:
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1

WARNING: line length of 110 exceeds 100 columns
#1228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1204:
+#define regDCCG_PERFMON_CNTL2                                                                           0x004e

WARNING: line length of 105 exceeds 100 columns
#1229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1205:
+#define regDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1

WARNING: line length of 110 exceeds 100 columns
#1230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1206:
+#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050

WARNING: line length of 105 exceeds 100 columns
#1231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1207:
+#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1

WARNING: line length of 110 exceeds 100 columns
#1232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1208:
+#define regDCCG_DS_DTO_INCR                                                                             0x0053

WARNING: line length of 105 exceeds 100 columns
#1233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1209:
+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1

WARNING: line length of 110 exceeds 100 columns
#1234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1210:
+#define regDCCG_DS_DTO_MODULO                                                                           0x0054

WARNING: line length of 105 exceeds 100 columns
#1235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1211:
+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1

WARNING: line length of 110 exceeds 100 columns
#1236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1212:
+#define regDCCG_DS_CNTL                                                                                 0x0055

WARNING: line length of 105 exceeds 100 columns
#1237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1213:
+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1

WARNING: line length of 110 exceeds 100 columns
#1238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1214:
+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056

WARNING: line length of 105 exceeds 100 columns
#1239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1215:
+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1

WARNING: line length of 110 exceeds 100 columns
#1240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1216:
+#define regDPREFCLK_CNTL                                                                                0x0058

WARNING: line length of 105 exceeds 100 columns
#1241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1217:
+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1

WARNING: line length of 110 exceeds 100 columns
#1242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1218:
+#define regDCE_VERSION                                                                                  0x005e

WARNING: line length of 105 exceeds 100 columns
#1243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1219:
+#define regDCE_VERSION_BASE_IDX                                                                         1

WARNING: line length of 110 exceeds 100 columns
#1244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1220:
+#define regDCCG_GTC_CNTL                                                                                0x0060

WARNING: line length of 105 exceeds 100 columns
#1245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1221:
+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1

WARNING: line length of 110 exceeds 100 columns
#1246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1222:
+#define regDCCG_GTC_DTO_INCR                                                                            0x0061

WARNING: line length of 105 exceeds 100 columns
#1247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1223:
+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1224:
+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062

WARNING: line length of 105 exceeds 100 columns
#1249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1225:
+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1

WARNING: line length of 110 exceeds 100 columns
#1250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1226:
+#define regDCCG_GTC_CURRENT                                                                             0x0063

WARNING: line length of 105 exceeds 100 columns
#1251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1227:
+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1

WARNING: line length of 110 exceeds 100 columns
#1252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1228:
+#define regSYMCLK32_SE_CNTL                                                                             0x0065

WARNING: line length of 105 exceeds 100 columns
#1253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1229:
+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1

WARNING: line length of 110 exceeds 100 columns
#1254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1230:
+#define regSYMCLK32_LE_CNTL                                                                             0x0066

WARNING: line length of 105 exceeds 100 columns
#1255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1231:
+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1

WARNING: line length of 110 exceeds 100 columns
#1256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1232:
+#define regDTBCLK_P_CNTL                                                                                0x0068

WARNING: line length of 105 exceeds 100 columns
#1257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1233:
+#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1

WARNING: line length of 110 exceeds 100 columns
#1258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1234:
+#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069

WARNING: line length of 105 exceeds 100 columns
#1259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1235:
+#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1

WARNING: line length of 110 exceeds 100 columns
#1260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1236:
+#define regDSCCLK0_DTO_PARAM                                                                            0x006c

WARNING: line length of 105 exceeds 100 columns
#1261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1237:
+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1238:
+#define regDSCCLK1_DTO_PARAM                                                                            0x006d

WARNING: line length of 105 exceeds 100 columns
#1263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1239:
+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1240:
+#define regDSCCLK2_DTO_PARAM                                                                            0x006e

WARNING: line length of 105 exceeds 100 columns
#1265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1241:
+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1242:
+#define regOTG_PIXEL_RATE_DIV                                                                           0x006f

WARNING: line length of 105 exceeds 100 columns
#1267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1243:
+#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1

WARNING: line length of 110 exceeds 100 columns
#1268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1244:
+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070

WARNING: line length of 105 exceeds 100 columns
#1269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1245:
+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1

WARNING: line length of 110 exceeds 100 columns
#1270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1246:
+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071

WARNING: line length of 105 exceeds 100 columns
#1271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1247:
+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1

WARNING: line length of 110 exceeds 100 columns
#1272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1248:
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072

WARNING: line length of 105 exceeds 100 columns
#1273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1249:
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1

WARNING: line length of 110 exceeds 100 columns
#1274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1250:
+#define regDCCG_PERFMON_CNTL                                                                            0x0073

WARNING: line length of 105 exceeds 100 columns
#1275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1251:
+#define regDCCG_PERFMON_CNTL_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1252:
+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074

WARNING: line length of 105 exceeds 100 columns
#1277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1253:
+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1

WARNING: line length of 110 exceeds 100 columns
#1278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1254:
+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075

WARNING: line length of 105 exceeds 100 columns
#1279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1255:
+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1

WARNING: line length of 110 exceeds 100 columns
#1280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1256:
+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076

WARNING: line length of 105 exceeds 100 columns
#1281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1257:
+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1

WARNING: line length of 110 exceeds 100 columns
#1282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1258:
+#define regDCCG_CAC_STATUS                                                                              0x0077

WARNING: line length of 105 exceeds 100 columns
#1283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1259:
+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1

WARNING: line length of 110 exceeds 100 columns
#1284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1260:
+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b

WARNING: line length of 105 exceeds 100 columns
#1285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1261:
+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1

WARNING: line length of 110 exceeds 100 columns
#1286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1262:
+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c

WARNING: line length of 105 exceeds 100 columns
#1287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1263:
+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1

WARNING: line length of 110 exceeds 100 columns
#1288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1264:
+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d

WARNING: line length of 105 exceeds 100 columns
#1289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1265:
+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1

WARNING: line length of 110 exceeds 100 columns
#1290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1266:
+#define regDCCG_DISP_CNTL_REG                                                                           0x007f

WARNING: line length of 105 exceeds 100 columns
#1291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1267:
+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1

WARNING: line length of 110 exceeds 100 columns
#1292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1268:
+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080

WARNING: line length of 105 exceeds 100 columns
#1293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1269:
+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1270:
+#define regDP_DTO0_PHASE                                                                                0x0081

WARNING: line length of 105 exceeds 100 columns
#1295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1271:
+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1

WARNING: line length of 110 exceeds 100 columns
#1296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1272:
+#define regDP_DTO0_MODULO                                                                               0x0082

WARNING: line length of 105 exceeds 100 columns
#1297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1273:
+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1

WARNING: line length of 110 exceeds 100 columns
#1298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1274:
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083

WARNING: line length of 105 exceeds 100 columns
#1299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1275:
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1276:
+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084

WARNING: line length of 105 exceeds 100 columns
#1301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1277:
+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1278:
+#define regDP_DTO1_PHASE                                                                                0x0085

WARNING: line length of 105 exceeds 100 columns
#1303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1279:
+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1

WARNING: line length of 110 exceeds 100 columns
#1304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1280:
+#define regDP_DTO1_MODULO                                                                               0x0086

WARNING: line length of 105 exceeds 100 columns
#1305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1281:
+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1

WARNING: line length of 110 exceeds 100 columns
#1306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1282:
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087

WARNING: line length of 105 exceeds 100 columns
#1307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1283:
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1284:
+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088

WARNING: line length of 105 exceeds 100 columns
#1309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1285:
+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1286:
+#define regDP_DTO2_PHASE                                                                                0x0089

WARNING: line length of 105 exceeds 100 columns
#1311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1287:
+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1

WARNING: line length of 110 exceeds 100 columns
#1312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1288:
+#define regDP_DTO2_MODULO                                                                               0x008a

WARNING: line length of 105 exceeds 100 columns
#1313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1289:
+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1

WARNING: line length of 110 exceeds 100 columns
#1314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1290:
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b

WARNING: line length of 105 exceeds 100 columns
#1315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1291:
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1292:
+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c

WARNING: line length of 105 exceeds 100 columns
#1317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1293:
+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1294:
+#define regDP_DTO3_PHASE                                                                                0x008d

WARNING: line length of 105 exceeds 100 columns
#1319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1295:
+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1

WARNING: line length of 110 exceeds 100 columns
#1320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1296:
+#define regDP_DTO3_MODULO                                                                               0x008e

WARNING: line length of 105 exceeds 100 columns
#1321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1297:
+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1

WARNING: line length of 110 exceeds 100 columns
#1322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1298:
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f

WARNING: line length of 105 exceeds 100 columns
#1323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1299:
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1300:
+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098

WARNING: line length of 105 exceeds 100 columns
#1325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1301:
+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1

WARNING: line length of 110 exceeds 100 columns
#1326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1302:
+#define regDPPCLK0_DTO_PARAM                                                                            0x0099

WARNING: line length of 105 exceeds 100 columns
#1327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1303:
+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1304:
+#define regDPPCLK1_DTO_PARAM                                                                            0x009a

WARNING: line length of 105 exceeds 100 columns
#1329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1305:
+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1306:
+#define regDPPCLK2_DTO_PARAM                                                                            0x009b

WARNING: line length of 105 exceeds 100 columns
#1331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1307:
+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1308:
+#define regDPPCLK3_DTO_PARAM                                                                            0x009c

WARNING: line length of 105 exceeds 100 columns
#1333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1309:
+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1

WARNING: line length of 110 exceeds 100 columns
#1334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1310:
+#define regDCCG_CAC_STATUS2                                                                             0x009f

WARNING: line length of 105 exceeds 100 columns
#1335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1311:
+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1

WARNING: line length of 110 exceeds 100 columns
#1336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1312:
+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0

WARNING: line length of 105 exceeds 100 columns
#1337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1313:
+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1314:
+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1

WARNING: line length of 105 exceeds 100 columns
#1339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1315:
+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1316:
+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2

WARNING: line length of 105 exceeds 100 columns
#1341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1317:
+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1318:
+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3

WARNING: line length of 105 exceeds 100 columns
#1343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1319:
+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1320:
+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4

WARNING: line length of 105 exceeds 100 columns
#1345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1321:
+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1322:
+#define regDCCG_SOFT_RESET                                                                              0x00a6

WARNING: line length of 105 exceeds 100 columns
#1347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1323:
+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1

WARNING: line length of 110 exceeds 100 columns
#1348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1324:
+#define regDSCCLK_DTO_CTRL                                                                              0x00a7

WARNING: line length of 105 exceeds 100 columns
#1349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1325:
+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1

WARNING: line length of 110 exceeds 100 columns
#1350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1326:
+#define regDPPCLK_CTRL                                                                                  0x00a8

WARNING: line length of 105 exceeds 100 columns
#1351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1327:
+#define regDPPCLK_CTRL_BASE_IDX                                                                         1

WARNING: line length of 110 exceeds 100 columns
#1352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1328:
+#define regDCCG_GATE_DISABLE_CNTL6                                                                      0x00a9

WARNING: line length of 105 exceeds 100 columns
#1353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1329:
+#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX                                                             1

WARNING: line length of 110 exceeds 100 columns
#1354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1330:
+#define regSYMCLK_PSP_CNTL                                                                              0x00aa

WARNING: line length of 105 exceeds 100 columns
#1355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1331:
+#define regSYMCLK_PSP_CNTL_BASE_IDX                                                                     1

WARNING: line length of 110 exceeds 100 columns
#1356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1332:
+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab

WARNING: line length of 105 exceeds 100 columns
#1357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1333:
+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1

WARNING: line length of 110 exceeds 100 columns
#1358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1334:
+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac

WARNING: line length of 105 exceeds 100 columns
#1359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1335:
+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1

WARNING: line length of 110 exceeds 100 columns
#1360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1336:
+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad

WARNING: line length of 105 exceeds 100 columns
#1361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1337:
+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1

WARNING: line length of 110 exceeds 100 columns
#1362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1338:
+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae

WARNING: line length of 105 exceeds 100 columns
#1363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1339:
+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1

WARNING: line length of 110 exceeds 100 columns
#1364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1340:
+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af

WARNING: line length of 105 exceeds 100 columns
#1365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1341:
+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1

WARNING: line length of 110 exceeds 100 columns
#1366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1342:
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0

WARNING: line length of 105 exceeds 100 columns
#1367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1343:
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1344:
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1

WARNING: line length of 105 exceeds 100 columns
#1369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1345:
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1346:
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2

WARNING: line length of 105 exceeds 100 columns
#1371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1347:
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1348:
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3

WARNING: line length of 105 exceeds 100 columns
#1373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1349:
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1350:
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4

WARNING: line length of 105 exceeds 100 columns
#1375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1351:
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1352:
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5

WARNING: line length of 105 exceeds 100 columns
#1377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1353:
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1

WARNING: line length of 110 exceeds 100 columns
#1378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1354:
+#define regDPPCLK_DTO_CTRL                                                                              0x00b6

WARNING: line length of 105 exceeds 100 columns
#1379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1355:
+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1

WARNING: line length of 110 exceeds 100 columns
#1380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1356:
+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8

WARNING: line length of 105 exceeds 100 columns
#1381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1357:
+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1

WARNING: line length of 110 exceeds 100 columns
#1382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1358:
+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9

WARNING: line length of 105 exceeds 100 columns
#1383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1359:
+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1

WARNING: line length of 110 exceeds 100 columns
#1384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1360:
+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba

WARNING: line length of 105 exceeds 100 columns
#1385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1361:
+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1

WARNING: line length of 110 exceeds 100 columns
#1386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1362:
+#define regDTBCLK_DTO0_PHASE                                                                            0x0018

WARNING: line length of 105 exceeds 100 columns
#1387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1363:
+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1364:
+#define regDTBCLK_DTO1_PHASE                                                                            0x0019

WARNING: line length of 105 exceeds 100 columns
#1389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1365:
+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1366:
+#define regDTBCLK_DTO2_PHASE                                                                            0x001a

WARNING: line length of 105 exceeds 100 columns
#1391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1367:
+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1368:
+#define regDTBCLK_DTO3_PHASE                                                                            0x001b

WARNING: line length of 105 exceeds 100 columns
#1393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1369:
+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1370:
+#define regDTBCLK_DTO0_MODULO                                                                           0x001f

WARNING: line length of 105 exceeds 100 columns
#1395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1371:
+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1372:
+#define regDTBCLK_DTO1_MODULO                                                                           0x0020

WARNING: line length of 105 exceeds 100 columns
#1397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1373:
+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1374:
+#define regDTBCLK_DTO2_MODULO                                                                           0x0021

WARNING: line length of 105 exceeds 100 columns
#1399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1375:
+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1376:
+#define regDTBCLK_DTO3_MODULO                                                                           0x0022

WARNING: line length of 105 exceeds 100 columns
#1401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1377:
+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1378:
+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a

WARNING: line length of 105 exceeds 100 columns
#1403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1379:
+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1380:
+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052

WARNING: line length of 105 exceeds 100 columns
#1405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1381:
+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1382:
+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053

WARNING: line length of 105 exceeds 100 columns
#1407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1383:
+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1384:
+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054

WARNING: line length of 105 exceeds 100 columns
#1409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1385:
+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1386:
+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055

WARNING: line length of 105 exceeds 100 columns
#1411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1387:
+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1388:
+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056

WARNING: line length of 105 exceeds 100 columns
#1413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1389:
+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1390:
+#define regHDMISTREAMCLK_CNTL                                                                           0x0059

WARNING: line length of 105 exceeds 100 columns
#1415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1391:
+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1392:
+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a

WARNING: line length of 105 exceeds 100 columns
#1417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1393:
+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1394:
+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b

WARNING: line length of 105 exceeds 100 columns
#1419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1395:
+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1396:
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061

WARNING: line length of 105 exceeds 100 columns
#1421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1397:
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#1422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1398:
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062

WARNING: line length of 105 exceeds 100 columns
#1423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1399:
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#1424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1400:
+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063

WARNING: line length of 105 exceeds 100 columns
#1425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1401:
+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1405:
+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064

WARNING: line length of 105 exceeds 100 columns
#1430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1406:
+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1

WARNING: line length of 109 exceeds 100 columns
#1435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1411:
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00

WARNING: line length of 109 exceeds 100 columns
#1436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1412:
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02

WARNING: line length of 109 exceeds 100 columns
#1437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1413:
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04

WARNING: line length of 109 exceeds 100 columns
#1438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1414:
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705

WARNING: line length of 109 exceeds 100 columns
#1439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1415:
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720

WARNING: line length of 109 exceeds 100 columns
#1440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1416:
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721

WARNING: line length of 109 exceeds 100 columns
#1441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1417:
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722

WARNING: line length of 109 exceeds 100 columns
#1442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1418:
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723

WARNING: line length of 109 exceeds 100 columns
#1443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1419:
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770

WARNING: line length of 109 exceeds 100 columns
#1444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1420:
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff

WARNING: line length of 109 exceeds 100 columns
#1445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1421:
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04

WARNING: line length of 109 exceeds 100 columns
#1446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1422:
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05

WARNING: line length of 109 exceeds 100 columns
#1447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1423:
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a

WARNING: line length of 109 exceeds 100 columns
#1448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1424:
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b

WARNING: line length of 109 exceeds 100 columns
#1449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1425:
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f

WARNING: line length of 109 exceeds 100 columns
#1454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1430:
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200

WARNING: line length of 109 exceeds 100 columns
#1455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1431:
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706

WARNING: line length of 109 exceeds 100 columns
#1456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1432:
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d

WARNING: line length of 109 exceeds 100 columns
#1457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1433:
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e

WARNING: line length of 109 exceeds 100 columns
#1458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1434:
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724

WARNING: line length of 109 exceeds 100 columns
#1459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1435:
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e

WARNING: line length of 109 exceeds 100 columns
#1460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1436:
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770

WARNING: line length of 109 exceeds 100 columns
#1461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1437:
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771

WARNING: line length of 109 exceeds 100 columns
#1462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1438:
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09

WARNING: line length of 109 exceeds 100 columns
#1463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1439:
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a

WARNING: line length of 109 exceeds 100 columns
#1464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1440:
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b

WARNING: line length of 109 exceeds 100 columns
#1465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1441:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702

WARNING: line length of 109 exceeds 100 columns
#1466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1442:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707

WARNING: line length of 109 exceeds 100 columns
#1467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1443:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708

WARNING: line length of 109 exceeds 100 columns
#1468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1444:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709

WARNING: line length of 109 exceeds 100 columns
#1469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1445:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c

WARNING: line length of 109 exceeds 100 columns
#1470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1446:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d

WARNING: line length of 109 exceeds 100 columns
#1471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1447:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e

WARNING: line length of 109 exceeds 100 columns
#1472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1448:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f

WARNING: line length of 109 exceeds 100 columns
#1473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1449:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770

WARNING: line length of 109 exceeds 100 columns
#1474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1450:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771

WARNING: line length of 109 exceeds 100 columns
#1475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1451:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772

WARNING: line length of 109 exceeds 100 columns
#1476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1452:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776

WARNING: line length of 109 exceeds 100 columns
#1477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1453:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776

WARNING: line length of 109 exceeds 100 columns
#1478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1454:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777

WARNING: line length of 109 exceeds 100 columns
#1479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1455:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778

WARNING: line length of 109 exceeds 100 columns
#1480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1456:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779

WARNING: line length of 109 exceeds 100 columns
#1481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1457:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a

WARNING: line length of 109 exceeds 100 columns
#1482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1458:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b

WARNING: line length of 109 exceeds 100 columns
#1483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1459:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c

WARNING: line length of 109 exceeds 100 columns
#1484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1460:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780

WARNING: line length of 109 exceeds 100 columns
#1485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1461:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781

WARNING: line length of 109 exceeds 100 columns
#1486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1462:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785

WARNING: line length of 109 exceeds 100 columns
#1487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1463:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786

WARNING: line length of 109 exceeds 100 columns
#1488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1464:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787

WARNING: line length of 109 exceeds 100 columns
#1489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1465:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788

WARNING: line length of 109 exceeds 100 columns
#1490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1466:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789

WARNING: line length of 109 exceeds 100 columns
#1491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1467:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a

WARNING: line length of 109 exceeds 100 columns
#1492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1468:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b

WARNING: line length of 109 exceeds 100 columns
#1493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1469:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c

WARNING: line length of 109 exceeds 100 columns
#1494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1470:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d

WARNING: line length of 109 exceeds 100 columns
#1495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1471:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e

WARNING: line length of 109 exceeds 100 columns
#1496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1472:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f

WARNING: line length of 109 exceeds 100 columns
#1497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1473:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790

WARNING: line length of 109 exceeds 100 columns
#1498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1474:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791

WARNING: line length of 109 exceeds 100 columns
#1499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1475:
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792

WARNING: line length of 109 exceeds 100 columns
#1500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1476:
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793

WARNING: line length of 109 exceeds 100 columns
#1501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1477:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797

WARNING: line length of 109 exceeds 100 columns
#1502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1478:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798

WARNING: line length of 109 exceeds 100 columns
#1503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1479:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799

WARNING: line length of 109 exceeds 100 columns
#1504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1480:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a

WARNING: line length of 109 exceeds 100 columns
#1505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1481:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b

WARNING: line length of 109 exceeds 100 columns
#1506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1482:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c

WARNING: line length of 109 exceeds 100 columns
#1507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1483:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d

WARNING: line length of 109 exceeds 100 columns
#1508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1484:
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e

WARNING: line length of 109 exceeds 100 columns
#1509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1485:
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09

WARNING: line length of 109 exceeds 100 columns
#1510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1486:
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c

WARNING: line length of 109 exceeds 100 columns
#1511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1487:
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e

WARNING: line length of 109 exceeds 100 columns
#1516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1492:
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200

WARNING: line length of 109 exceeds 100 columns
#1517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1493:
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706

WARNING: line length of 109 exceeds 100 columns
#1518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1494:
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d

WARNING: line length of 109 exceeds 100 columns
#1519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1495:
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09

WARNING: line length of 109 exceeds 100 columns
#1520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1496:
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a

WARNING: line length of 109 exceeds 100 columns
#1521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1497:
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b

WARNING: line length of 109 exceeds 100 columns
#1522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1498:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707

WARNING: line length of 109 exceeds 100 columns
#1523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1499:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708

WARNING: line length of 109 exceeds 100 columns
#1524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1500:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709

WARNING: line length of 109 exceeds 100 columns
#1525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1501:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c

WARNING: line length of 109 exceeds 100 columns
#1526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1502:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d

WARNING: line length of 109 exceeds 100 columns
#1527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1503:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e

WARNING: line length of 109 exceeds 100 columns
#1528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1504:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f

WARNING: line length of 109 exceeds 100 columns
#1529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1505:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771

WARNING: line length of 109 exceeds 100 columns
#1530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1506:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777

WARNING: line length of 109 exceeds 100 columns
#1531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1507:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778

WARNING: line length of 109 exceeds 100 columns
#1532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1508:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779

WARNING: line length of 109 exceeds 100 columns
#1533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1509:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a

WARNING: line length of 109 exceeds 100 columns
#1534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1510:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c

WARNING: line length of 109 exceeds 100 columns
#1535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1511:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785

WARNING: line length of 109 exceeds 100 columns
#1536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1512:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786

WARNING: line length of 109 exceeds 100 columns
#1537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1513:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787

WARNING: line length of 109 exceeds 100 columns
#1538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1514:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788

WARNING: line length of 109 exceeds 100 columns
#1539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1515:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798

WARNING: line length of 109 exceeds 100 columns
#1540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1516:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799

WARNING: line length of 109 exceeds 100 columns
#1541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1517:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a

WARNING: line length of 109 exceeds 100 columns
#1542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1518:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b

WARNING: line length of 109 exceeds 100 columns
#1543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1519:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c

WARNING: line length of 109 exceeds 100 columns
#1544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1520:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d

WARNING: line length of 109 exceeds 100 columns
#1545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1521:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e

WARNING: line length of 109 exceeds 100 columns
#1546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1522:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09

WARNING: line length of 109 exceeds 100 columns
#1547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1523:
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c

WARNING: line length of 110 exceeds 100 columns
#1552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1528:
+#define regDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000

WARNING: line length of 105 exceeds 100 columns
#1553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1529:
+#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#1554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1530:
+#define regDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001

WARNING: line length of 105 exceeds 100 columns
#1555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1531:
+#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1532:
+#define regDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002

WARNING: line length of 105 exceeds 100 columns
#1557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1533:
+#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1534:
+#define regDC_PERFMON0_PERFMON_CNTL                                                                     0x0003

WARNING: line length of 105 exceeds 100 columns
#1559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1535:
+#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1536:
+#define regDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004

WARNING: line length of 105 exceeds 100 columns
#1561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1537:
+#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1538:
+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005

WARNING: line length of 105 exceeds 100 columns
#1563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1539:
+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#1564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1540:
+#define regDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006

WARNING: line length of 105 exceeds 100 columns
#1565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1541:
+#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1542:
+#define regDC_PERFMON0_PERFMON_HI                                                                       0x0007

WARNING: line length of 105 exceeds 100 columns
#1567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1543:
+#define regDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#1568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1544:
+#define regDC_PERFMON0_PERFMON_LOW                                                                      0x0008

WARNING: line length of 105 exceeds 100 columns
#1569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1545:
+#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1550:
+#define regDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c

WARNING: line length of 105 exceeds 100 columns
#1575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1551:
+#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#1576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1552:
+#define regDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d

WARNING: line length of 105 exceeds 100 columns
#1577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1553:
+#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1554:
+#define regDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e

WARNING: line length of 105 exceeds 100 columns
#1579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1555:
+#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1556:
+#define regDC_PERFMON1_PERFMON_CNTL                                                                     0x000f

WARNING: line length of 105 exceeds 100 columns
#1581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1557:
+#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1558:
+#define regDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010

WARNING: line length of 105 exceeds 100 columns
#1583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1559:
+#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1560:
+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011

WARNING: line length of 105 exceeds 100 columns
#1585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1561:
+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#1586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1562:
+#define regDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012

WARNING: line length of 105 exceeds 100 columns
#1587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1563:
+#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1564:
+#define regDC_PERFMON1_PERFMON_HI                                                                       0x0013

WARNING: line length of 105 exceeds 100 columns
#1589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1565:
+#define regDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#1590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1566:
+#define regDC_PERFMON1_PERFMON_LOW                                                                      0x0014

WARNING: line length of 105 exceeds 100 columns
#1591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1567:
+#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1572:
+#define regDOMAIN0_PG_CONFIG                                                                            0x0080

WARNING: line length of 105 exceeds 100 columns
#1597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1573:
+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1574:
+#define regDOMAIN0_PG_STATUS                                                                            0x0081

WARNING: line length of 105 exceeds 100 columns
#1599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1575:
+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1576:
+#define regDOMAIN1_PG_CONFIG                                                                            0x0082

WARNING: line length of 105 exceeds 100 columns
#1601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1577:
+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1578:
+#define regDOMAIN1_PG_STATUS                                                                            0x0083

WARNING: line length of 105 exceeds 100 columns
#1603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1579:
+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1580:
+#define regDOMAIN2_PG_CONFIG                                                                            0x0084

WARNING: line length of 105 exceeds 100 columns
#1605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1581:
+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1582:
+#define regDOMAIN2_PG_STATUS                                                                            0x0085

WARNING: line length of 105 exceeds 100 columns
#1607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1583:
+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1584:
+#define regDOMAIN3_PG_CONFIG                                                                            0x0086

WARNING: line length of 105 exceeds 100 columns
#1609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1585:
+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1586:
+#define regDOMAIN3_PG_STATUS                                                                            0x0087

WARNING: line length of 105 exceeds 100 columns
#1611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1587:
+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1588:
+#define regDOMAIN16_PG_CONFIG                                                                           0x0089

WARNING: line length of 105 exceeds 100 columns
#1613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1589:
+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1590:
+#define regDOMAIN16_PG_STATUS                                                                           0x008a

WARNING: line length of 105 exceeds 100 columns
#1615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1591:
+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1592:
+#define regDOMAIN17_PG_CONFIG                                                                           0x008b

WARNING: line length of 105 exceeds 100 columns
#1617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1593:
+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1594:
+#define regDOMAIN17_PG_STATUS                                                                           0x008c

WARNING: line length of 105 exceeds 100 columns
#1619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1595:
+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1596:
+#define regDOMAIN18_PG_CONFIG                                                                           0x008d

WARNING: line length of 105 exceeds 100 columns
#1621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1597:
+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1598:
+#define regDOMAIN18_PG_STATUS                                                                           0x008e

WARNING: line length of 105 exceeds 100 columns
#1623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1599:
+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1600:
+#define regDOMAIN19_PG_CONFIG                                                                           0x008f

WARNING: line length of 105 exceeds 100 columns
#1625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1601:
+#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1602:
+#define regDOMAIN19_PG_STATUS                                                                           0x0090

WARNING: line length of 105 exceeds 100 columns
#1627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1603:
+#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1604:
+#define regDOMAIN22_PG_CONFIG                                                                           0x0092

WARNING: line length of 105 exceeds 100 columns
#1629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1605:
+#define regDOMAIN22_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1606:
+#define regDOMAIN22_PG_STATUS                                                                           0x0093

WARNING: line length of 105 exceeds 100 columns
#1631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1607:
+#define regDOMAIN22_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1608:
+#define regDOMAIN23_PG_CONFIG                                                                           0x0094

WARNING: line length of 105 exceeds 100 columns
#1633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1609:
+#define regDOMAIN23_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1610:
+#define regDOMAIN23_PG_STATUS                                                                           0x0095

WARNING: line length of 105 exceeds 100 columns
#1635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1611:
+#define regDOMAIN23_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1612:
+#define regDOMAIN24_PG_CONFIG                                                                           0x0096

WARNING: line length of 105 exceeds 100 columns
#1637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1613:
+#define regDOMAIN24_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1614:
+#define regDOMAIN24_PG_STATUS                                                                           0x0097

WARNING: line length of 105 exceeds 100 columns
#1639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1615:
+#define regDOMAIN24_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1616:
+#define regDOMAIN25_PG_CONFIG                                                                           0x0098

WARNING: line length of 105 exceeds 100 columns
#1641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1617:
+#define regDOMAIN25_PG_CONFIG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1618:
+#define regDOMAIN25_PG_STATUS                                                                           0x0099

WARNING: line length of 105 exceeds 100 columns
#1643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1619:
+#define regDOMAIN25_PG_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1620:
+#define regDCPG_INTERRUPT_STATUS                                                                        0x009a

WARNING: line length of 105 exceeds 100 columns
#1645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1621:
+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1622:
+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x009b

WARNING: line length of 105 exceeds 100 columns
#1647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1623:
+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1624:
+#define regDCPG_INTERRUPT_STATUS_3                                                                      0x009c

WARNING: line length of 105 exceeds 100 columns
#1649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1625:
+#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1626:
+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x009d

WARNING: line length of 105 exceeds 100 columns
#1651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1627:
+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1628:
+#define regDCPG_INTERRUPT_CONTROL_2                                                                     0x009e

WARNING: line length of 105 exceeds 100 columns
#1653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1629:
+#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1630:
+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x009f

WARNING: line length of 105 exceeds 100 columns
#1655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1631:
+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1632:
+#define regDC_IP_REQUEST_CNTL                                                                           0x00a0

WARNING: line length of 105 exceeds 100 columns
#1657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1633:
+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1634:
+#define regLONO_MEM_PWR_REQ_CNTL                                                                        0x00a4

WARNING: line length of 105 exceeds 100 columns
#1659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1635:
+#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1640:
+#define regDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be

WARNING: line length of 105 exceeds 100 columns
#1665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1641:
+#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#1666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1642:
+#define regDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf

WARNING: line length of 105 exceeds 100 columns
#1667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1643:
+#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1644:
+#define regDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0

WARNING: line length of 105 exceeds 100 columns
#1669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1645:
+#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1646:
+#define regDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1

WARNING: line length of 105 exceeds 100 columns
#1671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1647:
+#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1648:
+#define regDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2

WARNING: line length of 105 exceeds 100 columns
#1673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1649:
+#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1650:
+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3

WARNING: line length of 105 exceeds 100 columns
#1675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1651:
+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#1676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1652:
+#define regDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4

WARNING: line length of 105 exceeds 100 columns
#1677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1653:
+#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1654:
+#define regDC_PERFMON2_PERFMON_HI                                                                       0x00c5

WARNING: line length of 105 exceeds 100 columns
#1679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1655:
+#define regDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#1680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1656:
+#define regDC_PERFMON2_PERFMON_LOW                                                                      0x00c6

WARNING: line length of 105 exceeds 100 columns
#1681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1657:
+#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1662:
+#define regCC_DC_PIPE_DIS                                                                               0x00ca

WARNING: line length of 105 exceeds 100 columns
#1687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1663:
+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#1688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1664:
+#define regDMU_CLK_CNTL                                                                                 0x00cb

WARNING: line length of 105 exceeds 100 columns
#1689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1665:
+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#1690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1666:
+#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd

WARNING: line length of 105 exceeds 100 columns
#1691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1667:
+#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1668:
+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce

WARNING: line length of 105 exceeds 100 columns
#1693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1669:
+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1670:
+#define regZSC_CNTL                                                                                     0x00cf

WARNING: line length of 105 exceeds 100 columns
#1695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1671:
+#define regZSC_CNTL_BASE_IDX                                                                            2

WARNING: line length of 110 exceeds 100 columns
#1696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1672:
+#define regZSC_CNTL2                                                                                    0x00d0

WARNING: line length of 105 exceeds 100 columns
#1697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1673:
+#define regZSC_CNTL2_BASE_IDX                                                                           2

WARNING: line length of 110 exceeds 100 columns
#1698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1674:
+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6

WARNING: line length of 105 exceeds 100 columns
#1699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1675:
+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1676:
+#define regZSC_STATUS                                                                                   0x00d7

WARNING: line length of 105 exceeds 100 columns
#1701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1677:
+#define regZSC_STATUS_BASE_IDX                                                                          2

WARNING: line length of 110 exceeds 100 columns
#1702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1678:
+#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG                                                                0x00d8

WARNING: line length of 105 exceeds 100 columns
#1703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1679:
+#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1680:
+#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG                                                                 0x00d9

WARNING: line length of 105 exceeds 100 columns
#1705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1681:
+#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#1706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1682:
+#define regZPR_CLK_UNGATE_DELAY                                                                         0x00da

WARNING: line length of 105 exceeds 100 columns
#1707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1683:
+#define regZPR_CLK_UNGATE_DELAY_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1689:
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126

WARNING: line length of 105 exceeds 100 columns
#1714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1690:
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#1715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1691:
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127

WARNING: line length of 105 exceeds 100 columns
#1716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1692:
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#1717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1693:
+#define regDC_GPU_TIMER_READ                                                                            0x0128

WARNING: line length of 105 exceeds 100 columns
#1718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1694:
+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1695:
+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129

WARNING: line length of 105 exceeds 100 columns
#1720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1696:
+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#1721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1697:
+#define regDISP_INTERRUPT_STATUS                                                                        0x012a

WARNING: line length of 105 exceeds 100 columns
#1722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1698:
+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1699:
+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b

WARNING: line length of 105 exceeds 100 columns
#1724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1700:
+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1701:
+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c

WARNING: line length of 105 exceeds 100 columns
#1726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1702:
+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1703:
+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d

WARNING: line length of 105 exceeds 100 columns
#1728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1704:
+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1705:
+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e

WARNING: line length of 105 exceeds 100 columns
#1730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1706:
+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1707:
+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f

WARNING: line length of 105 exceeds 100 columns
#1732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1708:
+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1709:
+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130

WARNING: line length of 105 exceeds 100 columns
#1734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1710:
+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1711:
+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131

WARNING: line length of 105 exceeds 100 columns
#1736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1712:
+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1713:
+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132

WARNING: line length of 105 exceeds 100 columns
#1738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1714:
+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1715:
+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133

WARNING: line length of 105 exceeds 100 columns
#1740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1716:
+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#1741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1717:
+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134

WARNING: line length of 105 exceeds 100 columns
#1742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1718:
+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1719:
+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135

WARNING: line length of 105 exceeds 100 columns
#1744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1720:
+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1721:
+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136

WARNING: line length of 105 exceeds 100 columns
#1746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1722:
+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1723:
+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137

WARNING: line length of 105 exceeds 100 columns
#1748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1724:
+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1725:
+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138

WARNING: line length of 105 exceeds 100 columns
#1750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1726:
+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1727:
+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139

WARNING: line length of 105 exceeds 100 columns
#1752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1728:
+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1729:
+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a

WARNING: line length of 105 exceeds 100 columns
#1754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1730:
+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1731:
+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b

WARNING: line length of 105 exceeds 100 columns
#1756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1732:
+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1733:
+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c

WARNING: line length of 105 exceeds 100 columns
#1758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1734:
+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1735:
+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d

WARNING: line length of 105 exceeds 100 columns
#1760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1736:
+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1737:
+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e

WARNING: line length of 105 exceeds 100 columns
#1762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1738:
+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1739:
+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f

WARNING: line length of 105 exceeds 100 columns
#1764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1740:
+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1741:
+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140

WARNING: line length of 105 exceeds 100 columns
#1766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1742:
+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1743:
+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141

WARNING: line length of 105 exceeds 100 columns
#1768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1744:
+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#1769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1745:
+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142

WARNING: line length of 105 exceeds 100 columns
#1770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1746:
+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1747:
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143

WARNING: line length of 105 exceeds 100 columns
#1772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1748:
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#1773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1749:
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144

WARNING: line length of 105 exceeds 100 columns
#1774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1750:
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#1775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1751:
+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145

WARNING: line length of 105 exceeds 100 columns
#1776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1752:
+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1753:
+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146

WARNING: line length of 105 exceeds 100 columns
#1778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1754:
+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1755:
+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147

WARNING: line length of 105 exceeds 100 columns
#1780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1756:
+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1757:
+#define regDCCG_INTERRUPT_DEST                                                                          0x0148

WARNING: line length of 105 exceeds 100 columns
#1782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1758:
+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1759:
+#define regDMU_INTERRUPT_DEST                                                                           0x0149

WARNING: line length of 105 exceeds 100 columns
#1784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1760:
+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1761:
+#define regDMU_INTERRUPT_DEST2                                                                          0x014a

WARNING: line length of 105 exceeds 100 columns
#1786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1762:
+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1763:
+#define regDCPG_INTERRUPT_DEST                                                                          0x014b

WARNING: line length of 105 exceeds 100 columns
#1788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1764:
+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1765:
+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c

WARNING: line length of 105 exceeds 100 columns
#1790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1766:
+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1767:
+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d

WARNING: line length of 105 exceeds 100 columns
#1792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1768:
+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1769:
+#define regWB_INTERRUPT_DEST                                                                            0x014e

WARNING: line length of 105 exceeds 100 columns
#1794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1770:
+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1771:
+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f

WARNING: line length of 105 exceeds 100 columns
#1796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1772:
+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1773:
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150

WARNING: line length of 105 exceeds 100 columns
#1798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1774:
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#1799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1775:
+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151

WARNING: line length of 105 exceeds 100 columns
#1800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1776:
+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1777:
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152

WARNING: line length of 105 exceeds 100 columns
#1802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1778:
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1779:
+#define regMPC_INTERRUPT_DEST                                                                           0x0153

WARNING: line length of 105 exceeds 100 columns
#1804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1780:
+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1781:
+#define regOPP_INTERRUPT_DEST                                                                           0x0154

WARNING: line length of 105 exceeds 100 columns
#1806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1782:
+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1783:
+#define regOPTC_INTERRUPT_DEST                                                                          0x0155

WARNING: line length of 105 exceeds 100 columns
#1808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1784:
+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1785:
+#define regOTG0_INTERRUPT_DEST                                                                          0x0156

WARNING: line length of 105 exceeds 100 columns
#1810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1786:
+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1787:
+#define regOTG1_INTERRUPT_DEST                                                                          0x0157

WARNING: line length of 105 exceeds 100 columns
#1812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1788:
+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1789:
+#define regOTG2_INTERRUPT_DEST                                                                          0x0158

WARNING: line length of 105 exceeds 100 columns
#1814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1790:
+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1791:
+#define regOTG3_INTERRUPT_DEST                                                                          0x0159

WARNING: line length of 105 exceeds 100 columns
#1816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1792:
+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1793:
+#define regOTG4_INTERRUPT_DEST                                                                          0x015a

WARNING: line length of 105 exceeds 100 columns
#1818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1794:
+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1795:
+#define regOTG5_INTERRUPT_DEST                                                                          0x015b

WARNING: line length of 105 exceeds 100 columns
#1820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1796:
+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1797:
+#define regDIG_INTERRUPT_DEST                                                                           0x015c

WARNING: line length of 105 exceeds 100 columns
#1822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1798:
+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1799:
+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d

WARNING: line length of 105 exceeds 100 columns
#1824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1800:
+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#1825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1801:
+#define regDIO_INTERRUPT_DEST                                                                           0x015f

WARNING: line length of 105 exceeds 100 columns
#1826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1802:
+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1803:
+#define regDCIO_INTERRUPT_DEST                                                                          0x0160

WARNING: line length of 105 exceeds 100 columns
#1828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1804:
+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1805:
+#define regHPD_INTERRUPT_DEST                                                                           0x0161

WARNING: line length of 105 exceeds 100 columns
#1830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1806:
+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1807:
+#define regAZ_INTERRUPT_DEST                                                                            0x0162

WARNING: line length of 105 exceeds 100 columns
#1832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1808:
+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1809:
+#define regAUX_INTERRUPT_DEST                                                                           0x0163

WARNING: line length of 105 exceeds 100 columns
#1834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1810:
+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1811:
+#define regDSC_INTERRUPT_DEST                                                                           0x0164

WARNING: line length of 105 exceeds 100 columns
#1836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1812:
+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1813:
+#define regHPO_INTERRUPT_DEST                                                                           0x0165

WARNING: line length of 105 exceeds 100 columns
#1838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1814:
+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1819:
+#define regDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a

WARNING: line length of 105 exceeds 100 columns
#1844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1820:
+#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#1849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1825:
+#define regRBBMIF_TIMEOUT                                                                               0x017f

WARNING: line length of 105 exceeds 100 columns
#1850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1826:
+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#1851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1827:
+#define regRBBMIF_STATUS                                                                                0x0180

WARNING: line length of 105 exceeds 100 columns
#1852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1828:
+#define regRBBMIF_STATUS_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#1853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1829:
+#define regRBBMIF_STATUS_2                                                                              0x0181

WARNING: line length of 105 exceeds 100 columns
#1854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1830:
+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#1855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1831:
+#define regRBBMIF_INT_STATUS                                                                            0x0182

WARNING: line length of 105 exceeds 100 columns
#1856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1832:
+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1833:
+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183

WARNING: line length of 105 exceeds 100 columns
#1858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1834:
+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1835:
+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184

WARNING: line length of 105 exceeds 100 columns
#1860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1836:
+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1837:
+#define regRBBMIF_STATUS_FLAG                                                                           0x0185

WARNING: line length of 105 exceeds 100 columns
#1862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1838:
+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#1867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1843:
+#define regDMCUB_REGION0_OFFSET                                                                         0x018e

WARNING: line length of 105 exceeds 100 columns
#1868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1844:
+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1845:
+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f

WARNING: line length of 105 exceeds 100 columns
#1870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1846:
+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1847:
+#define regDMCUB_REGION1_OFFSET                                                                         0x0190

WARNING: line length of 105 exceeds 100 columns
#1872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1848:
+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1849:
+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191

WARNING: line length of 105 exceeds 100 columns
#1874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1850:
+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1851:
+#define regDMCUB_REGION2_OFFSET                                                                         0x0192

WARNING: line length of 105 exceeds 100 columns
#1876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1852:
+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1853:
+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193

WARNING: line length of 105 exceeds 100 columns
#1878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1854:
+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1855:
+#define regDMCUB_REGION4_OFFSET                                                                         0x0196

WARNING: line length of 105 exceeds 100 columns
#1880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1856:
+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1857:
+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197

WARNING: line length of 105 exceeds 100 columns
#1882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1858:
+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1859:
+#define regDMCUB_REGION5_OFFSET                                                                         0x0198

WARNING: line length of 105 exceeds 100 columns
#1884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1860:
+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1861:
+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199

WARNING: line length of 105 exceeds 100 columns
#1886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1862:
+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1863:
+#define regDMCUB_REGION6_OFFSET                                                                         0x019a

WARNING: line length of 105 exceeds 100 columns
#1888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1864:
+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1865:
+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b

WARNING: line length of 105 exceeds 100 columns
#1890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1866:
+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1867:
+#define regDMCUB_REGION7_OFFSET                                                                         0x019c

WARNING: line length of 105 exceeds 100 columns
#1892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1868:
+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1869:
+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d

WARNING: line length of 105 exceeds 100 columns
#1894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1870:
+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1871:
+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e

WARNING: line length of 105 exceeds 100 columns
#1896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1872:
+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1873:
+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f

WARNING: line length of 105 exceeds 100 columns
#1898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1874:
+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1875:
+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0

WARNING: line length of 105 exceeds 100 columns
#1900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1876:
+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1877:
+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1

WARNING: line length of 105 exceeds 100 columns
#1902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1878:
+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1879:
+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2

WARNING: line length of 105 exceeds 100 columns
#1904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1880:
+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1881:
+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3

WARNING: line length of 105 exceeds 100 columns
#1906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1882:
+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1883:
+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4

WARNING: line length of 105 exceeds 100 columns
#1908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1884:
+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1885:
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5

WARNING: line length of 105 exceeds 100 columns
#1910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1886:
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1887:
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6

WARNING: line length of 105 exceeds 100 columns
#1912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1888:
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1889:
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7

WARNING: line length of 105 exceeds 100 columns
#1914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1890:
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1891:
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8

WARNING: line length of 105 exceeds 100 columns
#1916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1892:
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1893:
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9

WARNING: line length of 105 exceeds 100 columns
#1918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1894:
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1895:
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa

WARNING: line length of 105 exceeds 100 columns
#1920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1896:
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1897:
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab

WARNING: line length of 105 exceeds 100 columns
#1922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1898:
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1899:
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac

WARNING: line length of 105 exceeds 100 columns
#1924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1900:
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#1925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1901:
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad

WARNING: line length of 105 exceeds 100 columns
#1926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1902:
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1903:
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae

WARNING: line length of 105 exceeds 100 columns
#1928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1904:
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1905:
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af

WARNING: line length of 105 exceeds 100 columns
#1930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1906:
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1907:
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0

WARNING: line length of 105 exceeds 100 columns
#1932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1908:
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1909:
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1

WARNING: line length of 105 exceeds 100 columns
#1934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1910:
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1911:
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2

WARNING: line length of 105 exceeds 100 columns
#1936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1912:
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1913:
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3

WARNING: line length of 105 exceeds 100 columns
#1938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1914:
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1915:
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4

WARNING: line length of 105 exceeds 100 columns
#1940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1916:
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1917:
+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5

WARNING: line length of 105 exceeds 100 columns
#1942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1918:
+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1919:
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6

WARNING: line length of 105 exceeds 100 columns
#1944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1920:
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1921:
+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7

WARNING: line length of 105 exceeds 100 columns
#1946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1922:
+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1923:
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8

WARNING: line length of 105 exceeds 100 columns
#1948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1924:
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1925:
+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9

WARNING: line length of 105 exceeds 100 columns
#1950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1926:
+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1927:
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba

WARNING: line length of 105 exceeds 100 columns
#1952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1928:
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1929:
+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb

WARNING: line length of 105 exceeds 100 columns
#1954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1930:
+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1931:
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc

WARNING: line length of 105 exceeds 100 columns
#1956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1932:
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1933:
+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd

WARNING: line length of 105 exceeds 100 columns
#1958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1934:
+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1935:
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be

WARNING: line length of 105 exceeds 100 columns
#1960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1936:
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1937:
+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf

WARNING: line length of 105 exceeds 100 columns
#1962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1938:
+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1939:
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0

WARNING: line length of 105 exceeds 100 columns
#1964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1940:
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1941:
+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1

WARNING: line length of 105 exceeds 100 columns
#1966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1942:
+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1943:
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2

WARNING: line length of 105 exceeds 100 columns
#1968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1944:
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1945:
+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3

WARNING: line length of 105 exceeds 100 columns
#1970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1946:
+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#1971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1947:
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4

WARNING: line length of 105 exceeds 100 columns
#1972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1948:
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#1973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1949:
+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5

WARNING: line length of 105 exceeds 100 columns
#1974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1950:
+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#1975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1951:
+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6

WARNING: line length of 105 exceeds 100 columns
#1976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1952:
+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#1977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1953:
+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7

WARNING: line length of 105 exceeds 100 columns
#1978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1954:
+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#1979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1955:
+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8

WARNING: line length of 105 exceeds 100 columns
#1980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1956:
+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#1981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1957:
+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9

WARNING: line length of 105 exceeds 100 columns
#1982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1958:
+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#1983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1959:
+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca

WARNING: line length of 105 exceeds 100 columns
#1984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1960:
+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1961:
+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb

WARNING: line length of 105 exceeds 100 columns
#1986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1962:
+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#1987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1963:
+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc

WARNING: line length of 105 exceeds 100 columns
#1988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1964:
+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#1989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1965:
+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd

WARNING: line length of 105 exceeds 100 columns
#1990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1966:
+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#1991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1967:
+#define regDMCUB_SEC_CNTL                                                                               0x01ce

WARNING: line length of 105 exceeds 100 columns
#1992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1968:
+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#1993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1969:
+#define regDMCUB_MEM_CNTL                                                                               0x01cf

WARNING: line length of 105 exceeds 100 columns
#1994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1970:
+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#1995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1971:
+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0

WARNING: line length of 105 exceeds 100 columns
#1996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1972:
+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#1997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1973:
+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1

WARNING: line length of 105 exceeds 100 columns
#1998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1974:
+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#1999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1975:
+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2

WARNING: line length of 105 exceeds 100 columns
#2000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1976:
+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1977:
+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3

WARNING: line length of 105 exceeds 100 columns
#2002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1978:
+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1979:
+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4

WARNING: line length of 105 exceeds 100 columns
#2004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1980:
+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1981:
+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5

WARNING: line length of 105 exceeds 100 columns
#2006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1982:
+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1983:
+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6

WARNING: line length of 105 exceeds 100 columns
#2008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1984:
+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1985:
+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7

WARNING: line length of 105 exceeds 100 columns
#2010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1986:
+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1987:
+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8

WARNING: line length of 105 exceeds 100 columns
#2012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1988:
+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1989:
+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9

WARNING: line length of 105 exceeds 100 columns
#2014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1990:
+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1991:
+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da

WARNING: line length of 105 exceeds 100 columns
#2016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1992:
+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1993:
+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db

WARNING: line length of 105 exceeds 100 columns
#2018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1994:
+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1995:
+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc

WARNING: line length of 105 exceeds 100 columns
#2020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1996:
+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1997:
+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd

WARNING: line length of 105 exceeds 100 columns
#2022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1998:
+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:1999:
+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de

WARNING: line length of 105 exceeds 100 columns
#2024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2000:
+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2001:
+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df

WARNING: line length of 105 exceeds 100 columns
#2026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2002:
+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2003:
+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0

WARNING: line length of 105 exceeds 100 columns
#2028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2004:
+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2005:
+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1

WARNING: line length of 105 exceeds 100 columns
#2030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2006:
+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2007:
+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2

WARNING: line length of 105 exceeds 100 columns
#2032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2008:
+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2009:
+#define regDMCUB_SCRATCH0                                                                               0x01e3

WARNING: line length of 105 exceeds 100 columns
#2034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2010:
+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2011:
+#define regDMCUB_SCRATCH1                                                                               0x01e4

WARNING: line length of 105 exceeds 100 columns
#2036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2012:
+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2013:
+#define regDMCUB_SCRATCH2                                                                               0x01e5

WARNING: line length of 105 exceeds 100 columns
#2038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2014:
+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2015:
+#define regDMCUB_SCRATCH3                                                                               0x01e6

WARNING: line length of 105 exceeds 100 columns
#2040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2016:
+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2017:
+#define regDMCUB_SCRATCH4                                                                               0x01e7

WARNING: line length of 105 exceeds 100 columns
#2042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2018:
+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2019:
+#define regDMCUB_SCRATCH5                                                                               0x01e8

WARNING: line length of 105 exceeds 100 columns
#2044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2020:
+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2021:
+#define regDMCUB_SCRATCH6                                                                               0x01e9

WARNING: line length of 105 exceeds 100 columns
#2046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2022:
+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2023:
+#define regDMCUB_SCRATCH7                                                                               0x01ea

WARNING: line length of 105 exceeds 100 columns
#2048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2024:
+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2025:
+#define regDMCUB_SCRATCH8                                                                               0x01eb

WARNING: line length of 105 exceeds 100 columns
#2050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2026:
+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2027:
+#define regDMCUB_SCRATCH9                                                                               0x01ec

WARNING: line length of 105 exceeds 100 columns
#2052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2028:
+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2029:
+#define regDMCUB_SCRATCH10                                                                              0x01ed

WARNING: line length of 105 exceeds 100 columns
#2054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2030:
+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2031:
+#define regDMCUB_SCRATCH11                                                                              0x01ee

WARNING: line length of 105 exceeds 100 columns
#2056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2032:
+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2033:
+#define regDMCUB_SCRATCH12                                                                              0x01ef

WARNING: line length of 105 exceeds 100 columns
#2058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2034:
+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2035:
+#define regDMCUB_SCRATCH13                                                                              0x01f0

WARNING: line length of 105 exceeds 100 columns
#2060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2036:
+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2037:
+#define regDMCUB_SCRATCH14                                                                              0x01f1

WARNING: line length of 105 exceeds 100 columns
#2062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2038:
+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2039:
+#define regDMCUB_SCRATCH15                                                                              0x01f2

WARNING: line length of 105 exceeds 100 columns
#2064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2040:
+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2041:
+#define regDMCUB_SCRATCH16                                                                              0x01f3

WARNING: line length of 105 exceeds 100 columns
#2066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2042:
+#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2043:
+#define regDMCUB_SCRATCH17                                                                              0x01f4

WARNING: line length of 105 exceeds 100 columns
#2068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2044:
+#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2045:
+#define regDMCUB_SCRATCH18                                                                              0x01f5

WARNING: line length of 105 exceeds 100 columns
#2070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2046:
+#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2047:
+#define regDMCUB_CNTL                                                                                   0x01f6

WARNING: line length of 105 exceeds 100 columns
#2072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2048:
+#define regDMCUB_CNTL_BASE_IDX                                                                          2

WARNING: line length of 110 exceeds 100 columns
#2073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2049:
+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7

WARNING: line length of 105 exceeds 100 columns
#2074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2050:
+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2051:
+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8

WARNING: line length of 105 exceeds 100 columns
#2076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2052:
+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2053:
+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9

WARNING: line length of 105 exceeds 100 columns
#2078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2054:
+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2055:
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa

WARNING: line length of 105 exceeds 100 columns
#2080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2056:
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#2081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2057:
+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb

WARNING: line length of 105 exceeds 100 columns
#2082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2058:
+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2059:
+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc

WARNING: line length of 105 exceeds 100 columns
#2084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2060:
+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2061:
+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd

WARNING: line length of 105 exceeds 100 columns
#2086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2062:
+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2063:
+#define regDMCUB_PROC_ID                                                                                0x01ff

WARNING: line length of 105 exceeds 100 columns
#2088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2064:
+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#2089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2065:
+#define regDMCUB_CNTL2                                                                                  0x0200

WARNING: line length of 105 exceeds 100 columns
#2090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2066:
+#define regDMCUB_CNTL2_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#2091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2067:
+#define regDMCUB_GPINT_DATAIN2                                                                          0x0215

WARNING: line length of 105 exceeds 100 columns
#2092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2068:
+#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2069:
+#define regDMCUB_GPINT_DATAIN3                                                                          0x0216

WARNING: line length of 105 exceeds 100 columns
#2094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2070:
+#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2071:
+#define regDMCUB_GPINT_DATAIN4                                                                          0x0217

WARNING: line length of 105 exceeds 100 columns
#2096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2072:
+#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2073:
+#define regDMCUB_GPINT_DATAIN5                                                                          0x0218

WARNING: line length of 105 exceeds 100 columns
#2098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2074:
+#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2075:
+#define regDMCUB_GPINT_DATAIN6                                                                          0x0219

WARNING: line length of 105 exceeds 100 columns
#2100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2076:
+#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2077:
+#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a

WARNING: line length of 105 exceeds 100 columns
#2102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2078:
+#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2079:
+#define regDMCUB_SCRATCH19                                                                              0x022e

WARNING: line length of 105 exceeds 100 columns
#2104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2080:
+#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2081:
+#define regDMCUB_SCRATCH20                                                                              0x022f

WARNING: line length of 105 exceeds 100 columns
#2106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2082:
+#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2083:
+#define regDMCUB_SCRATCH21                                                                              0x0230

WARNING: line length of 105 exceeds 100 columns
#2108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2084:
+#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2085:
+#define regDMCUB_SCRATCH22                                                                              0x0231

WARNING: line length of 105 exceeds 100 columns
#2110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2086:
+#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2087:
+#define regDMCUB_SCRATCH23                                                                              0x0232

WARNING: line length of 105 exceeds 100 columns
#2112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2088:
+#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2093:
+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272

WARNING: line length of 105 exceeds 100 columns
#2118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2094:
+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2095:
+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274

WARNING: line length of 105 exceeds 100 columns
#2120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2096:
+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2097:
+#define regMCIF_WB_BUF_PITCH                                                                            0x0275

WARNING: line length of 105 exceeds 100 columns
#2122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2098:
+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2099:
+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276

WARNING: line length of 105 exceeds 100 columns
#2124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2100:
+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2101:
+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277

WARNING: line length of 105 exceeds 100 columns
#2126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2102:
+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2103:
+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278

WARNING: line length of 105 exceeds 100 columns
#2128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2104:
+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2105:
+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279

WARNING: line length of 105 exceeds 100 columns
#2130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2106:
+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2107:
+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a

WARNING: line length of 105 exceeds 100 columns
#2132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2108:
+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2109:
+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b

WARNING: line length of 105 exceeds 100 columns
#2134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2110:
+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2111:
+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c

WARNING: line length of 105 exceeds 100 columns
#2136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2112:
+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2113:
+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d

WARNING: line length of 105 exceeds 100 columns
#2138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2114:
+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2115:
+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e

WARNING: line length of 105 exceeds 100 columns
#2140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2116:
+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2117:
+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f

WARNING: line length of 105 exceeds 100 columns
#2142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2118:
+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2119:
+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282

WARNING: line length of 105 exceeds 100 columns
#2144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2120:
+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2121:
+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284

WARNING: line length of 105 exceeds 100 columns
#2146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2122:
+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2123:
+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286

WARNING: line length of 105 exceeds 100 columns
#2148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2124:
+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2125:
+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288

WARNING: line length of 105 exceeds 100 columns
#2150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2126:
+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2127:
+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a

WARNING: line length of 105 exceeds 100 columns
#2152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2128:
+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2129:
+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c

WARNING: line length of 105 exceeds 100 columns
#2154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2130:
+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2131:
+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e

WARNING: line length of 105 exceeds 100 columns
#2156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2132:
+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2133:
+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290

WARNING: line length of 105 exceeds 100 columns
#2158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2134:
+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2135:
+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292

WARNING: line length of 105 exceeds 100 columns
#2160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2136:
+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2137:
+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293

WARNING: line length of 105 exceeds 100 columns
#2162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2138:
+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2139:
+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294

WARNING: line length of 105 exceeds 100 columns
#2164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2140:
+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2141:
+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296

WARNING: line length of 105 exceeds 100 columns
#2166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2142:
+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2143:
+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297

WARNING: line length of 105 exceeds 100 columns
#2168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2144:
+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2145:
+#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298

WARNING: line length of 105 exceeds 100 columns
#2170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2146:
+#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2147:
+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299

WARNING: line length of 105 exceeds 100 columns
#2172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2148:
+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2149:
+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a

WARNING: line length of 105 exceeds 100 columns
#2174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2150:
+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2151:
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b

WARNING: line length of 105 exceeds 100 columns
#2176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2152:
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2153:
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c

WARNING: line length of 105 exceeds 100 columns
#2178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2154:
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2155:
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d

WARNING: line length of 105 exceeds 100 columns
#2180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2156:
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2157:
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e

WARNING: line length of 105 exceeds 100 columns
#2182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2158:
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2159:
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f

WARNING: line length of 105 exceeds 100 columns
#2184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2160:
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2161:
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0

WARNING: line length of 105 exceeds 100 columns
#2186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2162:
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2163:
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1

WARNING: line length of 105 exceeds 100 columns
#2188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2164:
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2165:
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2

WARNING: line length of 105 exceeds 100 columns
#2190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2166:
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2167:
+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3

WARNING: line length of 105 exceeds 100 columns
#2192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2168:
+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2169:
+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4

WARNING: line length of 105 exceeds 100 columns
#2194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2170:
+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2171:
+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5

WARNING: line length of 105 exceeds 100 columns
#2196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2172:
+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2173:
+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6

WARNING: line length of 105 exceeds 100 columns
#2198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2174:
+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2175:
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7

WARNING: line length of 105 exceeds 100 columns
#2200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2176:
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#2201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2177:
+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8

WARNING: line length of 105 exceeds 100 columns
#2202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2178:
+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2179:
+#define regMCIF_WB_MIN_TTO                                                                              0x02a9

WARNING: line length of 105 exceeds 100 columns
#2204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2180:
+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2185:
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa

WARNING: line length of 105 exceeds 100 columns
#2210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2186:
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#2211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2187:
+#define regMCIF_WB_WATERMARK                                                                            0x02ab

WARNING: line length of 105 exceeds 100 columns
#2212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2188:
+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2189:
+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac

WARNING: line length of 105 exceeds 100 columns
#2214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2190:
+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2191:
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad

WARNING: line length of 105 exceeds 100 columns
#2216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2192:
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2193:
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae

WARNING: line length of 105 exceeds 100 columns
#2218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2194:
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2195:
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af

WARNING: line length of 105 exceeds 100 columns
#2220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2196:
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2197:
+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0

WARNING: line length of 105 exceeds 100 columns
#2222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2198:
+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2199:
+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1

WARNING: line length of 105 exceeds 100 columns
#2224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2200:
+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#2225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2201:
+#define regMMHUBBUB_CTRL                                                                                0x0333

WARNING: line length of 105 exceeds 100 columns
#2226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2202:
+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#2227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2203:
+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334

WARNING: line length of 105 exceeds 100 columns
#2228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2204:
+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2205:
+#define regWBIF0_MISC_CTRL                                                                              0x0335

WARNING: line length of 105 exceeds 100 columns
#2230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2206:
+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2207:
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336

WARNING: line length of 105 exceeds 100 columns
#2232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2208:
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2209:
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337

WARNING: line length of 105 exceeds 100 columns
#2234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2210:
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2211:
+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e

WARNING: line length of 105 exceeds 100 columns
#2236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2212:
+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2213:
+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f

WARNING: line length of 105 exceeds 100 columns
#2238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2214:
+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2215:
+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0340

WARNING: line length of 105 exceeds 100 columns
#2240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2216:
+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2217:
+#define regMMHUBBUB_SOFT_RESET                                                                          0x0341

WARNING: line length of 105 exceeds 100 columns
#2242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2218:
+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2219:
+#define regDMU_IF_ERR_STATUS                                                                            0x0345

WARNING: line length of 105 exceeds 100 columns
#2244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2220:
+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2221:
+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346

WARNING: line length of 105 exceeds 100 columns
#2246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2222:
+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2223:
+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348

WARNING: line length of 105 exceeds 100 columns
#2248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2224:
+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2229:
+#define regDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352

WARNING: line length of 105 exceeds 100 columns
#2254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2230:
+#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2231:
+#define regDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353

WARNING: line length of 105 exceeds 100 columns
#2256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2232:
+#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2233:
+#define regDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354

WARNING: line length of 105 exceeds 100 columns
#2258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2234:
+#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2235:
+#define regDC_PERFMON4_PERFMON_CNTL                                                                     0x0355

WARNING: line length of 105 exceeds 100 columns
#2260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2236:
+#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2237:
+#define regDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356

WARNING: line length of 105 exceeds 100 columns
#2262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2238:
+#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2239:
+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357

WARNING: line length of 105 exceeds 100 columns
#2264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2240:
+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#2265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2241:
+#define regDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358

WARNING: line length of 105 exceeds 100 columns
#2266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2242:
+#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2243:
+#define regDC_PERFMON4_PERFMON_HI                                                                       0x0359

WARNING: line length of 105 exceeds 100 columns
#2268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2244:
+#define regDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2245:
+#define regDC_PERFMON4_PERFMON_LOW                                                                      0x035a

WARNING: line length of 105 exceeds 100 columns
#2270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2246:
+#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2253:
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e

WARNING: line length of 105 exceeds 100 columns
#2278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2254:
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2255:
+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f

WARNING: line length of 105 exceeds 100 columns
#2280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2256:
+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2261:
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360

WARNING: line length of 105 exceeds 100 columns
#2286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2262:
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2263:
+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361

WARNING: line length of 105 exceeds 100 columns
#2288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2264:
+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2269:
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362

WARNING: line length of 105 exceeds 100 columns
#2294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2270:
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2271:
+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363

WARNING: line length of 105 exceeds 100 columns
#2296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2272:
+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2277:
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364

WARNING: line length of 105 exceeds 100 columns
#2302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2278:
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2279:
+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365

WARNING: line length of 105 exceeds 100 columns
#2304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2280:
+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2285:
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366

WARNING: line length of 105 exceeds 100 columns
#2310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2286:
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2287:
+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367

WARNING: line length of 105 exceeds 100 columns
#2312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2288:
+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2293:
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368

WARNING: line length of 105 exceeds 100 columns
#2318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2294:
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2295:
+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369

WARNING: line length of 105 exceeds 100 columns
#2320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2296:
+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2301:
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a

WARNING: line length of 105 exceeds 100 columns
#2326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2302:
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2303:
+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b

WARNING: line length of 105 exceeds 100 columns
#2328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2304:
+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2309:
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c

WARNING: line length of 105 exceeds 100 columns
#2334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2310:
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2311:
+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d

WARNING: line length of 105 exceeds 100 columns
#2336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2312:
+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2317:
+#define regAZ_CLOCK_CNTL                                                                                0x0372

WARNING: line length of 105 exceeds 100 columns
#2342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2318:
+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#2343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2319:
+#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0373

WARNING: line length of 105 exceeds 100 columns
#2344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2320:
+#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2324:
+#define regDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a

WARNING: line length of 105 exceeds 100 columns
#2349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2325:
+#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2326:
+#define regDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b

WARNING: line length of 105 exceeds 100 columns
#2351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2327:
+#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2328:
+#define regDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c

WARNING: line length of 105 exceeds 100 columns
#2353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2329:
+#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2330:
+#define regDC_PERFMON5_PERFMON_CNTL                                                                     0x037d

WARNING: line length of 105 exceeds 100 columns
#2355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2331:
+#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2332:
+#define regDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e

WARNING: line length of 105 exceeds 100 columns
#2357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2333:
+#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2334:
+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f

WARNING: line length of 105 exceeds 100 columns
#2359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2335:
+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#2360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2336:
+#define regDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380

WARNING: line length of 105 exceeds 100 columns
#2361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2337:
+#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2338:
+#define regDC_PERFMON5_PERFMON_HI                                                                       0x0381

WARNING: line length of 105 exceeds 100 columns
#2363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2339:
+#define regDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2340:
+#define regDC_PERFMON5_PERFMON_LOW                                                                      0x0382

WARNING: line length of 105 exceeds 100 columns
#2365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2341:
+#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2347:
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386

WARNING: line length of 105 exceeds 100 columns
#2372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2348:
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2349:
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387

WARNING: line length of 105 exceeds 100 columns
#2374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2350:
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2355:
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c

WARNING: line length of 105 exceeds 100 columns
#2380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2356:
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2357:
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d

WARNING: line length of 105 exceeds 100 columns
#2382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2358:
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2363:
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392

WARNING: line length of 105 exceeds 100 columns
#2388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2364:
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2365:
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393

WARNING: line length of 105 exceeds 100 columns
#2390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2366:
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2371:
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398

WARNING: line length of 105 exceeds 100 columns
#2396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2372:
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2373:
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399

WARNING: line length of 105 exceeds 100 columns
#2398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2374:
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2379:
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e

WARNING: line length of 105 exceeds 100 columns
#2404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2380:
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2381:
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f

WARNING: line length of 105 exceeds 100 columns
#2406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2382:
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2387:
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4

WARNING: line length of 105 exceeds 100 columns
#2412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2388:
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2389:
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5

WARNING: line length of 105 exceeds 100 columns
#2414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2390:
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2395:
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa

WARNING: line length of 105 exceeds 100 columns
#2420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2396:
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2397:
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab

WARNING: line length of 105 exceeds 100 columns
#2422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2398:
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2403:
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0

WARNING: line length of 105 exceeds 100 columns
#2428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2404:
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2405:
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1

WARNING: line length of 105 exceeds 100 columns
#2430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2406:
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2411:
+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2

WARNING: line length of 105 exceeds 100 columns
#2436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2412:
+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2413:
+#define regAZALIA_AUDIO_DTO                                                                             0x03c3

WARNING: line length of 105 exceeds 100 columns
#2438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2414:
+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#2439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2415:
+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4

WARNING: line length of 105 exceeds 100 columns
#2440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2416:
+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2417:
+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5

WARNING: line length of 105 exceeds 100 columns
#2442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2418:
+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2419:
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6

WARNING: line length of 105 exceeds 100 columns
#2444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2420:
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2421:
+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7

WARNING: line length of 105 exceeds 100 columns
#2446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2422:
+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2423:
+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8

WARNING: line length of 105 exceeds 100 columns
#2448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2424:
+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2425:
+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9

WARNING: line length of 105 exceeds 100 columns
#2450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2426:
+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2427:
+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca

WARNING: line length of 105 exceeds 100 columns
#2452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2428:
+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2429:
+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3

WARNING: line length of 105 exceeds 100 columns
#2454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2430:
+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2431:
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4

WARNING: line length of 105 exceeds 100 columns
#2456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2432:
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2433:
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5

WARNING: line length of 105 exceeds 100 columns
#2458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2434:
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#2459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2435:
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6

WARNING: line length of 105 exceeds 100 columns
#2460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2436:
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2437:
+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9

WARNING: line length of 105 exceeds 100 columns
#2462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2438:
+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2439:
+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da

WARNING: line length of 105 exceeds 100 columns
#2464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2440:
+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2441:
+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db

WARNING: line length of 105 exceeds 100 columns
#2466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2442:
+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2443:
+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc

WARNING: line length of 105 exceeds 100 columns
#2468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2444:
+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2445:
+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd

WARNING: line length of 105 exceeds 100 columns
#2470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2446:
+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2447:
+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de

WARNING: line length of 105 exceeds 100 columns
#2472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2448:
+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2449:
+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df

WARNING: line length of 105 exceeds 100 columns
#2474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2450:
+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2451:
+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0

WARNING: line length of 105 exceeds 100 columns
#2476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2452:
+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2453:
+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1

WARNING: line length of 105 exceeds 100 columns
#2478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2454:
+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2455:
+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2

WARNING: line length of 105 exceeds 100 columns
#2480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2456:
+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2457:
+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3

WARNING: line length of 105 exceeds 100 columns
#2482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2458:
+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2459:
+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4

WARNING: line length of 105 exceeds 100 columns
#2484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2460:
+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2461:
+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5

WARNING: line length of 105 exceeds 100 columns
#2486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2462:
+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2463:
+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6

WARNING: line length of 105 exceeds 100 columns
#2488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2464:
+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2465:
+#define regAZALIA_CRC0_RESULT                                                                           0x03e7

WARNING: line length of 105 exceeds 100 columns
#2490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2466:
+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2467:
+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8

WARNING: line length of 105 exceeds 100 columns
#2492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2468:
+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2469:
+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9

WARNING: line length of 105 exceeds 100 columns
#2494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2470:
+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2471:
+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea

WARNING: line length of 105 exceeds 100 columns
#2496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2472:
+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2473:
+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb

WARNING: line length of 105 exceeds 100 columns
#2498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2474:
+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2475:
+#define regAZALIA_CRC1_RESULT                                                                           0x03ec

WARNING: line length of 105 exceeds 100 columns
#2500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2476:
+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2477:
+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee

WARNING: line length of 105 exceeds 100 columns
#2502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2478:
+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2479:
+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef

WARNING: line length of 105 exceeds 100 columns
#2504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2480:
+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2486:
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406

WARNING: line length of 105 exceeds 100 columns
#2511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2487:
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#2512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2488:
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407

WARNING: line length of 105 exceeds 100 columns
#2513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2489:
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2490:
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408

WARNING: line length of 105 exceeds 100 columns
#2515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2491:
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#2516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2492:
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409

WARNING: line length of 105 exceeds 100 columns
#2517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2493:
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#2518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2494:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a

WARNING: line length of 105 exceeds 100 columns
#2519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2495:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#2520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2496:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b

WARNING: line length of 105 exceeds 100 columns
#2521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2497:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2498:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c

WARNING: line length of 105 exceeds 100 columns
#2523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2499:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#2524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2500:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d

WARNING: line length of 105 exceeds 100 columns
#2525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2501:
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2

WARNING: line length of 110 exceeds 100 columns
#2526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2502:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e

WARNING: line length of 105 exceeds 100 columns
#2527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2503:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#2528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2504:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f

WARNING: line length of 105 exceeds 100 columns
#2529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2505:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#2530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2506:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410

WARNING: line length of 105 exceeds 100 columns
#2531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2507:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2508:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411

WARNING: line length of 105 exceeds 100 columns
#2533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2509:
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2

WARNING: line length of 110 exceeds 100 columns
#2534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2510:
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412

WARNING: line length of 105 exceeds 100 columns
#2535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2511:
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#2536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2512:
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413

WARNING: line length of 105 exceeds 100 columns
#2537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2513:
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2514:
+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415

WARNING: line length of 105 exceeds 100 columns
#2539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2515:
+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2516:
+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416

WARNING: line length of 105 exceeds 100 columns
#2541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2517:
+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2518:
+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417

WARNING: line length of 105 exceeds 100 columns
#2543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2519:
+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2520:
+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418

WARNING: line length of 105 exceeds 100 columns
#2545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2521:
+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2522:
+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419

WARNING: line length of 105 exceeds 100 columns
#2547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2523:
+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2524:
+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a

WARNING: line length of 105 exceeds 100 columns
#2549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2525:
+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2526:
+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b

WARNING: line length of 105 exceeds 100 columns
#2551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2527:
+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2528:
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c

WARNING: line length of 105 exceeds 100 columns
#2553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2529:
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2530:
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d

WARNING: line length of 105 exceeds 100 columns
#2555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2531:
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#2561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2537:
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426

WARNING: line length of 105 exceeds 100 columns
#2562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2538:
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2539:
+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427

WARNING: line length of 105 exceeds 100 columns
#2564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2540:
+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2545:
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428

WARNING: line length of 105 exceeds 100 columns
#2570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2546:
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2547:
+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429

WARNING: line length of 105 exceeds 100 columns
#2572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2548:
+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2553:
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a

WARNING: line length of 105 exceeds 100 columns
#2578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2554:
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2555:
+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b

WARNING: line length of 105 exceeds 100 columns
#2580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2556:
+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2561:
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c

WARNING: line length of 105 exceeds 100 columns
#2586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2562:
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2563:
+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d

WARNING: line length of 105 exceeds 100 columns
#2588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2564:
+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2569:
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e

WARNING: line length of 105 exceeds 100 columns
#2594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2570:
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2571:
+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f

WARNING: line length of 105 exceeds 100 columns
#2596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2572:
+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2577:
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430

WARNING: line length of 105 exceeds 100 columns
#2602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2578:
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2579:
+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431

WARNING: line length of 105 exceeds 100 columns
#2604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2580:
+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2585:
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432

WARNING: line length of 105 exceeds 100 columns
#2610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2586:
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2587:
+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433

WARNING: line length of 105 exceeds 100 columns
#2612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2588:
+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2593:
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434

WARNING: line length of 105 exceeds 100 columns
#2618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2594:
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2595:
+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435

WARNING: line length of 105 exceeds 100 columns
#2620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2596:
+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2602:
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a

WARNING: line length of 105 exceeds 100 columns
#2627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2603:
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2604:
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b

WARNING: line length of 105 exceeds 100 columns
#2629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2605:
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2610:
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e

WARNING: line length of 105 exceeds 100 columns
#2635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2611:
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2612:
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f

WARNING: line length of 105 exceeds 100 columns
#2637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2613:
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2618:
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442

WARNING: line length of 105 exceeds 100 columns
#2643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2619:
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2620:
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443

WARNING: line length of 105 exceeds 100 columns
#2645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2621:
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2626:
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446

WARNING: line length of 105 exceeds 100 columns
#2651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2627:
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2628:
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447

WARNING: line length of 105 exceeds 100 columns
#2653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2629:
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2634:
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a

WARNING: line length of 105 exceeds 100 columns
#2659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2635:
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2636:
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b

WARNING: line length of 105 exceeds 100 columns
#2661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2637:
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2642:
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e

WARNING: line length of 105 exceeds 100 columns
#2667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2643:
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2644:
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f

WARNING: line length of 105 exceeds 100 columns
#2669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2645:
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2650:
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452

WARNING: line length of 105 exceeds 100 columns
#2675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2651:
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2652:
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453

WARNING: line length of 105 exceeds 100 columns
#2677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2653:
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2658:
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456

WARNING: line length of 105 exceeds 100 columns
#2683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2659:
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2

WARNING: line length of 110 exceeds 100 columns
#2684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2660:
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457

WARNING: line length of 105 exceeds 100 columns
#2685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2661:
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#2691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2667:
+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f

WARNING: line length of 105 exceeds 100 columns
#2692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2668:
+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2669:
+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470

WARNING: line length of 105 exceeds 100 columns
#2694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2670:
+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2671:
+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471

WARNING: line length of 105 exceeds 100 columns
#2696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2672:
+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2673:
+#define regVM_REQUEST_PHYSICAL                                                                          0x0472

WARNING: line length of 105 exceeds 100 columns
#2698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2674:
+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2675:
+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473

WARNING: line length of 105 exceeds 100 columns
#2700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2676:
+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2677:
+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474

WARNING: line length of 105 exceeds 100 columns
#2702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2678:
+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2679:
+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475

WARNING: line length of 105 exceeds 100 columns
#2704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2680:
+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2681:
+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476

WARNING: line length of 105 exceeds 100 columns
#2706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2682:
+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2683:
+#define regDCN_VM_FB_OFFSET                                                                             0x0477

WARNING: line length of 105 exceeds 100 columns
#2708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2684:
+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#2709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2685:
+#define regDCN_VM_AGP_BOT                                                                               0x0478

WARNING: line length of 105 exceeds 100 columns
#2710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2686:
+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2687:
+#define regDCN_VM_AGP_TOP                                                                               0x0479

WARNING: line length of 105 exceeds 100 columns
#2712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2688:
+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#2713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2689:
+#define regDCN_VM_AGP_BASE                                                                              0x047a

WARNING: line length of 105 exceeds 100 columns
#2714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2690:
+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#2715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2691:
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b

WARNING: line length of 105 exceeds 100 columns
#2716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2692:
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2693:
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c

WARNING: line length of 105 exceeds 100 columns
#2718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2694:
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2695:
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d

WARNING: line length of 105 exceeds 100 columns
#2720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2696:
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#2721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2697:
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e

WARNING: line length of 105 exceeds 100 columns
#2722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2698:
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2699:
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f

WARNING: line length of 105 exceeds 100 columns
#2724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2700:
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2701:
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480

WARNING: line length of 105 exceeds 100 columns
#2726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2702:
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#2727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2703:
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481

WARNING: line length of 105 exceeds 100 columns
#2728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2704:
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#2729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2705:
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482

WARNING: line length of 105 exceeds 100 columns
#2730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2706:
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#2731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2707:
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483

WARNING: line length of 105 exceeds 100 columns
#2732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2708:
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#2733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2709:
+#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484

WARNING: line length of 105 exceeds 100 columns
#2734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2710:
+#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2711:
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485

WARNING: line length of 105 exceeds 100 columns
#2736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2712:
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2713:
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486

WARNING: line length of 105 exceeds 100 columns
#2738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2714:
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2719:
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af

WARNING: line length of 105 exceeds 100 columns
#2744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2720:
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2721:
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0

WARNING: line length of 105 exceeds 100 columns
#2746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2722:
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2723:
+#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1

WARNING: line length of 105 exceeds 100 columns
#2748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2724:
+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#2749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2725:
+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2

WARNING: line length of 105 exceeds 100 columns
#2750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2726:
+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2727:
+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3

WARNING: line length of 105 exceeds 100 columns
#2752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2728:
+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2729:
+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4

WARNING: line length of 105 exceeds 100 columns
#2754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2730:
+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2731:
+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5

WARNING: line length of 105 exceeds 100 columns
#2756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2732:
+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2733:
+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6

WARNING: line length of 105 exceeds 100 columns
#2758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2734:
+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2735:
+#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7

WARNING: line length of 105 exceeds 100 columns
#2760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2736:
+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2737:
+#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8

WARNING: line length of 105 exceeds 100 columns
#2762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2738:
+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2739:
+#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9

WARNING: line length of 105 exceeds 100 columns
#2764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2740:
+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2741:
+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba

WARNING: line length of 105 exceeds 100 columns
#2766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2742:
+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2743:
+#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb

WARNING: line length of 105 exceeds 100 columns
#2768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2744:
+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2745:
+#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc

WARNING: line length of 105 exceeds 100 columns
#2770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2746:
+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2747:
+#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd

WARNING: line length of 105 exceeds 100 columns
#2772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2748:
+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2749:
+#define regDCHUBBUB_DET3_CTRL                                                                           0x04be

WARNING: line length of 105 exceeds 100 columns
#2774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2750:
+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#2775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2751:
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0

WARNING: line length of 105 exceeds 100 columns
#2776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2752:
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2753:
+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1

WARNING: line length of 105 exceeds 100 columns
#2778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2754:
+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2755:
+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2

WARNING: line length of 105 exceeds 100 columns
#2780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2756:
+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2757:
+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3

WARNING: line length of 105 exceeds 100 columns
#2782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2758:
+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2759:
+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4

WARNING: line length of 105 exceeds 100 columns
#2784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2760:
+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2761:
+#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5

WARNING: line length of 105 exceeds 100 columns
#2786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2762:
+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#2791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2767:
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9

WARNING: line length of 105 exceeds 100 columns
#2792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2768:
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2769:
+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa

WARNING: line length of 105 exceeds 100 columns
#2794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2770:
+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2771:
+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb

WARNING: line length of 105 exceeds 100 columns
#2796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2772:
+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2773:
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc

WARNING: line length of 105 exceeds 100 columns
#2798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2774:
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2775:
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd

WARNING: line length of 105 exceeds 100 columns
#2800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2776:
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2777:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe

WARNING: line length of 105 exceeds 100 columns
#2802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2778:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#2803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2779:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff

WARNING: line length of 105 exceeds 100 columns
#2804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2780:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2781:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500

WARNING: line length of 105 exceeds 100 columns
#2806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2782:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#2807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2783:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501

WARNING: line length of 105 exceeds 100 columns
#2808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2784:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2785:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A                                                   0x0502

WARNING: line length of 105 exceeds 100 columns
#2810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2786:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2787:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0503

WARNING: line length of 105 exceeds 100 columns
#2812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2788:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#2813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2789:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A                                                    0x0504

WARNING: line length of 105 exceeds 100 columns
#2814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2790:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2791:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0505

WARNING: line length of 105 exceeds 100 columns
#2816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2792:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2793:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0506

WARNING: line length of 105 exceeds 100 columns
#2818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2794:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2795:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0507

WARNING: line length of 105 exceeds 100 columns
#2820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2796:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2797:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0508

WARNING: line length of 105 exceeds 100 columns
#2822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2798:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2799:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0509

WARNING: line length of 105 exceeds 100 columns
#2824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2800:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#2825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2801:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x050a

WARNING: line length of 105 exceeds 100 columns
#2826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2802:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2803:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050b

WARNING: line length of 105 exceeds 100 columns
#2828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2804:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#2829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2805:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050c

WARNING: line length of 105 exceeds 100 columns
#2830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2806:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2807:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B                                                   0x050d

WARNING: line length of 105 exceeds 100 columns
#2832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2808:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2809:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050e

WARNING: line length of 105 exceeds 100 columns
#2834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2810:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#2835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2811:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B                                                    0x050f

WARNING: line length of 105 exceeds 100 columns
#2836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2812:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2813:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x0510

WARNING: line length of 105 exceeds 100 columns
#2838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2814:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2815:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x0511

WARNING: line length of 105 exceeds 100 columns
#2840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2816:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2817:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0512

WARNING: line length of 105 exceeds 100 columns
#2842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2818:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2819:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0513

WARNING: line length of 105 exceeds 100 columns
#2844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2820:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2821:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0514

WARNING: line length of 105 exceeds 100 columns
#2846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2822:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#2847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2823:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0515

WARNING: line length of 105 exceeds 100 columns
#2848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2824:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2825:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0516

WARNING: line length of 105 exceeds 100 columns
#2850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2826:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#2851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2827:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0517

WARNING: line length of 105 exceeds 100 columns
#2852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2828:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2829:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C                                                   0x0518

WARNING: line length of 105 exceeds 100 columns
#2854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2830:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2831:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0519

WARNING: line length of 105 exceeds 100 columns
#2856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2832:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#2857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2833:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C                                                    0x051a

WARNING: line length of 105 exceeds 100 columns
#2858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2834:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2835:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x051b

WARNING: line length of 105 exceeds 100 columns
#2860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2836:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2837:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x051c

WARNING: line length of 105 exceeds 100 columns
#2862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2838:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2839:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x051d

WARNING: line length of 105 exceeds 100 columns
#2864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2840:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2841:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x051e

WARNING: line length of 105 exceeds 100 columns
#2866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2842:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2843:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x051f

WARNING: line length of 105 exceeds 100 columns
#2868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2844:
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#2869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2845:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x0520

WARNING: line length of 105 exceeds 100 columns
#2870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2846:
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2847:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0521

WARNING: line length of 105 exceeds 100 columns
#2872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2848:
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#2873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2849:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x0522

WARNING: line length of 105 exceeds 100 columns
#2874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2850:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#2875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2851:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D                                                   0x0523

WARNING: line length of 105 exceeds 100 columns
#2876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2852:
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2853:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x0524

WARNING: line length of 105 exceeds 100 columns
#2878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2854:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#2879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2855:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D                                                    0x0525

WARNING: line length of 105 exceeds 100 columns
#2880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2856:
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2857:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x0526

WARNING: line length of 105 exceeds 100 columns
#2882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2858:
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2859:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x0527

WARNING: line length of 105 exceeds 100 columns
#2884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2860:
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#2885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2861:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0528

WARNING: line length of 105 exceeds 100 columns
#2886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2862:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2863:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0529

WARNING: line length of 105 exceeds 100 columns
#2888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2864:
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#2889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2865:
+#define regDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x052a

WARNING: line length of 105 exceeds 100 columns
#2890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2866:
+#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2867:
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x052b

WARNING: line length of 105 exceeds 100 columns
#2892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2868:
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#2893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2869:
+#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x052c

WARNING: line length of 105 exceeds 100 columns
#2894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2870:
+#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2871:
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x052d

WARNING: line length of 105 exceeds 100 columns
#2896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2872:
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#2897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2873:
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x052e

WARNING: line length of 105 exceeds 100 columns
#2898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2874:
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2875:
+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x052f

WARNING: line length of 105 exceeds 100 columns
#2900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2876:
+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2877:
+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0530

WARNING: line length of 105 exceeds 100 columns
#2902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2878:
+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2879:
+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0531

WARNING: line length of 105 exceeds 100 columns
#2904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2880:
+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2881:
+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0532

WARNING: line length of 105 exceeds 100 columns
#2906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2882:
+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2883:
+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0533

WARNING: line length of 105 exceeds 100 columns
#2908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2884:
+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2885:
+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0534

WARNING: line length of 105 exceeds 100 columns
#2910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2886:
+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2887:
+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0535

WARNING: line length of 105 exceeds 100 columns
#2912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2888:
+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2889:
+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0536

WARNING: line length of 105 exceeds 100 columns
#2914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2890:
+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#2915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2891:
+#define regVTG0_CONTROL                                                                                 0x0537

WARNING: line length of 105 exceeds 100 columns
#2916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2892:
+#define regVTG0_CONTROL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#2917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2893:
+#define regVTG1_CONTROL                                                                                 0x0538

WARNING: line length of 105 exceeds 100 columns
#2918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2894:
+#define regVTG1_CONTROL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#2919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2895:
+#define regVTG2_CONTROL                                                                                 0x0539

WARNING: line length of 105 exceeds 100 columns
#2920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2896:
+#define regVTG2_CONTROL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#2921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2897:
+#define regVTG3_CONTROL                                                                                 0x053a

WARNING: line length of 105 exceeds 100 columns
#2922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2898:
+#define regVTG3_CONTROL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#2923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2899:
+#define regDCHUBBUB_SOFT_RESET                                                                          0x053b

WARNING: line length of 105 exceeds 100 columns
#2924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2900:
+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2901:
+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x053c

WARNING: line length of 105 exceeds 100 columns
#2926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2902:
+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#2927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2903:
+#define regDCFCLK_CNTL                                                                                  0x053d

WARNING: line length of 105 exceeds 100 columns
#2928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2904:
+#define regDCFCLK_CNTL_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#2929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2905:
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x053e

WARNING: line length of 105 exceeds 100 columns
#2930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2906:
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#2931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2907:
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x053f

WARNING: line length of 105 exceeds 100 columns
#2932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2908:
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#2933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2909:
+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0540

WARNING: line length of 105 exceeds 100 columns
#2934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2910:
+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2911:
+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0541

WARNING: line length of 105 exceeds 100 columns
#2936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2912:
+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2913:
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x0547

WARNING: line length of 105 exceeds 100 columns
#2938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2914:
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2915:
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x0548

WARNING: line length of 105 exceeds 100 columns
#2940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2916:
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#2941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2917:
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0549

WARNING: line length of 105 exceeds 100 columns
#2942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2918:
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#2943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2919:
+#define regFMON_CTRL                                                                                    0x054a

WARNING: line length of 105 exceeds 100 columns
#2944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2920:
+#define regFMON_CTRL_BASE_IDX                                                                           2

WARNING: line length of 110 exceeds 100 columns
#2945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2921:
+#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x054b

WARNING: line length of 105 exceeds 100 columns
#2946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2922:
+#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2923:
+#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x054c

WARNING: line length of 105 exceeds 100 columns
#2948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2924:
+#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2928:
+#define regDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d

WARNING: line length of 105 exceeds 100 columns
#2953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2929:
+#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#2954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2930:
+#define regDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e

WARNING: line length of 105 exceeds 100 columns
#2955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2931:
+#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2932:
+#define regDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f

WARNING: line length of 105 exceeds 100 columns
#2957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2933:
+#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#2958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2934:
+#define regDC_PERFMON6_PERFMON_CNTL                                                                     0x0550

WARNING: line length of 105 exceeds 100 columns
#2959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2935:
+#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#2960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2936:
+#define regDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551

WARNING: line length of 105 exceeds 100 columns
#2961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2937:
+#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#2962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2938:
+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552

WARNING: line length of 105 exceeds 100 columns
#2963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2939:
+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#2964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2940:
+#define regDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553

WARNING: line length of 105 exceeds 100 columns
#2965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2941:
+#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#2966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2942:
+#define regDC_PERFMON6_PERFMON_HI                                                                       0x0554

WARNING: line length of 105 exceeds 100 columns
#2967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2943:
+#define regDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#2968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2944:
+#define regDC_PERFMON6_PERFMON_LOW                                                                      0x0555

WARNING: line length of 105 exceeds 100 columns
#2969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2945:
+#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#2974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2950:
+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559

WARNING: line length of 105 exceeds 100 columns
#2975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2951:
+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2952:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a

WARNING: line length of 105 exceeds 100 columns
#2977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2953:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2954:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b

WARNING: line length of 105 exceeds 100 columns
#2979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2955:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2956:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c

WARNING: line length of 105 exceeds 100 columns
#2981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2957:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2958:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d

WARNING: line length of 105 exceeds 100 columns
#2983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2959:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2960:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e

WARNING: line length of 105 exceeds 100 columns
#2985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2961:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#2986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2962:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f

WARNING: line length of 105 exceeds 100 columns
#2987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2963:
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#2988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2964:
+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560

WARNING: line length of 105 exceeds 100 columns
#2989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2965:
+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#2990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2966:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561

WARNING: line length of 105 exceeds 100 columns
#2991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2967:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2968:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562

WARNING: line length of 105 exceeds 100 columns
#2993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2969:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#2994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2970:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563

WARNING: line length of 105 exceeds 100 columns
#2995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2971:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2972:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564

WARNING: line length of 105 exceeds 100 columns
#2997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2973:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#2998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2974:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565

WARNING: line length of 105 exceeds 100 columns
#2999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2975:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2976:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566

WARNING: line length of 105 exceeds 100 columns
#3001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2977:
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2978:
+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567

WARNING: line length of 105 exceeds 100 columns
#3003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2979:
+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2980:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568

WARNING: line length of 105 exceeds 100 columns
#3005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2981:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2982:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569

WARNING: line length of 105 exceeds 100 columns
#3007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2983:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2984:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a

WARNING: line length of 105 exceeds 100 columns
#3009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2985:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2986:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b

WARNING: line length of 105 exceeds 100 columns
#3011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2987:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2988:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c

WARNING: line length of 105 exceeds 100 columns
#3013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2989:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2990:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d

WARNING: line length of 105 exceeds 100 columns
#3015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2991:
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2992:
+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e

WARNING: line length of 105 exceeds 100 columns
#3017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2993:
+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2994:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f

WARNING: line length of 105 exceeds 100 columns
#3019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2995:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2996:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570

WARNING: line length of 105 exceeds 100 columns
#3021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2997:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2998:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571

WARNING: line length of 105 exceeds 100 columns
#3023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:2999:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3000:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572

WARNING: line length of 105 exceeds 100 columns
#3025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3001:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3002:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573

WARNING: line length of 105 exceeds 100 columns
#3027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3003:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3004:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574

WARNING: line length of 105 exceeds 100 columns
#3029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3005:
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3006:
+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575

WARNING: line length of 105 exceeds 100 columns
#3031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3007:
+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3008:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576

WARNING: line length of 105 exceeds 100 columns
#3033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3009:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3010:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577

WARNING: line length of 105 exceeds 100 columns
#3035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3011:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3012:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578

WARNING: line length of 105 exceeds 100 columns
#3037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3013:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3014:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579

WARNING: line length of 105 exceeds 100 columns
#3039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3015:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3016:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a

WARNING: line length of 105 exceeds 100 columns
#3041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3017:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3018:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b

WARNING: line length of 105 exceeds 100 columns
#3043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3019:
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3020:
+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c

WARNING: line length of 105 exceeds 100 columns
#3045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3021:
+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3022:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d

WARNING: line length of 105 exceeds 100 columns
#3047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3023:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3024:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e

WARNING: line length of 105 exceeds 100 columns
#3049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3025:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3026:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f

WARNING: line length of 105 exceeds 100 columns
#3051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3027:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3028:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580

WARNING: line length of 105 exceeds 100 columns
#3053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3029:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3030:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581

WARNING: line length of 105 exceeds 100 columns
#3055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3031:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3032:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582

WARNING: line length of 105 exceeds 100 columns
#3057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3033:
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3034:
+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583

WARNING: line length of 105 exceeds 100 columns
#3059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3035:
+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3036:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584

WARNING: line length of 105 exceeds 100 columns
#3061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3037:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3038:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585

WARNING: line length of 105 exceeds 100 columns
#3063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3039:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3040:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586

WARNING: line length of 105 exceeds 100 columns
#3065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3041:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3042:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587

WARNING: line length of 105 exceeds 100 columns
#3067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3043:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3044:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588

WARNING: line length of 105 exceeds 100 columns
#3069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3045:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3046:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589

WARNING: line length of 105 exceeds 100 columns
#3071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3047:
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3048:
+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a

WARNING: line length of 105 exceeds 100 columns
#3073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3049:
+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3050:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b

WARNING: line length of 105 exceeds 100 columns
#3075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3051:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3052:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c

WARNING: line length of 105 exceeds 100 columns
#3077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3053:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3054:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d

WARNING: line length of 105 exceeds 100 columns
#3079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3055:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3056:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e

WARNING: line length of 105 exceeds 100 columns
#3081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3057:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3058:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f

WARNING: line length of 105 exceeds 100 columns
#3083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3059:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3060:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590

WARNING: line length of 105 exceeds 100 columns
#3085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3061:
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3062:
+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591

WARNING: line length of 105 exceeds 100 columns
#3087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3063:
+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3064:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592

WARNING: line length of 105 exceeds 100 columns
#3089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3065:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3066:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593

WARNING: line length of 105 exceeds 100 columns
#3091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3067:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3068:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594

WARNING: line length of 105 exceeds 100 columns
#3093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3069:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3070:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595

WARNING: line length of 105 exceeds 100 columns
#3095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3071:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3072:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596

WARNING: line length of 105 exceeds 100 columns
#3097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3073:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3074:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597

WARNING: line length of 105 exceeds 100 columns
#3099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3075:
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3076:
+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598

WARNING: line length of 105 exceeds 100 columns
#3101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3077:
+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#3102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3078:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599

WARNING: line length of 105 exceeds 100 columns
#3103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3079:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3080:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a

WARNING: line length of 105 exceeds 100 columns
#3105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3081:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3082:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b

WARNING: line length of 105 exceeds 100 columns
#3107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3083:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3084:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c

WARNING: line length of 105 exceeds 100 columns
#3109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3085:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3086:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d

WARNING: line length of 105 exceeds 100 columns
#3111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3087:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3088:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e

WARNING: line length of 105 exceeds 100 columns
#3113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3089:
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3090:
+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f

WARNING: line length of 105 exceeds 100 columns
#3115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3091:
+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3092:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0

WARNING: line length of 105 exceeds 100 columns
#3117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3093:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3094:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1

WARNING: line length of 105 exceeds 100 columns
#3119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3095:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3096:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2

WARNING: line length of 105 exceeds 100 columns
#3121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3097:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3098:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3

WARNING: line length of 105 exceeds 100 columns
#3123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3099:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3100:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4

WARNING: line length of 105 exceeds 100 columns
#3125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3101:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3102:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5

WARNING: line length of 105 exceeds 100 columns
#3127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3103:
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3104:
+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6

WARNING: line length of 105 exceeds 100 columns
#3129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3105:
+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3106:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7

WARNING: line length of 105 exceeds 100 columns
#3131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3107:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3108:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8

WARNING: line length of 105 exceeds 100 columns
#3133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3109:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3110:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9

WARNING: line length of 105 exceeds 100 columns
#3135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3111:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3112:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa

WARNING: line length of 105 exceeds 100 columns
#3137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3113:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3114:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab

WARNING: line length of 105 exceeds 100 columns
#3139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3115:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3116:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac

WARNING: line length of 105 exceeds 100 columns
#3141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3117:
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3118:
+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad

WARNING: line length of 105 exceeds 100 columns
#3143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3119:
+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3120:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae

WARNING: line length of 105 exceeds 100 columns
#3145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3121:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3122:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af

WARNING: line length of 105 exceeds 100 columns
#3147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3123:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3124:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0

WARNING: line length of 105 exceeds 100 columns
#3149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3125:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3126:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1

WARNING: line length of 105 exceeds 100 columns
#3151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3127:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3128:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2

WARNING: line length of 105 exceeds 100 columns
#3153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3129:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3130:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3

WARNING: line length of 105 exceeds 100 columns
#3155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3131:
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3132:
+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4

WARNING: line length of 105 exceeds 100 columns
#3157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3133:
+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3134:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5

WARNING: line length of 105 exceeds 100 columns
#3159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3135:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3136:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6

WARNING: line length of 105 exceeds 100 columns
#3161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3137:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3138:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7

WARNING: line length of 105 exceeds 100 columns
#3163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3139:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3140:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8

WARNING: line length of 105 exceeds 100 columns
#3165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3141:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3142:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9

WARNING: line length of 105 exceeds 100 columns
#3167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3143:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3144:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba

WARNING: line length of 105 exceeds 100 columns
#3169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3145:
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3146:
+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb

WARNING: line length of 105 exceeds 100 columns
#3171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3147:
+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3148:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc

WARNING: line length of 105 exceeds 100 columns
#3173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3149:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3150:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd

WARNING: line length of 105 exceeds 100 columns
#3175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3151:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3152:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be

WARNING: line length of 105 exceeds 100 columns
#3177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3153:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3154:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf

WARNING: line length of 105 exceeds 100 columns
#3179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3155:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3156:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0

WARNING: line length of 105 exceeds 100 columns
#3181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3157:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3158:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1

WARNING: line length of 105 exceeds 100 columns
#3183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3159:
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3160:
+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2

WARNING: line length of 105 exceeds 100 columns
#3185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3161:
+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3162:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3

WARNING: line length of 105 exceeds 100 columns
#3187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3163:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3164:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4

WARNING: line length of 105 exceeds 100 columns
#3189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3165:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#3190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3166:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5

WARNING: line length of 105 exceeds 100 columns
#3191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3167:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3168:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6

WARNING: line length of 105 exceeds 100 columns
#3193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3169:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3170:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7

WARNING: line length of 105 exceeds 100 columns
#3195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3171:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3172:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8

WARNING: line length of 105 exceeds 100 columns
#3197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3173:
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3174:
+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9

WARNING: line length of 105 exceeds 100 columns
#3199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3175:
+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3176:
+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca

WARNING: line length of 105 exceeds 100 columns
#3201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3177:
+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3178:
+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb

WARNING: line length of 105 exceeds 100 columns
#3203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3179:
+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#3204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3180:
+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc

WARNING: line length of 105 exceeds 100 columns
#3205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3181:
+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#3206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3182:
+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd

WARNING: line length of 105 exceeds 100 columns
#3207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3183:
+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3184:
+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce

WARNING: line length of 105 exceeds 100 columns
#3209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3185:
+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3191:
+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5

WARNING: line length of 105 exceeds 100 columns
#3216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3192:
+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3193:
+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6

WARNING: line length of 105 exceeds 100 columns
#3218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3194:
+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3195:
+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7

WARNING: line length of 105 exceeds 100 columns
#3220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3196:
+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3197:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9

WARNING: line length of 105 exceeds 100 columns
#3222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3198:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3199:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea

WARNING: line length of 105 exceeds 100 columns
#3224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3200:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3201:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb

WARNING: line length of 105 exceeds 100 columns
#3226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3202:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3203:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec

WARNING: line length of 105 exceeds 100 columns
#3228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3204:
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3205:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed

WARNING: line length of 105 exceeds 100 columns
#3230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3206:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3207:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee

WARNING: line length of 105 exceeds 100 columns
#3232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3208:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3209:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef

WARNING: line length of 105 exceeds 100 columns
#3234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3210:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3211:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0

WARNING: line length of 105 exceeds 100 columns
#3236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3212:
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3213:
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1

WARNING: line length of 105 exceeds 100 columns
#3238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3214:
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3215:
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2

WARNING: line length of 105 exceeds 100 columns
#3240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3216:
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3217:
+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3

WARNING: line length of 105 exceeds 100 columns
#3242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3218:
+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#3243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3219:
+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4

WARNING: line length of 105 exceeds 100 columns
#3244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3220:
+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#3245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3221:
+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5

WARNING: line length of 105 exceeds 100 columns
#3246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3222:
+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3223:
+#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6

WARNING: line length of 105 exceeds 100 columns
#3248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3224:
+#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3225:
+#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7

WARNING: line length of 105 exceeds 100 columns
#3250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3226:
+#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3227:
+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8

WARNING: line length of 105 exceeds 100 columns
#3252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3228:
+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3229:
+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9

WARNING: line length of 105 exceeds 100 columns
#3254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3230:
+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#3255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3231:
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd

WARNING: line length of 105 exceeds 100 columns
#3256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3232:
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3233:
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe

WARNING: line length of 105 exceeds 100 columns
#3258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3234:
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3235:
+#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff

WARNING: line length of 105 exceeds 100 columns
#3260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3236:
+#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3241:
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607

WARNING: line length of 105 exceeds 100 columns
#3266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3242:
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3243:
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608

WARNING: line length of 105 exceeds 100 columns
#3268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3244:
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3245:
+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609

WARNING: line length of 105 exceeds 100 columns
#3270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3246:
+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3247:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a

WARNING: line length of 105 exceeds 100 columns
#3272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3248:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#3273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3249:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b

WARNING: line length of 105 exceeds 100 columns
#3274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3250:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#3275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3251:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c

WARNING: line length of 105 exceeds 100 columns
#3276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3252:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3253:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d

WARNING: line length of 105 exceeds 100 columns
#3278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3254:
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3255:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e

WARNING: line length of 105 exceeds 100 columns
#3280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3256:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3257:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f

WARNING: line length of 105 exceeds 100 columns
#3282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3258:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3259:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610

WARNING: line length of 105 exceeds 100 columns
#3284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3260:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3261:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611

WARNING: line length of 105 exceeds 100 columns
#3286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3262:
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#3287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3263:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612

WARNING: line length of 105 exceeds 100 columns
#3288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3264:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#3289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3265:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613

WARNING: line length of 105 exceeds 100 columns
#3290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3266:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#3291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3267:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614

WARNING: line length of 105 exceeds 100 columns
#3292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3268:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3269:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615

WARNING: line length of 105 exceeds 100 columns
#3294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3270:
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#3295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3271:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616

WARNING: line length of 105 exceeds 100 columns
#3296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3272:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3273:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617

WARNING: line length of 105 exceeds 100 columns
#3298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3274:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#3299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3275:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618

WARNING: line length of 105 exceeds 100 columns
#3300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3276:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#3301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3277:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619

WARNING: line length of 105 exceeds 100 columns
#3302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3278:
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2

WARNING: line length of 110 exceeds 100 columns
#3303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3279:
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a

WARNING: line length of 105 exceeds 100 columns
#3304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3280:
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3281:
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b

WARNING: line length of 105 exceeds 100 columns
#3306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3282:
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3283:
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c

WARNING: line length of 105 exceeds 100 columns
#3308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3284:
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3285:
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f

WARNING: line length of 105 exceeds 100 columns
#3310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3286:
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#3311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3287:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620

WARNING: line length of 105 exceeds 100 columns
#3312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3288:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3289:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621

WARNING: line length of 105 exceeds 100 columns
#3314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3290:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3291:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622

WARNING: line length of 105 exceeds 100 columns
#3316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3292:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3293:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623

WARNING: line length of 105 exceeds 100 columns
#3318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3294:
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#3319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3295:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624

WARNING: line length of 105 exceeds 100 columns
#3320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3296:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#3321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3297:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625

WARNING: line length of 105 exceeds 100 columns
#3322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3298:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3299:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626

WARNING: line length of 105 exceeds 100 columns
#3324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3300:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3301:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627

WARNING: line length of 105 exceeds 100 columns
#3326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3302:
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#3327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3303:
+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628

WARNING: line length of 105 exceeds 100 columns
#3328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3304:
+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3305:
+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629

WARNING: line length of 105 exceeds 100 columns
#3330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3306:
+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3307:
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a

WARNING: line length of 105 exceeds 100 columns
#3332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3308:
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3309:
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b

WARNING: line length of 105 exceeds 100 columns
#3334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3310:
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3311:
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c

WARNING: line length of 105 exceeds 100 columns
#3336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3312:
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3313:
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d

WARNING: line length of 105 exceeds 100 columns
#3338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3314:
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3315:
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e

WARNING: line length of 105 exceeds 100 columns
#3340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3316:
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3317:
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f

WARNING: line length of 105 exceeds 100 columns
#3342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3318:
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3319:
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630

WARNING: line length of 105 exceeds 100 columns
#3344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3320:
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3321:
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631

WARNING: line length of 105 exceeds 100 columns
#3346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3322:
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3323:
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632

WARNING: line length of 105 exceeds 100 columns
#3348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3324:
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3325:
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633

WARNING: line length of 105 exceeds 100 columns
#3350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3326:
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3327:
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634

WARNING: line length of 105 exceeds 100 columns
#3352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3328:
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3329:
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635

WARNING: line length of 105 exceeds 100 columns
#3354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3330:
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3331:
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642

WARNING: line length of 105 exceeds 100 columns
#3356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3332:
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3333:
+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643

WARNING: line length of 105 exceeds 100 columns
#3358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3334:
+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3335:
+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644

WARNING: line length of 105 exceeds 100 columns
#3360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3336:
+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3337:
+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645

WARNING: line length of 105 exceeds 100 columns
#3362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3338:
+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3339:
+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646

WARNING: line length of 105 exceeds 100 columns
#3364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3340:
+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3341:
+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647

WARNING: line length of 105 exceeds 100 columns
#3366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3342:
+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3343:
+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648

WARNING: line length of 105 exceeds 100 columns
#3368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3344:
+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3345:
+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649

WARNING: line length of 105 exceeds 100 columns
#3370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3346:
+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3347:
+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a

WARNING: line length of 105 exceeds 100 columns
#3372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3348:
+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3349:
+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b

WARNING: line length of 105 exceeds 100 columns
#3374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3350:
+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3351:
+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c

WARNING: line length of 105 exceeds 100 columns
#3376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3352:
+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3353:
+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d

WARNING: line length of 105 exceeds 100 columns
#3378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3354:
+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3355:
+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e

WARNING: line length of 105 exceeds 100 columns
#3380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3356:
+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3357:
+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f

WARNING: line length of 105 exceeds 100 columns
#3382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3358:
+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3359:
+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650

WARNING: line length of 105 exceeds 100 columns
#3384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3360:
+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3361:
+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651

WARNING: line length of 105 exceeds 100 columns
#3386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3362:
+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3363:
+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652

WARNING: line length of 105 exceeds 100 columns
#3388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3364:
+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3365:
+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653

WARNING: line length of 105 exceeds 100 columns
#3390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3366:
+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3367:
+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654

WARNING: line length of 105 exceeds 100 columns
#3392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3368:
+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3369:
+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655

WARNING: line length of 105 exceeds 100 columns
#3394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3370:
+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3371:
+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656

WARNING: line length of 105 exceeds 100 columns
#3396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3372:
+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3373:
+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657

WARNING: line length of 105 exceeds 100 columns
#3398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3374:
+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3375:
+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658

WARNING: line length of 105 exceeds 100 columns
#3400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3376:
+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3377:
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659

WARNING: line length of 105 exceeds 100 columns
#3402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3378:
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3379:
+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a

WARNING: line length of 105 exceeds 100 columns
#3404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3380:
+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3381:
+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b

WARNING: line length of 105 exceeds 100 columns
#3406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3382:
+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3383:
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c

WARNING: line length of 105 exceeds 100 columns
#3408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3384:
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3385:
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d

WARNING: line length of 105 exceeds 100 columns
#3410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3386:
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3387:
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e

WARNING: line length of 105 exceeds 100 columns
#3412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3388:
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3389:
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f

WARNING: line length of 105 exceeds 100 columns
#3414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3390:
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3391:
+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662

WARNING: line length of 105 exceeds 100 columns
#3416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3392:
+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3393:
+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663

WARNING: line length of 105 exceeds 100 columns
#3418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3394:
+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3395:
+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664

WARNING: line length of 105 exceeds 100 columns
#3420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3396:
+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3397:
+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665

WARNING: line length of 105 exceeds 100 columns
#3422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3398:
+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3399:
+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666

WARNING: line length of 105 exceeds 100 columns
#3424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3400:
+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3401:
+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667

WARNING: line length of 105 exceeds 100 columns
#3426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3402:
+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3403:
+#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668

WARNING: line length of 105 exceeds 100 columns
#3428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3404:
+#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3405:
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669

WARNING: line length of 105 exceeds 100 columns
#3430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3406:
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3407:
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a

WARNING: line length of 105 exceeds 100 columns
#3432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3408:
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3409:
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b

WARNING: line length of 105 exceeds 100 columns
#3434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3410:
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3415:
+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c

WARNING: line length of 105 exceeds 100 columns
#3440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3416:
+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3417:
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d

WARNING: line length of 105 exceeds 100 columns
#3442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3418:
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3419:
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e

WARNING: line length of 105 exceeds 100 columns
#3444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3420:
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3421:
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f

WARNING: line length of 105 exceeds 100 columns
#3446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3422:
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3423:
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670

WARNING: line length of 105 exceeds 100 columns
#3448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3424:
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3425:
+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671

WARNING: line length of 105 exceeds 100 columns
#3450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3426:
+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3427:
+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672

WARNING: line length of 105 exceeds 100 columns
#3452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3428:
+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3429:
+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673

WARNING: line length of 105 exceeds 100 columns
#3454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3430:
+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3431:
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674

WARNING: line length of 105 exceeds 100 columns
#3456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3432:
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3433:
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675

WARNING: line length of 105 exceeds 100 columns
#3458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3434:
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3439:
+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678

WARNING: line length of 105 exceeds 100 columns
#3464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3440:
+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3441:
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679

WARNING: line length of 105 exceeds 100 columns
#3466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3442:
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3443:
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a

WARNING: line length of 105 exceeds 100 columns
#3468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3444:
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3445:
+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b

WARNING: line length of 105 exceeds 100 columns
#3470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3446:
+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3447:
+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c

WARNING: line length of 105 exceeds 100 columns
#3472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3448:
+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3449:
+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d

WARNING: line length of 105 exceeds 100 columns
#3474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3450:
+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3451:
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e

WARNING: line length of 105 exceeds 100 columns
#3476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3452:
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3453:
+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f

WARNING: line length of 105 exceeds 100 columns
#3478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3454:
+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3455:
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680

WARNING: line length of 105 exceeds 100 columns
#3480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3456:
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3457:
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681

WARNING: line length of 105 exceeds 100 columns
#3482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3458:
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3459:
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682

WARNING: line length of 105 exceeds 100 columns
#3484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3460:
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3461:
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683

WARNING: line length of 105 exceeds 100 columns
#3486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3462:
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3463:
+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684

WARNING: line length of 105 exceeds 100 columns
#3488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3464:
+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3465:
+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685

WARNING: line length of 105 exceeds 100 columns
#3490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3466:
+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3467:
+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686

WARNING: line length of 105 exceeds 100 columns
#3492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3468:
+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3469:
+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687

WARNING: line length of 105 exceeds 100 columns
#3494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3470:
+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3471:
+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688

WARNING: line length of 105 exceeds 100 columns
#3496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3472:
+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3477:
+#define regDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d

WARNING: line length of 105 exceeds 100 columns
#3502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3478:
+#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3479:
+#define regDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e

WARNING: line length of 105 exceeds 100 columns
#3504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3480:
+#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3481:
+#define regDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f

WARNING: line length of 105 exceeds 100 columns
#3506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3482:
+#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3483:
+#define regDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0

WARNING: line length of 105 exceeds 100 columns
#3508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3484:
+#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3485:
+#define regDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1

WARNING: line length of 105 exceeds 100 columns
#3510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3486:
+#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3487:
+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2

WARNING: line length of 105 exceeds 100 columns
#3512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3488:
+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3489:
+#define regDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3

WARNING: line length of 105 exceeds 100 columns
#3514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3490:
+#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3491:
+#define regDC_PERFMON7_PERFMON_HI                                                                       0x06a4

WARNING: line length of 105 exceeds 100 columns
#3516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3492:
+#define regDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3493:
+#define regDC_PERFMON7_PERFMON_LOW                                                                      0x06a5

WARNING: line length of 105 exceeds 100 columns
#3518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3494:
+#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3499:
+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1

WARNING: line length of 105 exceeds 100 columns
#3524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3500:
+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3501:
+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2

WARNING: line length of 105 exceeds 100 columns
#3526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3502:
+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3503:
+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3

WARNING: line length of 105 exceeds 100 columns
#3528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3504:
+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3505:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5

WARNING: line length of 105 exceeds 100 columns
#3530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3506:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3507:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6

WARNING: line length of 105 exceeds 100 columns
#3532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3508:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3509:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7

WARNING: line length of 105 exceeds 100 columns
#3534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3510:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3511:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8

WARNING: line length of 105 exceeds 100 columns
#3536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3512:
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3513:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9

WARNING: line length of 105 exceeds 100 columns
#3538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3514:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3515:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca

WARNING: line length of 105 exceeds 100 columns
#3540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3516:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3517:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb

WARNING: line length of 105 exceeds 100 columns
#3542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3518:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3519:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc

WARNING: line length of 105 exceeds 100 columns
#3544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3520:
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3521:
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd

WARNING: line length of 105 exceeds 100 columns
#3546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3522:
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3523:
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce

WARNING: line length of 105 exceeds 100 columns
#3548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3524:
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3525:
+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf

WARNING: line length of 105 exceeds 100 columns
#3550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3526:
+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#3551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3527:
+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0

WARNING: line length of 105 exceeds 100 columns
#3552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3528:
+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#3553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3529:
+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1

WARNING: line length of 105 exceeds 100 columns
#3554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3530:
+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3531:
+#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2

WARNING: line length of 105 exceeds 100 columns
#3556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3532:
+#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3533:
+#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3

WARNING: line length of 105 exceeds 100 columns
#3558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3534:
+#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3535:
+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4

WARNING: line length of 105 exceeds 100 columns
#3560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3536:
+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3537:
+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5

WARNING: line length of 105 exceeds 100 columns
#3562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3538:
+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#3563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3539:
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9

WARNING: line length of 105 exceeds 100 columns
#3564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3540:
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3541:
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da

WARNING: line length of 105 exceeds 100 columns
#3566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3542:
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3543:
+#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db

WARNING: line length of 105 exceeds 100 columns
#3568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3544:
+#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3549:
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3

WARNING: line length of 105 exceeds 100 columns
#3574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3550:
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3551:
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4

WARNING: line length of 105 exceeds 100 columns
#3576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3552:
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3553:
+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5

WARNING: line length of 105 exceeds 100 columns
#3578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3554:
+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3555:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6

WARNING: line length of 105 exceeds 100 columns
#3580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3556:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#3581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3557:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7

WARNING: line length of 105 exceeds 100 columns
#3582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3558:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#3583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3559:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8

WARNING: line length of 105 exceeds 100 columns
#3584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3560:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3561:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9

WARNING: line length of 105 exceeds 100 columns
#3586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3562:
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3563:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea

WARNING: line length of 105 exceeds 100 columns
#3588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3564:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3565:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb

WARNING: line length of 105 exceeds 100 columns
#3590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3566:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3567:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec

WARNING: line length of 105 exceeds 100 columns
#3592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3568:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3569:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed

WARNING: line length of 105 exceeds 100 columns
#3594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3570:
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#3595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3571:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee

WARNING: line length of 105 exceeds 100 columns
#3596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3572:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#3597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3573:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef

WARNING: line length of 105 exceeds 100 columns
#3598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3574:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#3599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3575:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0

WARNING: line length of 105 exceeds 100 columns
#3600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3576:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3577:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1

WARNING: line length of 105 exceeds 100 columns
#3602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3578:
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#3603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3579:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2

WARNING: line length of 105 exceeds 100 columns
#3604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3580:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3581:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3

WARNING: line length of 105 exceeds 100 columns
#3606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3582:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#3607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3583:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4

WARNING: line length of 105 exceeds 100 columns
#3608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3584:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#3609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3585:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5

WARNING: line length of 105 exceeds 100 columns
#3610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3586:
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2

WARNING: line length of 110 exceeds 100 columns
#3611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3587:
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6

WARNING: line length of 105 exceeds 100 columns
#3612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3588:
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3589:
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7

WARNING: line length of 105 exceeds 100 columns
#3614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3590:
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3591:
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8

WARNING: line length of 105 exceeds 100 columns
#3616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3592:
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3593:
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb

WARNING: line length of 105 exceeds 100 columns
#3618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3594:
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#3619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3595:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc

WARNING: line length of 105 exceeds 100 columns
#3620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3596:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3597:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd

WARNING: line length of 105 exceeds 100 columns
#3622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3598:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3599:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe

WARNING: line length of 105 exceeds 100 columns
#3624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3600:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3601:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff

WARNING: line length of 105 exceeds 100 columns
#3626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3602:
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#3627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3603:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700

WARNING: line length of 105 exceeds 100 columns
#3628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3604:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#3629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3605:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701

WARNING: line length of 105 exceeds 100 columns
#3630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3606:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3607:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702

WARNING: line length of 105 exceeds 100 columns
#3632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3608:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3609:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703

WARNING: line length of 105 exceeds 100 columns
#3634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3610:
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#3635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3611:
+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704

WARNING: line length of 105 exceeds 100 columns
#3636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3612:
+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3613:
+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705

WARNING: line length of 105 exceeds 100 columns
#3638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3614:
+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3615:
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706

WARNING: line length of 105 exceeds 100 columns
#3640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3616:
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3617:
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707

WARNING: line length of 105 exceeds 100 columns
#3642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3618:
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3619:
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708

WARNING: line length of 105 exceeds 100 columns
#3644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3620:
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3621:
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709

WARNING: line length of 105 exceeds 100 columns
#3646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3622:
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3623:
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a

WARNING: line length of 105 exceeds 100 columns
#3648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3624:
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3625:
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b

WARNING: line length of 105 exceeds 100 columns
#3650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3626:
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3627:
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c

WARNING: line length of 105 exceeds 100 columns
#3652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3628:
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3629:
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d

WARNING: line length of 105 exceeds 100 columns
#3654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3630:
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3631:
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e

WARNING: line length of 105 exceeds 100 columns
#3656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3632:
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3633:
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f

WARNING: line length of 105 exceeds 100 columns
#3658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3634:
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3635:
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710

WARNING: line length of 105 exceeds 100 columns
#3660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3636:
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3637:
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711

WARNING: line length of 105 exceeds 100 columns
#3662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3638:
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3639:
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e

WARNING: line length of 105 exceeds 100 columns
#3664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3640:
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3641:
+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f

WARNING: line length of 105 exceeds 100 columns
#3666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3642:
+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3643:
+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720

WARNING: line length of 105 exceeds 100 columns
#3668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3644:
+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3645:
+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721

WARNING: line length of 105 exceeds 100 columns
#3670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3646:
+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3647:
+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722

WARNING: line length of 105 exceeds 100 columns
#3672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3648:
+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3649:
+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723

WARNING: line length of 105 exceeds 100 columns
#3674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3650:
+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3651:
+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724

WARNING: line length of 105 exceeds 100 columns
#3676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3652:
+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3653:
+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725

WARNING: line length of 105 exceeds 100 columns
#3678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3654:
+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3655:
+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726

WARNING: line length of 105 exceeds 100 columns
#3680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3656:
+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3657:
+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727

WARNING: line length of 105 exceeds 100 columns
#3682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3658:
+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3659:
+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728

WARNING: line length of 105 exceeds 100 columns
#3684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3660:
+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3661:
+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729

WARNING: line length of 105 exceeds 100 columns
#3686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3662:
+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3663:
+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a

WARNING: line length of 105 exceeds 100 columns
#3688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3664:
+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3665:
+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b

WARNING: line length of 105 exceeds 100 columns
#3690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3666:
+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3667:
+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c

WARNING: line length of 105 exceeds 100 columns
#3692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3668:
+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3669:
+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d

WARNING: line length of 105 exceeds 100 columns
#3694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3670:
+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3671:
+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e

WARNING: line length of 105 exceeds 100 columns
#3696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3672:
+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3673:
+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f

WARNING: line length of 105 exceeds 100 columns
#3698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3674:
+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3675:
+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730

WARNING: line length of 105 exceeds 100 columns
#3700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3676:
+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3677:
+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731

WARNING: line length of 105 exceeds 100 columns
#3702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3678:
+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3679:
+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732

WARNING: line length of 105 exceeds 100 columns
#3704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3680:
+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3681:
+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733

WARNING: line length of 105 exceeds 100 columns
#3706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3682:
+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3683:
+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734

WARNING: line length of 105 exceeds 100 columns
#3708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3684:
+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3685:
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735

WARNING: line length of 105 exceeds 100 columns
#3710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3686:
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3687:
+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736

WARNING: line length of 105 exceeds 100 columns
#3712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3688:
+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3689:
+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737

WARNING: line length of 105 exceeds 100 columns
#3714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3690:
+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3691:
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738

WARNING: line length of 105 exceeds 100 columns
#3716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3692:
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3693:
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739

WARNING: line length of 105 exceeds 100 columns
#3718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3694:
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3695:
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a

WARNING: line length of 105 exceeds 100 columns
#3720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3696:
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3697:
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b

WARNING: line length of 105 exceeds 100 columns
#3722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3698:
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3699:
+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e

WARNING: line length of 105 exceeds 100 columns
#3724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3700:
+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3701:
+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f

WARNING: line length of 105 exceeds 100 columns
#3726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3702:
+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3703:
+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740

WARNING: line length of 105 exceeds 100 columns
#3728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3704:
+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3705:
+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741

WARNING: line length of 105 exceeds 100 columns
#3730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3706:
+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3707:
+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742

WARNING: line length of 105 exceeds 100 columns
#3732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3708:
+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3709:
+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743

WARNING: line length of 105 exceeds 100 columns
#3734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3710:
+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3711:
+#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744

WARNING: line length of 105 exceeds 100 columns
#3736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3712:
+#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3713:
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745

WARNING: line length of 105 exceeds 100 columns
#3738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3714:
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3715:
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746

WARNING: line length of 105 exceeds 100 columns
#3740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3716:
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3717:
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747

WARNING: line length of 105 exceeds 100 columns
#3742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3718:
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3723:
+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748

WARNING: line length of 105 exceeds 100 columns
#3748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3724:
+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3725:
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749

WARNING: line length of 105 exceeds 100 columns
#3750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3726:
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3727:
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a

WARNING: line length of 105 exceeds 100 columns
#3752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3728:
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3729:
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b

WARNING: line length of 105 exceeds 100 columns
#3754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3730:
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3731:
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c

WARNING: line length of 105 exceeds 100 columns
#3756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3732:
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3733:
+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d

WARNING: line length of 105 exceeds 100 columns
#3758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3734:
+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3735:
+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e

WARNING: line length of 105 exceeds 100 columns
#3760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3736:
+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3737:
+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f

WARNING: line length of 105 exceeds 100 columns
#3762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3738:
+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3739:
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750

WARNING: line length of 105 exceeds 100 columns
#3764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3740:
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3741:
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751

WARNING: line length of 105 exceeds 100 columns
#3766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3742:
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3747:
+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754

WARNING: line length of 105 exceeds 100 columns
#3772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3748:
+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3749:
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755

WARNING: line length of 105 exceeds 100 columns
#3774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3750:
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#3775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3751:
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756

WARNING: line length of 105 exceeds 100 columns
#3776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3752:
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3753:
+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757

WARNING: line length of 105 exceeds 100 columns
#3778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3754:
+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3755:
+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758

WARNING: line length of 105 exceeds 100 columns
#3780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3756:
+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3757:
+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759

WARNING: line length of 105 exceeds 100 columns
#3782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3758:
+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3759:
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a

WARNING: line length of 105 exceeds 100 columns
#3784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3760:
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3761:
+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b

WARNING: line length of 105 exceeds 100 columns
#3786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3762:
+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3763:
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c

WARNING: line length of 105 exceeds 100 columns
#3788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3764:
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3765:
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d

WARNING: line length of 105 exceeds 100 columns
#3790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3766:
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3767:
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e

WARNING: line length of 105 exceeds 100 columns
#3792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3768:
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3769:
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f

WARNING: line length of 105 exceeds 100 columns
#3794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3770:
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3771:
+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760

WARNING: line length of 105 exceeds 100 columns
#3796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3772:
+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#3797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3773:
+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761

WARNING: line length of 105 exceeds 100 columns
#3798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3774:
+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3775:
+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762

WARNING: line length of 105 exceeds 100 columns
#3800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3776:
+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3777:
+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763

WARNING: line length of 105 exceeds 100 columns
#3802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3778:
+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3779:
+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764

WARNING: line length of 105 exceeds 100 columns
#3804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3780:
+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3785:
+#define regDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779

WARNING: line length of 105 exceeds 100 columns
#3810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3786:
+#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3787:
+#define regDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a

WARNING: line length of 105 exceeds 100 columns
#3812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3788:
+#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3789:
+#define regDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b

WARNING: line length of 105 exceeds 100 columns
#3814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3790:
+#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3791:
+#define regDC_PERFMON8_PERFMON_CNTL                                                                     0x077c

WARNING: line length of 105 exceeds 100 columns
#3816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3792:
+#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3793:
+#define regDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d

WARNING: line length of 105 exceeds 100 columns
#3818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3794:
+#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3795:
+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e

WARNING: line length of 105 exceeds 100 columns
#3820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3796:
+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3797:
+#define regDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f

WARNING: line length of 105 exceeds 100 columns
#3822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3798:
+#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3799:
+#define regDC_PERFMON8_PERFMON_HI                                                                       0x0780

WARNING: line length of 105 exceeds 100 columns
#3824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3800:
+#define regDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3801:
+#define regDC_PERFMON8_PERFMON_LOW                                                                      0x0781

WARNING: line length of 105 exceeds 100 columns
#3826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3802:
+#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3807:
+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d

WARNING: line length of 105 exceeds 100 columns
#3832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3808:
+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3809:
+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e

WARNING: line length of 105 exceeds 100 columns
#3834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3810:
+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3811:
+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f

WARNING: line length of 105 exceeds 100 columns
#3836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3812:
+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3813:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1

WARNING: line length of 105 exceeds 100 columns
#3838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3814:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3815:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2

WARNING: line length of 105 exceeds 100 columns
#3840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3816:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3817:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3

WARNING: line length of 105 exceeds 100 columns
#3842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3818:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3819:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4

WARNING: line length of 105 exceeds 100 columns
#3844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3820:
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3821:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5

WARNING: line length of 105 exceeds 100 columns
#3846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3822:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3823:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6

WARNING: line length of 105 exceeds 100 columns
#3848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3824:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#3849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3825:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7

WARNING: line length of 105 exceeds 100 columns
#3850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3826:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#3851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3827:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8

WARNING: line length of 105 exceeds 100 columns
#3852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3828:
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#3853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3829:
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9

WARNING: line length of 105 exceeds 100 columns
#3854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3830:
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3831:
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa

WARNING: line length of 105 exceeds 100 columns
#3856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3832:
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3833:
+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab

WARNING: line length of 105 exceeds 100 columns
#3858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3834:
+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#3859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3835:
+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac

WARNING: line length of 105 exceeds 100 columns
#3860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3836:
+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#3861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3837:
+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad

WARNING: line length of 105 exceeds 100 columns
#3862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3838:
+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3839:
+#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae

WARNING: line length of 105 exceeds 100 columns
#3864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3840:
+#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3841:
+#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af

WARNING: line length of 105 exceeds 100 columns
#3866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3842:
+#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3843:
+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0

WARNING: line length of 105 exceeds 100 columns
#3868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3844:
+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3845:
+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1

WARNING: line length of 105 exceeds 100 columns
#3870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3846:
+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#3871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3847:
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5

WARNING: line length of 105 exceeds 100 columns
#3872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3848:
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3849:
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6

WARNING: line length of 105 exceeds 100 columns
#3874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3850:
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3851:
+#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7

WARNING: line length of 105 exceeds 100 columns
#3876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3852:
+#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#3881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3857:
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf

WARNING: line length of 105 exceeds 100 columns
#3882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3858:
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3859:
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0

WARNING: line length of 105 exceeds 100 columns
#3884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3860:
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3861:
+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1

WARNING: line length of 105 exceeds 100 columns
#3886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3862:
+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#3887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3863:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2

WARNING: line length of 105 exceeds 100 columns
#3888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3864:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#3889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3865:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3

WARNING: line length of 105 exceeds 100 columns
#3890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3866:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#3891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3867:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4

WARNING: line length of 105 exceeds 100 columns
#3892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3868:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3869:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5

WARNING: line length of 105 exceeds 100 columns
#3894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3870:
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3871:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6

WARNING: line length of 105 exceeds 100 columns
#3896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3872:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3873:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7

WARNING: line length of 105 exceeds 100 columns
#3898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3874:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3875:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8

WARNING: line length of 105 exceeds 100 columns
#3900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3876:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3877:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9

WARNING: line length of 105 exceeds 100 columns
#3902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3878:
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#3903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3879:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca

WARNING: line length of 105 exceeds 100 columns
#3904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3880:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#3905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3881:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb

WARNING: line length of 105 exceeds 100 columns
#3906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3882:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#3907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3883:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc

WARNING: line length of 105 exceeds 100 columns
#3908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3884:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3885:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd

WARNING: line length of 105 exceeds 100 columns
#3910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3886:
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#3911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3887:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce

WARNING: line length of 105 exceeds 100 columns
#3912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3888:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#3913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3889:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf

WARNING: line length of 105 exceeds 100 columns
#3914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3890:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#3915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3891:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0

WARNING: line length of 105 exceeds 100 columns
#3916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3892:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#3917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3893:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1

WARNING: line length of 105 exceeds 100 columns
#3918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3894:
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2

WARNING: line length of 110 exceeds 100 columns
#3919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3895:
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2

WARNING: line length of 105 exceeds 100 columns
#3920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3896:
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3897:
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3

WARNING: line length of 105 exceeds 100 columns
#3922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3898:
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3899:
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4

WARNING: line length of 105 exceeds 100 columns
#3924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3900:
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3901:
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7

WARNING: line length of 105 exceeds 100 columns
#3926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3902:
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#3927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3903:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8

WARNING: line length of 105 exceeds 100 columns
#3928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3904:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#3929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3905:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9

WARNING: line length of 105 exceeds 100 columns
#3930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3906:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#3931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3907:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da

WARNING: line length of 105 exceeds 100 columns
#3932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3908:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#3933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3909:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db

WARNING: line length of 105 exceeds 100 columns
#3934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3910:
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#3935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3911:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc

WARNING: line length of 105 exceeds 100 columns
#3936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3912:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#3937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3913:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd

WARNING: line length of 105 exceeds 100 columns
#3938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3914:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#3939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3915:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de

WARNING: line length of 105 exceeds 100 columns
#3940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3916:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3917:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df

WARNING: line length of 105 exceeds 100 columns
#3942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3918:
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#3943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3919:
+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0

WARNING: line length of 105 exceeds 100 columns
#3944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3920:
+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3921:
+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1

WARNING: line length of 105 exceeds 100 columns
#3946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3922:
+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3923:
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2

WARNING: line length of 105 exceeds 100 columns
#3948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3924:
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3925:
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3

WARNING: line length of 105 exceeds 100 columns
#3950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3926:
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3927:
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4

WARNING: line length of 105 exceeds 100 columns
#3952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3928:
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3929:
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5

WARNING: line length of 105 exceeds 100 columns
#3954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3930:
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3931:
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6

WARNING: line length of 105 exceeds 100 columns
#3956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3932:
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3933:
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7

WARNING: line length of 105 exceeds 100 columns
#3958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3934:
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3935:
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8

WARNING: line length of 105 exceeds 100 columns
#3960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3936:
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3937:
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9

WARNING: line length of 105 exceeds 100 columns
#3962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3938:
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3939:
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea

WARNING: line length of 105 exceeds 100 columns
#3964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3940:
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3941:
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb

WARNING: line length of 105 exceeds 100 columns
#3966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3942:
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#3967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3943:
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec

WARNING: line length of 105 exceeds 100 columns
#3968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3944:
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#3969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3945:
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed

WARNING: line length of 105 exceeds 100 columns
#3970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3946:
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#3971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3947:
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa

WARNING: line length of 105 exceeds 100 columns
#3972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3948:
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#3973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3949:
+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb

WARNING: line length of 105 exceeds 100 columns
#3974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3950:
+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3951:
+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc

WARNING: line length of 105 exceeds 100 columns
#3976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3952:
+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3953:
+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd

WARNING: line length of 105 exceeds 100 columns
#3978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3954:
+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#3979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3955:
+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe

WARNING: line length of 105 exceeds 100 columns
#3980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3956:
+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#3981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3957:
+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff

WARNING: line length of 105 exceeds 100 columns
#3982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3958:
+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3959:
+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800

WARNING: line length of 105 exceeds 100 columns
#3984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3960:
+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3961:
+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801

WARNING: line length of 105 exceeds 100 columns
#3986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3962:
+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3963:
+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802

WARNING: line length of 105 exceeds 100 columns
#3988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3964:
+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3965:
+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803

WARNING: line length of 105 exceeds 100 columns
#3990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3966:
+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3967:
+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804

WARNING: line length of 105 exceeds 100 columns
#3992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3968:
+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3969:
+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805

WARNING: line length of 105 exceeds 100 columns
#3994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3970:
+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#3995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3971:
+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806

WARNING: line length of 105 exceeds 100 columns
#3996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3972:
+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3973:
+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807

WARNING: line length of 105 exceeds 100 columns
#3998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3974:
+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#3999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3975:
+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808

WARNING: line length of 105 exceeds 100 columns
#4000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3976:
+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3977:
+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809

WARNING: line length of 105 exceeds 100 columns
#4002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3978:
+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3979:
+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a

WARNING: line length of 105 exceeds 100 columns
#4004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3980:
+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3981:
+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b

WARNING: line length of 105 exceeds 100 columns
#4006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3982:
+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3983:
+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c

WARNING: line length of 105 exceeds 100 columns
#4008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3984:
+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3985:
+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d

WARNING: line length of 105 exceeds 100 columns
#4010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3986:
+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3987:
+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e

WARNING: line length of 105 exceeds 100 columns
#4012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3988:
+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3989:
+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f

WARNING: line length of 105 exceeds 100 columns
#4014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3990:
+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3991:
+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810

WARNING: line length of 105 exceeds 100 columns
#4016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3992:
+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3993:
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811

WARNING: line length of 105 exceeds 100 columns
#4018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3994:
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3995:
+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812

WARNING: line length of 105 exceeds 100 columns
#4020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3996:
+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3997:
+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813

WARNING: line length of 105 exceeds 100 columns
#4022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3998:
+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:3999:
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814

WARNING: line length of 105 exceeds 100 columns
#4024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4000:
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4001:
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815

WARNING: line length of 105 exceeds 100 columns
#4026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4002:
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4003:
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816

WARNING: line length of 105 exceeds 100 columns
#4028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4004:
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4005:
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817

WARNING: line length of 105 exceeds 100 columns
#4030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4006:
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4007:
+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a

WARNING: line length of 105 exceeds 100 columns
#4032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4008:
+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4009:
+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b

WARNING: line length of 105 exceeds 100 columns
#4034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4010:
+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4011:
+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c

WARNING: line length of 105 exceeds 100 columns
#4036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4012:
+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4013:
+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d

WARNING: line length of 105 exceeds 100 columns
#4038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4014:
+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4015:
+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e

WARNING: line length of 105 exceeds 100 columns
#4040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4016:
+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4017:
+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f

WARNING: line length of 105 exceeds 100 columns
#4042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4018:
+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4019:
+#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820

WARNING: line length of 105 exceeds 100 columns
#4044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4020:
+#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4021:
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821

WARNING: line length of 105 exceeds 100 columns
#4046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4022:
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4023:
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822

WARNING: line length of 105 exceeds 100 columns
#4048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4024:
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4025:
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823

WARNING: line length of 105 exceeds 100 columns
#4050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4026:
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4031:
+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824

WARNING: line length of 105 exceeds 100 columns
#4056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4032:
+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4033:
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825

WARNING: line length of 105 exceeds 100 columns
#4058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4034:
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4035:
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826

WARNING: line length of 105 exceeds 100 columns
#4060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4036:
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4037:
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827

WARNING: line length of 105 exceeds 100 columns
#4062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4038:
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4039:
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828

WARNING: line length of 105 exceeds 100 columns
#4064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4040:
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4041:
+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829

WARNING: line length of 105 exceeds 100 columns
#4066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4042:
+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4043:
+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a

WARNING: line length of 105 exceeds 100 columns
#4068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4044:
+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4045:
+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b

WARNING: line length of 105 exceeds 100 columns
#4070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4046:
+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4047:
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c

WARNING: line length of 105 exceeds 100 columns
#4072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4048:
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4049:
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d

WARNING: line length of 105 exceeds 100 columns
#4074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4050:
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4055:
+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830

WARNING: line length of 105 exceeds 100 columns
#4080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4056:
+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4057:
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831

WARNING: line length of 105 exceeds 100 columns
#4082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4058:
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4059:
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832

WARNING: line length of 105 exceeds 100 columns
#4084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4060:
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4061:
+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833

WARNING: line length of 105 exceeds 100 columns
#4086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4062:
+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4063:
+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834

WARNING: line length of 105 exceeds 100 columns
#4088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4064:
+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4065:
+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835

WARNING: line length of 105 exceeds 100 columns
#4090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4066:
+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4067:
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836

WARNING: line length of 105 exceeds 100 columns
#4092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4068:
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4069:
+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837

WARNING: line length of 105 exceeds 100 columns
#4094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4070:
+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4071:
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838

WARNING: line length of 105 exceeds 100 columns
#4096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4072:
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4073:
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839

WARNING: line length of 105 exceeds 100 columns
#4098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4074:
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4075:
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a

WARNING: line length of 105 exceeds 100 columns
#4100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4076:
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4077:
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b

WARNING: line length of 105 exceeds 100 columns
#4102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4078:
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4079:
+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c

WARNING: line length of 105 exceeds 100 columns
#4104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4080:
+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4081:
+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d

WARNING: line length of 105 exceeds 100 columns
#4106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4082:
+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4083:
+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e

WARNING: line length of 105 exceeds 100 columns
#4108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4084:
+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4085:
+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f

WARNING: line length of 105 exceeds 100 columns
#4110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4086:
+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4087:
+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840

WARNING: line length of 105 exceeds 100 columns
#4112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4088:
+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4093:
+#define regDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855

WARNING: line length of 105 exceeds 100 columns
#4118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4094:
+#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4095:
+#define regDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856

WARNING: line length of 105 exceeds 100 columns
#4120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4096:
+#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4097:
+#define regDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857

WARNING: line length of 105 exceeds 100 columns
#4122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4098:
+#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4099:
+#define regDC_PERFMON9_PERFMON_CNTL                                                                     0x0858

WARNING: line length of 105 exceeds 100 columns
#4124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4100:
+#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4101:
+#define regDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859

WARNING: line length of 105 exceeds 100 columns
#4126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4102:
+#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4103:
+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a

WARNING: line length of 105 exceeds 100 columns
#4128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4104:
+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4105:
+#define regDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b

WARNING: line length of 105 exceeds 100 columns
#4130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4106:
+#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4107:
+#define regDC_PERFMON9_PERFMON_HI                                                                       0x085c

WARNING: line length of 105 exceeds 100 columns
#4132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4108:
+#define regDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#4133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4109:
+#define regDC_PERFMON9_PERFMON_LOW                                                                      0x085d

WARNING: line length of 105 exceeds 100 columns
#4134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4110:
+#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4115:
+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879

WARNING: line length of 105 exceeds 100 columns
#4140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4116:
+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4117:
+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a

WARNING: line length of 105 exceeds 100 columns
#4142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4118:
+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4119:
+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b

WARNING: line length of 105 exceeds 100 columns
#4144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4120:
+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4121:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d

WARNING: line length of 105 exceeds 100 columns
#4146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4122:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4123:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e

WARNING: line length of 105 exceeds 100 columns
#4148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4124:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4125:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f

WARNING: line length of 105 exceeds 100 columns
#4150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4126:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4127:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880

WARNING: line length of 105 exceeds 100 columns
#4152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4128:
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4129:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881

WARNING: line length of 105 exceeds 100 columns
#4154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4130:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4131:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882

WARNING: line length of 105 exceeds 100 columns
#4156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4132:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4133:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883

WARNING: line length of 105 exceeds 100 columns
#4158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4134:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4135:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884

WARNING: line length of 105 exceeds 100 columns
#4160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4136:
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4137:
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885

WARNING: line length of 105 exceeds 100 columns
#4162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4138:
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4139:
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886

WARNING: line length of 105 exceeds 100 columns
#4164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4140:
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4141:
+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887

WARNING: line length of 105 exceeds 100 columns
#4166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4142:
+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4143:
+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888

WARNING: line length of 105 exceeds 100 columns
#4168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4144:
+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#4169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4145:
+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889

WARNING: line length of 105 exceeds 100 columns
#4170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4146:
+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4147:
+#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a

WARNING: line length of 105 exceeds 100 columns
#4172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4148:
+#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4149:
+#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b

WARNING: line length of 105 exceeds 100 columns
#4174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4150:
+#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4151:
+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c

WARNING: line length of 105 exceeds 100 columns
#4176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4152:
+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#4177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4153:
+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d

WARNING: line length of 105 exceeds 100 columns
#4178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4154:
+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#4179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4155:
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891

WARNING: line length of 105 exceeds 100 columns
#4180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4156:
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4157:
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892

WARNING: line length of 105 exceeds 100 columns
#4182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4158:
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4159:
+#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893

WARNING: line length of 105 exceeds 100 columns
#4184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4160:
+#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#4189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4165:
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b

WARNING: line length of 105 exceeds 100 columns
#4190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4166:
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4167:
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c

WARNING: line length of 105 exceeds 100 columns
#4192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4168:
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4169:
+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d

WARNING: line length of 105 exceeds 100 columns
#4194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4170:
+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4171:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e

WARNING: line length of 105 exceeds 100 columns
#4196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4172:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#4197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4173:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f

WARNING: line length of 105 exceeds 100 columns
#4198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4174:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#4199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4175:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0

WARNING: line length of 105 exceeds 100 columns
#4200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4176:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#4201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4177:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1

WARNING: line length of 105 exceeds 100 columns
#4202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4178:
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#4203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4179:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2

WARNING: line length of 105 exceeds 100 columns
#4204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4180:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#4205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4181:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3

WARNING: line length of 105 exceeds 100 columns
#4206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4182:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#4207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4183:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4

WARNING: line length of 105 exceeds 100 columns
#4208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4184:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#4209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4185:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5

WARNING: line length of 105 exceeds 100 columns
#4210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4186:
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#4211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4187:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6

WARNING: line length of 105 exceeds 100 columns
#4212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4188:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#4213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4189:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7

WARNING: line length of 105 exceeds 100 columns
#4214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4190:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#4215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4191:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8

WARNING: line length of 105 exceeds 100 columns
#4216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4192:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#4217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4193:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9

WARNING: line length of 105 exceeds 100 columns
#4218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4194:
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#4219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4195:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa

WARNING: line length of 105 exceeds 100 columns
#4220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4196:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#4221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4197:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab

WARNING: line length of 105 exceeds 100 columns
#4222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4198:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#4223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4199:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac

WARNING: line length of 105 exceeds 100 columns
#4224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4200:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2

WARNING: line length of 110 exceeds 100 columns
#4225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4201:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad

WARNING: line length of 105 exceeds 100 columns
#4226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4202:
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2

WARNING: line length of 110 exceeds 100 columns
#4227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4203:
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae

WARNING: line length of 105 exceeds 100 columns
#4228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4204:
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4205:
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af

WARNING: line length of 105 exceeds 100 columns
#4230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4206:
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4207:
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0

WARNING: line length of 105 exceeds 100 columns
#4232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4208:
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4209:
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3

WARNING: line length of 105 exceeds 100 columns
#4234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4210:
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#4235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4211:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4

WARNING: line length of 105 exceeds 100 columns
#4236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4212:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4213:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5

WARNING: line length of 105 exceeds 100 columns
#4238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4214:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4215:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6

WARNING: line length of 105 exceeds 100 columns
#4240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4216:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4217:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7

WARNING: line length of 105 exceeds 100 columns
#4242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4218:
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4219:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8

WARNING: line length of 105 exceeds 100 columns
#4244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4220:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#4245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4221:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9

WARNING: line length of 105 exceeds 100 columns
#4246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4222:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#4247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4223:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba

WARNING: line length of 105 exceeds 100 columns
#4248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4224:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#4249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4225:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb

WARNING: line length of 105 exceeds 100 columns
#4250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4226:
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#4251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4227:
+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc

WARNING: line length of 105 exceeds 100 columns
#4252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4228:
+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4229:
+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd

WARNING: line length of 105 exceeds 100 columns
#4254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4230:
+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4231:
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be

WARNING: line length of 105 exceeds 100 columns
#4256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4232:
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4233:
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf

WARNING: line length of 105 exceeds 100 columns
#4258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4234:
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4235:
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0

WARNING: line length of 105 exceeds 100 columns
#4260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4236:
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4237:
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1

WARNING: line length of 105 exceeds 100 columns
#4262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4238:
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4239:
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2

WARNING: line length of 105 exceeds 100 columns
#4264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4240:
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4241:
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3

WARNING: line length of 105 exceeds 100 columns
#4266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4242:
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4243:
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4

WARNING: line length of 105 exceeds 100 columns
#4268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4244:
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4245:
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5

WARNING: line length of 105 exceeds 100 columns
#4270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4246:
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4247:
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6

WARNING: line length of 105 exceeds 100 columns
#4272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4248:
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4249:
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7

WARNING: line length of 105 exceeds 100 columns
#4274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4250:
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4251:
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8

WARNING: line length of 105 exceeds 100 columns
#4276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4252:
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#4277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4253:
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9

WARNING: line length of 105 exceeds 100 columns
#4278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4254:
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#4279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4255:
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6

WARNING: line length of 105 exceeds 100 columns
#4280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4256:
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4257:
+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7

WARNING: line length of 105 exceeds 100 columns
#4282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4258:
+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4259:
+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8

WARNING: line length of 105 exceeds 100 columns
#4284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4260:
+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4261:
+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9

WARNING: line length of 105 exceeds 100 columns
#4286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4262:
+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4263:
+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da

WARNING: line length of 105 exceeds 100 columns
#4288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4264:
+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4265:
+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db

WARNING: line length of 105 exceeds 100 columns
#4290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4266:
+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4267:
+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc

WARNING: line length of 105 exceeds 100 columns
#4292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4268:
+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4269:
+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd

WARNING: line length of 105 exceeds 100 columns
#4294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4270:
+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4271:
+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de

WARNING: line length of 105 exceeds 100 columns
#4296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4272:
+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4273:
+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df

WARNING: line length of 105 exceeds 100 columns
#4298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4274:
+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4275:
+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0

WARNING: line length of 105 exceeds 100 columns
#4300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4276:
+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4277:
+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1

WARNING: line length of 105 exceeds 100 columns
#4302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4278:
+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4279:
+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2

WARNING: line length of 105 exceeds 100 columns
#4304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4280:
+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4281:
+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3

WARNING: line length of 105 exceeds 100 columns
#4306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4282:
+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4283:
+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4

WARNING: line length of 105 exceeds 100 columns
#4308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4284:
+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4285:
+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5

WARNING: line length of 105 exceeds 100 columns
#4310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4286:
+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4287:
+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6

WARNING: line length of 105 exceeds 100 columns
#4312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4288:
+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4289:
+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7

WARNING: line length of 105 exceeds 100 columns
#4314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4290:
+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4291:
+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8

WARNING: line length of 105 exceeds 100 columns
#4316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4292:
+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4293:
+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9

WARNING: line length of 105 exceeds 100 columns
#4318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4294:
+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4295:
+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea

WARNING: line length of 105 exceeds 100 columns
#4320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4296:
+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4297:
+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb

WARNING: line length of 105 exceeds 100 columns
#4322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4298:
+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4299:
+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec

WARNING: line length of 105 exceeds 100 columns
#4324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4300:
+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4301:
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed

WARNING: line length of 105 exceeds 100 columns
#4326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4302:
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4303:
+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee

WARNING: line length of 105 exceeds 100 columns
#4328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4304:
+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4305:
+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef

WARNING: line length of 105 exceeds 100 columns
#4330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4306:
+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4307:
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0

WARNING: line length of 105 exceeds 100 columns
#4332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4308:
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4309:
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1

WARNING: line length of 105 exceeds 100 columns
#4334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4310:
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4311:
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2

WARNING: line length of 105 exceeds 100 columns
#4336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4312:
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4313:
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3

WARNING: line length of 105 exceeds 100 columns
#4338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4314:
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4315:
+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6

WARNING: line length of 105 exceeds 100 columns
#4340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4316:
+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4317:
+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7

WARNING: line length of 105 exceeds 100 columns
#4342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4318:
+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4319:
+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8

WARNING: line length of 105 exceeds 100 columns
#4344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4320:
+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4321:
+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9

WARNING: line length of 105 exceeds 100 columns
#4346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4322:
+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4323:
+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa

WARNING: line length of 105 exceeds 100 columns
#4348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4324:
+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4325:
+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb

WARNING: line length of 105 exceeds 100 columns
#4350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4326:
+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4327:
+#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc

WARNING: line length of 105 exceeds 100 columns
#4352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4328:
+#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4329:
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd

WARNING: line length of 105 exceeds 100 columns
#4354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4330:
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4331:
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe

WARNING: line length of 105 exceeds 100 columns
#4356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4332:
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4333:
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff

WARNING: line length of 105 exceeds 100 columns
#4358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4334:
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4339:
+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900

WARNING: line length of 105 exceeds 100 columns
#4364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4340:
+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4341:
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901

WARNING: line length of 105 exceeds 100 columns
#4366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4342:
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4343:
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902

WARNING: line length of 105 exceeds 100 columns
#4368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4344:
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4345:
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903

WARNING: line length of 105 exceeds 100 columns
#4370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4346:
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4347:
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904

WARNING: line length of 105 exceeds 100 columns
#4372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4348:
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4349:
+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905

WARNING: line length of 105 exceeds 100 columns
#4374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4350:
+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4351:
+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906

WARNING: line length of 105 exceeds 100 columns
#4376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4352:
+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4353:
+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907

WARNING: line length of 105 exceeds 100 columns
#4378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4354:
+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4355:
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908

WARNING: line length of 105 exceeds 100 columns
#4380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4356:
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4357:
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909

WARNING: line length of 105 exceeds 100 columns
#4382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4358:
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4363:
+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c

WARNING: line length of 105 exceeds 100 columns
#4388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4364:
+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4365:
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d

WARNING: line length of 105 exceeds 100 columns
#4390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4366:
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4367:
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e

WARNING: line length of 105 exceeds 100 columns
#4392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4368:
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4369:
+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f

WARNING: line length of 105 exceeds 100 columns
#4394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4370:
+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4371:
+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910

WARNING: line length of 105 exceeds 100 columns
#4396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4372:
+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4373:
+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911

WARNING: line length of 105 exceeds 100 columns
#4398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4374:
+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4375:
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912

WARNING: line length of 105 exceeds 100 columns
#4400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4376:
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4377:
+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913

WARNING: line length of 105 exceeds 100 columns
#4402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4378:
+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4379:
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914

WARNING: line length of 105 exceeds 100 columns
#4404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4380:
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4381:
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915

WARNING: line length of 105 exceeds 100 columns
#4406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4382:
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4383:
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916

WARNING: line length of 105 exceeds 100 columns
#4408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4384:
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4385:
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917

WARNING: line length of 105 exceeds 100 columns
#4410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4386:
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4387:
+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918

WARNING: line length of 105 exceeds 100 columns
#4412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4388:
+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4389:
+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919

WARNING: line length of 105 exceeds 100 columns
#4414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4390:
+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4391:
+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a

WARNING: line length of 105 exceeds 100 columns
#4416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4392:
+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4393:
+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b

WARNING: line length of 105 exceeds 100 columns
#4418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4394:
+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4395:
+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c

WARNING: line length of 105 exceeds 100 columns
#4420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4396:
+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4401:
+#define regDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931

WARNING: line length of 105 exceeds 100 columns
#4426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4402:
+#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4403:
+#define regDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932

WARNING: line length of 105 exceeds 100 columns
#4428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4404:
+#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4405:
+#define regDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933

WARNING: line length of 105 exceeds 100 columns
#4430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4406:
+#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4407:
+#define regDC_PERFMON10_PERFMON_CNTL                                                                    0x0934

WARNING: line length of 105 exceeds 100 columns
#4432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4408:
+#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4409:
+#define regDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935

WARNING: line length of 105 exceeds 100 columns
#4434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4410:
+#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4411:
+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936

WARNING: line length of 105 exceeds 100 columns
#4436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4412:
+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4413:
+#define regDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937

WARNING: line length of 105 exceeds 100 columns
#4438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4414:
+#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4415:
+#define regDC_PERFMON10_PERFMON_HI                                                                      0x0938

WARNING: line length of 105 exceeds 100 columns
#4440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4416:
+#define regDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4417:
+#define regDC_PERFMON10_PERFMON_LOW                                                                     0x0939

WARNING: line length of 105 exceeds 100 columns
#4442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4418:
+#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4423:
+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5

WARNING: line length of 105 exceeds 100 columns
#4448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4424:
+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#4449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4425:
+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6

WARNING: line length of 105 exceeds 100 columns
#4450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4426:
+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4427:
+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7

WARNING: line length of 105 exceeds 100 columns
#4452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4428:
+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4429:
+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8

WARNING: line length of 105 exceeds 100 columns
#4454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4430:
+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4431:
+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9

WARNING: line length of 105 exceeds 100 columns
#4456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4432:
+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4433:
+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca

WARNING: line length of 105 exceeds 100 columns
#4458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4434:
+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4439:
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf

WARNING: line length of 105 exceeds 100 columns
#4464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4440:
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4441:
+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0

WARNING: line length of 105 exceeds 100 columns
#4466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4442:
+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4443:
+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1

WARNING: line length of 105 exceeds 100 columns
#4468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4444:
+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4445:
+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2

WARNING: line length of 105 exceeds 100 columns
#4470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4446:
+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4447:
+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3

WARNING: line length of 105 exceeds 100 columns
#4472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4448:
+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4449:
+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4

WARNING: line length of 105 exceeds 100 columns
#4474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4450:
+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4451:
+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5

WARNING: line length of 105 exceeds 100 columns
#4476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4452:
+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4453:
+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6

WARNING: line length of 105 exceeds 100 columns
#4478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4454:
+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4455:
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7

WARNING: line length of 105 exceeds 100 columns
#4480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4456:
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4457:
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8

WARNING: line length of 105 exceeds 100 columns
#4482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4458:
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4459:
+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9

WARNING: line length of 105 exceeds 100 columns
#4484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4460:
+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4461:
+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda

WARNING: line length of 105 exceeds 100 columns
#4486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4462:
+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4463:
+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb

WARNING: line length of 105 exceeds 100 columns
#4488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4464:
+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4465:
+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd

WARNING: line length of 105 exceeds 100 columns
#4490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4466:
+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4467:
+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde

WARNING: line length of 105 exceeds 100 columns
#4492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4468:
+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4469:
+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf

WARNING: line length of 105 exceeds 100 columns
#4494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4470:
+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#4495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4471:
+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0

WARNING: line length of 105 exceeds 100 columns
#4496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4472:
+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4473:
+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1

WARNING: line length of 105 exceeds 100 columns
#4498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4474:
+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4475:
+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2

WARNING: line length of 105 exceeds 100 columns
#4500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4476:
+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4477:
+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3

WARNING: line length of 105 exceeds 100 columns
#4502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4478:
+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4479:
+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4

WARNING: line length of 105 exceeds 100 columns
#4504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4480:
+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4481:
+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5

WARNING: line length of 105 exceeds 100 columns
#4506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4482:
+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4483:
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6

WARNING: line length of 105 exceeds 100 columns
#4508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4484:
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4485:
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7

WARNING: line length of 105 exceeds 100 columns
#4510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4486:
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4487:
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8

WARNING: line length of 105 exceeds 100 columns
#4512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4488:
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4489:
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9

WARNING: line length of 105 exceeds 100 columns
#4514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4490:
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4491:
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea

WARNING: line length of 105 exceeds 100 columns
#4516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4492:
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4493:
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb

WARNING: line length of 105 exceeds 100 columns
#4518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4494:
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4495:
+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec

WARNING: line length of 105 exceeds 100 columns
#4520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4496:
+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4497:
+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced

WARNING: line length of 105 exceeds 100 columns
#4522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4498:
+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#4523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4499:
+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee

WARNING: line length of 105 exceeds 100 columns
#4524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4500:
+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4505:
+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1

WARNING: line length of 105 exceeds 100 columns
#4530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4506:
+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4507:
+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2

WARNING: line length of 105 exceeds 100 columns
#4532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4508:
+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4509:
+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3

WARNING: line length of 105 exceeds 100 columns
#4534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4510:
+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4511:
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4

WARNING: line length of 105 exceeds 100 columns
#4536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4512:
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4517:
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9

WARNING: line length of 105 exceeds 100 columns
#4542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4518:
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4519:
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa

WARNING: line length of 105 exceeds 100 columns
#4544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4520:
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4521:
+#define regDSCL0_SCL_MODE                                                                               0x0cfb

WARNING: line length of 105 exceeds 100 columns
#4546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4522:
+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#4547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4523:
+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc

WARNING: line length of 105 exceeds 100 columns
#4548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4524:
+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4525:
+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd

WARNING: line length of 105 exceeds 100 columns
#4550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4526:
+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4527:
+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe

WARNING: line length of 105 exceeds 100 columns
#4552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4528:
+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4529:
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff

WARNING: line length of 105 exceeds 100 columns
#4554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4530:
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4531:
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00

WARNING: line length of 105 exceeds 100 columns
#4556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4532:
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4533:
+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01

WARNING: line length of 105 exceeds 100 columns
#4558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4534:
+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4535:
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02

WARNING: line length of 105 exceeds 100 columns
#4560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4536:
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4537:
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03

WARNING: line length of 105 exceeds 100 columns
#4562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4538:
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4539:
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04

WARNING: line length of 105 exceeds 100 columns
#4564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4540:
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4541:
+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05

WARNING: line length of 105 exceeds 100 columns
#4566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4542:
+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4543:
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06

WARNING: line length of 105 exceeds 100 columns
#4568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4544:
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4545:
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07

WARNING: line length of 105 exceeds 100 columns
#4570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4546:
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4547:
+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08

WARNING: line length of 105 exceeds 100 columns
#4572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4548:
+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4549:
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09

WARNING: line length of 105 exceeds 100 columns
#4574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4550:
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4551:
+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a

WARNING: line length of 105 exceeds 100 columns
#4576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4552:
+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4553:
+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b

WARNING: line length of 105 exceeds 100 columns
#4578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4554:
+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4555:
+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c

WARNING: line length of 105 exceeds 100 columns
#4580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4556:
+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4557:
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d

WARNING: line length of 105 exceeds 100 columns
#4582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4558:
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4559:
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e

WARNING: line length of 105 exceeds 100 columns
#4584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4560:
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4561:
+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f

WARNING: line length of 105 exceeds 100 columns
#4586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4562:
+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4563:
+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10

WARNING: line length of 105 exceeds 100 columns
#4588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4564:
+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4565:
+#define regDSCL0_RECOUT_START                                                                           0x0d11

WARNING: line length of 105 exceeds 100 columns
#4590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4566:
+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4567:
+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12

WARNING: line length of 105 exceeds 100 columns
#4592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4568:
+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4569:
+#define regDSCL0_MPC_SIZE                                                                               0x0d13

WARNING: line length of 105 exceeds 100 columns
#4594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4570:
+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#4595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4571:
+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14

WARNING: line length of 105 exceeds 100 columns
#4596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4572:
+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#4597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4573:
+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15

WARNING: line length of 105 exceeds 100 columns
#4598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4574:
+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#4599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4575:
+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16

WARNING: line length of 105 exceeds 100 columns
#4600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4576:
+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4577:
+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17

WARNING: line length of 105 exceeds 100 columns
#4602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4578:
+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4579:
+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18

WARNING: line length of 105 exceeds 100 columns
#4604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4580:
+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4581:
+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19

WARNING: line length of 105 exceeds 100 columns
#4606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4582:
+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4583:
+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a

WARNING: line length of 105 exceeds 100 columns
#4608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4584:
+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4589:
+#define regCM0_CM_CONTROL                                                                               0x0d20

WARNING: line length of 105 exceeds 100 columns
#4614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4590:
+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#4615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4591:
+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21

WARNING: line length of 105 exceeds 100 columns
#4616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4592:
+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4593:
+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22

WARNING: line length of 105 exceeds 100 columns
#4618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4594:
+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4595:
+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23

WARNING: line length of 105 exceeds 100 columns
#4620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4596:
+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4597:
+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24

WARNING: line length of 105 exceeds 100 columns
#4622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4598:
+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4599:
+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25

WARNING: line length of 105 exceeds 100 columns
#4624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4600:
+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4601:
+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26

WARNING: line length of 105 exceeds 100 columns
#4626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4602:
+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4603:
+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27

WARNING: line length of 105 exceeds 100 columns
#4628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4604:
+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4605:
+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28

WARNING: line length of 105 exceeds 100 columns
#4630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4606:
+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4607:
+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29

WARNING: line length of 105 exceeds 100 columns
#4632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4608:
+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4609:
+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a

WARNING: line length of 105 exceeds 100 columns
#4634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4610:
+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4611:
+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b

WARNING: line length of 105 exceeds 100 columns
#4636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4612:
+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4613:
+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c

WARNING: line length of 105 exceeds 100 columns
#4638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4614:
+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4615:
+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d

WARNING: line length of 105 exceeds 100 columns
#4640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4616:
+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4617:
+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e

WARNING: line length of 105 exceeds 100 columns
#4642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4618:
+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4619:
+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f

WARNING: line length of 105 exceeds 100 columns
#4644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4620:
+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4621:
+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30

WARNING: line length of 105 exceeds 100 columns
#4646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4622:
+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4623:
+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31

WARNING: line length of 105 exceeds 100 columns
#4648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4624:
+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4625:
+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32

WARNING: line length of 105 exceeds 100 columns
#4650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4626:
+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4627:
+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33

WARNING: line length of 105 exceeds 100 columns
#4652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4628:
+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4629:
+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34

WARNING: line length of 105 exceeds 100 columns
#4654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4630:
+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4631:
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35

WARNING: line length of 105 exceeds 100 columns
#4656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4632:
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4633:
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36

WARNING: line length of 105 exceeds 100 columns
#4658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4634:
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4635:
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37

WARNING: line length of 105 exceeds 100 columns
#4660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4636:
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4637:
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38

WARNING: line length of 105 exceeds 100 columns
#4662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4638:
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4639:
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39

WARNING: line length of 105 exceeds 100 columns
#4664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4640:
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4641:
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a

WARNING: line length of 105 exceeds 100 columns
#4666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4642:
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4643:
+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b

WARNING: line length of 105 exceeds 100 columns
#4668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4644:
+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#4669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4645:
+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c

WARNING: line length of 105 exceeds 100 columns
#4670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4646:
+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#4671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4647:
+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d

WARNING: line length of 105 exceeds 100 columns
#4672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4648:
+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4649:
+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e

WARNING: line length of 105 exceeds 100 columns
#4674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4650:
+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4651:
+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f

WARNING: line length of 105 exceeds 100 columns
#4676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4652:
+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#4677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4653:
+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40

WARNING: line length of 105 exceeds 100 columns
#4678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4654:
+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4655:
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41

WARNING: line length of 105 exceeds 100 columns
#4680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4656:
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4657:
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42

WARNING: line length of 105 exceeds 100 columns
#4682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4658:
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4659:
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43

WARNING: line length of 105 exceeds 100 columns
#4684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4660:
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4661:
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44

WARNING: line length of 105 exceeds 100 columns
#4686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4662:
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4663:
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45

WARNING: line length of 105 exceeds 100 columns
#4688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4664:
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4665:
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46

WARNING: line length of 105 exceeds 100 columns
#4690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4666:
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4667:
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47

WARNING: line length of 105 exceeds 100 columns
#4692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4668:
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4669:
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48

WARNING: line length of 105 exceeds 100 columns
#4694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4670:
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4671:
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49

WARNING: line length of 105 exceeds 100 columns
#4696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4672:
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4673:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a

WARNING: line length of 105 exceeds 100 columns
#4698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4674:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4675:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b

WARNING: line length of 105 exceeds 100 columns
#4700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4676:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4677:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c

WARNING: line length of 105 exceeds 100 columns
#4702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4678:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4679:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d

WARNING: line length of 105 exceeds 100 columns
#4704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4680:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4681:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e

WARNING: line length of 105 exceeds 100 columns
#4706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4682:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4683:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f

WARNING: line length of 105 exceeds 100 columns
#4708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4684:
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4685:
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50

WARNING: line length of 105 exceeds 100 columns
#4710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4686:
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4687:
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51

WARNING: line length of 105 exceeds 100 columns
#4712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4688:
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4689:
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52

WARNING: line length of 105 exceeds 100 columns
#4714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4690:
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4691:
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53

WARNING: line length of 105 exceeds 100 columns
#4716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4692:
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4693:
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54

WARNING: line length of 105 exceeds 100 columns
#4718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4694:
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4695:
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55

WARNING: line length of 105 exceeds 100 columns
#4720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4696:
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4697:
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56

WARNING: line length of 105 exceeds 100 columns
#4722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4698:
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4699:
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57

WARNING: line length of 105 exceeds 100 columns
#4724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4700:
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4701:
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58

WARNING: line length of 105 exceeds 100 columns
#4726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4702:
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4703:
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59

WARNING: line length of 105 exceeds 100 columns
#4728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4704:
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4705:
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a

WARNING: line length of 105 exceeds 100 columns
#4730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4706:
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4707:
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b

WARNING: line length of 105 exceeds 100 columns
#4732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4708:
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4709:
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c

WARNING: line length of 105 exceeds 100 columns
#4734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4710:
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4711:
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d

WARNING: line length of 105 exceeds 100 columns
#4736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4712:
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4713:
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e

WARNING: line length of 105 exceeds 100 columns
#4738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4714:
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4715:
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f

WARNING: line length of 105 exceeds 100 columns
#4740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4716:
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4717:
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60

WARNING: line length of 105 exceeds 100 columns
#4742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4718:
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4719:
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61

WARNING: line length of 105 exceeds 100 columns
#4744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4720:
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4721:
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62

WARNING: line length of 105 exceeds 100 columns
#4746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4722:
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4723:
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63

WARNING: line length of 105 exceeds 100 columns
#4748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4724:
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4725:
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64

WARNING: line length of 105 exceeds 100 columns
#4750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4726:
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4727:
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65

WARNING: line length of 105 exceeds 100 columns
#4752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4728:
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4729:
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66

WARNING: line length of 105 exceeds 100 columns
#4754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4730:
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4731:
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67

WARNING: line length of 105 exceeds 100 columns
#4756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4732:
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4733:
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68

WARNING: line length of 105 exceeds 100 columns
#4758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4734:
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4735:
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69

WARNING: line length of 105 exceeds 100 columns
#4760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4736:
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#4761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4737:
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a

WARNING: line length of 105 exceeds 100 columns
#4762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4738:
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4739:
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b

WARNING: line length of 105 exceeds 100 columns
#4764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4740:
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4741:
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c

WARNING: line length of 105 exceeds 100 columns
#4766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4742:
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4743:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d

WARNING: line length of 105 exceeds 100 columns
#4768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4744:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4745:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e

WARNING: line length of 105 exceeds 100 columns
#4770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4746:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4747:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f

WARNING: line length of 105 exceeds 100 columns
#4772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4748:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4749:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70

WARNING: line length of 105 exceeds 100 columns
#4774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4750:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4751:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71

WARNING: line length of 105 exceeds 100 columns
#4776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4752:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4753:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72

WARNING: line length of 105 exceeds 100 columns
#4778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4754:
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4755:
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73

WARNING: line length of 105 exceeds 100 columns
#4780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4756:
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4757:
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74

WARNING: line length of 105 exceeds 100 columns
#4782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4758:
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4759:
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75

WARNING: line length of 105 exceeds 100 columns
#4784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4760:
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4761:
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76

WARNING: line length of 105 exceeds 100 columns
#4786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4762:
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4763:
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77

WARNING: line length of 105 exceeds 100 columns
#4788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4764:
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4765:
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78

WARNING: line length of 105 exceeds 100 columns
#4790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4766:
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4767:
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79

WARNING: line length of 105 exceeds 100 columns
#4792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4768:
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4769:
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a

WARNING: line length of 105 exceeds 100 columns
#4794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4770:
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4771:
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b

WARNING: line length of 105 exceeds 100 columns
#4796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4772:
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4773:
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c

WARNING: line length of 105 exceeds 100 columns
#4798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4774:
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4775:
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d

WARNING: line length of 105 exceeds 100 columns
#4800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4776:
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4777:
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e

WARNING: line length of 105 exceeds 100 columns
#4802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4778:
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4779:
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f

WARNING: line length of 105 exceeds 100 columns
#4804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4780:
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4781:
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80

WARNING: line length of 105 exceeds 100 columns
#4806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4782:
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4783:
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81

WARNING: line length of 105 exceeds 100 columns
#4808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4784:
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4785:
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82

WARNING: line length of 105 exceeds 100 columns
#4810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4786:
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4787:
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83

WARNING: line length of 105 exceeds 100 columns
#4812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4788:
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4789:
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84

WARNING: line length of 105 exceeds 100 columns
#4814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4790:
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4791:
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85

WARNING: line length of 105 exceeds 100 columns
#4816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4792:
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4793:
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86

WARNING: line length of 105 exceeds 100 columns
#4818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4794:
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4795:
+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87

WARNING: line length of 105 exceeds 100 columns
#4820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4796:
+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#4821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4797:
+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88

WARNING: line length of 105 exceeds 100 columns
#4822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4798:
+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#4823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4799:
+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89

WARNING: line length of 105 exceeds 100 columns
#4824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4800:
+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4801:
+#define regCM0_CM_DEALPHA                                                                               0x0d8b

WARNING: line length of 105 exceeds 100 columns
#4826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4802:
+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#4827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4803:
+#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c

WARNING: line length of 105 exceeds 100 columns
#4828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4804:
+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4809:
+#define regDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24

WARNING: line length of 105 exceeds 100 columns
#4834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4810:
+#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4811:
+#define regDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25

WARNING: line length of 105 exceeds 100 columns
#4836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4812:
+#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4813:
+#define regDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26

WARNING: line length of 105 exceeds 100 columns
#4838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4814:
+#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4815:
+#define regDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27

WARNING: line length of 105 exceeds 100 columns
#4840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4816:
+#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4817:
+#define regDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28

WARNING: line length of 105 exceeds 100 columns
#4842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4818:
+#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4819:
+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29

WARNING: line length of 105 exceeds 100 columns
#4844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4820:
+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#4845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4821:
+#define regDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a

WARNING: line length of 105 exceeds 100 columns
#4846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4822:
+#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4823:
+#define regDC_PERFMON11_PERFMON_HI                                                                      0x0e2b

WARNING: line length of 105 exceeds 100 columns
#4848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4824:
+#define regDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4825:
+#define regDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c

WARNING: line length of 105 exceeds 100 columns
#4850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4826:
+#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4831:
+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30

WARNING: line length of 105 exceeds 100 columns
#4856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4832:
+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#4857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4833:
+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31

WARNING: line length of 105 exceeds 100 columns
#4858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4834:
+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4835:
+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32

WARNING: line length of 105 exceeds 100 columns
#4860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4836:
+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4837:
+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33

WARNING: line length of 105 exceeds 100 columns
#4862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4838:
+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4839:
+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34

WARNING: line length of 105 exceeds 100 columns
#4864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4840:
+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4841:
+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35

WARNING: line length of 105 exceeds 100 columns
#4866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4842:
+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4847:
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a

WARNING: line length of 105 exceeds 100 columns
#4872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4848:
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4849:
+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b

WARNING: line length of 105 exceeds 100 columns
#4874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4850:
+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4851:
+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c

WARNING: line length of 105 exceeds 100 columns
#4876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4852:
+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4853:
+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d

WARNING: line length of 105 exceeds 100 columns
#4878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4854:
+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4855:
+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e

WARNING: line length of 105 exceeds 100 columns
#4880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4856:
+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4857:
+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f

WARNING: line length of 105 exceeds 100 columns
#4882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4858:
+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4859:
+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40

WARNING: line length of 105 exceeds 100 columns
#4884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4860:
+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4861:
+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41

WARNING: line length of 105 exceeds 100 columns
#4886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4862:
+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4863:
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42

WARNING: line length of 105 exceeds 100 columns
#4888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4864:
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4865:
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43

WARNING: line length of 105 exceeds 100 columns
#4890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4866:
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4867:
+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44

WARNING: line length of 105 exceeds 100 columns
#4892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4868:
+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4869:
+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45

WARNING: line length of 105 exceeds 100 columns
#4894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4870:
+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4871:
+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46

WARNING: line length of 105 exceeds 100 columns
#4896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4872:
+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4873:
+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48

WARNING: line length of 105 exceeds 100 columns
#4898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4874:
+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4875:
+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49

WARNING: line length of 105 exceeds 100 columns
#4900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4876:
+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4877:
+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a

WARNING: line length of 105 exceeds 100 columns
#4902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4878:
+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#4903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4879:
+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b

WARNING: line length of 105 exceeds 100 columns
#4904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4880:
+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4881:
+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c

WARNING: line length of 105 exceeds 100 columns
#4906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4882:
+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4883:
+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d

WARNING: line length of 105 exceeds 100 columns
#4908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4884:
+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4885:
+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e

WARNING: line length of 105 exceeds 100 columns
#4910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4886:
+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4887:
+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f

WARNING: line length of 105 exceeds 100 columns
#4912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4888:
+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4889:
+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50

WARNING: line length of 105 exceeds 100 columns
#4914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4890:
+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4891:
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51

WARNING: line length of 105 exceeds 100 columns
#4916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4892:
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4893:
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52

WARNING: line length of 105 exceeds 100 columns
#4918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4894:
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4895:
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53

WARNING: line length of 105 exceeds 100 columns
#4920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4896:
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4897:
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54

WARNING: line length of 105 exceeds 100 columns
#4922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4898:
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4899:
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55

WARNING: line length of 105 exceeds 100 columns
#4924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4900:
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4901:
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56

WARNING: line length of 105 exceeds 100 columns
#4926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4902:
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4903:
+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57

WARNING: line length of 105 exceeds 100 columns
#4928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4904:
+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4905:
+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58

WARNING: line length of 105 exceeds 100 columns
#4930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4906:
+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#4931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4907:
+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59

WARNING: line length of 105 exceeds 100 columns
#4932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4908:
+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4913:
+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c

WARNING: line length of 105 exceeds 100 columns
#4938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4914:
+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#4939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4915:
+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d

WARNING: line length of 105 exceeds 100 columns
#4940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4916:
+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4917:
+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e

WARNING: line length of 105 exceeds 100 columns
#4942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4918:
+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#4943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4919:
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f

WARNING: line length of 105 exceeds 100 columns
#4944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4920:
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#4949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4925:
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64

WARNING: line length of 105 exceeds 100 columns
#4950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4926:
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#4951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4927:
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65

WARNING: line length of 105 exceeds 100 columns
#4952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4928:
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#4953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4929:
+#define regDSCL1_SCL_MODE                                                                               0x0e66

WARNING: line length of 105 exceeds 100 columns
#4954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4930:
+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#4955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4931:
+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67

WARNING: line length of 105 exceeds 100 columns
#4956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4932:
+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4933:
+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68

WARNING: line length of 105 exceeds 100 columns
#4958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4934:
+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4935:
+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69

WARNING: line length of 105 exceeds 100 columns
#4960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4936:
+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#4961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4937:
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a

WARNING: line length of 105 exceeds 100 columns
#4962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4938:
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4939:
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b

WARNING: line length of 105 exceeds 100 columns
#4964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4940:
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4941:
+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c

WARNING: line length of 105 exceeds 100 columns
#4966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4942:
+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4943:
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d

WARNING: line length of 105 exceeds 100 columns
#4968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4944:
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4945:
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e

WARNING: line length of 105 exceeds 100 columns
#4970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4946:
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4947:
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f

WARNING: line length of 105 exceeds 100 columns
#4972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4948:
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#4973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4949:
+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70

WARNING: line length of 105 exceeds 100 columns
#4974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4950:
+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#4975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4951:
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71

WARNING: line length of 105 exceeds 100 columns
#4976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4952:
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#4977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4953:
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72

WARNING: line length of 105 exceeds 100 columns
#4978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4954:
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#4979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4955:
+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73

WARNING: line length of 105 exceeds 100 columns
#4980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4956:
+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#4981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4957:
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74

WARNING: line length of 105 exceeds 100 columns
#4982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4958:
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#4983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4959:
+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75

WARNING: line length of 105 exceeds 100 columns
#4984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4960:
+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#4985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4961:
+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76

WARNING: line length of 105 exceeds 100 columns
#4986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4962:
+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4963:
+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77

WARNING: line length of 105 exceeds 100 columns
#4988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4964:
+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4965:
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78

WARNING: line length of 105 exceeds 100 columns
#4990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4966:
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4967:
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79

WARNING: line length of 105 exceeds 100 columns
#4992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4968:
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#4993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4969:
+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a

WARNING: line length of 105 exceeds 100 columns
#4994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4970:
+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4971:
+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b

WARNING: line length of 105 exceeds 100 columns
#4996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4972:
+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#4997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4973:
+#define regDSCL1_RECOUT_START                                                                           0x0e7c

WARNING: line length of 105 exceeds 100 columns
#4998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4974:
+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#4999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4975:
+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d

WARNING: line length of 105 exceeds 100 columns
#5000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4976:
+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4977:
+#define regDSCL1_MPC_SIZE                                                                               0x0e7e

WARNING: line length of 105 exceeds 100 columns
#5002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4978:
+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4979:
+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f

WARNING: line length of 105 exceeds 100 columns
#5004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4980:
+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4981:
+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80

WARNING: line length of 105 exceeds 100 columns
#5006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4982:
+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4983:
+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81

WARNING: line length of 105 exceeds 100 columns
#5008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4984:
+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4985:
+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82

WARNING: line length of 105 exceeds 100 columns
#5010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4986:
+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4987:
+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83

WARNING: line length of 105 exceeds 100 columns
#5012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4988:
+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4989:
+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84

WARNING: line length of 105 exceeds 100 columns
#5014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4990:
+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4991:
+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85

WARNING: line length of 105 exceeds 100 columns
#5016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4992:
+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4997:
+#define regCM1_CM_CONTROL                                                                               0x0e8b

WARNING: line length of 105 exceeds 100 columns
#5022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4998:
+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:4999:
+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c

WARNING: line length of 105 exceeds 100 columns
#5024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5000:
+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5001:
+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d

WARNING: line length of 105 exceeds 100 columns
#5026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5002:
+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5003:
+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e

WARNING: line length of 105 exceeds 100 columns
#5028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5004:
+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5005:
+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f

WARNING: line length of 105 exceeds 100 columns
#5030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5006:
+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5007:
+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90

WARNING: line length of 105 exceeds 100 columns
#5032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5008:
+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5009:
+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91

WARNING: line length of 105 exceeds 100 columns
#5034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5010:
+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5011:
+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92

WARNING: line length of 105 exceeds 100 columns
#5036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5012:
+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5013:
+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93

WARNING: line length of 105 exceeds 100 columns
#5038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5014:
+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5015:
+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94

WARNING: line length of 105 exceeds 100 columns
#5040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5016:
+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5017:
+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95

WARNING: line length of 105 exceeds 100 columns
#5042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5018:
+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5019:
+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96

WARNING: line length of 105 exceeds 100 columns
#5044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5020:
+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5021:
+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97

WARNING: line length of 105 exceeds 100 columns
#5046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5022:
+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5023:
+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98

WARNING: line length of 105 exceeds 100 columns
#5048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5024:
+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5025:
+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99

WARNING: line length of 105 exceeds 100 columns
#5050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5026:
+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5027:
+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a

WARNING: line length of 105 exceeds 100 columns
#5052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5028:
+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5029:
+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b

WARNING: line length of 105 exceeds 100 columns
#5054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5030:
+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5031:
+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c

WARNING: line length of 105 exceeds 100 columns
#5056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5032:
+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5033:
+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d

WARNING: line length of 105 exceeds 100 columns
#5058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5034:
+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5035:
+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e

WARNING: line length of 105 exceeds 100 columns
#5060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5036:
+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5037:
+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f

WARNING: line length of 105 exceeds 100 columns
#5062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5038:
+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5039:
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0

WARNING: line length of 105 exceeds 100 columns
#5064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5040:
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5041:
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1

WARNING: line length of 105 exceeds 100 columns
#5066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5042:
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5043:
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2

WARNING: line length of 105 exceeds 100 columns
#5068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5044:
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5045:
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3

WARNING: line length of 105 exceeds 100 columns
#5070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5046:
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5047:
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4

WARNING: line length of 105 exceeds 100 columns
#5072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5048:
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5049:
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5

WARNING: line length of 105 exceeds 100 columns
#5074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5050:
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5051:
+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6

WARNING: line length of 105 exceeds 100 columns
#5076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5052:
+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#5077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5053:
+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7

WARNING: line length of 105 exceeds 100 columns
#5078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5054:
+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5055:
+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8

WARNING: line length of 105 exceeds 100 columns
#5080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5056:
+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5057:
+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9

WARNING: line length of 105 exceeds 100 columns
#5082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5058:
+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5059:
+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa

WARNING: line length of 105 exceeds 100 columns
#5084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5060:
+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#5085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5061:
+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab

WARNING: line length of 105 exceeds 100 columns
#5086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5062:
+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5063:
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac

WARNING: line length of 105 exceeds 100 columns
#5088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5064:
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5065:
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead

WARNING: line length of 105 exceeds 100 columns
#5090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5066:
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5067:
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae

WARNING: line length of 105 exceeds 100 columns
#5092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5068:
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5069:
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf

WARNING: line length of 105 exceeds 100 columns
#5094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5070:
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5071:
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0

WARNING: line length of 105 exceeds 100 columns
#5096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5072:
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5073:
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1

WARNING: line length of 105 exceeds 100 columns
#5098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5074:
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5075:
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2

WARNING: line length of 105 exceeds 100 columns
#5100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5076:
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5077:
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3

WARNING: line length of 105 exceeds 100 columns
#5102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5078:
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5079:
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4

WARNING: line length of 105 exceeds 100 columns
#5104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5080:
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5081:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5

WARNING: line length of 105 exceeds 100 columns
#5106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5082:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5083:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6

WARNING: line length of 105 exceeds 100 columns
#5108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5084:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5085:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7

WARNING: line length of 105 exceeds 100 columns
#5110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5086:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5087:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8

WARNING: line length of 105 exceeds 100 columns
#5112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5088:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5089:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9

WARNING: line length of 105 exceeds 100 columns
#5114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5090:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5091:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba

WARNING: line length of 105 exceeds 100 columns
#5116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5092:
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5093:
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb

WARNING: line length of 105 exceeds 100 columns
#5118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5094:
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5095:
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc

WARNING: line length of 105 exceeds 100 columns
#5120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5096:
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5097:
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd

WARNING: line length of 105 exceeds 100 columns
#5122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5098:
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5099:
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe

WARNING: line length of 105 exceeds 100 columns
#5124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5100:
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5101:
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf

WARNING: line length of 105 exceeds 100 columns
#5126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5102:
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5103:
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0

WARNING: line length of 105 exceeds 100 columns
#5128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5104:
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5105:
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1

WARNING: line length of 105 exceeds 100 columns
#5130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5106:
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5107:
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2

WARNING: line length of 105 exceeds 100 columns
#5132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5108:
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5109:
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3

WARNING: line length of 105 exceeds 100 columns
#5134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5110:
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5111:
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4

WARNING: line length of 105 exceeds 100 columns
#5136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5112:
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5113:
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5

WARNING: line length of 105 exceeds 100 columns
#5138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5114:
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5115:
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6

WARNING: line length of 105 exceeds 100 columns
#5140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5116:
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5117:
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7

WARNING: line length of 105 exceeds 100 columns
#5142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5118:
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5119:
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8

WARNING: line length of 105 exceeds 100 columns
#5144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5120:
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5121:
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9

WARNING: line length of 105 exceeds 100 columns
#5146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5122:
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5123:
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca

WARNING: line length of 105 exceeds 100 columns
#5148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5124:
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5125:
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb

WARNING: line length of 105 exceeds 100 columns
#5150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5126:
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5127:
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc

WARNING: line length of 105 exceeds 100 columns
#5152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5128:
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5129:
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd

WARNING: line length of 105 exceeds 100 columns
#5154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5130:
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5131:
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece

WARNING: line length of 105 exceeds 100 columns
#5156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5132:
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5133:
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf

WARNING: line length of 105 exceeds 100 columns
#5158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5134:
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5135:
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0

WARNING: line length of 105 exceeds 100 columns
#5160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5136:
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5137:
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1

WARNING: line length of 105 exceeds 100 columns
#5162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5138:
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5139:
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2

WARNING: line length of 105 exceeds 100 columns
#5164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5140:
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5141:
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3

WARNING: line length of 105 exceeds 100 columns
#5166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5142:
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5143:
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4

WARNING: line length of 105 exceeds 100 columns
#5168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5144:
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5145:
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5

WARNING: line length of 105 exceeds 100 columns
#5170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5146:
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5147:
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6

WARNING: line length of 105 exceeds 100 columns
#5172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5148:
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5149:
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7

WARNING: line length of 105 exceeds 100 columns
#5174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5150:
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5151:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8

WARNING: line length of 105 exceeds 100 columns
#5176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5152:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5153:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9

WARNING: line length of 105 exceeds 100 columns
#5178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5154:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5155:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda

WARNING: line length of 105 exceeds 100 columns
#5180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5156:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5157:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb

WARNING: line length of 105 exceeds 100 columns
#5182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5158:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5159:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc

WARNING: line length of 105 exceeds 100 columns
#5184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5160:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5161:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd

WARNING: line length of 105 exceeds 100 columns
#5186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5162:
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5163:
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede

WARNING: line length of 105 exceeds 100 columns
#5188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5164:
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5165:
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf

WARNING: line length of 105 exceeds 100 columns
#5190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5166:
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5167:
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0

WARNING: line length of 105 exceeds 100 columns
#5192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5168:
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5169:
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1

WARNING: line length of 105 exceeds 100 columns
#5194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5170:
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5171:
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2

WARNING: line length of 105 exceeds 100 columns
#5196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5172:
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5173:
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3

WARNING: line length of 105 exceeds 100 columns
#5198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5174:
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5175:
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4

WARNING: line length of 105 exceeds 100 columns
#5200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5176:
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5177:
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5

WARNING: line length of 105 exceeds 100 columns
#5202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5178:
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5179:
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6

WARNING: line length of 105 exceeds 100 columns
#5204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5180:
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5181:
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7

WARNING: line length of 105 exceeds 100 columns
#5206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5182:
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5183:
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8

WARNING: line length of 105 exceeds 100 columns
#5208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5184:
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5185:
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9

WARNING: line length of 105 exceeds 100 columns
#5210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5186:
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5187:
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea

WARNING: line length of 105 exceeds 100 columns
#5212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5188:
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5189:
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb

WARNING: line length of 105 exceeds 100 columns
#5214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5190:
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5191:
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec

WARNING: line length of 105 exceeds 100 columns
#5216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5192:
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5193:
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed

WARNING: line length of 105 exceeds 100 columns
#5218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5194:
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5195:
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee

WARNING: line length of 105 exceeds 100 columns
#5220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5196:
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5197:
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef

WARNING: line length of 105 exceeds 100 columns
#5222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5198:
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5199:
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0

WARNING: line length of 105 exceeds 100 columns
#5224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5200:
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5201:
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1

WARNING: line length of 105 exceeds 100 columns
#5226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5202:
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5203:
+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2

WARNING: line length of 105 exceeds 100 columns
#5228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5204:
+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5205:
+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3

WARNING: line length of 105 exceeds 100 columns
#5230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5206:
+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#5231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5207:
+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4

WARNING: line length of 105 exceeds 100 columns
#5232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5208:
+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5209:
+#define regCM1_CM_DEALPHA                                                                               0x0ef6

WARNING: line length of 105 exceeds 100 columns
#5234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5210:
+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5211:
+#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7

WARNING: line length of 105 exceeds 100 columns
#5236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5212:
+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5217:
+#define regDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f

WARNING: line length of 105 exceeds 100 columns
#5242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5218:
+#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5219:
+#define regDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90

WARNING: line length of 105 exceeds 100 columns
#5244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5220:
+#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5221:
+#define regDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91

WARNING: line length of 105 exceeds 100 columns
#5246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5222:
+#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5223:
+#define regDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92

WARNING: line length of 105 exceeds 100 columns
#5248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5224:
+#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5225:
+#define regDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93

WARNING: line length of 105 exceeds 100 columns
#5250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5226:
+#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5227:
+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94

WARNING: line length of 105 exceeds 100 columns
#5252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5228:
+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5229:
+#define regDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95

WARNING: line length of 105 exceeds 100 columns
#5254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5230:
+#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5231:
+#define regDC_PERFMON12_PERFMON_HI                                                                      0x0f96

WARNING: line length of 105 exceeds 100 columns
#5256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5232:
+#define regDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5233:
+#define regDC_PERFMON12_PERFMON_LOW                                                                     0x0f97

WARNING: line length of 105 exceeds 100 columns
#5258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5234:
+#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5239:
+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b

WARNING: line length of 105 exceeds 100 columns
#5264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5240:
+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5241:
+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c

WARNING: line length of 105 exceeds 100 columns
#5266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5242:
+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5243:
+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d

WARNING: line length of 105 exceeds 100 columns
#5268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5244:
+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5245:
+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e

WARNING: line length of 105 exceeds 100 columns
#5270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5246:
+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5247:
+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f

WARNING: line length of 105 exceeds 100 columns
#5272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5248:
+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5249:
+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0

WARNING: line length of 105 exceeds 100 columns
#5274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5250:
+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5255:
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5

WARNING: line length of 105 exceeds 100 columns
#5280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5256:
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#5281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5257:
+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6

WARNING: line length of 105 exceeds 100 columns
#5282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5258:
+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5259:
+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7

WARNING: line length of 105 exceeds 100 columns
#5284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5260:
+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5261:
+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8

WARNING: line length of 105 exceeds 100 columns
#5286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5262:
+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5263:
+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9

WARNING: line length of 105 exceeds 100 columns
#5288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5264:
+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5265:
+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa

WARNING: line length of 105 exceeds 100 columns
#5290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5266:
+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5267:
+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab

WARNING: line length of 105 exceeds 100 columns
#5292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5268:
+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5269:
+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac

WARNING: line length of 105 exceeds 100 columns
#5294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5270:
+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5271:
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad

WARNING: line length of 105 exceeds 100 columns
#5296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5272:
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5273:
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae

WARNING: line length of 105 exceeds 100 columns
#5298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5274:
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5275:
+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf

WARNING: line length of 105 exceeds 100 columns
#5300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5276:
+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5277:
+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0

WARNING: line length of 105 exceeds 100 columns
#5302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5278:
+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5279:
+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1

WARNING: line length of 105 exceeds 100 columns
#5304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5280:
+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5281:
+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3

WARNING: line length of 105 exceeds 100 columns
#5306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5282:
+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5283:
+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4

WARNING: line length of 105 exceeds 100 columns
#5308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5284:
+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5285:
+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5

WARNING: line length of 105 exceeds 100 columns
#5310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5286:
+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#5311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5287:
+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6

WARNING: line length of 105 exceeds 100 columns
#5312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5288:
+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5289:
+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7

WARNING: line length of 105 exceeds 100 columns
#5314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5290:
+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5291:
+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8

WARNING: line length of 105 exceeds 100 columns
#5316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5292:
+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5293:
+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9

WARNING: line length of 105 exceeds 100 columns
#5318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5294:
+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5295:
+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba

WARNING: line length of 105 exceeds 100 columns
#5320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5296:
+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5297:
+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb

WARNING: line length of 105 exceeds 100 columns
#5322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5298:
+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5299:
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc

WARNING: line length of 105 exceeds 100 columns
#5324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5300:
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5301:
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd

WARNING: line length of 105 exceeds 100 columns
#5326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5302:
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5303:
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe

WARNING: line length of 105 exceeds 100 columns
#5328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5304:
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5305:
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf

WARNING: line length of 105 exceeds 100 columns
#5330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5306:
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5307:
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0

WARNING: line length of 105 exceeds 100 columns
#5332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5308:
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5309:
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1

WARNING: line length of 105 exceeds 100 columns
#5334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5310:
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5311:
+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2

WARNING: line length of 105 exceeds 100 columns
#5336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5312:
+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5313:
+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3

WARNING: line length of 105 exceeds 100 columns
#5338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5314:
+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#5339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5315:
+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4

WARNING: line length of 105 exceeds 100 columns
#5340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5316:
+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5321:
+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7

WARNING: line length of 105 exceeds 100 columns
#5346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5322:
+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5323:
+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8

WARNING: line length of 105 exceeds 100 columns
#5348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5324:
+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5325:
+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9

WARNING: line length of 105 exceeds 100 columns
#5350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5326:
+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5327:
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca

WARNING: line length of 105 exceeds 100 columns
#5352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5328:
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5333:
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf

WARNING: line length of 105 exceeds 100 columns
#5358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5334:
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5335:
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0

WARNING: line length of 105 exceeds 100 columns
#5360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5336:
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5337:
+#define regDSCL2_SCL_MODE                                                                               0x0fd1

WARNING: line length of 105 exceeds 100 columns
#5362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5338:
+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5339:
+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2

WARNING: line length of 105 exceeds 100 columns
#5364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5340:
+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5341:
+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3

WARNING: line length of 105 exceeds 100 columns
#5366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5342:
+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5343:
+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4

WARNING: line length of 105 exceeds 100 columns
#5368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5344:
+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5345:
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5

WARNING: line length of 105 exceeds 100 columns
#5370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5346:
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#5371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5347:
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6

WARNING: line length of 105 exceeds 100 columns
#5372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5348:
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#5373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5349:
+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7

WARNING: line length of 105 exceeds 100 columns
#5374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5350:
+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5351:
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8

WARNING: line length of 105 exceeds 100 columns
#5376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5352:
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#5377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5353:
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9

WARNING: line length of 105 exceeds 100 columns
#5378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5354:
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5355:
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda

WARNING: line length of 105 exceeds 100 columns
#5380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5356:
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#5381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5357:
+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb

WARNING: line length of 105 exceeds 100 columns
#5382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5358:
+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5359:
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc

WARNING: line length of 105 exceeds 100 columns
#5384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5360:
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5361:
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd

WARNING: line length of 105 exceeds 100 columns
#5386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5362:
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#5387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5363:
+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde

WARNING: line length of 105 exceeds 100 columns
#5388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5364:
+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5365:
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf

WARNING: line length of 105 exceeds 100 columns
#5390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5366:
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#5391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5367:
+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0

WARNING: line length of 105 exceeds 100 columns
#5392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5368:
+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5369:
+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1

WARNING: line length of 105 exceeds 100 columns
#5394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5370:
+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5371:
+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2

WARNING: line length of 105 exceeds 100 columns
#5396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5372:
+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5373:
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3

WARNING: line length of 105 exceeds 100 columns
#5398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5374:
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#5399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5375:
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4

WARNING: line length of 105 exceeds 100 columns
#5400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5376:
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#5401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5377:
+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5

WARNING: line length of 105 exceeds 100 columns
#5402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5378:
+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5379:
+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6

WARNING: line length of 105 exceeds 100 columns
#5404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5380:
+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5381:
+#define regDSCL2_RECOUT_START                                                                           0x0fe7

WARNING: line length of 105 exceeds 100 columns
#5406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5382:
+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5383:
+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8

WARNING: line length of 105 exceeds 100 columns
#5408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5384:
+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5385:
+#define regDSCL2_MPC_SIZE                                                                               0x0fe9

WARNING: line length of 105 exceeds 100 columns
#5410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5386:
+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5387:
+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea

WARNING: line length of 105 exceeds 100 columns
#5412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5388:
+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5389:
+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb

WARNING: line length of 105 exceeds 100 columns
#5414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5390:
+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5391:
+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec

WARNING: line length of 105 exceeds 100 columns
#5416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5392:
+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5393:
+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed

WARNING: line length of 105 exceeds 100 columns
#5418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5394:
+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5395:
+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee

WARNING: line length of 105 exceeds 100 columns
#5420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5396:
+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5397:
+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef

WARNING: line length of 105 exceeds 100 columns
#5422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5398:
+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5399:
+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0

WARNING: line length of 105 exceeds 100 columns
#5424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5400:
+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5405:
+#define regCM2_CM_CONTROL                                                                               0x0ff6

WARNING: line length of 105 exceeds 100 columns
#5430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5406:
+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5407:
+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7

WARNING: line length of 105 exceeds 100 columns
#5432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5408:
+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5409:
+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8

WARNING: line length of 105 exceeds 100 columns
#5434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5410:
+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5411:
+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9

WARNING: line length of 105 exceeds 100 columns
#5436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5412:
+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5413:
+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa

WARNING: line length of 105 exceeds 100 columns
#5438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5414:
+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5415:
+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb

WARNING: line length of 105 exceeds 100 columns
#5440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5416:
+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5417:
+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc

WARNING: line length of 105 exceeds 100 columns
#5442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5418:
+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5419:
+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd

WARNING: line length of 105 exceeds 100 columns
#5444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5420:
+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5421:
+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe

WARNING: line length of 105 exceeds 100 columns
#5446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5422:
+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5423:
+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff

WARNING: line length of 105 exceeds 100 columns
#5448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5424:
+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5425:
+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000

WARNING: line length of 105 exceeds 100 columns
#5450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5426:
+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5427:
+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001

WARNING: line length of 105 exceeds 100 columns
#5452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5428:
+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5429:
+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002

WARNING: line length of 105 exceeds 100 columns
#5454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5430:
+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5431:
+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003

WARNING: line length of 105 exceeds 100 columns
#5456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5432:
+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5433:
+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004

WARNING: line length of 105 exceeds 100 columns
#5458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5434:
+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5435:
+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005

WARNING: line length of 105 exceeds 100 columns
#5460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5436:
+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5437:
+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006

WARNING: line length of 105 exceeds 100 columns
#5462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5438:
+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5439:
+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007

WARNING: line length of 105 exceeds 100 columns
#5464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5440:
+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5441:
+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008

WARNING: line length of 105 exceeds 100 columns
#5466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5442:
+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5443:
+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009

WARNING: line length of 105 exceeds 100 columns
#5468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5444:
+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5445:
+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a

WARNING: line length of 105 exceeds 100 columns
#5470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5446:
+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5447:
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b

WARNING: line length of 105 exceeds 100 columns
#5472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5448:
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5449:
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c

WARNING: line length of 105 exceeds 100 columns
#5474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5450:
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5451:
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d

WARNING: line length of 105 exceeds 100 columns
#5476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5452:
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5453:
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e

WARNING: line length of 105 exceeds 100 columns
#5478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5454:
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5455:
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f

WARNING: line length of 105 exceeds 100 columns
#5480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5456:
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5457:
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010

WARNING: line length of 105 exceeds 100 columns
#5482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5458:
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5459:
+#define regCM2_CM_BIAS_CR_R                                                                             0x1011

WARNING: line length of 105 exceeds 100 columns
#5484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5460:
+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#5485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5461:
+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012

WARNING: line length of 105 exceeds 100 columns
#5486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5462:
+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5463:
+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013

WARNING: line length of 105 exceeds 100 columns
#5488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5464:
+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5465:
+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014

WARNING: line length of 105 exceeds 100 columns
#5490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5466:
+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5467:
+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015

WARNING: line length of 105 exceeds 100 columns
#5492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5468:
+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#5493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5469:
+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016

WARNING: line length of 105 exceeds 100 columns
#5494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5470:
+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5471:
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017

WARNING: line length of 105 exceeds 100 columns
#5496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5472:
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5473:
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018

WARNING: line length of 105 exceeds 100 columns
#5498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5474:
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5475:
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019

WARNING: line length of 105 exceeds 100 columns
#5500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5476:
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5477:
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a

WARNING: line length of 105 exceeds 100 columns
#5502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5478:
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5479:
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b

WARNING: line length of 105 exceeds 100 columns
#5504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5480:
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5481:
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c

WARNING: line length of 105 exceeds 100 columns
#5506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5482:
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5483:
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d

WARNING: line length of 105 exceeds 100 columns
#5508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5484:
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5485:
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e

WARNING: line length of 105 exceeds 100 columns
#5510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5486:
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5487:
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f

WARNING: line length of 105 exceeds 100 columns
#5512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5488:
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5489:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020

WARNING: line length of 105 exceeds 100 columns
#5514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5490:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5491:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021

WARNING: line length of 105 exceeds 100 columns
#5516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5492:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5493:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022

WARNING: line length of 105 exceeds 100 columns
#5518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5494:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5495:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023

WARNING: line length of 105 exceeds 100 columns
#5520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5496:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5497:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024

WARNING: line length of 105 exceeds 100 columns
#5522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5498:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5499:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025

WARNING: line length of 105 exceeds 100 columns
#5524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5500:
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5501:
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026

WARNING: line length of 105 exceeds 100 columns
#5526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5502:
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5503:
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027

WARNING: line length of 105 exceeds 100 columns
#5528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5504:
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5505:
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028

WARNING: line length of 105 exceeds 100 columns
#5530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5506:
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5507:
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029

WARNING: line length of 105 exceeds 100 columns
#5532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5508:
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5509:
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a

WARNING: line length of 105 exceeds 100 columns
#5534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5510:
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5511:
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b

WARNING: line length of 105 exceeds 100 columns
#5536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5512:
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5513:
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c

WARNING: line length of 105 exceeds 100 columns
#5538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5514:
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5515:
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d

WARNING: line length of 105 exceeds 100 columns
#5540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5516:
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5517:
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e

WARNING: line length of 105 exceeds 100 columns
#5542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5518:
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5519:
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f

WARNING: line length of 105 exceeds 100 columns
#5544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5520:
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5521:
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030

WARNING: line length of 105 exceeds 100 columns
#5546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5522:
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5523:
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031

WARNING: line length of 105 exceeds 100 columns
#5548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5524:
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5525:
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032

WARNING: line length of 105 exceeds 100 columns
#5550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5526:
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5527:
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033

WARNING: line length of 105 exceeds 100 columns
#5552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5528:
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5529:
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034

WARNING: line length of 105 exceeds 100 columns
#5554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5530:
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5531:
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035

WARNING: line length of 105 exceeds 100 columns
#5556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5532:
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5533:
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036

WARNING: line length of 105 exceeds 100 columns
#5558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5534:
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5535:
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037

WARNING: line length of 105 exceeds 100 columns
#5560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5536:
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5537:
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038

WARNING: line length of 105 exceeds 100 columns
#5562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5538:
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5539:
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039

WARNING: line length of 105 exceeds 100 columns
#5564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5540:
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5541:
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a

WARNING: line length of 105 exceeds 100 columns
#5566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5542:
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5543:
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b

WARNING: line length of 105 exceeds 100 columns
#5568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5544:
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5545:
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c

WARNING: line length of 105 exceeds 100 columns
#5570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5546:
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5547:
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d

WARNING: line length of 105 exceeds 100 columns
#5572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5548:
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5549:
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e

WARNING: line length of 105 exceeds 100 columns
#5574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5550:
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5551:
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f

WARNING: line length of 105 exceeds 100 columns
#5576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5552:
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5553:
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040

WARNING: line length of 105 exceeds 100 columns
#5578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5554:
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5555:
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041

WARNING: line length of 105 exceeds 100 columns
#5580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5556:
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5557:
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042

WARNING: line length of 105 exceeds 100 columns
#5582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5558:
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5559:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043

WARNING: line length of 105 exceeds 100 columns
#5584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5560:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5561:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044

WARNING: line length of 105 exceeds 100 columns
#5586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5562:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5563:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045

WARNING: line length of 105 exceeds 100 columns
#5588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5564:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5565:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046

WARNING: line length of 105 exceeds 100 columns
#5590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5566:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5567:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047

WARNING: line length of 105 exceeds 100 columns
#5592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5568:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5569:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048

WARNING: line length of 105 exceeds 100 columns
#5594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5570:
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5571:
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049

WARNING: line length of 105 exceeds 100 columns
#5596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5572:
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5573:
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a

WARNING: line length of 105 exceeds 100 columns
#5598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5574:
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5575:
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b

WARNING: line length of 105 exceeds 100 columns
#5600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5576:
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5577:
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c

WARNING: line length of 105 exceeds 100 columns
#5602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5578:
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5579:
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d

WARNING: line length of 105 exceeds 100 columns
#5604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5580:
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5581:
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e

WARNING: line length of 105 exceeds 100 columns
#5606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5582:
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5583:
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f

WARNING: line length of 105 exceeds 100 columns
#5608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5584:
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5585:
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050

WARNING: line length of 105 exceeds 100 columns
#5610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5586:
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5587:
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051

WARNING: line length of 105 exceeds 100 columns
#5612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5588:
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5589:
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052

WARNING: line length of 105 exceeds 100 columns
#5614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5590:
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5591:
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053

WARNING: line length of 105 exceeds 100 columns
#5616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5592:
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5593:
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054

WARNING: line length of 105 exceeds 100 columns
#5618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5594:
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5595:
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055

WARNING: line length of 105 exceeds 100 columns
#5620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5596:
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5597:
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056

WARNING: line length of 105 exceeds 100 columns
#5622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5598:
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5599:
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057

WARNING: line length of 105 exceeds 100 columns
#5624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5600:
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5601:
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058

WARNING: line length of 105 exceeds 100 columns
#5626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5602:
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5603:
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059

WARNING: line length of 105 exceeds 100 columns
#5628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5604:
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5605:
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a

WARNING: line length of 105 exceeds 100 columns
#5630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5606:
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5607:
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b

WARNING: line length of 105 exceeds 100 columns
#5632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5608:
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5609:
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c

WARNING: line length of 105 exceeds 100 columns
#5634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5610:
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5611:
+#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d

WARNING: line length of 105 exceeds 100 columns
#5636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5612:
+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5613:
+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e

WARNING: line length of 105 exceeds 100 columns
#5638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5614:
+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#5639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5615:
+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f

WARNING: line length of 105 exceeds 100 columns
#5640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5616:
+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5617:
+#define regCM2_CM_DEALPHA                                                                               0x1061

WARNING: line length of 105 exceeds 100 columns
#5642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5618:
+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5619:
+#define regCM2_CM_COEF_FORMAT                                                                           0x1062

WARNING: line length of 105 exceeds 100 columns
#5644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5620:
+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5625:
+#define regDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa

WARNING: line length of 105 exceeds 100 columns
#5650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5626:
+#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5627:
+#define regDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb

WARNING: line length of 105 exceeds 100 columns
#5652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5628:
+#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5629:
+#define regDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc

WARNING: line length of 105 exceeds 100 columns
#5654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5630:
+#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5631:
+#define regDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd

WARNING: line length of 105 exceeds 100 columns
#5656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5632:
+#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5633:
+#define regDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe

WARNING: line length of 105 exceeds 100 columns
#5658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5634:
+#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5635:
+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff

WARNING: line length of 105 exceeds 100 columns
#5660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5636:
+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5637:
+#define regDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100

WARNING: line length of 105 exceeds 100 columns
#5662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5638:
+#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5639:
+#define regDC_PERFMON13_PERFMON_HI                                                                      0x1101

WARNING: line length of 105 exceeds 100 columns
#5664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5640:
+#define regDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5641:
+#define regDC_PERFMON13_PERFMON_LOW                                                                     0x1102

WARNING: line length of 105 exceeds 100 columns
#5666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5642:
+#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5647:
+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106

WARNING: line length of 105 exceeds 100 columns
#5672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5648:
+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5649:
+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107

WARNING: line length of 105 exceeds 100 columns
#5674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5650:
+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5651:
+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108

WARNING: line length of 105 exceeds 100 columns
#5676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5652:
+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5653:
+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109

WARNING: line length of 105 exceeds 100 columns
#5678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5654:
+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5655:
+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a

WARNING: line length of 105 exceeds 100 columns
#5680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5656:
+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5657:
+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b

WARNING: line length of 105 exceeds 100 columns
#5682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5658:
+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5663:
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110

WARNING: line length of 105 exceeds 100 columns
#5688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5664:
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#5689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5665:
+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111

WARNING: line length of 105 exceeds 100 columns
#5690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5666:
+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5667:
+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112

WARNING: line length of 105 exceeds 100 columns
#5692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5668:
+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5669:
+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113

WARNING: line length of 105 exceeds 100 columns
#5694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5670:
+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5671:
+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114

WARNING: line length of 105 exceeds 100 columns
#5696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5672:
+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5673:
+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115

WARNING: line length of 105 exceeds 100 columns
#5698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5674:
+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5675:
+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116

WARNING: line length of 105 exceeds 100 columns
#5700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5676:
+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5677:
+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117

WARNING: line length of 105 exceeds 100 columns
#5702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5678:
+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5679:
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118

WARNING: line length of 105 exceeds 100 columns
#5704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5680:
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5681:
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119

WARNING: line length of 105 exceeds 100 columns
#5706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5682:
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5683:
+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a

WARNING: line length of 105 exceeds 100 columns
#5708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5684:
+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5685:
+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b

WARNING: line length of 105 exceeds 100 columns
#5710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5686:
+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5687:
+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c

WARNING: line length of 105 exceeds 100 columns
#5712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5688:
+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5689:
+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e

WARNING: line length of 105 exceeds 100 columns
#5714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5690:
+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5691:
+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f

WARNING: line length of 105 exceeds 100 columns
#5716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5692:
+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5693:
+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120

WARNING: line length of 105 exceeds 100 columns
#5718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5694:
+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#5719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5695:
+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121

WARNING: line length of 105 exceeds 100 columns
#5720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5696:
+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5697:
+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122

WARNING: line length of 105 exceeds 100 columns
#5722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5698:
+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5699:
+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123

WARNING: line length of 105 exceeds 100 columns
#5724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5700:
+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5701:
+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124

WARNING: line length of 105 exceeds 100 columns
#5726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5702:
+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5703:
+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125

WARNING: line length of 105 exceeds 100 columns
#5728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5704:
+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5705:
+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126

WARNING: line length of 105 exceeds 100 columns
#5730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5706:
+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5707:
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127

WARNING: line length of 105 exceeds 100 columns
#5732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5708:
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5709:
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128

WARNING: line length of 105 exceeds 100 columns
#5734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5710:
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5711:
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129

WARNING: line length of 105 exceeds 100 columns
#5736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5712:
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5713:
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a

WARNING: line length of 105 exceeds 100 columns
#5738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5714:
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5715:
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b

WARNING: line length of 105 exceeds 100 columns
#5740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5716:
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5717:
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c

WARNING: line length of 105 exceeds 100 columns
#5742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5718:
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5719:
+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d

WARNING: line length of 105 exceeds 100 columns
#5744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5720:
+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5721:
+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e

WARNING: line length of 105 exceeds 100 columns
#5746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5722:
+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#5747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5723:
+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f

WARNING: line length of 105 exceeds 100 columns
#5748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5724:
+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5729:
+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132

WARNING: line length of 105 exceeds 100 columns
#5754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5730:
+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5731:
+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133

WARNING: line length of 105 exceeds 100 columns
#5756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5732:
+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5733:
+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134

WARNING: line length of 105 exceeds 100 columns
#5758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5734:
+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#5759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5735:
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135

WARNING: line length of 105 exceeds 100 columns
#5760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5736:
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5741:
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a

WARNING: line length of 105 exceeds 100 columns
#5766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5742:
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5743:
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b

WARNING: line length of 105 exceeds 100 columns
#5768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5744:
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5745:
+#define regDSCL3_SCL_MODE                                                                               0x113c

WARNING: line length of 105 exceeds 100 columns
#5770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5746:
+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5747:
+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d

WARNING: line length of 105 exceeds 100 columns
#5772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5748:
+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5749:
+#define regDSCL3_DSCL_CONTROL                                                                           0x113e

WARNING: line length of 105 exceeds 100 columns
#5774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5750:
+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5751:
+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f

WARNING: line length of 105 exceeds 100 columns
#5776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5752:
+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5753:
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140

WARNING: line length of 105 exceeds 100 columns
#5778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5754:
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#5779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5755:
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141

WARNING: line length of 105 exceeds 100 columns
#5780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5756:
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#5781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5757:
+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142

WARNING: line length of 105 exceeds 100 columns
#5782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5758:
+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5759:
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143

WARNING: line length of 105 exceeds 100 columns
#5784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5760:
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#5785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5761:
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144

WARNING: line length of 105 exceeds 100 columns
#5786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5762:
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5763:
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145

WARNING: line length of 105 exceeds 100 columns
#5788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5764:
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#5789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5765:
+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146

WARNING: line length of 105 exceeds 100 columns
#5790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5766:
+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5767:
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147

WARNING: line length of 105 exceeds 100 columns
#5792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5768:
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5769:
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148

WARNING: line length of 105 exceeds 100 columns
#5794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5770:
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#5795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5771:
+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149

WARNING: line length of 105 exceeds 100 columns
#5796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5772:
+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5773:
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a

WARNING: line length of 105 exceeds 100 columns
#5798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5774:
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#5799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5775:
+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b

WARNING: line length of 105 exceeds 100 columns
#5800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5776:
+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5777:
+#define regDSCL3_DSCL_UPDATE                                                                            0x114c

WARNING: line length of 105 exceeds 100 columns
#5802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5778:
+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5779:
+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d

WARNING: line length of 105 exceeds 100 columns
#5804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5780:
+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5781:
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e

WARNING: line length of 105 exceeds 100 columns
#5806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5782:
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#5807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5783:
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f

WARNING: line length of 105 exceeds 100 columns
#5808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5784:
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#5809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5785:
+#define regDSCL3_OTG_H_BLANK                                                                            0x1150

WARNING: line length of 105 exceeds 100 columns
#5810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5786:
+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5787:
+#define regDSCL3_OTG_V_BLANK                                                                            0x1151

WARNING: line length of 105 exceeds 100 columns
#5812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5788:
+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5789:
+#define regDSCL3_RECOUT_START                                                                           0x1152

WARNING: line length of 105 exceeds 100 columns
#5814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5790:
+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5791:
+#define regDSCL3_RECOUT_SIZE                                                                            0x1153

WARNING: line length of 105 exceeds 100 columns
#5816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5792:
+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#5817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5793:
+#define regDSCL3_MPC_SIZE                                                                               0x1154

WARNING: line length of 105 exceeds 100 columns
#5818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5794:
+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5795:
+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155

WARNING: line length of 105 exceeds 100 columns
#5820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5796:
+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5797:
+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156

WARNING: line length of 105 exceeds 100 columns
#5822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5798:
+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5799:
+#define regDSCL3_LB_V_COUNTER                                                                           0x1157

WARNING: line length of 105 exceeds 100 columns
#5824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5800:
+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5801:
+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158

WARNING: line length of 105 exceeds 100 columns
#5826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5802:
+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5803:
+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159

WARNING: line length of 105 exceeds 100 columns
#5828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5804:
+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5805:
+#define regDSCL3_OBUF_CONTROL                                                                           0x115a

WARNING: line length of 105 exceeds 100 columns
#5830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5806:
+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#5831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5807:
+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b

WARNING: line length of 105 exceeds 100 columns
#5832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5808:
+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5813:
+#define regCM3_CM_CONTROL                                                                               0x1161

WARNING: line length of 105 exceeds 100 columns
#5838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5814:
+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#5839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5815:
+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162

WARNING: line length of 105 exceeds 100 columns
#5840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5816:
+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5817:
+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163

WARNING: line length of 105 exceeds 100 columns
#5842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5818:
+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5819:
+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164

WARNING: line length of 105 exceeds 100 columns
#5844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5820:
+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5821:
+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165

WARNING: line length of 105 exceeds 100 columns
#5846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5822:
+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5823:
+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166

WARNING: line length of 105 exceeds 100 columns
#5848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5824:
+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5825:
+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167

WARNING: line length of 105 exceeds 100 columns
#5850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5826:
+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5827:
+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168

WARNING: line length of 105 exceeds 100 columns
#5852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5828:
+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5829:
+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169

WARNING: line length of 105 exceeds 100 columns
#5854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5830:
+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5831:
+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a

WARNING: line length of 105 exceeds 100 columns
#5856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5832:
+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5833:
+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b

WARNING: line length of 105 exceeds 100 columns
#5858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5834:
+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5835:
+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c

WARNING: line length of 105 exceeds 100 columns
#5860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5836:
+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5837:
+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d

WARNING: line length of 105 exceeds 100 columns
#5862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5838:
+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5839:
+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e

WARNING: line length of 105 exceeds 100 columns
#5864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5840:
+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5841:
+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f

WARNING: line length of 105 exceeds 100 columns
#5866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5842:
+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5843:
+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170

WARNING: line length of 105 exceeds 100 columns
#5868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5844:
+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5845:
+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171

WARNING: line length of 105 exceeds 100 columns
#5870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5846:
+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5847:
+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172

WARNING: line length of 105 exceeds 100 columns
#5872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5848:
+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5849:
+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173

WARNING: line length of 105 exceeds 100 columns
#5874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5850:
+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5851:
+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174

WARNING: line length of 105 exceeds 100 columns
#5876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5852:
+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5853:
+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175

WARNING: line length of 105 exceeds 100 columns
#5878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5854:
+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#5879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5855:
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176

WARNING: line length of 105 exceeds 100 columns
#5880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5856:
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5857:
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177

WARNING: line length of 105 exceeds 100 columns
#5882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5858:
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5859:
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178

WARNING: line length of 105 exceeds 100 columns
#5884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5860:
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5861:
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179

WARNING: line length of 105 exceeds 100 columns
#5886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5862:
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5863:
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a

WARNING: line length of 105 exceeds 100 columns
#5888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5864:
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5865:
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b

WARNING: line length of 105 exceeds 100 columns
#5890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5866:
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#5891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5867:
+#define regCM3_CM_BIAS_CR_R                                                                             0x117c

WARNING: line length of 105 exceeds 100 columns
#5892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5868:
+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#5893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5869:
+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d

WARNING: line length of 105 exceeds 100 columns
#5894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5870:
+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#5895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5871:
+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e

WARNING: line length of 105 exceeds 100 columns
#5896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5872:
+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#5897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5873:
+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f

WARNING: line length of 105 exceeds 100 columns
#5898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5874:
+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#5899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5875:
+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180

WARNING: line length of 105 exceeds 100 columns
#5900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5876:
+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#5901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5877:
+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181

WARNING: line length of 105 exceeds 100 columns
#5902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5878:
+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#5903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5879:
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182

WARNING: line length of 105 exceeds 100 columns
#5904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5880:
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5881:
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183

WARNING: line length of 105 exceeds 100 columns
#5906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5882:
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5883:
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184

WARNING: line length of 105 exceeds 100 columns
#5908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5884:
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5885:
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185

WARNING: line length of 105 exceeds 100 columns
#5910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5886:
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5887:
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186

WARNING: line length of 105 exceeds 100 columns
#5912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5888:
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5889:
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187

WARNING: line length of 105 exceeds 100 columns
#5914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5890:
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5891:
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188

WARNING: line length of 105 exceeds 100 columns
#5916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5892:
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5893:
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189

WARNING: line length of 105 exceeds 100 columns
#5918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5894:
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5895:
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a

WARNING: line length of 105 exceeds 100 columns
#5920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5896:
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5897:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b

WARNING: line length of 105 exceeds 100 columns
#5922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5898:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5899:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c

WARNING: line length of 105 exceeds 100 columns
#5924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5900:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5901:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d

WARNING: line length of 105 exceeds 100 columns
#5926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5902:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5903:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e

WARNING: line length of 105 exceeds 100 columns
#5928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5904:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5905:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f

WARNING: line length of 105 exceeds 100 columns
#5930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5906:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5907:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190

WARNING: line length of 105 exceeds 100 columns
#5932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5908:
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5909:
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191

WARNING: line length of 105 exceeds 100 columns
#5934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5910:
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5911:
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192

WARNING: line length of 105 exceeds 100 columns
#5936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5912:
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5913:
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193

WARNING: line length of 105 exceeds 100 columns
#5938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5914:
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#5939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5915:
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194

WARNING: line length of 105 exceeds 100 columns
#5940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5916:
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5917:
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195

WARNING: line length of 105 exceeds 100 columns
#5942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5918:
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5919:
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196

WARNING: line length of 105 exceeds 100 columns
#5944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5920:
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5921:
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197

WARNING: line length of 105 exceeds 100 columns
#5946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5922:
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5923:
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198

WARNING: line length of 105 exceeds 100 columns
#5948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5924:
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#5949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5925:
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199

WARNING: line length of 105 exceeds 100 columns
#5950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5926:
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5927:
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a

WARNING: line length of 105 exceeds 100 columns
#5952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5928:
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5929:
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b

WARNING: line length of 105 exceeds 100 columns
#5954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5930:
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5931:
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c

WARNING: line length of 105 exceeds 100 columns
#5956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5932:
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5933:
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d

WARNING: line length of 105 exceeds 100 columns
#5958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5934:
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5935:
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e

WARNING: line length of 105 exceeds 100 columns
#5960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5936:
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5937:
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f

WARNING: line length of 105 exceeds 100 columns
#5962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5938:
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5939:
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0

WARNING: line length of 105 exceeds 100 columns
#5964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5940:
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5941:
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1

WARNING: line length of 105 exceeds 100 columns
#5966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5942:
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5943:
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2

WARNING: line length of 105 exceeds 100 columns
#5968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5944:
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5945:
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3

WARNING: line length of 105 exceeds 100 columns
#5970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5946:
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5947:
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4

WARNING: line length of 105 exceeds 100 columns
#5972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5948:
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5949:
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5

WARNING: line length of 105 exceeds 100 columns
#5974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5950:
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5951:
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6

WARNING: line length of 105 exceeds 100 columns
#5976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5952:
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5953:
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7

WARNING: line length of 105 exceeds 100 columns
#5978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5954:
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#5979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5955:
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8

WARNING: line length of 105 exceeds 100 columns
#5980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5956:
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5957:
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9

WARNING: line length of 105 exceeds 100 columns
#5982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5958:
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5959:
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa

WARNING: line length of 105 exceeds 100 columns
#5984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5960:
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#5985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5961:
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab

WARNING: line length of 105 exceeds 100 columns
#5986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5962:
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5963:
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac

WARNING: line length of 105 exceeds 100 columns
#5988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5964:
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5965:
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad

WARNING: line length of 105 exceeds 100 columns
#5990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5966:
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#5991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5967:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae

WARNING: line length of 105 exceeds 100 columns
#5992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5968:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5969:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af

WARNING: line length of 105 exceeds 100 columns
#5994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5970:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5971:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0

WARNING: line length of 105 exceeds 100 columns
#5996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5972:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5973:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1

WARNING: line length of 105 exceeds 100 columns
#5998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5974:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#5999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5975:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2

WARNING: line length of 105 exceeds 100 columns
#6000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5976:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5977:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3

WARNING: line length of 105 exceeds 100 columns
#6002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5978:
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5979:
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4

WARNING: line length of 105 exceeds 100 columns
#6004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5980:
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5981:
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5

WARNING: line length of 105 exceeds 100 columns
#6006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5982:
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5983:
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6

WARNING: line length of 105 exceeds 100 columns
#6008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5984:
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5985:
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7

WARNING: line length of 105 exceeds 100 columns
#6010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5986:
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5987:
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8

WARNING: line length of 105 exceeds 100 columns
#6012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5988:
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5989:
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9

WARNING: line length of 105 exceeds 100 columns
#6014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5990:
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5991:
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba

WARNING: line length of 105 exceeds 100 columns
#6016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5992:
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5993:
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb

WARNING: line length of 105 exceeds 100 columns
#6018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5994:
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5995:
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc

WARNING: line length of 105 exceeds 100 columns
#6020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5996:
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5997:
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd

WARNING: line length of 105 exceeds 100 columns
#6022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5998:
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:5999:
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be

WARNING: line length of 105 exceeds 100 columns
#6024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6000:
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6001:
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf

WARNING: line length of 105 exceeds 100 columns
#6026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6002:
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6003:
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0

WARNING: line length of 105 exceeds 100 columns
#6028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6004:
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6005:
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1

WARNING: line length of 105 exceeds 100 columns
#6030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6006:
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6007:
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2

WARNING: line length of 105 exceeds 100 columns
#6032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6008:
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6009:
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3

WARNING: line length of 105 exceeds 100 columns
#6034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6010:
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6011:
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4

WARNING: line length of 105 exceeds 100 columns
#6036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6012:
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6013:
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5

WARNING: line length of 105 exceeds 100 columns
#6038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6014:
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6015:
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6

WARNING: line length of 105 exceeds 100 columns
#6040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6016:
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6017:
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7

WARNING: line length of 105 exceeds 100 columns
#6042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6018:
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6019:
+#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8

WARNING: line length of 105 exceeds 100 columns
#6044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6020:
+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6021:
+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9

WARNING: line length of 105 exceeds 100 columns
#6046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6022:
+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6023:
+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca

WARNING: line length of 105 exceeds 100 columns
#6048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6024:
+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6025:
+#define regCM3_CM_DEALPHA                                                                               0x11cc

WARNING: line length of 105 exceeds 100 columns
#6050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6026:
+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#6051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6027:
+#define regCM3_CM_COEF_FORMAT                                                                           0x11cd

WARNING: line length of 105 exceeds 100 columns
#6052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6028:
+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#6057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6033:
+#define regDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265

WARNING: line length of 105 exceeds 100 columns
#6058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6034:
+#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6035:
+#define regDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266

WARNING: line length of 105 exceeds 100 columns
#6060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6036:
+#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6037:
+#define regDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267

WARNING: line length of 105 exceeds 100 columns
#6062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6038:
+#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6039:
+#define regDC_PERFMON14_PERFMON_CNTL                                                                    0x1268

WARNING: line length of 105 exceeds 100 columns
#6064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6040:
+#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6041:
+#define regDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269

WARNING: line length of 105 exceeds 100 columns
#6066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6042:
+#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6043:
+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a

WARNING: line length of 105 exceeds 100 columns
#6068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6044:
+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6045:
+#define regDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b

WARNING: line length of 105 exceeds 100 columns
#6070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6046:
+#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6047:
+#define regDC_PERFMON14_PERFMON_HI                                                                      0x126c

WARNING: line length of 105 exceeds 100 columns
#6072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6048:
+#define regDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6049:
+#define regDC_PERFMON14_PERFMON_LOW                                                                     0x126d

WARNING: line length of 105 exceeds 100 columns
#6074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6050:
+#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6055:
+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c

WARNING: line length of 105 exceeds 100 columns
#6080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6056:
+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6057:
+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d

WARNING: line length of 105 exceeds 100 columns
#6082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6058:
+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6059:
+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e

WARNING: line length of 105 exceeds 100 columns
#6084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6060:
+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6061:
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f

WARNING: line length of 105 exceeds 100 columns
#6086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6062:
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6063:
+#define regFMT0_FMT_CONTROL                                                                             0x1840

WARNING: line length of 105 exceeds 100 columns
#6088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6064:
+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6065:
+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841

WARNING: line length of 105 exceeds 100 columns
#6090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6066:
+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6067:
+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842

WARNING: line length of 105 exceeds 100 columns
#6092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6068:
+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6069:
+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843

WARNING: line length of 105 exceeds 100 columns
#6094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6070:
+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6071:
+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844

WARNING: line length of 105 exceeds 100 columns
#6096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6072:
+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6073:
+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845

WARNING: line length of 105 exceeds 100 columns
#6098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6074:
+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6075:
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846

WARNING: line length of 105 exceeds 100 columns
#6100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6076:
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6077:
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847

WARNING: line length of 105 exceeds 100 columns
#6102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6078:
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6079:
+#define regFMT0_FMT_422_CONTROL                                                                         0x1849

WARNING: line length of 105 exceeds 100 columns
#6104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6080:
+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6085:
+#define regDPG0_DPG_CONTROL                                                                             0x1854

WARNING: line length of 105 exceeds 100 columns
#6110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6086:
+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6087:
+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855

WARNING: line length of 105 exceeds 100 columns
#6112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6088:
+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6089:
+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856

WARNING: line length of 105 exceeds 100 columns
#6114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6090:
+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6091:
+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857

WARNING: line length of 105 exceeds 100 columns
#6116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6092:
+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6093:
+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858

WARNING: line length of 105 exceeds 100 columns
#6118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6094:
+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6095:
+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859

WARNING: line length of 105 exceeds 100 columns
#6120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6096:
+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6097:
+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a

WARNING: line length of 105 exceeds 100 columns
#6122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6098:
+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6099:
+#define regDPG0_DPG_STATUS                                                                              0x185b

WARNING: line length of 105 exceeds 100 columns
#6124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6100:
+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#6129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6105:
+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884

WARNING: line length of 105 exceeds 100 columns
#6130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6106:
+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6107:
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885

WARNING: line length of 105 exceeds 100 columns
#6132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6108:
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6109:
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886

WARNING: line length of 105 exceeds 100 columns
#6134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6110:
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6111:
+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889

WARNING: line length of 105 exceeds 100 columns
#6136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6112:
+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6117:
+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c

WARNING: line length of 105 exceeds 100 columns
#6142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6118:
+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6123:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891

WARNING: line length of 105 exceeds 100 columns
#6148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6124:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6125:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892

WARNING: line length of 105 exceeds 100 columns
#6150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6126:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6127:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893

WARNING: line length of 105 exceeds 100 columns
#6152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6128:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6129:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894

WARNING: line length of 105 exceeds 100 columns
#6154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6130:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6131:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895

WARNING: line length of 105 exceeds 100 columns
#6156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6132:
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6137:
+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896

WARNING: line length of 105 exceeds 100 columns
#6162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6138:
+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6139:
+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897

WARNING: line length of 105 exceeds 100 columns
#6164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6140:
+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6141:
+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898

WARNING: line length of 105 exceeds 100 columns
#6166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6142:
+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6143:
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899

WARNING: line length of 105 exceeds 100 columns
#6168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6144:
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6145:
+#define regFMT1_FMT_CONTROL                                                                             0x189a

WARNING: line length of 105 exceeds 100 columns
#6170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6146:
+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6147:
+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b

WARNING: line length of 105 exceeds 100 columns
#6172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6148:
+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6149:
+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c

WARNING: line length of 105 exceeds 100 columns
#6174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6150:
+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6151:
+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d

WARNING: line length of 105 exceeds 100 columns
#6176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6152:
+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6153:
+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e

WARNING: line length of 105 exceeds 100 columns
#6178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6154:
+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6155:
+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f

WARNING: line length of 105 exceeds 100 columns
#6180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6156:
+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6157:
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0

WARNING: line length of 105 exceeds 100 columns
#6182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6158:
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6159:
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1

WARNING: line length of 105 exceeds 100 columns
#6184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6160:
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6161:
+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3

WARNING: line length of 105 exceeds 100 columns
#6186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6162:
+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6167:
+#define regDPG1_DPG_CONTROL                                                                             0x18ae

WARNING: line length of 105 exceeds 100 columns
#6192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6168:
+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6169:
+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af

WARNING: line length of 105 exceeds 100 columns
#6194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6170:
+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6171:
+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0

WARNING: line length of 105 exceeds 100 columns
#6196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6172:
+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6173:
+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1

WARNING: line length of 105 exceeds 100 columns
#6198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6174:
+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6175:
+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2

WARNING: line length of 105 exceeds 100 columns
#6200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6176:
+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6177:
+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3

WARNING: line length of 105 exceeds 100 columns
#6202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6178:
+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6179:
+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4

WARNING: line length of 105 exceeds 100 columns
#6204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6180:
+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6181:
+#define regDPG1_DPG_STATUS                                                                              0x18b5

WARNING: line length of 105 exceeds 100 columns
#6206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6182:
+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#6210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6186:
+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de

WARNING: line length of 105 exceeds 100 columns
#6211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6187:
+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6188:
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df

WARNING: line length of 105 exceeds 100 columns
#6213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6189:
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6190:
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0

WARNING: line length of 105 exceeds 100 columns
#6215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6191:
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6192:
+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3

WARNING: line length of 105 exceeds 100 columns
#6217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6193:
+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6198:
+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6

WARNING: line length of 105 exceeds 100 columns
#6223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6199:
+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6204:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb

WARNING: line length of 105 exceeds 100 columns
#6229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6205:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6206:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec

WARNING: line length of 105 exceeds 100 columns
#6231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6207:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6208:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed

WARNING: line length of 105 exceeds 100 columns
#6233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6209:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6210:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee

WARNING: line length of 105 exceeds 100 columns
#6235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6211:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6212:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef

WARNING: line length of 105 exceeds 100 columns
#6237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6213:
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6218:
+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0

WARNING: line length of 105 exceeds 100 columns
#6243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6219:
+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6220:
+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1

WARNING: line length of 105 exceeds 100 columns
#6245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6221:
+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6222:
+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2

WARNING: line length of 105 exceeds 100 columns
#6247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6223:
+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6224:
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3

WARNING: line length of 105 exceeds 100 columns
#6249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6225:
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6226:
+#define regFMT2_FMT_CONTROL                                                                             0x18f4

WARNING: line length of 105 exceeds 100 columns
#6251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6227:
+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6228:
+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5

WARNING: line length of 105 exceeds 100 columns
#6253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6229:
+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6230:
+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6

WARNING: line length of 105 exceeds 100 columns
#6255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6231:
+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6232:
+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7

WARNING: line length of 105 exceeds 100 columns
#6257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6233:
+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6234:
+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8

WARNING: line length of 105 exceeds 100 columns
#6259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6235:
+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6236:
+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9

WARNING: line length of 105 exceeds 100 columns
#6261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6237:
+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6238:
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa

WARNING: line length of 105 exceeds 100 columns
#6263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6239:
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6240:
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb

WARNING: line length of 105 exceeds 100 columns
#6265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6241:
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6242:
+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd

WARNING: line length of 105 exceeds 100 columns
#6267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6243:
+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6248:
+#define regDPG2_DPG_CONTROL                                                                             0x1908

WARNING: line length of 105 exceeds 100 columns
#6273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6249:
+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6250:
+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909

WARNING: line length of 105 exceeds 100 columns
#6275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6251:
+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6252:
+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a

WARNING: line length of 105 exceeds 100 columns
#6277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6253:
+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6254:
+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b

WARNING: line length of 105 exceeds 100 columns
#6279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6255:
+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6256:
+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c

WARNING: line length of 105 exceeds 100 columns
#6281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6257:
+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6258:
+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d

WARNING: line length of 105 exceeds 100 columns
#6283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6259:
+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6260:
+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e

WARNING: line length of 105 exceeds 100 columns
#6285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6261:
+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6262:
+#define regDPG2_DPG_STATUS                                                                              0x190f

WARNING: line length of 105 exceeds 100 columns
#6287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6263:
+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#6292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6268:
+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938

WARNING: line length of 105 exceeds 100 columns
#6293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6269:
+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6270:
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939

WARNING: line length of 105 exceeds 100 columns
#6295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6271:
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6272:
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a

WARNING: line length of 105 exceeds 100 columns
#6297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6273:
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6274:
+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d

WARNING: line length of 105 exceeds 100 columns
#6299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6275:
+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6280:
+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940

WARNING: line length of 105 exceeds 100 columns
#6305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6281:
+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6286:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945

WARNING: line length of 105 exceeds 100 columns
#6311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6287:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6288:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946

WARNING: line length of 105 exceeds 100 columns
#6313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6289:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6290:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947

WARNING: line length of 105 exceeds 100 columns
#6315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6291:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6292:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948

WARNING: line length of 105 exceeds 100 columns
#6317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6293:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6294:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949

WARNING: line length of 105 exceeds 100 columns
#6319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6295:
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6300:
+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a

WARNING: line length of 105 exceeds 100 columns
#6325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6301:
+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6302:
+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b

WARNING: line length of 105 exceeds 100 columns
#6327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6303:
+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6304:
+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c

WARNING: line length of 105 exceeds 100 columns
#6329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6305:
+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6306:
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d

WARNING: line length of 105 exceeds 100 columns
#6331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6307:
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6308:
+#define regFMT3_FMT_CONTROL                                                                             0x194e

WARNING: line length of 105 exceeds 100 columns
#6333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6309:
+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6310:
+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f

WARNING: line length of 105 exceeds 100 columns
#6335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6311:
+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6312:
+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950

WARNING: line length of 105 exceeds 100 columns
#6337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6313:
+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6314:
+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951

WARNING: line length of 105 exceeds 100 columns
#6339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6315:
+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6316:
+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952

WARNING: line length of 105 exceeds 100 columns
#6341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6317:
+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6318:
+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953

WARNING: line length of 105 exceeds 100 columns
#6343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6319:
+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6320:
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954

WARNING: line length of 105 exceeds 100 columns
#6345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6321:
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6322:
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955

WARNING: line length of 105 exceeds 100 columns
#6347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6323:
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6324:
+#define regFMT3_FMT_422_CONTROL                                                                         0x1957

WARNING: line length of 105 exceeds 100 columns
#6349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6325:
+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6330:
+#define regDPG3_DPG_CONTROL                                                                             0x1962

WARNING: line length of 105 exceeds 100 columns
#6355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6331:
+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6332:
+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963

WARNING: line length of 105 exceeds 100 columns
#6357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6333:
+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6334:
+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964

WARNING: line length of 105 exceeds 100 columns
#6359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6335:
+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6336:
+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965

WARNING: line length of 105 exceeds 100 columns
#6361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6337:
+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6338:
+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966

WARNING: line length of 105 exceeds 100 columns
#6363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6339:
+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6340:
+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967

WARNING: line length of 105 exceeds 100 columns
#6365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6341:
+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6342:
+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968

WARNING: line length of 105 exceeds 100 columns
#6367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6343:
+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6344:
+#define regDPG3_DPG_STATUS                                                                              0x1969

WARNING: line length of 105 exceeds 100 columns
#6369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6345:
+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#6374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6350:
+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992

WARNING: line length of 105 exceeds 100 columns
#6375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6351:
+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6352:
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993

WARNING: line length of 105 exceeds 100 columns
#6377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6353:
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6354:
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994

WARNING: line length of 105 exceeds 100 columns
#6379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6355:
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6356:
+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997

WARNING: line length of 105 exceeds 100 columns
#6381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6357:
+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6362:
+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a

WARNING: line length of 105 exceeds 100 columns
#6387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6363:
+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6368:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f

WARNING: line length of 105 exceeds 100 columns
#6393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6369:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6370:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0

WARNING: line length of 105 exceeds 100 columns
#6395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6371:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6372:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1

WARNING: line length of 105 exceeds 100 columns
#6397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6373:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6374:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2

WARNING: line length of 105 exceeds 100 columns
#6399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6375:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6376:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3

WARNING: line length of 105 exceeds 100 columns
#6401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6377:
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6382:
+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e

WARNING: line length of 105 exceeds 100 columns
#6407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6383:
+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6384:
+#define regOPP_ABM_CONTROL                                                                              0x1a60

WARNING: line length of 105 exceeds 100 columns
#6409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6385:
+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#6414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6390:
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64

WARNING: line length of 105 exceeds 100 columns
#6415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6391:
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6396:
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65

WARNING: line length of 105 exceeds 100 columns
#6421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6397:
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6402:
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66

WARNING: line length of 105 exceeds 100 columns
#6427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6403:
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6408:
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67

WARNING: line length of 105 exceeds 100 columns
#6433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6409:
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6414:
+#define regDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe

WARNING: line length of 105 exceeds 100 columns
#6439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6415:
+#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6416:
+#define regDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf

WARNING: line length of 105 exceeds 100 columns
#6441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6417:
+#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6418:
+#define regDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0

WARNING: line length of 105 exceeds 100 columns
#6443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6419:
+#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6420:
+#define regDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1

WARNING: line length of 105 exceeds 100 columns
#6445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6421:
+#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6422:
+#define regDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2

WARNING: line length of 105 exceeds 100 columns
#6447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6423:
+#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6424:
+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3

WARNING: line length of 105 exceeds 100 columns
#6449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6425:
+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6426:
+#define regDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4

WARNING: line length of 105 exceeds 100 columns
#6451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6427:
+#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6428:
+#define regDC_PERFMON16_PERFMON_HI                                                                      0x1ac5

WARNING: line length of 105 exceeds 100 columns
#6453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6429:
+#define regDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6430:
+#define regDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6

WARNING: line length of 105 exceeds 100 columns
#6455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6431:
+#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6436:
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca

WARNING: line length of 105 exceeds 100 columns
#6461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6437:
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6438:
+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb

WARNING: line length of 105 exceeds 100 columns
#6463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6439:
+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#6464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6440:
+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc

WARNING: line length of 105 exceeds 100 columns
#6465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6441:
+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6442:
+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd

WARNING: line length of 105 exceeds 100 columns
#6467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6443:
+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6444:
+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace

WARNING: line length of 105 exceeds 100 columns
#6469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6445:
+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6446:
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf

WARNING: line length of 105 exceeds 100 columns
#6471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6447:
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6448:
+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0

WARNING: line length of 105 exceeds 100 columns
#6473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6449:
+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6450:
+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1

WARNING: line length of 105 exceeds 100 columns
#6475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6451:
+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6456:
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada

WARNING: line length of 105 exceeds 100 columns
#6481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6457:
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6458:
+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb

WARNING: line length of 105 exceeds 100 columns
#6483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6459:
+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#6484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6460:
+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc

WARNING: line length of 105 exceeds 100 columns
#6485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6461:
+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6462:
+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add

WARNING: line length of 105 exceeds 100 columns
#6487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6463:
+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6464:
+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade

WARNING: line length of 105 exceeds 100 columns
#6489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6465:
+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6466:
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf

WARNING: line length of 105 exceeds 100 columns
#6491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6467:
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6468:
+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0

WARNING: line length of 105 exceeds 100 columns
#6493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6469:
+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6470:
+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1

WARNING: line length of 105 exceeds 100 columns
#6495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6471:
+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6476:
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea

WARNING: line length of 105 exceeds 100 columns
#6501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6477:
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6478:
+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb

WARNING: line length of 105 exceeds 100 columns
#6503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6479:
+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#6504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6480:
+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec

WARNING: line length of 105 exceeds 100 columns
#6505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6481:
+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6482:
+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed

WARNING: line length of 105 exceeds 100 columns
#6507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6483:
+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6484:
+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee

WARNING: line length of 105 exceeds 100 columns
#6509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6485:
+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6486:
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef

WARNING: line length of 105 exceeds 100 columns
#6511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6487:
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6488:
+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0

WARNING: line length of 105 exceeds 100 columns
#6513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6489:
+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6490:
+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1

WARNING: line length of 105 exceeds 100 columns
#6515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6491:
+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6496:
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa

WARNING: line length of 105 exceeds 100 columns
#6521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6497:
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6498:
+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb

WARNING: line length of 105 exceeds 100 columns
#6523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6499:
+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#6524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6500:
+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc

WARNING: line length of 105 exceeds 100 columns
#6525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6501:
+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6502:
+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd

WARNING: line length of 105 exceeds 100 columns
#6527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6503:
+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6504:
+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe

WARNING: line length of 105 exceeds 100 columns
#6529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6505:
+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6506:
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff

WARNING: line length of 105 exceeds 100 columns
#6531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6507:
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6508:
+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00

WARNING: line length of 105 exceeds 100 columns
#6533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6509:
+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6510:
+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01

WARNING: line length of 105 exceeds 100 columns
#6535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6511:
+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6516:
+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a

WARNING: line length of 105 exceeds 100 columns
#6541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6517:
+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6518:
+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b

WARNING: line length of 105 exceeds 100 columns
#6543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6519:
+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6520:
+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c

WARNING: line length of 105 exceeds 100 columns
#6545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6521:
+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#6546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6522:
+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d

WARNING: line length of 105 exceeds 100 columns
#6547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6523:
+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6524:
+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e

WARNING: line length of 105 exceeds 100 columns
#6549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6525:
+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6526:
+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f

WARNING: line length of 105 exceeds 100 columns
#6551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6527:
+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6528:
+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30

WARNING: line length of 105 exceeds 100 columns
#6553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6529:
+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6530:
+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31

WARNING: line length of 105 exceeds 100 columns
#6555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6531:
+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6532:
+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32

WARNING: line length of 105 exceeds 100 columns
#6557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6533:
+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6534:
+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33

WARNING: line length of 105 exceeds 100 columns
#6559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6535:
+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6536:
+#define regOTG0_OTG_V_COUNT_STOP_CONTROL                                                                0x1b34

WARNING: line length of 105 exceeds 100 columns
#6561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6537:
+#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6538:
+#define regOTG0_OTG_V_COUNT_STOP_CONTROL2                                                               0x1b35

WARNING: line length of 105 exceeds 100 columns
#6563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6539:
+#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6540:
+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b36

WARNING: line length of 105 exceeds 100 columns
#6565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6541:
+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6542:
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b37

WARNING: line length of 105 exceeds 100 columns
#6567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6543:
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6544:
+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b38

WARNING: line length of 105 exceeds 100 columns
#6569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6545:
+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6546:
+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b39

WARNING: line length of 105 exceeds 100 columns
#6571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6547:
+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#6572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6548:
+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b3a

WARNING: line length of 105 exceeds 100 columns
#6573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6549:
+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6550:
+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b3b

WARNING: line length of 105 exceeds 100 columns
#6575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6551:
+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6552:
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3c

WARNING: line length of 105 exceeds 100 columns
#6577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6553:
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6554:
+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3d

WARNING: line length of 105 exceeds 100 columns
#6579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6555:
+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6556:
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3e

WARNING: line length of 105 exceeds 100 columns
#6581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6557:
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6558:
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3f

WARNING: line length of 105 exceeds 100 columns
#6583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6559:
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6560:
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b41

WARNING: line length of 105 exceeds 100 columns
#6585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6561:
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6562:
+#define regOTG0_OTG_CONTROL                                                                             0x1b43

WARNING: line length of 105 exceeds 100 columns
#6587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6563:
+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6564:
+#define regOTG0_OTG_DLPC_CONTROL                                                                        0x1b44

WARNING: line length of 105 exceeds 100 columns
#6589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6565:
+#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6566:
+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b45

WARNING: line length of 105 exceeds 100 columns
#6591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6567:
+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6568:
+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b46

WARNING: line length of 105 exceeds 100 columns
#6593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6569:
+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6570:
+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47

WARNING: line length of 105 exceeds 100 columns
#6595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6571:
+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6572:
+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48

WARNING: line length of 105 exceeds 100 columns
#6597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6573:
+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6574:
+#define regOTG0_OTG_STATUS                                                                              0x1b49

WARNING: line length of 105 exceeds 100 columns
#6599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6575:
+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#6600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6576:
+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a

WARNING: line length of 105 exceeds 100 columns
#6601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6577:
+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6578:
+#define regOTG0_OTG_LONG_VBLANK_STATUS                                                                  0x1b4b

WARNING: line length of 105 exceeds 100 columns
#6603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6579:
+#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6580:
+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4c

WARNING: line length of 105 exceeds 100 columns
#6605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6581:
+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6582:
+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4d

WARNING: line length of 105 exceeds 100 columns
#6607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6583:
+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6584:
+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4e

WARNING: line length of 105 exceeds 100 columns
#6609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6585:
+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6586:
+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4f

WARNING: line length of 105 exceeds 100 columns
#6611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6587:
+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6588:
+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b50

WARNING: line length of 105 exceeds 100 columns
#6613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6589:
+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6590:
+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b51

WARNING: line length of 105 exceeds 100 columns
#6615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6591:
+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6592:
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b52

WARNING: line length of 105 exceeds 100 columns
#6617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6593:
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6594:
+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b53

WARNING: line length of 105 exceeds 100 columns
#6619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6595:
+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6596:
+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b54

WARNING: line length of 105 exceeds 100 columns
#6621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6597:
+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6598:
+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b55

WARNING: line length of 105 exceeds 100 columns
#6623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6599:
+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6600:
+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b56

WARNING: line length of 105 exceeds 100 columns
#6625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6601:
+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6602:
+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b57

WARNING: line length of 105 exceeds 100 columns
#6627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6603:
+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6604:
+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b58

WARNING: line length of 105 exceeds 100 columns
#6629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6605:
+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6606:
+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b59

WARNING: line length of 105 exceeds 100 columns
#6631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6607:
+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6608:
+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b5a

WARNING: line length of 105 exceeds 100 columns
#6633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6609:
+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6610:
+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5b

WARNING: line length of 105 exceeds 100 columns
#6635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6611:
+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6612:
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5c

WARNING: line length of 105 exceeds 100 columns
#6637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6613:
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6614:
+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5d

WARNING: line length of 105 exceeds 100 columns
#6639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6615:
+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#6640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6616:
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b5f

WARNING: line length of 105 exceeds 100 columns
#6641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6617:
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6618:
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b60

WARNING: line length of 105 exceeds 100 columns
#6643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6619:
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6620:
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b61

WARNING: line length of 105 exceeds 100 columns
#6645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6621:
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6622:
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b62

WARNING: line length of 105 exceeds 100 columns
#6647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6623:
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6624:
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b63

WARNING: line length of 105 exceeds 100 columns
#6649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6625:
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6626:
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b64

WARNING: line length of 105 exceeds 100 columns
#6651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6627:
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6628:
+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b65

WARNING: line length of 105 exceeds 100 columns
#6653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6629:
+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#6654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6630:
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b66

WARNING: line length of 105 exceeds 100 columns
#6655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6631:
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6632:
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b67

WARNING: line length of 105 exceeds 100 columns
#6657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6633:
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6634:
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b68

WARNING: line length of 105 exceeds 100 columns
#6659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6635:
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6636:
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b69

WARNING: line length of 105 exceeds 100 columns
#6661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6637:
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6638:
+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6a

WARNING: line length of 105 exceeds 100 columns
#6663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6639:
+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6640:
+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6b

WARNING: line length of 105 exceeds 100 columns
#6665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6641:
+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6642:
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6c

WARNING: line length of 105 exceeds 100 columns
#6667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6643:
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6644:
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b6d

WARNING: line length of 105 exceeds 100 columns
#6669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6645:
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6646:
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b6e

WARNING: line length of 105 exceeds 100 columns
#6671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6647:
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6648:
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b6f

WARNING: line length of 105 exceeds 100 columns
#6673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6649:
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6650:
+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b70

WARNING: line length of 105 exceeds 100 columns
#6675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6651:
+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6652:
+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b71

WARNING: line length of 105 exceeds 100 columns
#6677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6653:
+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6654:
+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b72

WARNING: line length of 105 exceeds 100 columns
#6679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6655:
+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6656:
+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b73

WARNING: line length of 105 exceeds 100 columns
#6681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6657:
+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6658:
+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b74

WARNING: line length of 105 exceeds 100 columns
#6683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6659:
+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6660:
+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b75

WARNING: line length of 105 exceeds 100 columns
#6685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6661:
+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6662:
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b76

WARNING: line length of 105 exceeds 100 columns
#6687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6663:
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6664:
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b77

WARNING: line length of 105 exceeds 100 columns
#6689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6665:
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6666:
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1b78

WARNING: line length of 105 exceeds 100 columns
#6691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6667:
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6668:
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1b79

WARNING: line length of 105 exceeds 100 columns
#6693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6669:
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6670:
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1b7a

WARNING: line length of 105 exceeds 100 columns
#6695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6671:
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6672:
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7b

WARNING: line length of 105 exceeds 100 columns
#6697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6673:
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6674:
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1b7c

WARNING: line length of 105 exceeds 100 columns
#6699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6675:
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6676:
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1b7d

WARNING: line length of 105 exceeds 100 columns
#6701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6677:
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6678:
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1b7e

WARNING: line length of 105 exceeds 100 columns
#6703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6679:
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6680:
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7f

WARNING: line length of 105 exceeds 100 columns
#6705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6681:
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6682:
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b80

WARNING: line length of 105 exceeds 100 columns
#6707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6683:
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6684:
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b81

WARNING: line length of 105 exceeds 100 columns
#6709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6685:
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6686:
+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b82

WARNING: line length of 105 exceeds 100 columns
#6711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6687:
+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6688:
+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b83

WARNING: line length of 105 exceeds 100 columns
#6713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6689:
+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6690:
+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b84

WARNING: line length of 105 exceeds 100 columns
#6715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6691:
+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6692:
+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b85

WARNING: line length of 105 exceeds 100 columns
#6717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6693:
+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6694:
+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b86

WARNING: line length of 105 exceeds 100 columns
#6719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6695:
+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6696:
+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b87

WARNING: line length of 105 exceeds 100 columns
#6721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6697:
+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6698:
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b88

WARNING: line length of 105 exceeds 100 columns
#6723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6699:
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6700:
+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b89

WARNING: line length of 105 exceeds 100 columns
#6725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6701:
+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6702:
+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8a

WARNING: line length of 105 exceeds 100 columns
#6727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6703:
+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6704:
+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8b

WARNING: line length of 105 exceeds 100 columns
#6729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6705:
+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6706:
+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8c

WARNING: line length of 105 exceeds 100 columns
#6731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6707:
+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6708:
+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8d

WARNING: line length of 105 exceeds 100 columns
#6733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6709:
+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6710:
+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8e

WARNING: line length of 105 exceeds 100 columns
#6735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6711:
+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6712:
+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b8f

WARNING: line length of 105 exceeds 100 columns
#6737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6713:
+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6714:
+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b90

WARNING: line length of 105 exceeds 100 columns
#6739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6715:
+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6716:
+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b91

WARNING: line length of 105 exceeds 100 columns
#6741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6717:
+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6718:
+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b92

WARNING: line length of 105 exceeds 100 columns
#6743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6719:
+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6720:
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b93

WARNING: line length of 105 exceeds 100 columns
#6745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6721:
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#6746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6722:
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b95

WARNING: line length of 105 exceeds 100 columns
#6747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6723:
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6724:
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b96

WARNING: line length of 105 exceeds 100 columns
#6749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6725:
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#6750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6726:
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b97

WARNING: line length of 105 exceeds 100 columns
#6751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6727:
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6728:
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b98

WARNING: line length of 105 exceeds 100 columns
#6753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6729:
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6730:
+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b99

WARNING: line length of 105 exceeds 100 columns
#6755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6731:
+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6732:
+#define regOTG0_OTG_DRR_CONTOL2                                                                         0x1b9a

WARNING: line length of 105 exceeds 100 columns
#6757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6733:
+#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6734:
+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b

WARNING: line length of 105 exceeds 100 columns
#6759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6735:
+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6736:
+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c

WARNING: line length of 105 exceeds 100 columns
#6761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6737:
+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6738:
+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d

WARNING: line length of 105 exceeds 100 columns
#6763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6739:
+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6740:
+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9e

WARNING: line length of 105 exceeds 100 columns
#6765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6741:
+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6742:
+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9f

WARNING: line length of 105 exceeds 100 columns
#6767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6743:
+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6744:
+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba0

WARNING: line length of 105 exceeds 100 columns
#6769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6745:
+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6750:
+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa

WARNING: line length of 105 exceeds 100 columns
#6775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6751:
+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6752:
+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab

WARNING: line length of 105 exceeds 100 columns
#6777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6753:
+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6754:
+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac

WARNING: line length of 105 exceeds 100 columns
#6779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6755:
+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#6780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6756:
+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad

WARNING: line length of 105 exceeds 100 columns
#6781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6757:
+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6758:
+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae

WARNING: line length of 105 exceeds 100 columns
#6783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6759:
+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6760:
+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf

WARNING: line length of 105 exceeds 100 columns
#6785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6761:
+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6762:
+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0

WARNING: line length of 105 exceeds 100 columns
#6787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6763:
+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6764:
+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1

WARNING: line length of 105 exceeds 100 columns
#6789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6765:
+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6766:
+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2

WARNING: line length of 105 exceeds 100 columns
#6791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6767:
+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6768:
+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3

WARNING: line length of 105 exceeds 100 columns
#6793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6769:
+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6770:
+#define regOTG1_OTG_V_COUNT_STOP_CONTROL                                                                0x1bb4

WARNING: line length of 105 exceeds 100 columns
#6795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6771:
+#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6772:
+#define regOTG1_OTG_V_COUNT_STOP_CONTROL2                                                               0x1bb5

WARNING: line length of 105 exceeds 100 columns
#6797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6773:
+#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6774:
+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb6

WARNING: line length of 105 exceeds 100 columns
#6799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6775:
+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6776:
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb7

WARNING: line length of 105 exceeds 100 columns
#6801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6777:
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6778:
+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb8

WARNING: line length of 105 exceeds 100 columns
#6803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6779:
+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6780:
+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb9

WARNING: line length of 105 exceeds 100 columns
#6805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6781:
+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#6806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6782:
+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bba

WARNING: line length of 105 exceeds 100 columns
#6807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6783:
+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6784:
+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bbb

WARNING: line length of 105 exceeds 100 columns
#6809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6785:
+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6786:
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bbc

WARNING: line length of 105 exceeds 100 columns
#6811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6787:
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6788:
+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbd

WARNING: line length of 105 exceeds 100 columns
#6813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6789:
+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#6814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6790:
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbe

WARNING: line length of 105 exceeds 100 columns
#6815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6791:
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6792:
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbf

WARNING: line length of 105 exceeds 100 columns
#6817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6793:
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6794:
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bc1

WARNING: line length of 105 exceeds 100 columns
#6819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6795:
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6796:
+#define regOTG1_OTG_CONTROL                                                                             0x1bc3

WARNING: line length of 105 exceeds 100 columns
#6821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6797:
+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#6822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6798:
+#define regOTG1_OTG_DLPC_CONTROL                                                                        0x1bc4

WARNING: line length of 105 exceeds 100 columns
#6823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6799:
+#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6800:
+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc5

WARNING: line length of 105 exceeds 100 columns
#6825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6801:
+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6802:
+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc6

WARNING: line length of 105 exceeds 100 columns
#6827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6803:
+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6804:
+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7

WARNING: line length of 105 exceeds 100 columns
#6829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6805:
+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6806:
+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8

WARNING: line length of 105 exceeds 100 columns
#6831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6807:
+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6808:
+#define regOTG1_OTG_STATUS                                                                              0x1bc9

WARNING: line length of 105 exceeds 100 columns
#6833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6809:
+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#6834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6810:
+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca

WARNING: line length of 105 exceeds 100 columns
#6835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6811:
+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6812:
+#define regOTG1_OTG_LONG_VBLANK_STATUS                                                                  0x1bcb

WARNING: line length of 105 exceeds 100 columns
#6837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6813:
+#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6814:
+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcc

WARNING: line length of 105 exceeds 100 columns
#6839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6815:
+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6816:
+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcd

WARNING: line length of 105 exceeds 100 columns
#6841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6817:
+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6818:
+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bce

WARNING: line length of 105 exceeds 100 columns
#6843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6819:
+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6820:
+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bcf

WARNING: line length of 105 exceeds 100 columns
#6845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6821:
+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6822:
+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bd0

WARNING: line length of 105 exceeds 100 columns
#6847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6823:
+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6824:
+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd1

WARNING: line length of 105 exceeds 100 columns
#6849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6825:
+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6826:
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd2

WARNING: line length of 105 exceeds 100 columns
#6851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6827:
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6828:
+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd3

WARNING: line length of 105 exceeds 100 columns
#6853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6829:
+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6830:
+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd4

WARNING: line length of 105 exceeds 100 columns
#6855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6831:
+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6832:
+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd5

WARNING: line length of 105 exceeds 100 columns
#6857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6833:
+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6834:
+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd6

WARNING: line length of 105 exceeds 100 columns
#6859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6835:
+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6836:
+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd7

WARNING: line length of 105 exceeds 100 columns
#6861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6837:
+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#6862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6838:
+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd8

WARNING: line length of 105 exceeds 100 columns
#6863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6839:
+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6840:
+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd9

WARNING: line length of 105 exceeds 100 columns
#6865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6841:
+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6842:
+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bda

WARNING: line length of 105 exceeds 100 columns
#6867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6843:
+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#6868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6844:
+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bdb

WARNING: line length of 105 exceeds 100 columns
#6869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6845:
+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6846:
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdc

WARNING: line length of 105 exceeds 100 columns
#6871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6847:
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6848:
+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdd

WARNING: line length of 105 exceeds 100 columns
#6873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6849:
+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#6874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6850:
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1bdf

WARNING: line length of 105 exceeds 100 columns
#6875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6851:
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6852:
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be0

WARNING: line length of 105 exceeds 100 columns
#6877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6853:
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6854:
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be1

WARNING: line length of 105 exceeds 100 columns
#6879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6855:
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6856:
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be2

WARNING: line length of 105 exceeds 100 columns
#6881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6857:
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6858:
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be3

WARNING: line length of 105 exceeds 100 columns
#6883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6859:
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#6884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6860:
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be4

WARNING: line length of 105 exceeds 100 columns
#6885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6861:
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#6886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6862:
+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be5

WARNING: line length of 105 exceeds 100 columns
#6887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6863:
+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#6888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6864:
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be6

WARNING: line length of 105 exceeds 100 columns
#6889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6865:
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6866:
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1be7

WARNING: line length of 105 exceeds 100 columns
#6891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6867:
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6868:
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1be8

WARNING: line length of 105 exceeds 100 columns
#6893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6869:
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6870:
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1be9

WARNING: line length of 105 exceeds 100 columns
#6895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6871:
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6872:
+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bea

WARNING: line length of 105 exceeds 100 columns
#6897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6873:
+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6874:
+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1beb

WARNING: line length of 105 exceeds 100 columns
#6899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6875:
+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6876:
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bec

WARNING: line length of 105 exceeds 100 columns
#6901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6877:
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6878:
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bed

WARNING: line length of 105 exceeds 100 columns
#6903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6879:
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6880:
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bee

WARNING: line length of 105 exceeds 100 columns
#6905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6881:
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6882:
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bef

WARNING: line length of 105 exceeds 100 columns
#6907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6883:
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6884:
+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf0

WARNING: line length of 105 exceeds 100 columns
#6909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6885:
+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6886:
+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf1

WARNING: line length of 105 exceeds 100 columns
#6911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6887:
+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6888:
+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf2

WARNING: line length of 105 exceeds 100 columns
#6913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6889:
+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6890:
+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf3

WARNING: line length of 105 exceeds 100 columns
#6915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6891:
+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6892:
+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf4

WARNING: line length of 105 exceeds 100 columns
#6917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6893:
+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6894:
+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf5

WARNING: line length of 105 exceeds 100 columns
#6919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6895:
+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6896:
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf6

WARNING: line length of 105 exceeds 100 columns
#6921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6897:
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#6922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6898:
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bf7

WARNING: line length of 105 exceeds 100 columns
#6923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6899:
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#6924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6900:
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1bf8

WARNING: line length of 105 exceeds 100 columns
#6925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6901:
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6902:
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1bf9

WARNING: line length of 105 exceeds 100 columns
#6927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6903:
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6904:
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1bfa

WARNING: line length of 105 exceeds 100 columns
#6929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6905:
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6906:
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1bfb

WARNING: line length of 105 exceeds 100 columns
#6931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6907:
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6908:
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1bfc

WARNING: line length of 105 exceeds 100 columns
#6933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6909:
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6910:
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1bfd

WARNING: line length of 105 exceeds 100 columns
#6935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6911:
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6912:
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1bfe

WARNING: line length of 105 exceeds 100 columns
#6937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6913:
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6914:
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1bff

WARNING: line length of 105 exceeds 100 columns
#6939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6915:
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#6940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6916:
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c00

WARNING: line length of 105 exceeds 100 columns
#6941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6917:
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6918:
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c01

WARNING: line length of 105 exceeds 100 columns
#6943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6919:
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#6944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6920:
+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c02

WARNING: line length of 105 exceeds 100 columns
#6945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6921:
+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6922:
+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c03

WARNING: line length of 105 exceeds 100 columns
#6947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6923:
+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6924:
+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c04

WARNING: line length of 105 exceeds 100 columns
#6949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6925:
+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6926:
+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c05

WARNING: line length of 105 exceeds 100 columns
#6951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6927:
+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#6952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6928:
+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c06

WARNING: line length of 105 exceeds 100 columns
#6953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6929:
+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#6954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6930:
+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c07

WARNING: line length of 105 exceeds 100 columns
#6955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6931:
+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6932:
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c08

WARNING: line length of 105 exceeds 100 columns
#6957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6933:
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6934:
+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c09

WARNING: line length of 105 exceeds 100 columns
#6959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6935:
+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6936:
+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0a

WARNING: line length of 105 exceeds 100 columns
#6961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6937:
+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6938:
+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0b

WARNING: line length of 105 exceeds 100 columns
#6963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6939:
+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6940:
+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0c

WARNING: line length of 105 exceeds 100 columns
#6965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6941:
+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6942:
+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0d

WARNING: line length of 105 exceeds 100 columns
#6967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6943:
+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6944:
+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0e

WARNING: line length of 105 exceeds 100 columns
#6969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6945:
+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6946:
+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c0f

WARNING: line length of 105 exceeds 100 columns
#6971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6947:
+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6948:
+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c10

WARNING: line length of 105 exceeds 100 columns
#6973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6949:
+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6950:
+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c11

WARNING: line length of 105 exceeds 100 columns
#6975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6951:
+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6952:
+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c12

WARNING: line length of 105 exceeds 100 columns
#6977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6953:
+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6954:
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c13

WARNING: line length of 105 exceeds 100 columns
#6979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6955:
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#6980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6956:
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c15

WARNING: line length of 105 exceeds 100 columns
#6981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6957:
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#6982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6958:
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c16

WARNING: line length of 105 exceeds 100 columns
#6983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6959:
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#6984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6960:
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c17

WARNING: line length of 105 exceeds 100 columns
#6985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6961:
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6962:
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c18

WARNING: line length of 105 exceeds 100 columns
#6987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6963:
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#6988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6964:
+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c19

WARNING: line length of 105 exceeds 100 columns
#6989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6965:
+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6966:
+#define regOTG1_OTG_DRR_CONTOL2                                                                         0x1c1a

WARNING: line length of 105 exceeds 100 columns
#6991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6967:
+#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#6992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6968:
+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b

WARNING: line length of 105 exceeds 100 columns
#6993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6969:
+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6970:
+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c

WARNING: line length of 105 exceeds 100 columns
#6995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6971:
+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#6996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6972:
+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d

WARNING: line length of 105 exceeds 100 columns
#6997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6973:
+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#6998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6974:
+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1e

WARNING: line length of 105 exceeds 100 columns
#6999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6975:
+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6976:
+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1f

WARNING: line length of 105 exceeds 100 columns
#7001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6977:
+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6978:
+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c20

WARNING: line length of 105 exceeds 100 columns
#7003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6979:
+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6984:
+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a

WARNING: line length of 105 exceeds 100 columns
#7009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6985:
+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6986:
+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b

WARNING: line length of 105 exceeds 100 columns
#7011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6987:
+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6988:
+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c

WARNING: line length of 105 exceeds 100 columns
#7013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6989:
+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6990:
+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d

WARNING: line length of 105 exceeds 100 columns
#7015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6991:
+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6992:
+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e

WARNING: line length of 105 exceeds 100 columns
#7017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6993:
+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6994:
+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f

WARNING: line length of 105 exceeds 100 columns
#7019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6995:
+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6996:
+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30

WARNING: line length of 105 exceeds 100 columns
#7021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6997:
+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6998:
+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31

WARNING: line length of 105 exceeds 100 columns
#7023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:6999:
+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7000:
+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32

WARNING: line length of 105 exceeds 100 columns
#7025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7001:
+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7002:
+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33

WARNING: line length of 105 exceeds 100 columns
#7027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7003:
+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7004:
+#define regOTG2_OTG_V_COUNT_STOP_CONTROL                                                                0x1c34

WARNING: line length of 105 exceeds 100 columns
#7029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7005:
+#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7006:
+#define regOTG2_OTG_V_COUNT_STOP_CONTROL2                                                               0x1c35

WARNING: line length of 105 exceeds 100 columns
#7031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7007:
+#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7008:
+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c36

WARNING: line length of 105 exceeds 100 columns
#7033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7009:
+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7010:
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c37

WARNING: line length of 105 exceeds 100 columns
#7035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7011:
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7012:
+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c38

WARNING: line length of 105 exceeds 100 columns
#7037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7013:
+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7014:
+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c39

WARNING: line length of 105 exceeds 100 columns
#7039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7015:
+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7016:
+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c3a

WARNING: line length of 105 exceeds 100 columns
#7041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7017:
+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7018:
+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c3b

WARNING: line length of 105 exceeds 100 columns
#7043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7019:
+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7020:
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3c

WARNING: line length of 105 exceeds 100 columns
#7045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7021:
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7022:
+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3d

WARNING: line length of 105 exceeds 100 columns
#7047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7023:
+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7024:
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3e

WARNING: line length of 105 exceeds 100 columns
#7049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7025:
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7026:
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3f

WARNING: line length of 105 exceeds 100 columns
#7051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7027:
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7028:
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c41

WARNING: line length of 105 exceeds 100 columns
#7053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7029:
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7030:
+#define regOTG2_OTG_CONTROL                                                                             0x1c43

WARNING: line length of 105 exceeds 100 columns
#7055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7031:
+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7032:
+#define regOTG2_OTG_DLPC_CONTROL                                                                        0x1c44

WARNING: line length of 105 exceeds 100 columns
#7057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7033:
+#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7034:
+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c45

WARNING: line length of 105 exceeds 100 columns
#7059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7035:
+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7036:
+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c46

WARNING: line length of 105 exceeds 100 columns
#7061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7037:
+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7038:
+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47

WARNING: line length of 105 exceeds 100 columns
#7063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7039:
+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7040:
+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48

WARNING: line length of 105 exceeds 100 columns
#7065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7041:
+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7042:
+#define regOTG2_OTG_STATUS                                                                              0x1c49

WARNING: line length of 105 exceeds 100 columns
#7067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7043:
+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#7068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7044:
+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a

WARNING: line length of 105 exceeds 100 columns
#7069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7045:
+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7046:
+#define regOTG2_OTG_LONG_VBLANK_STATUS                                                                  0x1c4b

WARNING: line length of 105 exceeds 100 columns
#7071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7047:
+#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7048:
+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4c

WARNING: line length of 105 exceeds 100 columns
#7073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7049:
+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7050:
+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4d

WARNING: line length of 105 exceeds 100 columns
#7075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7051:
+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7052:
+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4e

WARNING: line length of 105 exceeds 100 columns
#7077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7053:
+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7054:
+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4f

WARNING: line length of 105 exceeds 100 columns
#7079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7055:
+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7056:
+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c50

WARNING: line length of 105 exceeds 100 columns
#7081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7057:
+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7058:
+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c51

WARNING: line length of 105 exceeds 100 columns
#7083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7059:
+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7060:
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c52

WARNING: line length of 105 exceeds 100 columns
#7085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7061:
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7062:
+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c53

WARNING: line length of 105 exceeds 100 columns
#7087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7063:
+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7064:
+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c54

WARNING: line length of 105 exceeds 100 columns
#7089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7065:
+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7066:
+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c55

WARNING: line length of 105 exceeds 100 columns
#7091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7067:
+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7068:
+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c56

WARNING: line length of 105 exceeds 100 columns
#7093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7069:
+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7070:
+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c57

WARNING: line length of 105 exceeds 100 columns
#7095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7071:
+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7072:
+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c58

WARNING: line length of 105 exceeds 100 columns
#7097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7073:
+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7074:
+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c59

WARNING: line length of 105 exceeds 100 columns
#7099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7075:
+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7076:
+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c5a

WARNING: line length of 105 exceeds 100 columns
#7101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7077:
+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7078:
+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5b

WARNING: line length of 105 exceeds 100 columns
#7103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7079:
+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7080:
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5c

WARNING: line length of 105 exceeds 100 columns
#7105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7081:
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7082:
+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5d

WARNING: line length of 105 exceeds 100 columns
#7107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7083:
+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7084:
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c5f

WARNING: line length of 105 exceeds 100 columns
#7109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7085:
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7086:
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c60

WARNING: line length of 105 exceeds 100 columns
#7111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7087:
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7088:
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c61

WARNING: line length of 105 exceeds 100 columns
#7113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7089:
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7090:
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c62

WARNING: line length of 105 exceeds 100 columns
#7115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7091:
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7092:
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c63

WARNING: line length of 105 exceeds 100 columns
#7117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7093:
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7094:
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c64

WARNING: line length of 105 exceeds 100 columns
#7119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7095:
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7096:
+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c65

WARNING: line length of 105 exceeds 100 columns
#7121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7097:
+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7098:
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c66

WARNING: line length of 105 exceeds 100 columns
#7123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7099:
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7100:
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c67

WARNING: line length of 105 exceeds 100 columns
#7125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7101:
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7102:
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c68

WARNING: line length of 105 exceeds 100 columns
#7127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7103:
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7104:
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c69

WARNING: line length of 105 exceeds 100 columns
#7129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7105:
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7106:
+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6a

WARNING: line length of 105 exceeds 100 columns
#7131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7107:
+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7108:
+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6b

WARNING: line length of 105 exceeds 100 columns
#7133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7109:
+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7110:
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6c

WARNING: line length of 105 exceeds 100 columns
#7135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7111:
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7112:
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c6d

WARNING: line length of 105 exceeds 100 columns
#7137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7113:
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7114:
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c6e

WARNING: line length of 105 exceeds 100 columns
#7139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7115:
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7116:
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c6f

WARNING: line length of 105 exceeds 100 columns
#7141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7117:
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7118:
+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c70

WARNING: line length of 105 exceeds 100 columns
#7143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7119:
+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7120:
+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c71

WARNING: line length of 105 exceeds 100 columns
#7145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7121:
+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7122:
+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c72

WARNING: line length of 105 exceeds 100 columns
#7147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7123:
+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7124:
+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c73

WARNING: line length of 105 exceeds 100 columns
#7149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7125:
+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7126:
+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c74

WARNING: line length of 105 exceeds 100 columns
#7151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7127:
+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7128:
+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c75

WARNING: line length of 105 exceeds 100 columns
#7153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7129:
+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7130:
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c76

WARNING: line length of 105 exceeds 100 columns
#7155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7131:
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7132:
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c77

WARNING: line length of 105 exceeds 100 columns
#7157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7133:
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7134:
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1c78

WARNING: line length of 105 exceeds 100 columns
#7159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7135:
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7136:
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1c79

WARNING: line length of 105 exceeds 100 columns
#7161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7137:
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7138:
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1c7a

WARNING: line length of 105 exceeds 100 columns
#7163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7139:
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7140:
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7b

WARNING: line length of 105 exceeds 100 columns
#7165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7141:
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7142:
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1c7c

WARNING: line length of 105 exceeds 100 columns
#7167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7143:
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7144:
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1c7d

WARNING: line length of 105 exceeds 100 columns
#7169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7145:
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7146:
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1c7e

WARNING: line length of 105 exceeds 100 columns
#7171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7147:
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7148:
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7f

WARNING: line length of 105 exceeds 100 columns
#7173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7149:
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7150:
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c80

WARNING: line length of 105 exceeds 100 columns
#7175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7151:
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7152:
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c81

WARNING: line length of 105 exceeds 100 columns
#7177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7153:
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7154:
+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c82

WARNING: line length of 105 exceeds 100 columns
#7179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7155:
+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7156:
+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c83

WARNING: line length of 105 exceeds 100 columns
#7181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7157:
+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7158:
+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c84

WARNING: line length of 105 exceeds 100 columns
#7183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7159:
+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7160:
+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c85

WARNING: line length of 105 exceeds 100 columns
#7185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7161:
+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7162:
+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c86

WARNING: line length of 105 exceeds 100 columns
#7187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7163:
+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7164:
+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c87

WARNING: line length of 105 exceeds 100 columns
#7189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7165:
+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7166:
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c88

WARNING: line length of 105 exceeds 100 columns
#7191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7167:
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7168:
+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c89

WARNING: line length of 105 exceeds 100 columns
#7193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7169:
+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7170:
+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8a

WARNING: line length of 105 exceeds 100 columns
#7195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7171:
+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7172:
+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8b

WARNING: line length of 105 exceeds 100 columns
#7197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7173:
+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7174:
+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8c

WARNING: line length of 105 exceeds 100 columns
#7199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7175:
+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7176:
+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8d

WARNING: line length of 105 exceeds 100 columns
#7201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7177:
+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7178:
+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8e

WARNING: line length of 105 exceeds 100 columns
#7203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7179:
+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7180:
+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c8f

WARNING: line length of 105 exceeds 100 columns
#7205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7181:
+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7182:
+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c90

WARNING: line length of 105 exceeds 100 columns
#7207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7183:
+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7184:
+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c91

WARNING: line length of 105 exceeds 100 columns
#7209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7185:
+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7186:
+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c92

WARNING: line length of 105 exceeds 100 columns
#7211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7187:
+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7188:
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c93

WARNING: line length of 105 exceeds 100 columns
#7213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7189:
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7190:
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c95

WARNING: line length of 105 exceeds 100 columns
#7215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7191:
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7192:
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c96

WARNING: line length of 105 exceeds 100 columns
#7217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7193:
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#7218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7194:
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c97

WARNING: line length of 105 exceeds 100 columns
#7219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7195:
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7196:
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c98

WARNING: line length of 105 exceeds 100 columns
#7221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7197:
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7198:
+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c99

WARNING: line length of 105 exceeds 100 columns
#7223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7199:
+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7200:
+#define regOTG2_OTG_DRR_CONTOL2                                                                         0x1c9a

WARNING: line length of 105 exceeds 100 columns
#7225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7201:
+#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7202:
+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b

WARNING: line length of 105 exceeds 100 columns
#7227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7203:
+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7204:
+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c

WARNING: line length of 105 exceeds 100 columns
#7229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7205:
+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7206:
+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d

WARNING: line length of 105 exceeds 100 columns
#7231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7207:
+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7208:
+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9e

WARNING: line length of 105 exceeds 100 columns
#7233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7209:
+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7210:
+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9f

WARNING: line length of 105 exceeds 100 columns
#7235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7211:
+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7212:
+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca0

WARNING: line length of 105 exceeds 100 columns
#7237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7213:
+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7218:
+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa

WARNING: line length of 105 exceeds 100 columns
#7243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7219:
+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7220:
+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab

WARNING: line length of 105 exceeds 100 columns
#7245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7221:
+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7222:
+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac

WARNING: line length of 105 exceeds 100 columns
#7247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7223:
+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7224:
+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad

WARNING: line length of 105 exceeds 100 columns
#7249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7225:
+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7226:
+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae

WARNING: line length of 105 exceeds 100 columns
#7251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7227:
+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7228:
+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf

WARNING: line length of 105 exceeds 100 columns
#7253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7229:
+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7230:
+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0

WARNING: line length of 105 exceeds 100 columns
#7255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7231:
+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7232:
+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1

WARNING: line length of 105 exceeds 100 columns
#7257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7233:
+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7234:
+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2

WARNING: line length of 105 exceeds 100 columns
#7259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7235:
+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7236:
+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3

WARNING: line length of 105 exceeds 100 columns
#7261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7237:
+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7238:
+#define regOTG3_OTG_V_COUNT_STOP_CONTROL                                                                0x1cb4

WARNING: line length of 105 exceeds 100 columns
#7263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7239:
+#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7240:
+#define regOTG3_OTG_V_COUNT_STOP_CONTROL2                                                               0x1cb5

WARNING: line length of 105 exceeds 100 columns
#7265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7241:
+#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7242:
+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb6

WARNING: line length of 105 exceeds 100 columns
#7267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7243:
+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7244:
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb7

WARNING: line length of 105 exceeds 100 columns
#7269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7245:
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7246:
+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb8

WARNING: line length of 105 exceeds 100 columns
#7271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7247:
+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7248:
+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb9

WARNING: line length of 105 exceeds 100 columns
#7273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7249:
+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7250:
+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cba

WARNING: line length of 105 exceeds 100 columns
#7275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7251:
+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7252:
+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cbb

WARNING: line length of 105 exceeds 100 columns
#7277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7253:
+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7254:
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cbc

WARNING: line length of 105 exceeds 100 columns
#7279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7255:
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7256:
+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbd

WARNING: line length of 105 exceeds 100 columns
#7281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7257:
+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7258:
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbe

WARNING: line length of 105 exceeds 100 columns
#7283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7259:
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7260:
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbf

WARNING: line length of 105 exceeds 100 columns
#7285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7261:
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7262:
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cc1

WARNING: line length of 105 exceeds 100 columns
#7287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7263:
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7264:
+#define regOTG3_OTG_CONTROL                                                                             0x1cc3

WARNING: line length of 105 exceeds 100 columns
#7289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7265:
+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7266:
+#define regOTG3_OTG_DLPC_CONTROL                                                                        0x1cc4

WARNING: line length of 105 exceeds 100 columns
#7291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7267:
+#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7268:
+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc5

WARNING: line length of 105 exceeds 100 columns
#7293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7269:
+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7270:
+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc6

WARNING: line length of 105 exceeds 100 columns
#7295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7271:
+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7272:
+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7

WARNING: line length of 105 exceeds 100 columns
#7297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7273:
+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7274:
+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8

WARNING: line length of 105 exceeds 100 columns
#7299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7275:
+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7276:
+#define regOTG3_OTG_STATUS                                                                              0x1cc9

WARNING: line length of 105 exceeds 100 columns
#7301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7277:
+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#7302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7278:
+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca

WARNING: line length of 105 exceeds 100 columns
#7303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7279:
+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7280:
+#define regOTG3_OTG_LONG_VBLANK_STATUS                                                                  0x1ccb

WARNING: line length of 105 exceeds 100 columns
#7305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7281:
+#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7282:
+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccc

WARNING: line length of 105 exceeds 100 columns
#7307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7283:
+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7284:
+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccd

WARNING: line length of 105 exceeds 100 columns
#7309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7285:
+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7286:
+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1cce

WARNING: line length of 105 exceeds 100 columns
#7311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7287:
+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7288:
+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1ccf

WARNING: line length of 105 exceeds 100 columns
#7313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7289:
+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7290:
+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1cd0

WARNING: line length of 105 exceeds 100 columns
#7315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7291:
+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7292:
+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd1

WARNING: line length of 105 exceeds 100 columns
#7317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7293:
+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7294:
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd2

WARNING: line length of 105 exceeds 100 columns
#7319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7295:
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7296:
+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd3

WARNING: line length of 105 exceeds 100 columns
#7321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7297:
+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7298:
+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd4

WARNING: line length of 105 exceeds 100 columns
#7323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7299:
+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7300:
+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd5

WARNING: line length of 105 exceeds 100 columns
#7325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7301:
+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7302:
+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd6

WARNING: line length of 105 exceeds 100 columns
#7327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7303:
+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7304:
+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd7

WARNING: line length of 105 exceeds 100 columns
#7329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7305:
+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7306:
+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd8

WARNING: line length of 105 exceeds 100 columns
#7331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7307:
+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7308:
+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd9

WARNING: line length of 105 exceeds 100 columns
#7333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7309:
+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7310:
+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cda

WARNING: line length of 105 exceeds 100 columns
#7335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7311:
+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7312:
+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cdb

WARNING: line length of 105 exceeds 100 columns
#7337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7313:
+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7314:
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdc

WARNING: line length of 105 exceeds 100 columns
#7339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7315:
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7316:
+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdd

WARNING: line length of 105 exceeds 100 columns
#7341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7317:
+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7318:
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1cdf

WARNING: line length of 105 exceeds 100 columns
#7343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7319:
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7320:
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce0

WARNING: line length of 105 exceeds 100 columns
#7345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7321:
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7322:
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce1

WARNING: line length of 105 exceeds 100 columns
#7347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7323:
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7324:
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce2

WARNING: line length of 105 exceeds 100 columns
#7349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7325:
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7326:
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce3

WARNING: line length of 105 exceeds 100 columns
#7351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7327:
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2

WARNING: line length of 110 exceeds 100 columns
#7352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7328:
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce4

WARNING: line length of 105 exceeds 100 columns
#7353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7329:
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7330:
+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce5

WARNING: line length of 105 exceeds 100 columns
#7355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7331:
+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7332:
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce6

WARNING: line length of 105 exceeds 100 columns
#7357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7333:
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7334:
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ce7

WARNING: line length of 105 exceeds 100 columns
#7359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7335:
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7336:
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ce8

WARNING: line length of 105 exceeds 100 columns
#7361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7337:
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7338:
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ce9

WARNING: line length of 105 exceeds 100 columns
#7363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7339:
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7340:
+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1cea

WARNING: line length of 105 exceeds 100 columns
#7365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7341:
+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7342:
+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1ceb

WARNING: line length of 105 exceeds 100 columns
#7367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7343:
+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7344:
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cec

WARNING: line length of 105 exceeds 100 columns
#7369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7345:
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7346:
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1ced

WARNING: line length of 105 exceeds 100 columns
#7371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7347:
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7348:
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cee

WARNING: line length of 105 exceeds 100 columns
#7373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7349:
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7350:
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cef

WARNING: line length of 105 exceeds 100 columns
#7375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7351:
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7352:
+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf0

WARNING: line length of 105 exceeds 100 columns
#7377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7353:
+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7354:
+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf1

WARNING: line length of 105 exceeds 100 columns
#7379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7355:
+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7356:
+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf2

WARNING: line length of 105 exceeds 100 columns
#7381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7357:
+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7358:
+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf3

WARNING: line length of 105 exceeds 100 columns
#7383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7359:
+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7360:
+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf4

WARNING: line length of 105 exceeds 100 columns
#7385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7361:
+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7362:
+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf5

WARNING: line length of 105 exceeds 100 columns
#7387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7363:
+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7364:
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf6

WARNING: line length of 105 exceeds 100 columns
#7389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7365:
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7366:
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cf7

WARNING: line length of 105 exceeds 100 columns
#7391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7367:
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7368:
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1cf8

WARNING: line length of 105 exceeds 100 columns
#7393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7369:
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7370:
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1cf9

WARNING: line length of 105 exceeds 100 columns
#7395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7371:
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7372:
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1cfa

WARNING: line length of 105 exceeds 100 columns
#7397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7373:
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7374:
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1cfb

WARNING: line length of 105 exceeds 100 columns
#7399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7375:
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7376:
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1cfc

WARNING: line length of 105 exceeds 100 columns
#7401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7377:
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7378:
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1cfd

WARNING: line length of 105 exceeds 100 columns
#7403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7379:
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7380:
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1cfe

WARNING: line length of 105 exceeds 100 columns
#7405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7381:
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7382:
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1cff

WARNING: line length of 105 exceeds 100 columns
#7407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7383:
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#7408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7384:
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d00

WARNING: line length of 105 exceeds 100 columns
#7409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7385:
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7386:
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d01

WARNING: line length of 105 exceeds 100 columns
#7411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7387:
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7388:
+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d02

WARNING: line length of 105 exceeds 100 columns
#7413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7389:
+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7390:
+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d03

WARNING: line length of 105 exceeds 100 columns
#7415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7391:
+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7392:
+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d04

WARNING: line length of 105 exceeds 100 columns
#7417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7393:
+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7394:
+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d05

WARNING: line length of 105 exceeds 100 columns
#7419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7395:
+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7396:
+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d06

WARNING: line length of 105 exceeds 100 columns
#7421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7397:
+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7398:
+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d07

WARNING: line length of 105 exceeds 100 columns
#7423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7399:
+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7400:
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d08

WARNING: line length of 105 exceeds 100 columns
#7425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7401:
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7402:
+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d09

WARNING: line length of 105 exceeds 100 columns
#7427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7403:
+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7404:
+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0a

WARNING: line length of 105 exceeds 100 columns
#7429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7405:
+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7406:
+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0b

WARNING: line length of 105 exceeds 100 columns
#7431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7407:
+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7408:
+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0c

WARNING: line length of 105 exceeds 100 columns
#7433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7409:
+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7410:
+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0d

WARNING: line length of 105 exceeds 100 columns
#7435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7411:
+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7412:
+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0e

WARNING: line length of 105 exceeds 100 columns
#7437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7413:
+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7414:
+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d0f

WARNING: line length of 105 exceeds 100 columns
#7439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7415:
+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7416:
+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d10

WARNING: line length of 105 exceeds 100 columns
#7441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7417:
+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7418:
+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d11

WARNING: line length of 105 exceeds 100 columns
#7443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7419:
+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7420:
+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d12

WARNING: line length of 105 exceeds 100 columns
#7445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7421:
+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7422:
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d13

WARNING: line length of 105 exceeds 100 columns
#7447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7423:
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7424:
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d15

WARNING: line length of 105 exceeds 100 columns
#7449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7425:
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7426:
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d16

WARNING: line length of 105 exceeds 100 columns
#7451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7427:
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#7452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7428:
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d17

WARNING: line length of 105 exceeds 100 columns
#7453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7429:
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7430:
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d18

WARNING: line length of 105 exceeds 100 columns
#7455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7431:
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7432:
+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d19

WARNING: line length of 105 exceeds 100 columns
#7457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7433:
+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7434:
+#define regOTG3_OTG_DRR_CONTOL2                                                                         0x1d1a

WARNING: line length of 105 exceeds 100 columns
#7459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7435:
+#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#7460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7436:
+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b

WARNING: line length of 105 exceeds 100 columns
#7461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7437:
+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7438:
+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c

WARNING: line length of 105 exceeds 100 columns
#7463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7439:
+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7440:
+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d

WARNING: line length of 105 exceeds 100 columns
#7465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7441:
+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7442:
+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1e

WARNING: line length of 105 exceeds 100 columns
#7467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7443:
+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7444:
+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1f

WARNING: line length of 105 exceeds 100 columns
#7469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7445:
+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7446:
+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d20

WARNING: line length of 105 exceeds 100 columns
#7471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7447:
+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7452:
+#define regGSL_SOURCE_SELECT                                                                            0x1e2b

WARNING: line length of 105 exceeds 100 columns
#7477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7453:
+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7454:
+#define regOPTC_DLPC_CONTROL                                                                            0x1e2c

WARNING: line length of 105 exceeds 100 columns
#7479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7455:
+#define regOPTC_DLPC_CONTROL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7456:
+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2d

WARNING: line length of 105 exceeds 100 columns
#7481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7457:
+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7458:
+#define regODM_MEM_PWR_CTRL                                                                             0x1e2e

WARNING: line length of 105 exceeds 100 columns
#7483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7459:
+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7460:
+#define regODM_MEM_PWR_CTRL3                                                                            0x1e30

WARNING: line length of 105 exceeds 100 columns
#7485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7461:
+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7462:
+#define regODM_MEM_PWR_STATUS                                                                           0x1e31

WARNING: line length of 105 exceeds 100 columns
#7487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7463:
+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7464:
+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e32

WARNING: line length of 105 exceeds 100 columns
#7489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7465:
+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7470:
+#define regDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a

WARNING: line length of 105 exceeds 100 columns
#7495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7471:
+#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7472:
+#define regDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b

WARNING: line length of 105 exceeds 100 columns
#7497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7473:
+#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7474:
+#define regDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c

WARNING: line length of 105 exceeds 100 columns
#7499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7475:
+#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7476:
+#define regDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d

WARNING: line length of 105 exceeds 100 columns
#7501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7477:
+#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7478:
+#define regDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e

WARNING: line length of 105 exceeds 100 columns
#7503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7479:
+#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7480:
+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f

WARNING: line length of 105 exceeds 100 columns
#7505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7481:
+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7482:
+#define regDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70

WARNING: line length of 105 exceeds 100 columns
#7507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7483:
+#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7484:
+#define regDC_PERFMON17_PERFMON_HI                                                                      0x1e71

WARNING: line length of 105 exceeds 100 columns
#7509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7485:
+#define regDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7486:
+#define regDC_PERFMON17_PERFMON_LOW                                                                     0x1e72

WARNING: line length of 105 exceeds 100 columns
#7511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7487:
+#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7492:
+#define regDC_I2C_CONTROL                                                                               0x1e98

WARNING: line length of 105 exceeds 100 columns
#7517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7493:
+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7494:
+#define regDC_I2C_ARBITRATION                                                                           0x1e99

WARNING: line length of 105 exceeds 100 columns
#7519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7495:
+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7496:
+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a

WARNING: line length of 105 exceeds 100 columns
#7521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7497:
+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7498:
+#define regDC_I2C_SW_STATUS                                                                             0x1e9b

WARNING: line length of 105 exceeds 100 columns
#7523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7499:
+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7500:
+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c

WARNING: line length of 105 exceeds 100 columns
#7525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7501:
+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7502:
+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d

WARNING: line length of 105 exceeds 100 columns
#7527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7503:
+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7504:
+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e

WARNING: line length of 105 exceeds 100 columns
#7529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7505:
+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7506:
+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f

WARNING: line length of 105 exceeds 100 columns
#7531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7507:
+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7508:
+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0

WARNING: line length of 105 exceeds 100 columns
#7533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7509:
+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7510:
+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2

WARNING: line length of 105 exceeds 100 columns
#7535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7511:
+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7512:
+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3

WARNING: line length of 105 exceeds 100 columns
#7537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7513:
+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7514:
+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4

WARNING: line length of 105 exceeds 100 columns
#7539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7515:
+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7516:
+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5

WARNING: line length of 105 exceeds 100 columns
#7541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7517:
+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7518:
+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6

WARNING: line length of 105 exceeds 100 columns
#7543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7519:
+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7520:
+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7

WARNING: line length of 105 exceeds 100 columns
#7545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7521:
+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7522:
+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8

WARNING: line length of 105 exceeds 100 columns
#7547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7523:
+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7524:
+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9

WARNING: line length of 105 exceeds 100 columns
#7549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7525:
+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7526:
+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa

WARNING: line length of 105 exceeds 100 columns
#7551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7527:
+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7528:
+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab

WARNING: line length of 105 exceeds 100 columns
#7553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7529:
+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7530:
+#define regDC_I2C_TRANSACTION0                                                                          0x1eae

WARNING: line length of 105 exceeds 100 columns
#7555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7531:
+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7532:
+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf

WARNING: line length of 105 exceeds 100 columns
#7557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7533:
+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7534:
+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0

WARNING: line length of 105 exceeds 100 columns
#7559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7535:
+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7536:
+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1

WARNING: line length of 105 exceeds 100 columns
#7561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7537:
+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7538:
+#define regDC_I2C_DATA                                                                                  0x1eb2

WARNING: line length of 105 exceeds 100 columns
#7563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7539:
+#define regDC_I2C_DATA_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#7564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7540:
+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6

WARNING: line length of 105 exceeds 100 columns
#7565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7541:
+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7542:
+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7

WARNING: line length of 105 exceeds 100 columns
#7567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7543:
+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7548:
+#define regDIO_DCN_STATUS                                                                               0x1ec3

WARNING: line length of 105 exceeds 100 columns
#7573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7549:
+#define regDIO_DCN_STATUS_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7550:
+#define regDIO_SCRATCH0                                                                                 0x1eca

WARNING: line length of 105 exceeds 100 columns
#7575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7551:
+#define regDIO_SCRATCH0_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7552:
+#define regDIO_SCRATCH1                                                                                 0x1ecb

WARNING: line length of 105 exceeds 100 columns
#7577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7553:
+#define regDIO_SCRATCH1_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7554:
+#define regDIO_SCRATCH2                                                                                 0x1ecc

WARNING: line length of 105 exceeds 100 columns
#7579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7555:
+#define regDIO_SCRATCH2_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7556:
+#define regDIO_SCRATCH3                                                                                 0x1ecd

WARNING: line length of 105 exceeds 100 columns
#7581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7557:
+#define regDIO_SCRATCH3_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7558:
+#define regDIO_SCRATCH4                                                                                 0x1ece

WARNING: line length of 105 exceeds 100 columns
#7583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7559:
+#define regDIO_SCRATCH4_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7560:
+#define regDIO_SCRATCH5                                                                                 0x1ecf

WARNING: line length of 105 exceeds 100 columns
#7585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7561:
+#define regDIO_SCRATCH5_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7562:
+#define regDIO_SCRATCH6                                                                                 0x1ed0

WARNING: line length of 105 exceeds 100 columns
#7587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7563:
+#define regDIO_SCRATCH6_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7564:
+#define regDIO_SCRATCH7                                                                                 0x1ed1

WARNING: line length of 105 exceeds 100 columns
#7589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7565:
+#define regDIO_SCRATCH7_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7566:
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3

WARNING: line length of 105 exceeds 100 columns
#7591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7567:
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#7592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7568:
+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd

WARNING: line length of 105 exceeds 100 columns
#7593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7569:
+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7570:
+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede

WARNING: line length of 105 exceeds 100 columns
#7595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7571:
+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7572:
+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf

WARNING: line length of 105 exceeds 100 columns
#7597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7573:
+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7574:
+#define regDIO_CLK_CNTL                                                                                 0x1ee0

WARNING: line length of 105 exceeds 100 columns
#7599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7575:
+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#7600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7576:
+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4

WARNING: line length of 105 exceeds 100 columns
#7601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7577:
+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7578:
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff

WARNING: line length of 105 exceeds 100 columns
#7603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7579:
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7580:
+#define regDIO_PSP_INTERRUPT_STATUS                                                                     0x1f00

WARNING: line length of 105 exceeds 100 columns
#7605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7581:
+#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7582:
+#define regDIO_PSP_INTERRUPT_CLEAR                                                                      0x1f01

WARNING: line length of 105 exceeds 100 columns
#7607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7583:
+#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7584:
+#define regDIO_STATUS                                                                                   0x1f02

WARNING: line length of 105 exceeds 100 columns
#7609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7585:
+#define regDIO_STATUS_BASE_IDX                                                                          2

WARNING: line length of 110 exceeds 100 columns
#7610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7586:
+#define regDIO_LINKA_CNTL                                                                               0x1f04

WARNING: line length of 105 exceeds 100 columns
#7611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7587:
+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7588:
+#define regDIO_LINKB_CNTL                                                                               0x1f05

WARNING: line length of 105 exceeds 100 columns
#7613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7589:
+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7590:
+#define regDIO_LINKC_CNTL                                                                               0x1f06

WARNING: line length of 105 exceeds 100 columns
#7615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7591:
+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7592:
+#define regDIO_LINKD_CNTL                                                                               0x1f07

WARNING: line length of 105 exceeds 100 columns
#7617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7593:
+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7594:
+#define regDIO_LINKE_CNTL                                                                               0x1f08

WARNING: line length of 105 exceeds 100 columns
#7619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7595:
+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7596:
+#define regDIO_LINKF_CNTL                                                                               0x1f09

WARNING: line length of 105 exceeds 100 columns
#7621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7597:
+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7602:
+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14

WARNING: line length of 105 exceeds 100 columns
#7627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7603:
+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7604:
+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15

WARNING: line length of 105 exceeds 100 columns
#7629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7605:
+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7606:
+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16

WARNING: line length of 105 exceeds 100 columns
#7631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7607:
+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7608:
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17

WARNING: line length of 105 exceeds 100 columns
#7633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7609:
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7610:
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18

WARNING: line length of 105 exceeds 100 columns
#7635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7611:
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7616:
+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c

WARNING: line length of 105 exceeds 100 columns
#7641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7617:
+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7618:
+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d

WARNING: line length of 105 exceeds 100 columns
#7643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7619:
+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7620:
+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e

WARNING: line length of 105 exceeds 100 columns
#7645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7621:
+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7622:
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f

WARNING: line length of 105 exceeds 100 columns
#7647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7623:
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7624:
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20

WARNING: line length of 105 exceeds 100 columns
#7649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7625:
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7630:
+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24

WARNING: line length of 105 exceeds 100 columns
#7655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7631:
+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7632:
+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25

WARNING: line length of 105 exceeds 100 columns
#7657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7633:
+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7634:
+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26

WARNING: line length of 105 exceeds 100 columns
#7659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7635:
+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7636:
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27

WARNING: line length of 105 exceeds 100 columns
#7661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7637:
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7638:
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28

WARNING: line length of 105 exceeds 100 columns
#7663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7639:
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7644:
+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c

WARNING: line length of 105 exceeds 100 columns
#7669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7645:
+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7646:
+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d

WARNING: line length of 105 exceeds 100 columns
#7671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7647:
+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7648:
+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e

WARNING: line length of 105 exceeds 100 columns
#7673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7649:
+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7650:
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f

WARNING: line length of 105 exceeds 100 columns
#7675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7651:
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7652:
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30

WARNING: line length of 105 exceeds 100 columns
#7677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7653:
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7658:
+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34

WARNING: line length of 105 exceeds 100 columns
#7683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7659:
+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7660:
+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35

WARNING: line length of 105 exceeds 100 columns
#7685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7661:
+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7662:
+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36

WARNING: line length of 105 exceeds 100 columns
#7687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7663:
+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7664:
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37

WARNING: line length of 105 exceeds 100 columns
#7689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7665:
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7666:
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38

WARNING: line length of 105 exceeds 100 columns
#7691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7667:
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7672:
+#define regDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44

WARNING: line length of 105 exceeds 100 columns
#7697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7673:
+#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7674:
+#define regDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45

WARNING: line length of 105 exceeds 100 columns
#7699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7675:
+#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7676:
+#define regDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46

WARNING: line length of 105 exceeds 100 columns
#7701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7677:
+#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7678:
+#define regDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47

WARNING: line length of 105 exceeds 100 columns
#7703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7679:
+#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7680:
+#define regDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48

WARNING: line length of 105 exceeds 100 columns
#7705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7681:
+#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7682:
+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49

WARNING: line length of 105 exceeds 100 columns
#7707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7683:
+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#7708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7684:
+#define regDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a

WARNING: line length of 105 exceeds 100 columns
#7709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7685:
+#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7686:
+#define regDC_PERFMON18_PERFMON_HI                                                                      0x1f4b

WARNING: line length of 105 exceeds 100 columns
#7711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7687:
+#define regDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7688:
+#define regDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c

WARNING: line length of 105 exceeds 100 columns
#7713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7689:
+#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7694:
+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50

WARNING: line length of 105 exceeds 100 columns
#7719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7695:
+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7696:
+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51

WARNING: line length of 105 exceeds 100 columns
#7721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7697:
+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7698:
+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52

WARNING: line length of 105 exceeds 100 columns
#7723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7699:
+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7700:
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53

WARNING: line length of 105 exceeds 100 columns
#7725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7701:
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7702:
+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54

WARNING: line length of 105 exceeds 100 columns
#7727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7703:
+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7704:
+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55

WARNING: line length of 105 exceeds 100 columns
#7729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7705:
+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7706:
+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56

WARNING: line length of 105 exceeds 100 columns
#7731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7707:
+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7708:
+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57

WARNING: line length of 105 exceeds 100 columns
#7733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7709:
+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7710:
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58

WARNING: line length of 105 exceeds 100 columns
#7735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7711:
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7712:
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59

WARNING: line length of 105 exceeds 100 columns
#7737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7713:
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7714:
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a

WARNING: line length of 105 exceeds 100 columns
#7739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7715:
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7716:
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b

WARNING: line length of 105 exceeds 100 columns
#7741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7717:
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7718:
+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c

WARNING: line length of 105 exceeds 100 columns
#7743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7719:
+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7720:
+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d

WARNING: line length of 105 exceeds 100 columns
#7745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7721:
+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7722:
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e

WARNING: line length of 105 exceeds 100 columns
#7747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7723:
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7724:
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f

WARNING: line length of 105 exceeds 100 columns
#7749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7725:
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7726:
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60

WARNING: line length of 105 exceeds 100 columns
#7751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7727:
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#7752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7728:
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61

WARNING: line length of 105 exceeds 100 columns
#7753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7729:
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7730:
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66

WARNING: line length of 105 exceeds 100 columns
#7755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7731:
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7736:
+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c

WARNING: line length of 105 exceeds 100 columns
#7761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7737:
+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7738:
+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d

WARNING: line length of 105 exceeds 100 columns
#7763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7739:
+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7740:
+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e

WARNING: line length of 105 exceeds 100 columns
#7765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7741:
+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7742:
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f

WARNING: line length of 105 exceeds 100 columns
#7767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7743:
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7744:
+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70

WARNING: line length of 105 exceeds 100 columns
#7769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7745:
+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7746:
+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71

WARNING: line length of 105 exceeds 100 columns
#7771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7747:
+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7748:
+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72

WARNING: line length of 105 exceeds 100 columns
#7773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7749:
+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7750:
+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73

WARNING: line length of 105 exceeds 100 columns
#7775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7751:
+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7752:
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74

WARNING: line length of 105 exceeds 100 columns
#7777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7753:
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7754:
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75

WARNING: line length of 105 exceeds 100 columns
#7779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7755:
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7756:
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76

WARNING: line length of 105 exceeds 100 columns
#7781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7757:
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7758:
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77

WARNING: line length of 105 exceeds 100 columns
#7783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7759:
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7760:
+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78

WARNING: line length of 105 exceeds 100 columns
#7785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7761:
+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7762:
+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79

WARNING: line length of 105 exceeds 100 columns
#7787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7763:
+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7764:
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a

WARNING: line length of 105 exceeds 100 columns
#7789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7765:
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7766:
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b

WARNING: line length of 105 exceeds 100 columns
#7791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7767:
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7768:
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c

WARNING: line length of 105 exceeds 100 columns
#7793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7769:
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#7794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7770:
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d

WARNING: line length of 105 exceeds 100 columns
#7795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7771:
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7772:
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82

WARNING: line length of 105 exceeds 100 columns
#7797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7773:
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7778:
+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88

WARNING: line length of 105 exceeds 100 columns
#7803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7779:
+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7780:
+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89

WARNING: line length of 105 exceeds 100 columns
#7805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7781:
+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7782:
+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a

WARNING: line length of 105 exceeds 100 columns
#7807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7783:
+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7784:
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b

WARNING: line length of 105 exceeds 100 columns
#7809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7785:
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7786:
+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c

WARNING: line length of 105 exceeds 100 columns
#7811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7787:
+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7788:
+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d

WARNING: line length of 105 exceeds 100 columns
#7813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7789:
+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7790:
+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e

WARNING: line length of 105 exceeds 100 columns
#7815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7791:
+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7792:
+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f

WARNING: line length of 105 exceeds 100 columns
#7817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7793:
+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7794:
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90

WARNING: line length of 105 exceeds 100 columns
#7819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7795:
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7796:
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91

WARNING: line length of 105 exceeds 100 columns
#7821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7797:
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7798:
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92

WARNING: line length of 105 exceeds 100 columns
#7823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7799:
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7800:
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93

WARNING: line length of 105 exceeds 100 columns
#7825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7801:
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7802:
+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94

WARNING: line length of 105 exceeds 100 columns
#7827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7803:
+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7804:
+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95

WARNING: line length of 105 exceeds 100 columns
#7829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7805:
+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7806:
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96

WARNING: line length of 105 exceeds 100 columns
#7831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7807:
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7808:
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97

WARNING: line length of 105 exceeds 100 columns
#7833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7809:
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7810:
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98

WARNING: line length of 105 exceeds 100 columns
#7835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7811:
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#7836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7812:
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99

WARNING: line length of 105 exceeds 100 columns
#7837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7813:
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7814:
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e

WARNING: line length of 105 exceeds 100 columns
#7839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7815:
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7820:
+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4

WARNING: line length of 105 exceeds 100 columns
#7845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7821:
+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7822:
+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5

WARNING: line length of 105 exceeds 100 columns
#7847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7823:
+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7824:
+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6

WARNING: line length of 105 exceeds 100 columns
#7849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7825:
+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7826:
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7

WARNING: line length of 105 exceeds 100 columns
#7851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7827:
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7828:
+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8

WARNING: line length of 105 exceeds 100 columns
#7853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7829:
+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7830:
+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9

WARNING: line length of 105 exceeds 100 columns
#7855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7831:
+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7832:
+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa

WARNING: line length of 105 exceeds 100 columns
#7857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7833:
+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7834:
+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab

WARNING: line length of 105 exceeds 100 columns
#7859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7835:
+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7836:
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac

WARNING: line length of 105 exceeds 100 columns
#7861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7837:
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7838:
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad

WARNING: line length of 105 exceeds 100 columns
#7863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7839:
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7840:
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae

WARNING: line length of 105 exceeds 100 columns
#7865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7841:
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7842:
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf

WARNING: line length of 105 exceeds 100 columns
#7867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7843:
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7844:
+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0

WARNING: line length of 105 exceeds 100 columns
#7869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7845:
+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7846:
+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1

WARNING: line length of 105 exceeds 100 columns
#7871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7847:
+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7848:
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2

WARNING: line length of 105 exceeds 100 columns
#7873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7849:
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7850:
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3

WARNING: line length of 105 exceeds 100 columns
#7875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7851:
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7852:
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4

WARNING: line length of 105 exceeds 100 columns
#7877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7853:
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#7878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7854:
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5

WARNING: line length of 105 exceeds 100 columns
#7879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7855:
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7856:
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba

WARNING: line length of 105 exceeds 100 columns
#7881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7857:
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7862:
+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0

WARNING: line length of 105 exceeds 100 columns
#7887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7863:
+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7864:
+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1

WARNING: line length of 105 exceeds 100 columns
#7889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7865:
+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7866:
+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2

WARNING: line length of 105 exceeds 100 columns
#7891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7867:
+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7868:
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3

WARNING: line length of 105 exceeds 100 columns
#7893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7869:
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7870:
+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4

WARNING: line length of 105 exceeds 100 columns
#7895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7871:
+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7872:
+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5

WARNING: line length of 105 exceeds 100 columns
#7897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7873:
+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7874:
+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6

WARNING: line length of 105 exceeds 100 columns
#7899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7875:
+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7876:
+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7

WARNING: line length of 105 exceeds 100 columns
#7901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7877:
+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7878:
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8

WARNING: line length of 105 exceeds 100 columns
#7903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7879:
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7880:
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9

WARNING: line length of 105 exceeds 100 columns
#7905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7881:
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7882:
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca

WARNING: line length of 105 exceeds 100 columns
#7907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7883:
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7884:
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb

WARNING: line length of 105 exceeds 100 columns
#7909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7885:
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7886:
+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc

WARNING: line length of 105 exceeds 100 columns
#7911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7887:
+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7888:
+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd

WARNING: line length of 105 exceeds 100 columns
#7913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7889:
+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#7914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7890:
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce

WARNING: line length of 105 exceeds 100 columns
#7915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7891:
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7892:
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf

WARNING: line length of 105 exceeds 100 columns
#7917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7893:
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7894:
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0

WARNING: line length of 105 exceeds 100 columns
#7919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7895:
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#7920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7896:
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1

WARNING: line length of 105 exceeds 100 columns
#7921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7897:
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7898:
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6

WARNING: line length of 105 exceeds 100 columns
#7923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7899:
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#7928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7904:
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068

WARNING: line length of 105 exceeds 100 columns
#7929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7905:
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#7930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7906:
+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069

WARNING: line length of 105 exceeds 100 columns
#7931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7907:
+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7908:
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a

WARNING: line length of 105 exceeds 100 columns
#7933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7909:
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#7934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7910:
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b

WARNING: line length of 105 exceeds 100 columns
#7935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7911:
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#7936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7912:
+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c

WARNING: line length of 105 exceeds 100 columns
#7937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7913:
+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#7938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7914:
+#define regVPG0_VPG_MEM_PWR                                                                             0x206d

WARNING: line length of 105 exceeds 100 columns
#7939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7915:
+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7916:
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e

WARNING: line length of 105 exceeds 100 columns
#7941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7917:
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7918:
+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f

WARNING: line length of 105 exceeds 100 columns
#7943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7919:
+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#7944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7920:
+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070

WARNING: line length of 105 exceeds 100 columns
#7945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7921:
+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7922:
+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071

WARNING: line length of 105 exceeds 100 columns
#7947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7923:
+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#7952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7928:
+#define regAFMT0_AFMT_ACP                                                                               0x2073

WARNING: line length of 105 exceeds 100 columns
#7953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7929:
+#define regAFMT0_AFMT_ACP_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#7954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7930:
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074

WARNING: line length of 105 exceeds 100 columns
#7955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7931:
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7932:
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075

WARNING: line length of 105 exceeds 100 columns
#7957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7933:
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#7958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7934:
+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076

WARNING: line length of 105 exceeds 100 columns
#7959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7935:
+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7936:
+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077

WARNING: line length of 105 exceeds 100 columns
#7961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7937:
+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#7962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7938:
+#define regAFMT0_AFMT_60958_0                                                                           0x2078

WARNING: line length of 105 exceeds 100 columns
#7963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7939:
+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7940:
+#define regAFMT0_AFMT_60958_1                                                                           0x2079

WARNING: line length of 105 exceeds 100 columns
#7965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7941:
+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7942:
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a

WARNING: line length of 105 exceeds 100 columns
#7967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7943:
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7944:
+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b

WARNING: line length of 105 exceeds 100 columns
#7969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7945:
+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7946:
+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c

WARNING: line length of 105 exceeds 100 columns
#7971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7947:
+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7948:
+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d

WARNING: line length of 105 exceeds 100 columns
#7973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7949:
+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7950:
+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e

WARNING: line length of 105 exceeds 100 columns
#7975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7951:
+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#7976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7952:
+#define regAFMT0_AFMT_60958_2                                                                           0x207f

WARNING: line length of 105 exceeds 100 columns
#7977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7953:
+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7954:
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080

WARNING: line length of 105 exceeds 100 columns
#7979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7955:
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7956:
+#define regAFMT0_AFMT_STATUS                                                                            0x2081

WARNING: line length of 105 exceeds 100 columns
#7981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7957:
+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#7982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7958:
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082

WARNING: line length of 105 exceeds 100 columns
#7983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7959:
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#7984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7960:
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083

WARNING: line length of 105 exceeds 100 columns
#7985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7961:
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#7986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7962:
+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084

WARNING: line length of 105 exceeds 100 columns
#7987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7963:
+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#7988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7964:
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085

WARNING: line length of 105 exceeds 100 columns
#7989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7965:
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#7990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7966:
+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087

WARNING: line length of 105 exceeds 100 columns
#7991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7967:
+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#7996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7972:
+#define regDME0_DME_CONTROL                                                                             0x2091

WARNING: line length of 105 exceeds 100 columns
#7997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7973:
+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#7998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7974:
+#define regDME0_DME_MEMORY_CONTROL                                                                      0x2092

WARNING: line length of 105 exceeds 100 columns
#7999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7975:
+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7981:
+#define regDIG0_DIG_FE_CNTL                                                                             0x2093

WARNING: line length of 105 exceeds 100 columns
#8006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7982:
+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7983:
+#define regDIG0_DIG_FE_CLK_CNTL                                                                         0x2094

WARNING: line length of 105 exceeds 100 columns
#8008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7984:
+#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7985:
+#define regDIG0_DIG_FE_EN_CNTL                                                                          0x2095

WARNING: line length of 105 exceeds 100 columns
#8010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7986:
+#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7987:
+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x2096

WARNING: line length of 105 exceeds 100 columns
#8012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7988:
+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7989:
+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x2097

WARNING: line length of 105 exceeds 100 columns
#8014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7990:
+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#8015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7991:
+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x2098

WARNING: line length of 105 exceeds 100 columns
#8016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7992:
+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7993:
+#define regDIG0_DIG_TEST_PATTERN                                                                        0x2099

WARNING: line length of 105 exceeds 100 columns
#8018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7994:
+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7995:
+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x209a

WARNING: line length of 105 exceeds 100 columns
#8020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7996:
+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7997:
+#define regDIG0_DIG_FIFO_CTRL0                                                                          0x209b

WARNING: line length of 105 exceeds 100 columns
#8022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7998:
+#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:7999:
+#define regDIG0_DIG_FIFO_CTRL1                                                                          0x209c

WARNING: line length of 105 exceeds 100 columns
#8024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8000:
+#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8001:
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x209d

WARNING: line length of 105 exceeds 100 columns
#8026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8002:
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8003:
+#define regDIG0_HDMI_CONTROL                                                                            0x209e

WARNING: line length of 105 exceeds 100 columns
#8028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8004:
+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8005:
+#define regDIG0_HDMI_STATUS                                                                             0x209f

WARNING: line length of 105 exceeds 100 columns
#8030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8006:
+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8007:
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x20a0

WARNING: line length of 105 exceeds 100 columns
#8032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8008:
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#8033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8009:
+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x20a1

WARNING: line length of 105 exceeds 100 columns
#8034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8010:
+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8011:
+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x20a2

WARNING: line length of 105 exceeds 100 columns
#8036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8012:
+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8013:
+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x20a3

WARNING: line length of 105 exceeds 100 columns
#8038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8014:
+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8015:
+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x20a4

WARNING: line length of 105 exceeds 100 columns
#8040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8016:
+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8017:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x20a5

WARNING: line length of 105 exceeds 100 columns
#8042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8018:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8019:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x20a6

WARNING: line length of 105 exceeds 100 columns
#8044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8020:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8021:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x20a7

WARNING: line length of 105 exceeds 100 columns
#8046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8022:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8023:
+#define regDIG0_HDMI_GC                                                                                 0x20a8

WARNING: line length of 105 exceeds 100 columns
#8048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8024:
+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8025:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x20a9

WARNING: line length of 105 exceeds 100 columns
#8050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8026:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8027:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20aa

WARNING: line length of 105 exceeds 100 columns
#8052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8028:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8029:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20ab

WARNING: line length of 105 exceeds 100 columns
#8054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8030:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8031:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20ac

WARNING: line length of 105 exceeds 100 columns
#8056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8032:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8033:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20ad

WARNING: line length of 105 exceeds 100 columns
#8058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8034:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8035:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20ae

WARNING: line length of 105 exceeds 100 columns
#8060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8036:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8037:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20af

WARNING: line length of 105 exceeds 100 columns
#8062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8038:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8039:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20b0

WARNING: line length of 105 exceeds 100 columns
#8064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8040:
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#8065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8041:
+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20b1

WARNING: line length of 105 exceeds 100 columns
#8066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8042:
+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8043:
+#define regDIG0_HDMI_ACR_32_0                                                                           0x20b2

WARNING: line length of 105 exceeds 100 columns
#8068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8044:
+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8045:
+#define regDIG0_HDMI_ACR_32_1                                                                           0x20b3

WARNING: line length of 105 exceeds 100 columns
#8070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8046:
+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8047:
+#define regDIG0_HDMI_ACR_44_0                                                                           0x20b4

WARNING: line length of 105 exceeds 100 columns
#8072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8048:
+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8049:
+#define regDIG0_HDMI_ACR_44_1                                                                           0x20b5

WARNING: line length of 105 exceeds 100 columns
#8074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8050:
+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8051:
+#define regDIG0_HDMI_ACR_48_0                                                                           0x20b6

WARNING: line length of 105 exceeds 100 columns
#8076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8052:
+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8053:
+#define regDIG0_HDMI_ACR_48_1                                                                           0x20b7

WARNING: line length of 105 exceeds 100 columns
#8078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8054:
+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8055:
+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20b8

WARNING: line length of 105 exceeds 100 columns
#8080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8056:
+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8057:
+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20b9

WARNING: line length of 105 exceeds 100 columns
#8082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8058:
+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8059:
+#define regDIG0_AFMT_CNTL                                                                               0x20ba

WARNING: line length of 105 exceeds 100 columns
#8084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8060:
+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8061:
+#define regDIG0_DIG_BE_CLK_CNTL                                                                         0x20bb

WARNING: line length of 105 exceeds 100 columns
#8086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8062:
+#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8063:
+#define regDIG0_DIG_BE_CNTL                                                                             0x20bc

WARNING: line length of 105 exceeds 100 columns
#8088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8064:
+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8065:
+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20bd

WARNING: line length of 105 exceeds 100 columns
#8090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8066:
+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8067:
+#define regDIG0_TMDS_CNTL                                                                               0x20e4

WARNING: line length of 105 exceeds 100 columns
#8092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8068:
+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8069:
+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20e5

WARNING: line length of 105 exceeds 100 columns
#8094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8070:
+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8071:
+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20e6

WARNING: line length of 105 exceeds 100 columns
#8096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8072:
+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8073:
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20e7

WARNING: line length of 105 exceeds 100 columns
#8098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8074:
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8075:
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20e8

WARNING: line length of 105 exceeds 100 columns
#8100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8076:
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8077:
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20e9

WARNING: line length of 105 exceeds 100 columns
#8102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8078:
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8079:
+#define regDIG0_TMDS_CTL_BITS                                                                           0x20eb

WARNING: line length of 105 exceeds 100 columns
#8104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8080:
+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8081:
+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20ec

WARNING: line length of 105 exceeds 100 columns
#8106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8082:
+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8083:
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20ed

WARNING: line length of 105 exceeds 100 columns
#8108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8084:
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#8109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8085:
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20ee

WARNING: line length of 105 exceeds 100 columns
#8110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8086:
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8087:
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20ef

WARNING: line length of 105 exceeds 100 columns
#8112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8088:
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8089:
+#define regDIG0_DIG_VERSION                                                                             0x20f1

WARNING: line length of 105 exceeds 100 columns
#8114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8090:
+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8095:
+#define regDP0_DP_LINK_CNTL                                                                             0x211e

WARNING: line length of 105 exceeds 100 columns
#8120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8096:
+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8097:
+#define regDP0_DP_PIXEL_FORMAT                                                                          0x211f

WARNING: line length of 105 exceeds 100 columns
#8122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8098:
+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8099:
+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x2120

WARNING: line length of 105 exceeds 100 columns
#8124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8100:
+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8101:
+#define regDP0_DP_CONFIG                                                                                0x2121

WARNING: line length of 105 exceeds 100 columns
#8126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8102:
+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#8127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8103:
+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x2122

WARNING: line length of 105 exceeds 100 columns
#8128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8104:
+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8105:
+#define regDP0_DP_STEER_FIFO                                                                            0x2123

WARNING: line length of 105 exceeds 100 columns
#8130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8106:
+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8107:
+#define regDP0_DP_MSA_MISC                                                                              0x2124

WARNING: line length of 105 exceeds 100 columns
#8132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8108:
+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8109:
+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x2125

WARNING: line length of 105 exceeds 100 columns
#8134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8110:
+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8111:
+#define regDP0_DP_VID_TIMING                                                                            0x2126

WARNING: line length of 105 exceeds 100 columns
#8136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8112:
+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8113:
+#define regDP0_DP_VID_N                                                                                 0x2127

WARNING: line length of 105 exceeds 100 columns
#8138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8114:
+#define regDP0_DP_VID_N_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8115:
+#define regDP0_DP_VID_M                                                                                 0x2128

WARNING: line length of 105 exceeds 100 columns
#8140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8116:
+#define regDP0_DP_VID_M_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8117:
+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2129

WARNING: line length of 105 exceeds 100 columns
#8142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8118:
+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8119:
+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x212a

WARNING: line length of 105 exceeds 100 columns
#8144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8120:
+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8121:
+#define regDP0_DP_VID_MSA_VBID                                                                          0x212b

WARNING: line length of 105 exceeds 100 columns
#8146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8122:
+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8123:
+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x212c

WARNING: line length of 105 exceeds 100 columns
#8148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8124:
+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8125:
+#define regDP0_DP_DPHY_CNTL                                                                             0x212d

WARNING: line length of 105 exceeds 100 columns
#8150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8126:
+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8127:
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x212e

WARNING: line length of 105 exceeds 100 columns
#8152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8128:
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8129:
+#define regDP0_DP_DPHY_SYM0                                                                             0x212f

WARNING: line length of 105 exceeds 100 columns
#8154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8130:
+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8131:
+#define regDP0_DP_DPHY_SYM1                                                                             0x2130

WARNING: line length of 105 exceeds 100 columns
#8156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8132:
+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8133:
+#define regDP0_DP_DPHY_SYM2                                                                             0x2131

WARNING: line length of 105 exceeds 100 columns
#8158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8134:
+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8135:
+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x2132

WARNING: line length of 105 exceeds 100 columns
#8160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8136:
+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8137:
+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x2133

WARNING: line length of 105 exceeds 100 columns
#8162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8138:
+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8139:
+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x2134

WARNING: line length of 105 exceeds 100 columns
#8164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8140:
+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8141:
+#define regDP0_DP_DPHY_CRC_EN                                                                           0x2135

WARNING: line length of 105 exceeds 100 columns
#8166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8142:
+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8143:
+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2136

WARNING: line length of 105 exceeds 100 columns
#8168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8144:
+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8145:
+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2137

WARNING: line length of 105 exceeds 100 columns
#8170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8146:
+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8147:
+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2138

WARNING: line length of 105 exceeds 100 columns
#8172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8148:
+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8149:
+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2139

WARNING: line length of 105 exceeds 100 columns
#8174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8150:
+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#8175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8151:
+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x213a

WARNING: line length of 105 exceeds 100 columns
#8176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8152:
+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8153:
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x213b

WARNING: line length of 105 exceeds 100 columns
#8178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8154:
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8155:
+#define regDP0_DP_SEC_CNTL                                                                              0x2141

WARNING: line length of 105 exceeds 100 columns
#8180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8156:
+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8157:
+#define regDP0_DP_SEC_CNTL1                                                                             0x2142

WARNING: line length of 105 exceeds 100 columns
#8182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8158:
+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8159:
+#define regDP0_DP_SEC_FRAMING1                                                                          0x2143

WARNING: line length of 105 exceeds 100 columns
#8184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8160:
+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8161:
+#define regDP0_DP_SEC_FRAMING2                                                                          0x2144

WARNING: line length of 105 exceeds 100 columns
#8186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8162:
+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8163:
+#define regDP0_DP_SEC_FRAMING3                                                                          0x2145

WARNING: line length of 105 exceeds 100 columns
#8188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8164:
+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8165:
+#define regDP0_DP_SEC_FRAMING4                                                                          0x2146

WARNING: line length of 105 exceeds 100 columns
#8190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8166:
+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8167:
+#define regDP0_DP_SEC_AUD_N                                                                             0x2147

WARNING: line length of 105 exceeds 100 columns
#8192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8168:
+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8169:
+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2148

WARNING: line length of 105 exceeds 100 columns
#8194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8170:
+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8171:
+#define regDP0_DP_SEC_AUD_M                                                                             0x2149

WARNING: line length of 105 exceeds 100 columns
#8196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8172:
+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8173:
+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x214a

WARNING: line length of 105 exceeds 100 columns
#8198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8174:
+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8175:
+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x214b

WARNING: line length of 105 exceeds 100 columns
#8200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8176:
+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8177:
+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x214c

WARNING: line length of 105 exceeds 100 columns
#8202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8178:
+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8179:
+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x214d

WARNING: line length of 105 exceeds 100 columns
#8204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8180:
+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8181:
+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x214f

WARNING: line length of 105 exceeds 100 columns
#8206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8182:
+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8183:
+#define regDP0_DP_MSE_SAT0                                                                              0x2150

WARNING: line length of 105 exceeds 100 columns
#8208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8184:
+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8185:
+#define regDP0_DP_MSE_SAT1                                                                              0x2151

WARNING: line length of 105 exceeds 100 columns
#8210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8186:
+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8187:
+#define regDP0_DP_MSE_SAT2                                                                              0x2152

WARNING: line length of 105 exceeds 100 columns
#8212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8188:
+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8189:
+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x2153

WARNING: line length of 105 exceeds 100 columns
#8214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8190:
+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8191:
+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x2154

WARNING: line length of 105 exceeds 100 columns
#8216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8192:
+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8193:
+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x2155

WARNING: line length of 105 exceeds 100 columns
#8218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8194:
+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8195:
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x215a

WARNING: line length of 105 exceeds 100 columns
#8220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8196:
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8197:
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x215b

WARNING: line length of 105 exceeds 100 columns
#8222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8198:
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8199:
+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x215d

WARNING: line length of 105 exceeds 100 columns
#8224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8200:
+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8201:
+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x215e

WARNING: line length of 105 exceeds 100 columns
#8226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8202:
+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8203:
+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x215f

WARNING: line length of 105 exceeds 100 columns
#8228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8204:
+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8205:
+#define regDP0_DP_DPIA_SPARE                                                                            0x2160

WARNING: line length of 105 exceeds 100 columns
#8230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8206:
+#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8207:
+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x2162

WARNING: line length of 105 exceeds 100 columns
#8232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8208:
+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8209:
+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x2163

WARNING: line length of 105 exceeds 100 columns
#8234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8210:
+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8211:
+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x2164

WARNING: line length of 105 exceeds 100 columns
#8236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8212:
+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8213:
+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x2165

WARNING: line length of 105 exceeds 100 columns
#8238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8214:
+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8215:
+#define regDP0_DP_MSO_CNTL                                                                              0x2166

WARNING: line length of 105 exceeds 100 columns
#8240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8216:
+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8217:
+#define regDP0_DP_MSO_CNTL1                                                                             0x2167

WARNING: line length of 105 exceeds 100 columns
#8242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8218:
+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8219:
+#define regDP0_DP_DSC_CNTL                                                                              0x2168

WARNING: line length of 105 exceeds 100 columns
#8244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8220:
+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8221:
+#define regDP0_DP_SEC_CNTL2                                                                             0x2169

WARNING: line length of 105 exceeds 100 columns
#8246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8222:
+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8223:
+#define regDP0_DP_SEC_CNTL3                                                                             0x216a

WARNING: line length of 105 exceeds 100 columns
#8248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8224:
+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8225:
+#define regDP0_DP_SEC_CNTL4                                                                             0x216b

WARNING: line length of 105 exceeds 100 columns
#8250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8226:
+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8227:
+#define regDP0_DP_SEC_CNTL5                                                                             0x216c

WARNING: line length of 105 exceeds 100 columns
#8252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8228:
+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8229:
+#define regDP0_DP_SEC_CNTL6                                                                             0x216d

WARNING: line length of 105 exceeds 100 columns
#8254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8230:
+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8231:
+#define regDP0_DP_SEC_CNTL7                                                                             0x216e

WARNING: line length of 105 exceeds 100 columns
#8256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8232:
+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8233:
+#define regDP0_DP_DB_CNTL                                                                               0x216f

WARNING: line length of 105 exceeds 100 columns
#8258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8234:
+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8235:
+#define regDP0_DP_MSA_VBID_MISC                                                                         0x2170

WARNING: line length of 105 exceeds 100 columns
#8260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8236:
+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8237:
+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x2171

WARNING: line length of 105 exceeds 100 columns
#8262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8238:
+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8239:
+#define regDP0_DP_ALPM_CNTL                                                                             0x2173

WARNING: line length of 105 exceeds 100 columns
#8264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8240:
+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8241:
+#define regDP0_DP_GSP8_CNTL                                                                             0x2174

WARNING: line length of 105 exceeds 100 columns
#8266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8242:
+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8243:
+#define regDP0_DP_GSP9_CNTL                                                                             0x2175

WARNING: line length of 105 exceeds 100 columns
#8268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8244:
+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8245:
+#define regDP0_DP_GSP10_CNTL                                                                            0x2176

WARNING: line length of 105 exceeds 100 columns
#8270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8246:
+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8247:
+#define regDP0_DP_GSP11_CNTL                                                                            0x2177

WARNING: line length of 105 exceeds 100 columns
#8272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8248:
+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8249:
+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2178

WARNING: line length of 105 exceeds 100 columns
#8274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8250:
+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8251:
+#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2179

WARNING: line length of 105 exceeds 100 columns
#8276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8252:
+#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8253:
+#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x217a

WARNING: line length of 105 exceeds 100 columns
#8278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8254:
+#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8255:
+#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x217b

WARNING: line length of 105 exceeds 100 columns
#8280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8256:
+#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8257:
+#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x217c

WARNING: line length of 105 exceeds 100 columns
#8282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8258:
+#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8259:
+#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x217d

WARNING: line length of 105 exceeds 100 columns
#8284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8260:
+#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8261:
+#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x217e

WARNING: line length of 105 exceeds 100 columns
#8286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8262:
+#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8263:
+#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x217f

WARNING: line length of 105 exceeds 100 columns
#8288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8264:
+#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#8289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8265:
+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x2180

WARNING: line length of 105 exceeds 100 columns
#8290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8266:
+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8267:
+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x2181

WARNING: line length of 105 exceeds 100 columns
#8292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8268:
+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8269:
+#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x2182

WARNING: line length of 105 exceeds 100 columns
#8294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8270:
+#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8275:
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x218c

WARNING: line length of 105 exceeds 100 columns
#8300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8276:
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#8301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8277:
+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x218d

WARNING: line length of 105 exceeds 100 columns
#8302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8278:
+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8279:
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x218e

WARNING: line length of 105 exceeds 100 columns
#8304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8280:
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#8305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8281:
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x218f

WARNING: line length of 105 exceeds 100 columns
#8306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8282:
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#8307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8283:
+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x2190

WARNING: line length of 105 exceeds 100 columns
#8308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8284:
+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8285:
+#define regVPG1_VPG_MEM_PWR                                                                             0x2191

WARNING: line length of 105 exceeds 100 columns
#8310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8286:
+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8287:
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x2192

WARNING: line length of 105 exceeds 100 columns
#8312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8288:
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8289:
+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x2193

WARNING: line length of 105 exceeds 100 columns
#8314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8290:
+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8291:
+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2194

WARNING: line length of 105 exceeds 100 columns
#8316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8292:
+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8293:
+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2195

WARNING: line length of 105 exceeds 100 columns
#8318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8294:
+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8299:
+#define regAFMT1_AFMT_ACP                                                                               0x2197

WARNING: line length of 105 exceeds 100 columns
#8324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8300:
+#define regAFMT1_AFMT_ACP_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8301:
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2198

WARNING: line length of 105 exceeds 100 columns
#8326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8302:
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#8327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8303:
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2199

WARNING: line length of 105 exceeds 100 columns
#8328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8304:
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8305:
+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x219a

WARNING: line length of 105 exceeds 100 columns
#8330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8306:
+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8307:
+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x219b

WARNING: line length of 105 exceeds 100 columns
#8332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8308:
+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8309:
+#define regAFMT1_AFMT_60958_0                                                                           0x219c

WARNING: line length of 105 exceeds 100 columns
#8334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8310:
+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8311:
+#define regAFMT1_AFMT_60958_1                                                                           0x219d

WARNING: line length of 105 exceeds 100 columns
#8336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8312:
+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8313:
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x219e

WARNING: line length of 105 exceeds 100 columns
#8338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8314:
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8315:
+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x219f

WARNING: line length of 105 exceeds 100 columns
#8340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8316:
+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8317:
+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x21a0

WARNING: line length of 105 exceeds 100 columns
#8342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8318:
+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8319:
+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x21a1

WARNING: line length of 105 exceeds 100 columns
#8344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8320:
+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8321:
+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x21a2

WARNING: line length of 105 exceeds 100 columns
#8346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8322:
+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8323:
+#define regAFMT1_AFMT_60958_2                                                                           0x21a3

WARNING: line length of 105 exceeds 100 columns
#8348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8324:
+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8325:
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x21a4

WARNING: line length of 105 exceeds 100 columns
#8350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8326:
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8327:
+#define regAFMT1_AFMT_STATUS                                                                            0x21a5

WARNING: line length of 105 exceeds 100 columns
#8352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8328:
+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8329:
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x21a6

WARNING: line length of 105 exceeds 100 columns
#8354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8330:
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8331:
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x21a7

WARNING: line length of 105 exceeds 100 columns
#8356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8332:
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#8357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8333:
+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x21a8

WARNING: line length of 105 exceeds 100 columns
#8358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8334:
+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8335:
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x21a9

WARNING: line length of 105 exceeds 100 columns
#8360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8336:
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8337:
+#define regAFMT1_AFMT_MEM_PWR                                                                           0x21ab

WARNING: line length of 105 exceeds 100 columns
#8362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8338:
+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8343:
+#define regDME1_DME_CONTROL                                                                             0x21b5

WARNING: line length of 105 exceeds 100 columns
#8368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8344:
+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8345:
+#define regDME1_DME_MEMORY_CONTROL                                                                      0x21b6

WARNING: line length of 105 exceeds 100 columns
#8370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8346:
+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8351:
+#define regDIG1_DIG_FE_CNTL                                                                             0x21b7

WARNING: line length of 105 exceeds 100 columns
#8376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8352:
+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8353:
+#define regDIG1_DIG_FE_CLK_CNTL                                                                         0x21b8

WARNING: line length of 105 exceeds 100 columns
#8378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8354:
+#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8355:
+#define regDIG1_DIG_FE_EN_CNTL                                                                          0x21b9

WARNING: line length of 105 exceeds 100 columns
#8380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8356:
+#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8357:
+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x21ba

WARNING: line length of 105 exceeds 100 columns
#8382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8358:
+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8359:
+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x21bb

WARNING: line length of 105 exceeds 100 columns
#8384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8360:
+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#8385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8361:
+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x21bc

WARNING: line length of 105 exceeds 100 columns
#8386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8362:
+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8363:
+#define regDIG1_DIG_TEST_PATTERN                                                                        0x21bd

WARNING: line length of 105 exceeds 100 columns
#8388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8364:
+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8365:
+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x21be

WARNING: line length of 105 exceeds 100 columns
#8390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8366:
+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8367:
+#define regDIG1_DIG_FIFO_CTRL0                                                                          0x21bf

WARNING: line length of 105 exceeds 100 columns
#8392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8368:
+#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8369:
+#define regDIG1_DIG_FIFO_CTRL1                                                                          0x21c0

WARNING: line length of 105 exceeds 100 columns
#8394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8370:
+#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8371:
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x21c1

WARNING: line length of 105 exceeds 100 columns
#8396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8372:
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8373:
+#define regDIG1_HDMI_CONTROL                                                                            0x21c2

WARNING: line length of 105 exceeds 100 columns
#8398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8374:
+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8375:
+#define regDIG1_HDMI_STATUS                                                                             0x21c3

WARNING: line length of 105 exceeds 100 columns
#8400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8376:
+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8377:
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x21c4

WARNING: line length of 105 exceeds 100 columns
#8402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8378:
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#8403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8379:
+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x21c5

WARNING: line length of 105 exceeds 100 columns
#8404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8380:
+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8381:
+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x21c6

WARNING: line length of 105 exceeds 100 columns
#8406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8382:
+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8383:
+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x21c7

WARNING: line length of 105 exceeds 100 columns
#8408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8384:
+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8385:
+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x21c8

WARNING: line length of 105 exceeds 100 columns
#8410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8386:
+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8387:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x21c9

WARNING: line length of 105 exceeds 100 columns
#8412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8388:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8389:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x21ca

WARNING: line length of 105 exceeds 100 columns
#8414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8390:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8391:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x21cb

WARNING: line length of 105 exceeds 100 columns
#8416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8392:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8393:
+#define regDIG1_HDMI_GC                                                                                 0x21cc

WARNING: line length of 105 exceeds 100 columns
#8418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8394:
+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8395:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x21cd

WARNING: line length of 105 exceeds 100 columns
#8420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8396:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8397:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21ce

WARNING: line length of 105 exceeds 100 columns
#8422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8398:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8399:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21cf

WARNING: line length of 105 exceeds 100 columns
#8424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8400:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8401:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21d0

WARNING: line length of 105 exceeds 100 columns
#8426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8402:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8403:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21d1

WARNING: line length of 105 exceeds 100 columns
#8428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8404:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8405:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21d2

WARNING: line length of 105 exceeds 100 columns
#8430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8406:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8407:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21d3

WARNING: line length of 105 exceeds 100 columns
#8432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8408:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8409:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21d4

WARNING: line length of 105 exceeds 100 columns
#8434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8410:
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#8435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8411:
+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21d5

WARNING: line length of 105 exceeds 100 columns
#8436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8412:
+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8413:
+#define regDIG1_HDMI_ACR_32_0                                                                           0x21d6

WARNING: line length of 105 exceeds 100 columns
#8438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8414:
+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8415:
+#define regDIG1_HDMI_ACR_32_1                                                                           0x21d7

WARNING: line length of 105 exceeds 100 columns
#8440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8416:
+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8417:
+#define regDIG1_HDMI_ACR_44_0                                                                           0x21d8

WARNING: line length of 105 exceeds 100 columns
#8442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8418:
+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8419:
+#define regDIG1_HDMI_ACR_44_1                                                                           0x21d9

WARNING: line length of 105 exceeds 100 columns
#8444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8420:
+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8421:
+#define regDIG1_HDMI_ACR_48_0                                                                           0x21da

WARNING: line length of 105 exceeds 100 columns
#8446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8422:
+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8423:
+#define regDIG1_HDMI_ACR_48_1                                                                           0x21db

WARNING: line length of 105 exceeds 100 columns
#8448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8424:
+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8425:
+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21dc

WARNING: line length of 105 exceeds 100 columns
#8450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8426:
+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8427:
+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21dd

WARNING: line length of 105 exceeds 100 columns
#8452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8428:
+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8429:
+#define regDIG1_AFMT_CNTL                                                                               0x21de

WARNING: line length of 105 exceeds 100 columns
#8454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8430:
+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8431:
+#define regDIG1_DIG_BE_CLK_CNTL                                                                         0x21df

WARNING: line length of 105 exceeds 100 columns
#8456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8432:
+#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8433:
+#define regDIG1_DIG_BE_CNTL                                                                             0x21e0

WARNING: line length of 105 exceeds 100 columns
#8458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8434:
+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8435:
+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21e1

WARNING: line length of 105 exceeds 100 columns
#8460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8436:
+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8437:
+#define regDIG1_TMDS_CNTL                                                                               0x2208

WARNING: line length of 105 exceeds 100 columns
#8462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8438:
+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8439:
+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x2209

WARNING: line length of 105 exceeds 100 columns
#8464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8440:
+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8441:
+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x220a

WARNING: line length of 105 exceeds 100 columns
#8466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8442:
+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8443:
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x220b

WARNING: line length of 105 exceeds 100 columns
#8468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8444:
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8445:
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x220c

WARNING: line length of 105 exceeds 100 columns
#8470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8446:
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8447:
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x220d

WARNING: line length of 105 exceeds 100 columns
#8472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8448:
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8449:
+#define regDIG1_TMDS_CTL_BITS                                                                           0x220f

WARNING: line length of 105 exceeds 100 columns
#8474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8450:
+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8451:
+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x2210

WARNING: line length of 105 exceeds 100 columns
#8476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8452:
+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8453:
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2211

WARNING: line length of 105 exceeds 100 columns
#8478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8454:
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#8479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8455:
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x2212

WARNING: line length of 105 exceeds 100 columns
#8480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8456:
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8457:
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x2213

WARNING: line length of 105 exceeds 100 columns
#8482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8458:
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8459:
+#define regDIG1_DIG_VERSION                                                                             0x2215

WARNING: line length of 105 exceeds 100 columns
#8484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8460:
+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8465:
+#define regDP1_DP_LINK_CNTL                                                                             0x2242

WARNING: line length of 105 exceeds 100 columns
#8490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8466:
+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8467:
+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2243

WARNING: line length of 105 exceeds 100 columns
#8492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8468:
+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8469:
+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x2244

WARNING: line length of 105 exceeds 100 columns
#8494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8470:
+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8471:
+#define regDP1_DP_CONFIG                                                                                0x2245

WARNING: line length of 105 exceeds 100 columns
#8496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8472:
+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#8497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8473:
+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x2246

WARNING: line length of 105 exceeds 100 columns
#8498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8474:
+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8475:
+#define regDP1_DP_STEER_FIFO                                                                            0x2247

WARNING: line length of 105 exceeds 100 columns
#8500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8476:
+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8477:
+#define regDP1_DP_MSA_MISC                                                                              0x2248

WARNING: line length of 105 exceeds 100 columns
#8502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8478:
+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8479:
+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x2249

WARNING: line length of 105 exceeds 100 columns
#8504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8480:
+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8481:
+#define regDP1_DP_VID_TIMING                                                                            0x224a

WARNING: line length of 105 exceeds 100 columns
#8506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8482:
+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8483:
+#define regDP1_DP_VID_N                                                                                 0x224b

WARNING: line length of 105 exceeds 100 columns
#8508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8484:
+#define regDP1_DP_VID_N_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8485:
+#define regDP1_DP_VID_M                                                                                 0x224c

WARNING: line length of 105 exceeds 100 columns
#8510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8486:
+#define regDP1_DP_VID_M_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8487:
+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x224d

WARNING: line length of 105 exceeds 100 columns
#8512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8488:
+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8489:
+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x224e

WARNING: line length of 105 exceeds 100 columns
#8514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8490:
+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8491:
+#define regDP1_DP_VID_MSA_VBID                                                                          0x224f

WARNING: line length of 105 exceeds 100 columns
#8516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8492:
+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8493:
+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2250

WARNING: line length of 105 exceeds 100 columns
#8518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8494:
+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8495:
+#define regDP1_DP_DPHY_CNTL                                                                             0x2251

WARNING: line length of 105 exceeds 100 columns
#8520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8496:
+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8497:
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2252

WARNING: line length of 105 exceeds 100 columns
#8522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8498:
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8499:
+#define regDP1_DP_DPHY_SYM0                                                                             0x2253

WARNING: line length of 105 exceeds 100 columns
#8524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8500:
+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8501:
+#define regDP1_DP_DPHY_SYM1                                                                             0x2254

WARNING: line length of 105 exceeds 100 columns
#8526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8502:
+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8503:
+#define regDP1_DP_DPHY_SYM2                                                                             0x2255

WARNING: line length of 105 exceeds 100 columns
#8528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8504:
+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8505:
+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x2256

WARNING: line length of 105 exceeds 100 columns
#8530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8506:
+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8507:
+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x2257

WARNING: line length of 105 exceeds 100 columns
#8532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8508:
+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8509:
+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x2258

WARNING: line length of 105 exceeds 100 columns
#8534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8510:
+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8511:
+#define regDP1_DP_DPHY_CRC_EN                                                                           0x2259

WARNING: line length of 105 exceeds 100 columns
#8536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8512:
+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8513:
+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x225a

WARNING: line length of 105 exceeds 100 columns
#8538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8514:
+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8515:
+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x225b

WARNING: line length of 105 exceeds 100 columns
#8540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8516:
+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8517:
+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x225c

WARNING: line length of 105 exceeds 100 columns
#8542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8518:
+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8519:
+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x225d

WARNING: line length of 105 exceeds 100 columns
#8544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8520:
+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#8545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8521:
+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x225e

WARNING: line length of 105 exceeds 100 columns
#8546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8522:
+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8523:
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x225f

WARNING: line length of 105 exceeds 100 columns
#8548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8524:
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8525:
+#define regDP1_DP_SEC_CNTL                                                                              0x2265

WARNING: line length of 105 exceeds 100 columns
#8550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8526:
+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8527:
+#define regDP1_DP_SEC_CNTL1                                                                             0x2266

WARNING: line length of 105 exceeds 100 columns
#8552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8528:
+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8529:
+#define regDP1_DP_SEC_FRAMING1                                                                          0x2267

WARNING: line length of 105 exceeds 100 columns
#8554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8530:
+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8531:
+#define regDP1_DP_SEC_FRAMING2                                                                          0x2268

WARNING: line length of 105 exceeds 100 columns
#8556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8532:
+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8533:
+#define regDP1_DP_SEC_FRAMING3                                                                          0x2269

WARNING: line length of 105 exceeds 100 columns
#8558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8534:
+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8535:
+#define regDP1_DP_SEC_FRAMING4                                                                          0x226a

WARNING: line length of 105 exceeds 100 columns
#8560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8536:
+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8537:
+#define regDP1_DP_SEC_AUD_N                                                                             0x226b

WARNING: line length of 105 exceeds 100 columns
#8562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8538:
+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8539:
+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x226c

WARNING: line length of 105 exceeds 100 columns
#8564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8540:
+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8541:
+#define regDP1_DP_SEC_AUD_M                                                                             0x226d

WARNING: line length of 105 exceeds 100 columns
#8566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8542:
+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8543:
+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x226e

WARNING: line length of 105 exceeds 100 columns
#8568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8544:
+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8545:
+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x226f

WARNING: line length of 105 exceeds 100 columns
#8570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8546:
+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8547:
+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2270

WARNING: line length of 105 exceeds 100 columns
#8572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8548:
+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8549:
+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2271

WARNING: line length of 105 exceeds 100 columns
#8574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8550:
+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8551:
+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2273

WARNING: line length of 105 exceeds 100 columns
#8576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8552:
+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8553:
+#define regDP1_DP_MSE_SAT0                                                                              0x2274

WARNING: line length of 105 exceeds 100 columns
#8578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8554:
+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8555:
+#define regDP1_DP_MSE_SAT1                                                                              0x2275

WARNING: line length of 105 exceeds 100 columns
#8580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8556:
+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8557:
+#define regDP1_DP_MSE_SAT2                                                                              0x2276

WARNING: line length of 105 exceeds 100 columns
#8582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8558:
+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8559:
+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x2277

WARNING: line length of 105 exceeds 100 columns
#8584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8560:
+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8561:
+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x2278

WARNING: line length of 105 exceeds 100 columns
#8586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8562:
+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8563:
+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x2279

WARNING: line length of 105 exceeds 100 columns
#8588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8564:
+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8565:
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x227e

WARNING: line length of 105 exceeds 100 columns
#8590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8566:
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8567:
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x227f

WARNING: line length of 105 exceeds 100 columns
#8592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8568:
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8569:
+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2281

WARNING: line length of 105 exceeds 100 columns
#8594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8570:
+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8571:
+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2282

WARNING: line length of 105 exceeds 100 columns
#8596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8572:
+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8573:
+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2283

WARNING: line length of 105 exceeds 100 columns
#8598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8574:
+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8575:
+#define regDP1_DP_DPIA_SPARE                                                                            0x2284

WARNING: line length of 105 exceeds 100 columns
#8600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8576:
+#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8577:
+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x2286

WARNING: line length of 105 exceeds 100 columns
#8602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8578:
+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8579:
+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x2287

WARNING: line length of 105 exceeds 100 columns
#8604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8580:
+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8581:
+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x2288

WARNING: line length of 105 exceeds 100 columns
#8606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8582:
+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8583:
+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x2289

WARNING: line length of 105 exceeds 100 columns
#8608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8584:
+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8585:
+#define regDP1_DP_MSO_CNTL                                                                              0x228a

WARNING: line length of 105 exceeds 100 columns
#8610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8586:
+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8587:
+#define regDP1_DP_MSO_CNTL1                                                                             0x228b

WARNING: line length of 105 exceeds 100 columns
#8612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8588:
+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8589:
+#define regDP1_DP_DSC_CNTL                                                                              0x228c

WARNING: line length of 105 exceeds 100 columns
#8614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8590:
+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8591:
+#define regDP1_DP_SEC_CNTL2                                                                             0x228d

WARNING: line length of 105 exceeds 100 columns
#8616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8592:
+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8593:
+#define regDP1_DP_SEC_CNTL3                                                                             0x228e

WARNING: line length of 105 exceeds 100 columns
#8618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8594:
+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8595:
+#define regDP1_DP_SEC_CNTL4                                                                             0x228f

WARNING: line length of 105 exceeds 100 columns
#8620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8596:
+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8597:
+#define regDP1_DP_SEC_CNTL5                                                                             0x2290

WARNING: line length of 105 exceeds 100 columns
#8622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8598:
+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8599:
+#define regDP1_DP_SEC_CNTL6                                                                             0x2291

WARNING: line length of 105 exceeds 100 columns
#8624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8600:
+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8601:
+#define regDP1_DP_SEC_CNTL7                                                                             0x2292

WARNING: line length of 105 exceeds 100 columns
#8626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8602:
+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8603:
+#define regDP1_DP_DB_CNTL                                                                               0x2293

WARNING: line length of 105 exceeds 100 columns
#8628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8604:
+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8605:
+#define regDP1_DP_MSA_VBID_MISC                                                                         0x2294

WARNING: line length of 105 exceeds 100 columns
#8630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8606:
+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8607:
+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x2295

WARNING: line length of 105 exceeds 100 columns
#8632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8608:
+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8609:
+#define regDP1_DP_ALPM_CNTL                                                                             0x2297

WARNING: line length of 105 exceeds 100 columns
#8634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8610:
+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8611:
+#define regDP1_DP_GSP8_CNTL                                                                             0x2298

WARNING: line length of 105 exceeds 100 columns
#8636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8612:
+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8613:
+#define regDP1_DP_GSP9_CNTL                                                                             0x2299

WARNING: line length of 105 exceeds 100 columns
#8638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8614:
+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8615:
+#define regDP1_DP_GSP10_CNTL                                                                            0x229a

WARNING: line length of 105 exceeds 100 columns
#8640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8616:
+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8617:
+#define regDP1_DP_GSP11_CNTL                                                                            0x229b

WARNING: line length of 105 exceeds 100 columns
#8642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8618:
+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8619:
+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x229c

WARNING: line length of 105 exceeds 100 columns
#8644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8620:
+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8621:
+#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x229d

WARNING: line length of 105 exceeds 100 columns
#8646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8622:
+#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8623:
+#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x229e

WARNING: line length of 105 exceeds 100 columns
#8648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8624:
+#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8625:
+#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x229f

WARNING: line length of 105 exceeds 100 columns
#8650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8626:
+#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8627:
+#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x22a0

WARNING: line length of 105 exceeds 100 columns
#8652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8628:
+#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8629:
+#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x22a1

WARNING: line length of 105 exceeds 100 columns
#8654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8630:
+#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8631:
+#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x22a2

WARNING: line length of 105 exceeds 100 columns
#8656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8632:
+#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8633:
+#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x22a3

WARNING: line length of 105 exceeds 100 columns
#8658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8634:
+#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#8659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8635:
+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x22a4

WARNING: line length of 105 exceeds 100 columns
#8660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8636:
+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8637:
+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x22a5

WARNING: line length of 105 exceeds 100 columns
#8662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8638:
+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8639:
+#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x22a6

WARNING: line length of 105 exceeds 100 columns
#8664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8640:
+#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8645:
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x22b0

WARNING: line length of 105 exceeds 100 columns
#8670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8646:
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#8671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8647:
+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x22b1

WARNING: line length of 105 exceeds 100 columns
#8672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8648:
+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8649:
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x22b2

WARNING: line length of 105 exceeds 100 columns
#8674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8650:
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#8675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8651:
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x22b3

WARNING: line length of 105 exceeds 100 columns
#8676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8652:
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#8677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8653:
+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x22b4

WARNING: line length of 105 exceeds 100 columns
#8678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8654:
+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8655:
+#define regVPG2_VPG_MEM_PWR                                                                             0x22b5

WARNING: line length of 105 exceeds 100 columns
#8680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8656:
+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8657:
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x22b6

WARNING: line length of 105 exceeds 100 columns
#8682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8658:
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8659:
+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x22b7

WARNING: line length of 105 exceeds 100 columns
#8684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8660:
+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8661:
+#define regVPG2_VPG_MPEG_INFO0                                                                          0x22b8

WARNING: line length of 105 exceeds 100 columns
#8686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8662:
+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8663:
+#define regVPG2_VPG_MPEG_INFO1                                                                          0x22b9

WARNING: line length of 105 exceeds 100 columns
#8688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8664:
+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8669:
+#define regAFMT2_AFMT_ACP                                                                               0x22bb

WARNING: line length of 105 exceeds 100 columns
#8694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8670:
+#define regAFMT2_AFMT_ACP_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8671:
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x22bc

WARNING: line length of 105 exceeds 100 columns
#8696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8672:
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#8697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8673:
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x22bd

WARNING: line length of 105 exceeds 100 columns
#8698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8674:
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8675:
+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x22be

WARNING: line length of 105 exceeds 100 columns
#8700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8676:
+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8677:
+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x22bf

WARNING: line length of 105 exceeds 100 columns
#8702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8678:
+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8679:
+#define regAFMT2_AFMT_60958_0                                                                           0x22c0

WARNING: line length of 105 exceeds 100 columns
#8704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8680:
+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8681:
+#define regAFMT2_AFMT_60958_1                                                                           0x22c1

WARNING: line length of 105 exceeds 100 columns
#8706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8682:
+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8683:
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x22c2

WARNING: line length of 105 exceeds 100 columns
#8708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8684:
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8685:
+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x22c3

WARNING: line length of 105 exceeds 100 columns
#8710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8686:
+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8687:
+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x22c4

WARNING: line length of 105 exceeds 100 columns
#8712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8688:
+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8689:
+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x22c5

WARNING: line length of 105 exceeds 100 columns
#8714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8690:
+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8691:
+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x22c6

WARNING: line length of 105 exceeds 100 columns
#8716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8692:
+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8693:
+#define regAFMT2_AFMT_60958_2                                                                           0x22c7

WARNING: line length of 105 exceeds 100 columns
#8718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8694:
+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8695:
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x22c8

WARNING: line length of 105 exceeds 100 columns
#8720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8696:
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8697:
+#define regAFMT2_AFMT_STATUS                                                                            0x22c9

WARNING: line length of 105 exceeds 100 columns
#8722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8698:
+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8699:
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x22ca

WARNING: line length of 105 exceeds 100 columns
#8724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8700:
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8701:
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x22cb

WARNING: line length of 105 exceeds 100 columns
#8726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8702:
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#8727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8703:
+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x22cc

WARNING: line length of 105 exceeds 100 columns
#8728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8704:
+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8705:
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x22cd

WARNING: line length of 105 exceeds 100 columns
#8730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8706:
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8707:
+#define regAFMT2_AFMT_MEM_PWR                                                                           0x22cf

WARNING: line length of 105 exceeds 100 columns
#8732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8708:
+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8713:
+#define regDME2_DME_CONTROL                                                                             0x22d9

WARNING: line length of 105 exceeds 100 columns
#8738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8714:
+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8715:
+#define regDME2_DME_MEMORY_CONTROL                                                                      0x22da

WARNING: line length of 105 exceeds 100 columns
#8740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8716:
+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8721:
+#define regDIG2_DIG_FE_CNTL                                                                             0x22db

WARNING: line length of 105 exceeds 100 columns
#8746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8722:
+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8723:
+#define regDIG2_DIG_FE_CLK_CNTL                                                                         0x22dc

WARNING: line length of 105 exceeds 100 columns
#8748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8724:
+#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8725:
+#define regDIG2_DIG_FE_EN_CNTL                                                                          0x22dd

WARNING: line length of 105 exceeds 100 columns
#8750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8726:
+#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8727:
+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x22de

WARNING: line length of 105 exceeds 100 columns
#8752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8728:
+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8729:
+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x22df

WARNING: line length of 105 exceeds 100 columns
#8754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8730:
+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#8755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8731:
+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x22e0

WARNING: line length of 105 exceeds 100 columns
#8756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8732:
+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8733:
+#define regDIG2_DIG_TEST_PATTERN                                                                        0x22e1

WARNING: line length of 105 exceeds 100 columns
#8758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8734:
+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8735:
+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x22e2

WARNING: line length of 105 exceeds 100 columns
#8760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8736:
+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8737:
+#define regDIG2_DIG_FIFO_CTRL0                                                                          0x22e3

WARNING: line length of 105 exceeds 100 columns
#8762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8738:
+#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8739:
+#define regDIG2_DIG_FIFO_CTRL1                                                                          0x22e4

WARNING: line length of 105 exceeds 100 columns
#8764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8740:
+#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8741:
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x22e5

WARNING: line length of 105 exceeds 100 columns
#8766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8742:
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8743:
+#define regDIG2_HDMI_CONTROL                                                                            0x22e6

WARNING: line length of 105 exceeds 100 columns
#8768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8744:
+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8745:
+#define regDIG2_HDMI_STATUS                                                                             0x22e7

WARNING: line length of 105 exceeds 100 columns
#8770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8746:
+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8747:
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x22e8

WARNING: line length of 105 exceeds 100 columns
#8772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8748:
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#8773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8749:
+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x22e9

WARNING: line length of 105 exceeds 100 columns
#8774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8750:
+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8751:
+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x22ea

WARNING: line length of 105 exceeds 100 columns
#8776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8752:
+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8753:
+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x22eb

WARNING: line length of 105 exceeds 100 columns
#8778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8754:
+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8755:
+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x22ec

WARNING: line length of 105 exceeds 100 columns
#8780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8756:
+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8757:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x22ed

WARNING: line length of 105 exceeds 100 columns
#8782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8758:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8759:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x22ee

WARNING: line length of 105 exceeds 100 columns
#8784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8760:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8761:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x22ef

WARNING: line length of 105 exceeds 100 columns
#8786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8762:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8763:
+#define regDIG2_HDMI_GC                                                                                 0x22f0

WARNING: line length of 105 exceeds 100 columns
#8788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8764:
+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8765:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x22f1

WARNING: line length of 105 exceeds 100 columns
#8790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8766:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8767:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22f2

WARNING: line length of 105 exceeds 100 columns
#8792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8768:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8769:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22f3

WARNING: line length of 105 exceeds 100 columns
#8794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8770:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8771:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22f4

WARNING: line length of 105 exceeds 100 columns
#8796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8772:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8773:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22f5

WARNING: line length of 105 exceeds 100 columns
#8798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8774:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8775:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22f6

WARNING: line length of 105 exceeds 100 columns
#8800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8776:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8777:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22f7

WARNING: line length of 105 exceeds 100 columns
#8802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8778:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#8803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8779:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22f8

WARNING: line length of 105 exceeds 100 columns
#8804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8780:
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#8805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8781:
+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22f9

WARNING: line length of 105 exceeds 100 columns
#8806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8782:
+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8783:
+#define regDIG2_HDMI_ACR_32_0                                                                           0x22fa

WARNING: line length of 105 exceeds 100 columns
#8808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8784:
+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8785:
+#define regDIG2_HDMI_ACR_32_1                                                                           0x22fb

WARNING: line length of 105 exceeds 100 columns
#8810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8786:
+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8787:
+#define regDIG2_HDMI_ACR_44_0                                                                           0x22fc

WARNING: line length of 105 exceeds 100 columns
#8812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8788:
+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8789:
+#define regDIG2_HDMI_ACR_44_1                                                                           0x22fd

WARNING: line length of 105 exceeds 100 columns
#8814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8790:
+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8791:
+#define regDIG2_HDMI_ACR_48_0                                                                           0x22fe

WARNING: line length of 105 exceeds 100 columns
#8816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8792:
+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8793:
+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ff

WARNING: line length of 105 exceeds 100 columns
#8818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8794:
+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8795:
+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x2300

WARNING: line length of 105 exceeds 100 columns
#8820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8796:
+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8797:
+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x2301

WARNING: line length of 105 exceeds 100 columns
#8822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8798:
+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8799:
+#define regDIG2_AFMT_CNTL                                                                               0x2302

WARNING: line length of 105 exceeds 100 columns
#8824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8800:
+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8801:
+#define regDIG2_DIG_BE_CLK_CNTL                                                                         0x2303

WARNING: line length of 105 exceeds 100 columns
#8826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8802:
+#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8803:
+#define regDIG2_DIG_BE_CNTL                                                                             0x2304

WARNING: line length of 105 exceeds 100 columns
#8828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8804:
+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8805:
+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x2305

WARNING: line length of 105 exceeds 100 columns
#8830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8806:
+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8807:
+#define regDIG2_TMDS_CNTL                                                                               0x232c

WARNING: line length of 105 exceeds 100 columns
#8832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8808:
+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8809:
+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x232d

WARNING: line length of 105 exceeds 100 columns
#8834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8810:
+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8811:
+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x232e

WARNING: line length of 105 exceeds 100 columns
#8836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8812:
+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8813:
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x232f

WARNING: line length of 105 exceeds 100 columns
#8838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8814:
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8815:
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2330

WARNING: line length of 105 exceeds 100 columns
#8840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8816:
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8817:
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2331

WARNING: line length of 105 exceeds 100 columns
#8842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8818:
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#8843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8819:
+#define regDIG2_TMDS_CTL_BITS                                                                           0x2333

WARNING: line length of 105 exceeds 100 columns
#8844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8820:
+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8821:
+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x2334

WARNING: line length of 105 exceeds 100 columns
#8846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8822:
+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#8847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8823:
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2335

WARNING: line length of 105 exceeds 100 columns
#8848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8824:
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#8849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8825:
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x2336

WARNING: line length of 105 exceeds 100 columns
#8850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8826:
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8827:
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x2337

WARNING: line length of 105 exceeds 100 columns
#8852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8828:
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8829:
+#define regDIG2_DIG_VERSION                                                                             0x2339

WARNING: line length of 105 exceeds 100 columns
#8854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8830:
+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8835:
+#define regDP2_DP_LINK_CNTL                                                                             0x2366

WARNING: line length of 105 exceeds 100 columns
#8860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8836:
+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8837:
+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2367

WARNING: line length of 105 exceeds 100 columns
#8862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8838:
+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8839:
+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x2368

WARNING: line length of 105 exceeds 100 columns
#8864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8840:
+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8841:
+#define regDP2_DP_CONFIG                                                                                0x2369

WARNING: line length of 105 exceeds 100 columns
#8866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8842:
+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#8867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8843:
+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x236a

WARNING: line length of 105 exceeds 100 columns
#8868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8844:
+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8845:
+#define regDP2_DP_STEER_FIFO                                                                            0x236b

WARNING: line length of 105 exceeds 100 columns
#8870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8846:
+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8847:
+#define regDP2_DP_MSA_MISC                                                                              0x236c

WARNING: line length of 105 exceeds 100 columns
#8872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8848:
+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8849:
+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x236d

WARNING: line length of 105 exceeds 100 columns
#8874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8850:
+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8851:
+#define regDP2_DP_VID_TIMING                                                                            0x236e

WARNING: line length of 105 exceeds 100 columns
#8876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8852:
+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8853:
+#define regDP2_DP_VID_N                                                                                 0x236f

WARNING: line length of 105 exceeds 100 columns
#8878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8854:
+#define regDP2_DP_VID_N_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8855:
+#define regDP2_DP_VID_M                                                                                 0x2370

WARNING: line length of 105 exceeds 100 columns
#8880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8856:
+#define regDP2_DP_VID_M_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#8881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8857:
+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2371

WARNING: line length of 105 exceeds 100 columns
#8882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8858:
+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8859:
+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2372

WARNING: line length of 105 exceeds 100 columns
#8884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8860:
+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#8885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8861:
+#define regDP2_DP_VID_MSA_VBID                                                                          0x2373

WARNING: line length of 105 exceeds 100 columns
#8886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8862:
+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8863:
+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2374

WARNING: line length of 105 exceeds 100 columns
#8888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8864:
+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8865:
+#define regDP2_DP_DPHY_CNTL                                                                             0x2375

WARNING: line length of 105 exceeds 100 columns
#8890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8866:
+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8867:
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2376

WARNING: line length of 105 exceeds 100 columns
#8892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8868:
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8869:
+#define regDP2_DP_DPHY_SYM0                                                                             0x2377

WARNING: line length of 105 exceeds 100 columns
#8894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8870:
+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8871:
+#define regDP2_DP_DPHY_SYM1                                                                             0x2378

WARNING: line length of 105 exceeds 100 columns
#8896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8872:
+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8873:
+#define regDP2_DP_DPHY_SYM2                                                                             0x2379

WARNING: line length of 105 exceeds 100 columns
#8898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8874:
+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8875:
+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x237a

WARNING: line length of 105 exceeds 100 columns
#8900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8876:
+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8877:
+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x237b

WARNING: line length of 105 exceeds 100 columns
#8902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8878:
+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8879:
+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x237c

WARNING: line length of 105 exceeds 100 columns
#8904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8880:
+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8881:
+#define regDP2_DP_DPHY_CRC_EN                                                                           0x237d

WARNING: line length of 105 exceeds 100 columns
#8906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8882:
+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#8907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8883:
+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x237e

WARNING: line length of 105 exceeds 100 columns
#8908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8884:
+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8885:
+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x237f

WARNING: line length of 105 exceeds 100 columns
#8910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8886:
+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8887:
+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2380

WARNING: line length of 105 exceeds 100 columns
#8912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8888:
+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8889:
+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2381

WARNING: line length of 105 exceeds 100 columns
#8914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8890:
+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#8915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8891:
+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2382

WARNING: line length of 105 exceeds 100 columns
#8916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8892:
+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8893:
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2383

WARNING: line length of 105 exceeds 100 columns
#8918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8894:
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8895:
+#define regDP2_DP_SEC_CNTL                                                                              0x2389

WARNING: line length of 105 exceeds 100 columns
#8920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8896:
+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8897:
+#define regDP2_DP_SEC_CNTL1                                                                             0x238a

WARNING: line length of 105 exceeds 100 columns
#8922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8898:
+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8899:
+#define regDP2_DP_SEC_FRAMING1                                                                          0x238b

WARNING: line length of 105 exceeds 100 columns
#8924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8900:
+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8901:
+#define regDP2_DP_SEC_FRAMING2                                                                          0x238c

WARNING: line length of 105 exceeds 100 columns
#8926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8902:
+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8903:
+#define regDP2_DP_SEC_FRAMING3                                                                          0x238d

WARNING: line length of 105 exceeds 100 columns
#8928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8904:
+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8905:
+#define regDP2_DP_SEC_FRAMING4                                                                          0x238e

WARNING: line length of 105 exceeds 100 columns
#8930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8906:
+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#8931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8907:
+#define regDP2_DP_SEC_AUD_N                                                                             0x238f

WARNING: line length of 105 exceeds 100 columns
#8932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8908:
+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8909:
+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2390

WARNING: line length of 105 exceeds 100 columns
#8934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8910:
+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8911:
+#define regDP2_DP_SEC_AUD_M                                                                             0x2391

WARNING: line length of 105 exceeds 100 columns
#8936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8912:
+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8913:
+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2392

WARNING: line length of 105 exceeds 100 columns
#8938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8914:
+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#8939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8915:
+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2393

WARNING: line length of 105 exceeds 100 columns
#8940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8916:
+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8917:
+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2394

WARNING: line length of 105 exceeds 100 columns
#8942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8918:
+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8919:
+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2395

WARNING: line length of 105 exceeds 100 columns
#8944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8920:
+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8921:
+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2397

WARNING: line length of 105 exceeds 100 columns
#8946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8922:
+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8923:
+#define regDP2_DP_MSE_SAT0                                                                              0x2398

WARNING: line length of 105 exceeds 100 columns
#8948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8924:
+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8925:
+#define regDP2_DP_MSE_SAT1                                                                              0x2399

WARNING: line length of 105 exceeds 100 columns
#8950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8926:
+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8927:
+#define regDP2_DP_MSE_SAT2                                                                              0x239a

WARNING: line length of 105 exceeds 100 columns
#8952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8928:
+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8929:
+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x239b

WARNING: line length of 105 exceeds 100 columns
#8954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8930:
+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#8955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8931:
+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x239c

WARNING: line length of 105 exceeds 100 columns
#8956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8932:
+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8933:
+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x239d

WARNING: line length of 105 exceeds 100 columns
#8958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8934:
+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#8959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8935:
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x23a2

WARNING: line length of 105 exceeds 100 columns
#8960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8936:
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#8961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8937:
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x23a3

WARNING: line length of 105 exceeds 100 columns
#8962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8938:
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#8963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8939:
+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x23a5

WARNING: line length of 105 exceeds 100 columns
#8964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8940:
+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8941:
+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x23a6

WARNING: line length of 105 exceeds 100 columns
#8966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8942:
+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8943:
+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x23a7

WARNING: line length of 105 exceeds 100 columns
#8968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8944:
+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#8969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8945:
+#define regDP2_DP_DPIA_SPARE                                                                            0x23a8

WARNING: line length of 105 exceeds 100 columns
#8970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8946:
+#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#8971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8947:
+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x23aa

WARNING: line length of 105 exceeds 100 columns
#8972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8948:
+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8949:
+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x23ab

WARNING: line length of 105 exceeds 100 columns
#8974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8950:
+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8951:
+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x23ac

WARNING: line length of 105 exceeds 100 columns
#8976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8952:
+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8953:
+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x23ad

WARNING: line length of 105 exceeds 100 columns
#8978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8954:
+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#8979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8955:
+#define regDP2_DP_MSO_CNTL                                                                              0x23ae

WARNING: line length of 105 exceeds 100 columns
#8980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8956:
+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8957:
+#define regDP2_DP_MSO_CNTL1                                                                             0x23af

WARNING: line length of 105 exceeds 100 columns
#8982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8958:
+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8959:
+#define regDP2_DP_DSC_CNTL                                                                              0x23b0

WARNING: line length of 105 exceeds 100 columns
#8984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8960:
+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#8985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8961:
+#define regDP2_DP_SEC_CNTL2                                                                             0x23b1

WARNING: line length of 105 exceeds 100 columns
#8986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8962:
+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8963:
+#define regDP2_DP_SEC_CNTL3                                                                             0x23b2

WARNING: line length of 105 exceeds 100 columns
#8988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8964:
+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8965:
+#define regDP2_DP_SEC_CNTL4                                                                             0x23b3

WARNING: line length of 105 exceeds 100 columns
#8990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8966:
+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8967:
+#define regDP2_DP_SEC_CNTL5                                                                             0x23b4

WARNING: line length of 105 exceeds 100 columns
#8992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8968:
+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8969:
+#define regDP2_DP_SEC_CNTL6                                                                             0x23b5

WARNING: line length of 105 exceeds 100 columns
#8994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8970:
+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8971:
+#define regDP2_DP_SEC_CNTL7                                                                             0x23b6

WARNING: line length of 105 exceeds 100 columns
#8996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8972:
+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#8997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8973:
+#define regDP2_DP_DB_CNTL                                                                               0x23b7

WARNING: line length of 105 exceeds 100 columns
#8998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8974:
+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#8999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8975:
+#define regDP2_DP_MSA_VBID_MISC                                                                         0x23b8

WARNING: line length of 105 exceeds 100 columns
#9000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8976:
+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8977:
+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x23b9

WARNING: line length of 105 exceeds 100 columns
#9002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8978:
+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8979:
+#define regDP2_DP_ALPM_CNTL                                                                             0x23bb

WARNING: line length of 105 exceeds 100 columns
#9004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8980:
+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8981:
+#define regDP2_DP_GSP8_CNTL                                                                             0x23bc

WARNING: line length of 105 exceeds 100 columns
#9006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8982:
+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8983:
+#define regDP2_DP_GSP9_CNTL                                                                             0x23bd

WARNING: line length of 105 exceeds 100 columns
#9008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8984:
+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8985:
+#define regDP2_DP_GSP10_CNTL                                                                            0x23be

WARNING: line length of 105 exceeds 100 columns
#9010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8986:
+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8987:
+#define regDP2_DP_GSP11_CNTL                                                                            0x23bf

WARNING: line length of 105 exceeds 100 columns
#9012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8988:
+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8989:
+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x23c0

WARNING: line length of 105 exceeds 100 columns
#9014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8990:
+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8991:
+#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x23c1

WARNING: line length of 105 exceeds 100 columns
#9016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8992:
+#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8993:
+#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x23c2

WARNING: line length of 105 exceeds 100 columns
#9018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8994:
+#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8995:
+#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x23c3

WARNING: line length of 105 exceeds 100 columns
#9020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8996:
+#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8997:
+#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x23c4

WARNING: line length of 105 exceeds 100 columns
#9022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8998:
+#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:8999:
+#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x23c5

WARNING: line length of 105 exceeds 100 columns
#9024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9000:
+#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9001:
+#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x23c6

WARNING: line length of 105 exceeds 100 columns
#9026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9002:
+#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9003:
+#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x23c7

WARNING: line length of 105 exceeds 100 columns
#9028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9004:
+#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#9029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9005:
+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x23c8

WARNING: line length of 105 exceeds 100 columns
#9030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9006:
+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9007:
+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x23c9

WARNING: line length of 105 exceeds 100 columns
#9032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9008:
+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9009:
+#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x23ca

WARNING: line length of 105 exceeds 100 columns
#9034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9010:
+#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9015:
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x23d4

WARNING: line length of 105 exceeds 100 columns
#9040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9016:
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#9041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9017:
+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x23d5

WARNING: line length of 105 exceeds 100 columns
#9042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9018:
+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9019:
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x23d6

WARNING: line length of 105 exceeds 100 columns
#9044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9020:
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#9045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9021:
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x23d7

WARNING: line length of 105 exceeds 100 columns
#9046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9022:
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#9047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9023:
+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x23d8

WARNING: line length of 105 exceeds 100 columns
#9048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9024:
+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9025:
+#define regVPG3_VPG_MEM_PWR                                                                             0x23d9

WARNING: line length of 105 exceeds 100 columns
#9050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9026:
+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9027:
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x23da

WARNING: line length of 105 exceeds 100 columns
#9052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9028:
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9029:
+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x23db

WARNING: line length of 105 exceeds 100 columns
#9054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9030:
+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9031:
+#define regVPG3_VPG_MPEG_INFO0                                                                          0x23dc

WARNING: line length of 105 exceeds 100 columns
#9056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9032:
+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9033:
+#define regVPG3_VPG_MPEG_INFO1                                                                          0x23dd

WARNING: line length of 105 exceeds 100 columns
#9058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9034:
+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9039:
+#define regAFMT3_AFMT_ACP                                                                               0x23df

WARNING: line length of 105 exceeds 100 columns
#9064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9040:
+#define regAFMT3_AFMT_ACP_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9041:
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x23e0

WARNING: line length of 105 exceeds 100 columns
#9066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9042:
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#9067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9043:
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x23e1

WARNING: line length of 105 exceeds 100 columns
#9068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9044:
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9045:
+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x23e2

WARNING: line length of 105 exceeds 100 columns
#9070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9046:
+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9047:
+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x23e3

WARNING: line length of 105 exceeds 100 columns
#9072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9048:
+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9049:
+#define regAFMT3_AFMT_60958_0                                                                           0x23e4

WARNING: line length of 105 exceeds 100 columns
#9074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9050:
+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9051:
+#define regAFMT3_AFMT_60958_1                                                                           0x23e5

WARNING: line length of 105 exceeds 100 columns
#9076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9052:
+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9053:
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x23e6

WARNING: line length of 105 exceeds 100 columns
#9078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9054:
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9055:
+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x23e7

WARNING: line length of 105 exceeds 100 columns
#9080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9056:
+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9057:
+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x23e8

WARNING: line length of 105 exceeds 100 columns
#9082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9058:
+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9059:
+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x23e9

WARNING: line length of 105 exceeds 100 columns
#9084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9060:
+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9061:
+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x23ea

WARNING: line length of 105 exceeds 100 columns
#9086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9062:
+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9063:
+#define regAFMT3_AFMT_60958_2                                                                           0x23eb

WARNING: line length of 105 exceeds 100 columns
#9088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9064:
+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9065:
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x23ec

WARNING: line length of 105 exceeds 100 columns
#9090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9066:
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9067:
+#define regAFMT3_AFMT_STATUS                                                                            0x23ed

WARNING: line length of 105 exceeds 100 columns
#9092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9068:
+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9069:
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x23ee

WARNING: line length of 105 exceeds 100 columns
#9094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9070:
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#9095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9071:
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x23ef

WARNING: line length of 105 exceeds 100 columns
#9096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9072:
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#9097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9073:
+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x23f0

WARNING: line length of 105 exceeds 100 columns
#9098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9074:
+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9075:
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x23f1

WARNING: line length of 105 exceeds 100 columns
#9100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9076:
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9077:
+#define regAFMT3_AFMT_MEM_PWR                                                                           0x23f3

WARNING: line length of 105 exceeds 100 columns
#9102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9078:
+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9083:
+#define regDME3_DME_CONTROL                                                                             0x23fd

WARNING: line length of 105 exceeds 100 columns
#9108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9084:
+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9085:
+#define regDME3_DME_MEMORY_CONTROL                                                                      0x23fe

WARNING: line length of 105 exceeds 100 columns
#9110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9086:
+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9091:
+#define regDIG3_DIG_FE_CNTL                                                                             0x23ff

WARNING: line length of 105 exceeds 100 columns
#9116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9092:
+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9093:
+#define regDIG3_DIG_FE_CLK_CNTL                                                                         0x2400

WARNING: line length of 105 exceeds 100 columns
#9118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9094:
+#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9095:
+#define regDIG3_DIG_FE_EN_CNTL                                                                          0x2401

WARNING: line length of 105 exceeds 100 columns
#9120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9096:
+#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9097:
+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x2402

WARNING: line length of 105 exceeds 100 columns
#9122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9098:
+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9099:
+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x2403

WARNING: line length of 105 exceeds 100 columns
#9124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9100:
+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#9125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9101:
+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x2404

WARNING: line length of 105 exceeds 100 columns
#9126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9102:
+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9103:
+#define regDIG3_DIG_TEST_PATTERN                                                                        0x2405

WARNING: line length of 105 exceeds 100 columns
#9128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9104:
+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9105:
+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2406

WARNING: line length of 105 exceeds 100 columns
#9130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9106:
+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9107:
+#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2407

WARNING: line length of 105 exceeds 100 columns
#9132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9108:
+#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9109:
+#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2408

WARNING: line length of 105 exceeds 100 columns
#9134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9110:
+#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9111:
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2409

WARNING: line length of 105 exceeds 100 columns
#9136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9112:
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9113:
+#define regDIG3_HDMI_CONTROL                                                                            0x240a

WARNING: line length of 105 exceeds 100 columns
#9138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9114:
+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9115:
+#define regDIG3_HDMI_STATUS                                                                             0x240b

WARNING: line length of 105 exceeds 100 columns
#9140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9116:
+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9117:
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x240c

WARNING: line length of 105 exceeds 100 columns
#9142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9118:
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#9143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9119:
+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x240d

WARNING: line length of 105 exceeds 100 columns
#9144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9120:
+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9121:
+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x240e

WARNING: line length of 105 exceeds 100 columns
#9146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9122:
+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9123:
+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x240f

WARNING: line length of 105 exceeds 100 columns
#9148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9124:
+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9125:
+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2410

WARNING: line length of 105 exceeds 100 columns
#9150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9126:
+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9127:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2411

WARNING: line length of 105 exceeds 100 columns
#9152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9128:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9129:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x2412

WARNING: line length of 105 exceeds 100 columns
#9154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9130:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9131:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x2413

WARNING: line length of 105 exceeds 100 columns
#9156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9132:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9133:
+#define regDIG3_HDMI_GC                                                                                 0x2414

WARNING: line length of 105 exceeds 100 columns
#9158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9134:
+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9135:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2415

WARNING: line length of 105 exceeds 100 columns
#9160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9136:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9137:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2416

WARNING: line length of 105 exceeds 100 columns
#9162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9138:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9139:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2417

WARNING: line length of 105 exceeds 100 columns
#9164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9140:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9141:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2418

WARNING: line length of 105 exceeds 100 columns
#9166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9142:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9143:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x2419

WARNING: line length of 105 exceeds 100 columns
#9168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9144:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9145:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x241a

WARNING: line length of 105 exceeds 100 columns
#9170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9146:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9147:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x241b

WARNING: line length of 105 exceeds 100 columns
#9172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9148:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9149:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x241c

WARNING: line length of 105 exceeds 100 columns
#9174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9150:
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#9175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9151:
+#define regDIG3_HDMI_DB_CONTROL                                                                         0x241d

WARNING: line length of 105 exceeds 100 columns
#9176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9152:
+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9153:
+#define regDIG3_HDMI_ACR_32_0                                                                           0x241e

WARNING: line length of 105 exceeds 100 columns
#9178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9154:
+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9155:
+#define regDIG3_HDMI_ACR_32_1                                                                           0x241f

WARNING: line length of 105 exceeds 100 columns
#9180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9156:
+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9157:
+#define regDIG3_HDMI_ACR_44_0                                                                           0x2420

WARNING: line length of 105 exceeds 100 columns
#9182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9158:
+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9159:
+#define regDIG3_HDMI_ACR_44_1                                                                           0x2421

WARNING: line length of 105 exceeds 100 columns
#9184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9160:
+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9161:
+#define regDIG3_HDMI_ACR_48_0                                                                           0x2422

WARNING: line length of 105 exceeds 100 columns
#9186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9162:
+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9163:
+#define regDIG3_HDMI_ACR_48_1                                                                           0x2423

WARNING: line length of 105 exceeds 100 columns
#9188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9164:
+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9165:
+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x2424

WARNING: line length of 105 exceeds 100 columns
#9190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9166:
+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9167:
+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x2425

WARNING: line length of 105 exceeds 100 columns
#9192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9168:
+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9169:
+#define regDIG3_AFMT_CNTL                                                                               0x2426

WARNING: line length of 105 exceeds 100 columns
#9194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9170:
+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9171:
+#define regDIG3_DIG_BE_CLK_CNTL                                                                         0x2427

WARNING: line length of 105 exceeds 100 columns
#9196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9172:
+#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9173:
+#define regDIG3_DIG_BE_CNTL                                                                             0x2428

WARNING: line length of 105 exceeds 100 columns
#9198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9174:
+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9175:
+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x2429

WARNING: line length of 105 exceeds 100 columns
#9200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9176:
+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9177:
+#define regDIG3_TMDS_CNTL                                                                               0x2450

WARNING: line length of 105 exceeds 100 columns
#9202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9178:
+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9179:
+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x2451

WARNING: line length of 105 exceeds 100 columns
#9204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9180:
+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9181:
+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x2452

WARNING: line length of 105 exceeds 100 columns
#9206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9182:
+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9183:
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x2453

WARNING: line length of 105 exceeds 100 columns
#9208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9184:
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9185:
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2454

WARNING: line length of 105 exceeds 100 columns
#9210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9186:
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#9211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9187:
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2455

WARNING: line length of 105 exceeds 100 columns
#9212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9188:
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#9213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9189:
+#define regDIG3_TMDS_CTL_BITS                                                                           0x2457

WARNING: line length of 105 exceeds 100 columns
#9214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9190:
+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9191:
+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x2458

WARNING: line length of 105 exceeds 100 columns
#9216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9192:
+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9193:
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2459

WARNING: line length of 105 exceeds 100 columns
#9218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9194:
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#9219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9195:
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x245a

WARNING: line length of 105 exceeds 100 columns
#9220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9196:
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9197:
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x245b

WARNING: line length of 105 exceeds 100 columns
#9222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9198:
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9199:
+#define regDIG3_DIG_VERSION                                                                             0x245d

WARNING: line length of 105 exceeds 100 columns
#9224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9200:
+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9205:
+#define regDP3_DP_LINK_CNTL                                                                             0x248a

WARNING: line length of 105 exceeds 100 columns
#9230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9206:
+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9207:
+#define regDP3_DP_PIXEL_FORMAT                                                                          0x248b

WARNING: line length of 105 exceeds 100 columns
#9232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9208:
+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9209:
+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x248c

WARNING: line length of 105 exceeds 100 columns
#9234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9210:
+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9211:
+#define regDP3_DP_CONFIG                                                                                0x248d

WARNING: line length of 105 exceeds 100 columns
#9236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9212:
+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#9237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9213:
+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x248e

WARNING: line length of 105 exceeds 100 columns
#9238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9214:
+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9215:
+#define regDP3_DP_STEER_FIFO                                                                            0x248f

WARNING: line length of 105 exceeds 100 columns
#9240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9216:
+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9217:
+#define regDP3_DP_MSA_MISC                                                                              0x2490

WARNING: line length of 105 exceeds 100 columns
#9242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9218:
+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9219:
+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x2491

WARNING: line length of 105 exceeds 100 columns
#9244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9220:
+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9221:
+#define regDP3_DP_VID_TIMING                                                                            0x2492

WARNING: line length of 105 exceeds 100 columns
#9246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9222:
+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9223:
+#define regDP3_DP_VID_N                                                                                 0x2493

WARNING: line length of 105 exceeds 100 columns
#9248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9224:
+#define regDP3_DP_VID_N_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9225:
+#define regDP3_DP_VID_M                                                                                 0x2494

WARNING: line length of 105 exceeds 100 columns
#9250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9226:
+#define regDP3_DP_VID_M_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9227:
+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2495

WARNING: line length of 105 exceeds 100 columns
#9252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9228:
+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9229:
+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2496

WARNING: line length of 105 exceeds 100 columns
#9254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9230:
+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9231:
+#define regDP3_DP_VID_MSA_VBID                                                                          0x2497

WARNING: line length of 105 exceeds 100 columns
#9256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9232:
+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9233:
+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2498

WARNING: line length of 105 exceeds 100 columns
#9258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9234:
+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9235:
+#define regDP3_DP_DPHY_CNTL                                                                             0x2499

WARNING: line length of 105 exceeds 100 columns
#9260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9236:
+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9237:
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x249a

WARNING: line length of 105 exceeds 100 columns
#9262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9238:
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9239:
+#define regDP3_DP_DPHY_SYM0                                                                             0x249b

WARNING: line length of 105 exceeds 100 columns
#9264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9240:
+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9241:
+#define regDP3_DP_DPHY_SYM1                                                                             0x249c

WARNING: line length of 105 exceeds 100 columns
#9266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9242:
+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9243:
+#define regDP3_DP_DPHY_SYM2                                                                             0x249d

WARNING: line length of 105 exceeds 100 columns
#9268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9244:
+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9245:
+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x249e

WARNING: line length of 105 exceeds 100 columns
#9270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9246:
+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9247:
+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x249f

WARNING: line length of 105 exceeds 100 columns
#9272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9248:
+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9249:
+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x24a0

WARNING: line length of 105 exceeds 100 columns
#9274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9250:
+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9251:
+#define regDP3_DP_DPHY_CRC_EN                                                                           0x24a1

WARNING: line length of 105 exceeds 100 columns
#9276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9252:
+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9253:
+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x24a2

WARNING: line length of 105 exceeds 100 columns
#9278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9254:
+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9255:
+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x24a3

WARNING: line length of 105 exceeds 100 columns
#9280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9256:
+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9257:
+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x24a4

WARNING: line length of 105 exceeds 100 columns
#9282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9258:
+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9259:
+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x24a5

WARNING: line length of 105 exceeds 100 columns
#9284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9260:
+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#9285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9261:
+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x24a6

WARNING: line length of 105 exceeds 100 columns
#9286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9262:
+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9263:
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x24a7

WARNING: line length of 105 exceeds 100 columns
#9288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9264:
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9265:
+#define regDP3_DP_SEC_CNTL                                                                              0x24ad

WARNING: line length of 105 exceeds 100 columns
#9290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9266:
+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9267:
+#define regDP3_DP_SEC_CNTL1                                                                             0x24ae

WARNING: line length of 105 exceeds 100 columns
#9292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9268:
+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9269:
+#define regDP3_DP_SEC_FRAMING1                                                                          0x24af

WARNING: line length of 105 exceeds 100 columns
#9294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9270:
+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9271:
+#define regDP3_DP_SEC_FRAMING2                                                                          0x24b0

WARNING: line length of 105 exceeds 100 columns
#9296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9272:
+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9273:
+#define regDP3_DP_SEC_FRAMING3                                                                          0x24b1

WARNING: line length of 105 exceeds 100 columns
#9298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9274:
+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9275:
+#define regDP3_DP_SEC_FRAMING4                                                                          0x24b2

WARNING: line length of 105 exceeds 100 columns
#9300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9276:
+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9277:
+#define regDP3_DP_SEC_AUD_N                                                                             0x24b3

WARNING: line length of 105 exceeds 100 columns
#9302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9278:
+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9279:
+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x24b4

WARNING: line length of 105 exceeds 100 columns
#9304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9280:
+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9281:
+#define regDP3_DP_SEC_AUD_M                                                                             0x24b5

WARNING: line length of 105 exceeds 100 columns
#9306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9282:
+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9283:
+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x24b6

WARNING: line length of 105 exceeds 100 columns
#9308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9284:
+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9285:
+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x24b7

WARNING: line length of 105 exceeds 100 columns
#9310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9286:
+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9287:
+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x24b8

WARNING: line length of 105 exceeds 100 columns
#9312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9288:
+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9289:
+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x24b9

WARNING: line length of 105 exceeds 100 columns
#9314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9290:
+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9291:
+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x24bb

WARNING: line length of 105 exceeds 100 columns
#9316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9292:
+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9293:
+#define regDP3_DP_MSE_SAT0                                                                              0x24bc

WARNING: line length of 105 exceeds 100 columns
#9318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9294:
+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9295:
+#define regDP3_DP_MSE_SAT1                                                                              0x24bd

WARNING: line length of 105 exceeds 100 columns
#9320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9296:
+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9297:
+#define regDP3_DP_MSE_SAT2                                                                              0x24be

WARNING: line length of 105 exceeds 100 columns
#9322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9298:
+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9299:
+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x24bf

WARNING: line length of 105 exceeds 100 columns
#9324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9300:
+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9301:
+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x24c0

WARNING: line length of 105 exceeds 100 columns
#9326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9302:
+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9303:
+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x24c1

WARNING: line length of 105 exceeds 100 columns
#9328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9304:
+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9305:
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x24c6

WARNING: line length of 105 exceeds 100 columns
#9330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9306:
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9307:
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x24c7

WARNING: line length of 105 exceeds 100 columns
#9332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9308:
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9309:
+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x24c9

WARNING: line length of 105 exceeds 100 columns
#9334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9310:
+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9311:
+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x24ca

WARNING: line length of 105 exceeds 100 columns
#9336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9312:
+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9313:
+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x24cb

WARNING: line length of 105 exceeds 100 columns
#9338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9314:
+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9315:
+#define regDP3_DP_DPIA_SPARE                                                                            0x24cc

WARNING: line length of 105 exceeds 100 columns
#9340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9316:
+#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9317:
+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x24ce

WARNING: line length of 105 exceeds 100 columns
#9342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9318:
+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9319:
+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x24cf

WARNING: line length of 105 exceeds 100 columns
#9344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9320:
+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9321:
+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x24d0

WARNING: line length of 105 exceeds 100 columns
#9346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9322:
+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9323:
+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x24d1

WARNING: line length of 105 exceeds 100 columns
#9348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9324:
+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9325:
+#define regDP3_DP_MSO_CNTL                                                                              0x24d2

WARNING: line length of 105 exceeds 100 columns
#9350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9326:
+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9327:
+#define regDP3_DP_MSO_CNTL1                                                                             0x24d3

WARNING: line length of 105 exceeds 100 columns
#9352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9328:
+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9329:
+#define regDP3_DP_DSC_CNTL                                                                              0x24d4

WARNING: line length of 105 exceeds 100 columns
#9354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9330:
+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9331:
+#define regDP3_DP_SEC_CNTL2                                                                             0x24d5

WARNING: line length of 105 exceeds 100 columns
#9356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9332:
+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9333:
+#define regDP3_DP_SEC_CNTL3                                                                             0x24d6

WARNING: line length of 105 exceeds 100 columns
#9358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9334:
+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9335:
+#define regDP3_DP_SEC_CNTL4                                                                             0x24d7

WARNING: line length of 105 exceeds 100 columns
#9360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9336:
+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9337:
+#define regDP3_DP_SEC_CNTL5                                                                             0x24d8

WARNING: line length of 105 exceeds 100 columns
#9362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9338:
+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9339:
+#define regDP3_DP_SEC_CNTL6                                                                             0x24d9

WARNING: line length of 105 exceeds 100 columns
#9364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9340:
+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9341:
+#define regDP3_DP_SEC_CNTL7                                                                             0x24da

WARNING: line length of 105 exceeds 100 columns
#9366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9342:
+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9343:
+#define regDP3_DP_DB_CNTL                                                                               0x24db

WARNING: line length of 105 exceeds 100 columns
#9368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9344:
+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9345:
+#define regDP3_DP_MSA_VBID_MISC                                                                         0x24dc

WARNING: line length of 105 exceeds 100 columns
#9370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9346:
+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9347:
+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x24dd

WARNING: line length of 105 exceeds 100 columns
#9372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9348:
+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9349:
+#define regDP3_DP_ALPM_CNTL                                                                             0x24df

WARNING: line length of 105 exceeds 100 columns
#9374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9350:
+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9351:
+#define regDP3_DP_GSP8_CNTL                                                                             0x24e0

WARNING: line length of 105 exceeds 100 columns
#9376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9352:
+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9353:
+#define regDP3_DP_GSP9_CNTL                                                                             0x24e1

WARNING: line length of 105 exceeds 100 columns
#9378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9354:
+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9355:
+#define regDP3_DP_GSP10_CNTL                                                                            0x24e2

WARNING: line length of 105 exceeds 100 columns
#9380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9356:
+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9357:
+#define regDP3_DP_GSP11_CNTL                                                                            0x24e3

WARNING: line length of 105 exceeds 100 columns
#9382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9358:
+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9359:
+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x24e4

WARNING: line length of 105 exceeds 100 columns
#9384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9360:
+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9361:
+#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x24e5

WARNING: line length of 105 exceeds 100 columns
#9386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9362:
+#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9363:
+#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x24e6

WARNING: line length of 105 exceeds 100 columns
#9388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9364:
+#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9365:
+#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x24e7

WARNING: line length of 105 exceeds 100 columns
#9390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9366:
+#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9367:
+#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x24e8

WARNING: line length of 105 exceeds 100 columns
#9392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9368:
+#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9369:
+#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x24e9

WARNING: line length of 105 exceeds 100 columns
#9394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9370:
+#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9371:
+#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x24ea

WARNING: line length of 105 exceeds 100 columns
#9396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9372:
+#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9373:
+#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x24eb

WARNING: line length of 105 exceeds 100 columns
#9398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9374:
+#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#9399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9375:
+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x24ec

WARNING: line length of 105 exceeds 100 columns
#9400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9376:
+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9377:
+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x24ed

WARNING: line length of 105 exceeds 100 columns
#9402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9378:
+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9379:
+#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x24ee

WARNING: line length of 105 exceeds 100 columns
#9404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9380:
+#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9385:
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x24f8

WARNING: line length of 105 exceeds 100 columns
#9410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9386:
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#9411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9387:
+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x24f9

WARNING: line length of 105 exceeds 100 columns
#9412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9388:
+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9389:
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x24fa

WARNING: line length of 105 exceeds 100 columns
#9414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9390:
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#9415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9391:
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x24fb

WARNING: line length of 105 exceeds 100 columns
#9416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9392:
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#9417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9393:
+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x24fc

WARNING: line length of 105 exceeds 100 columns
#9418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9394:
+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9395:
+#define regVPG4_VPG_MEM_PWR                                                                             0x24fd

WARNING: line length of 105 exceeds 100 columns
#9420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9396:
+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9397:
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x24fe

WARNING: line length of 105 exceeds 100 columns
#9422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9398:
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9399:
+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x24ff

WARNING: line length of 105 exceeds 100 columns
#9424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9400:
+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9401:
+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2500

WARNING: line length of 105 exceeds 100 columns
#9426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9402:
+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9403:
+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2501

WARNING: line length of 105 exceeds 100 columns
#9428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9404:
+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9409:
+#define regAFMT4_AFMT_ACP                                                                               0x2503

WARNING: line length of 105 exceeds 100 columns
#9434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9410:
+#define regAFMT4_AFMT_ACP_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9411:
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2504

WARNING: line length of 105 exceeds 100 columns
#9436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9412:
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#9437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9413:
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2505

WARNING: line length of 105 exceeds 100 columns
#9438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9414:
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9415:
+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2506

WARNING: line length of 105 exceeds 100 columns
#9440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9416:
+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9417:
+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2507

WARNING: line length of 105 exceeds 100 columns
#9442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9418:
+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9419:
+#define regAFMT4_AFMT_60958_0                                                                           0x2508

WARNING: line length of 105 exceeds 100 columns
#9444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9420:
+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9421:
+#define regAFMT4_AFMT_60958_1                                                                           0x2509

WARNING: line length of 105 exceeds 100 columns
#9446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9422:
+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9423:
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x250a

WARNING: line length of 105 exceeds 100 columns
#9448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9424:
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9425:
+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x250b

WARNING: line length of 105 exceeds 100 columns
#9450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9426:
+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9427:
+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x250c

WARNING: line length of 105 exceeds 100 columns
#9452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9428:
+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9429:
+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x250d

WARNING: line length of 105 exceeds 100 columns
#9454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9430:
+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9431:
+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x250e

WARNING: line length of 105 exceeds 100 columns
#9456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9432:
+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9433:
+#define regAFMT4_AFMT_60958_2                                                                           0x250f

WARNING: line length of 105 exceeds 100 columns
#9458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9434:
+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9435:
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2510

WARNING: line length of 105 exceeds 100 columns
#9460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9436:
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9437:
+#define regAFMT4_AFMT_STATUS                                                                            0x2511

WARNING: line length of 105 exceeds 100 columns
#9462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9438:
+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9439:
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2512

WARNING: line length of 105 exceeds 100 columns
#9464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9440:
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#9465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9441:
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2513

WARNING: line length of 105 exceeds 100 columns
#9466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9442:
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#9467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9443:
+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2514

WARNING: line length of 105 exceeds 100 columns
#9468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9444:
+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9445:
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2515

WARNING: line length of 105 exceeds 100 columns
#9470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9446:
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9447:
+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2517

WARNING: line length of 105 exceeds 100 columns
#9472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9448:
+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9453:
+#define regDME4_DME_CONTROL                                                                             0x2521

WARNING: line length of 105 exceeds 100 columns
#9478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9454:
+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9455:
+#define regDME4_DME_MEMORY_CONTROL                                                                      0x2522

WARNING: line length of 105 exceeds 100 columns
#9480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9456:
+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9461:
+#define regDIG4_DIG_FE_CNTL                                                                             0x2523

WARNING: line length of 105 exceeds 100 columns
#9486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9462:
+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9463:
+#define regDIG4_DIG_FE_CLK_CNTL                                                                         0x2524

WARNING: line length of 105 exceeds 100 columns
#9488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9464:
+#define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9465:
+#define regDIG4_DIG_FE_EN_CNTL                                                                          0x2525

WARNING: line length of 105 exceeds 100 columns
#9490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9466:
+#define regDIG4_DIG_FE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9467:
+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x2526

WARNING: line length of 105 exceeds 100 columns
#9492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9468:
+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9469:
+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x2527

WARNING: line length of 105 exceeds 100 columns
#9494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9470:
+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#9495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9471:
+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x2528

WARNING: line length of 105 exceeds 100 columns
#9496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9472:
+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9473:
+#define regDIG4_DIG_TEST_PATTERN                                                                        0x2529

WARNING: line length of 105 exceeds 100 columns
#9498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9474:
+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9475:
+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x252a

WARNING: line length of 105 exceeds 100 columns
#9500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9476:
+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9477:
+#define regDIG4_DIG_FIFO_CTRL0                                                                          0x252b

WARNING: line length of 105 exceeds 100 columns
#9502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9478:
+#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9479:
+#define regDIG4_DIG_FIFO_CTRL1                                                                          0x252c

WARNING: line length of 105 exceeds 100 columns
#9504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9480:
+#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9481:
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x252d

WARNING: line length of 105 exceeds 100 columns
#9506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9482:
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9483:
+#define regDIG4_HDMI_CONTROL                                                                            0x252e

WARNING: line length of 105 exceeds 100 columns
#9508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9484:
+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9485:
+#define regDIG4_HDMI_STATUS                                                                             0x252f

WARNING: line length of 105 exceeds 100 columns
#9510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9486:
+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9487:
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2530

WARNING: line length of 105 exceeds 100 columns
#9512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9488:
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#9513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9489:
+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2531

WARNING: line length of 105 exceeds 100 columns
#9514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9490:
+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9491:
+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2532

WARNING: line length of 105 exceeds 100 columns
#9516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9492:
+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9493:
+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2533

WARNING: line length of 105 exceeds 100 columns
#9518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9494:
+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9495:
+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2534

WARNING: line length of 105 exceeds 100 columns
#9520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9496:
+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9497:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2535

WARNING: line length of 105 exceeds 100 columns
#9522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9498:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9499:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x2536

WARNING: line length of 105 exceeds 100 columns
#9524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9500:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9501:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x2537

WARNING: line length of 105 exceeds 100 columns
#9526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9502:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9503:
+#define regDIG4_HDMI_GC                                                                                 0x2538

WARNING: line length of 105 exceeds 100 columns
#9528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9504:
+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9505:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2539

WARNING: line length of 105 exceeds 100 columns
#9530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9506:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9507:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x253a

WARNING: line length of 105 exceeds 100 columns
#9532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9508:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9509:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x253b

WARNING: line length of 105 exceeds 100 columns
#9534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9510:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9511:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x253c

WARNING: line length of 105 exceeds 100 columns
#9536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9512:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9513:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x253d

WARNING: line length of 105 exceeds 100 columns
#9538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9514:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9515:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x253e

WARNING: line length of 105 exceeds 100 columns
#9540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9516:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9517:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x253f

WARNING: line length of 105 exceeds 100 columns
#9542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9518:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9519:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x2540

WARNING: line length of 105 exceeds 100 columns
#9544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9520:
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#9545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9521:
+#define regDIG4_HDMI_DB_CONTROL                                                                         0x2541

WARNING: line length of 105 exceeds 100 columns
#9546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9522:
+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9523:
+#define regDIG4_HDMI_ACR_32_0                                                                           0x2542

WARNING: line length of 105 exceeds 100 columns
#9548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9524:
+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9525:
+#define regDIG4_HDMI_ACR_32_1                                                                           0x2543

WARNING: line length of 105 exceeds 100 columns
#9550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9526:
+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9527:
+#define regDIG4_HDMI_ACR_44_0                                                                           0x2544

WARNING: line length of 105 exceeds 100 columns
#9552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9528:
+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9529:
+#define regDIG4_HDMI_ACR_44_1                                                                           0x2545

WARNING: line length of 105 exceeds 100 columns
#9554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9530:
+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9531:
+#define regDIG4_HDMI_ACR_48_0                                                                           0x2546

WARNING: line length of 105 exceeds 100 columns
#9556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9532:
+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9533:
+#define regDIG4_HDMI_ACR_48_1                                                                           0x2547

WARNING: line length of 105 exceeds 100 columns
#9558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9534:
+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9535:
+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x2548

WARNING: line length of 105 exceeds 100 columns
#9560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9536:
+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9537:
+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x2549

WARNING: line length of 105 exceeds 100 columns
#9562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9538:
+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9539:
+#define regDIG4_AFMT_CNTL                                                                               0x254a

WARNING: line length of 105 exceeds 100 columns
#9564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9540:
+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9541:
+#define regDIG4_DIG_BE_CLK_CNTL                                                                         0x254b

WARNING: line length of 105 exceeds 100 columns
#9566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9542:
+#define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9543:
+#define regDIG4_DIG_BE_CNTL                                                                             0x254c

WARNING: line length of 105 exceeds 100 columns
#9568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9544:
+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9545:
+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x254d

WARNING: line length of 105 exceeds 100 columns
#9570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9546:
+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9547:
+#define regDIG4_TMDS_CNTL                                                                               0x2574

WARNING: line length of 105 exceeds 100 columns
#9572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9548:
+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9549:
+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x2575

WARNING: line length of 105 exceeds 100 columns
#9574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9550:
+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9551:
+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x2576

WARNING: line length of 105 exceeds 100 columns
#9576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9552:
+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9553:
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x2577

WARNING: line length of 105 exceeds 100 columns
#9578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9554:
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9555:
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2578

WARNING: line length of 105 exceeds 100 columns
#9580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9556:
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#9581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9557:
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2579

WARNING: line length of 105 exceeds 100 columns
#9582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9558:
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#9583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9559:
+#define regDIG4_TMDS_CTL_BITS                                                                           0x257b

WARNING: line length of 105 exceeds 100 columns
#9584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9560:
+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9561:
+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x257c

WARNING: line length of 105 exceeds 100 columns
#9586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9562:
+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#9587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9563:
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x257d

WARNING: line length of 105 exceeds 100 columns
#9588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9564:
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#9589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9565:
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x257e

WARNING: line length of 105 exceeds 100 columns
#9590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9566:
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9567:
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x257f

WARNING: line length of 105 exceeds 100 columns
#9592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9568:
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9569:
+#define regDIG4_DIG_VERSION                                                                             0x2581

WARNING: line length of 105 exceeds 100 columns
#9594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9570:
+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9575:
+#define regDP4_DP_LINK_CNTL                                                                             0x25ae

WARNING: line length of 105 exceeds 100 columns
#9600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9576:
+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9577:
+#define regDP4_DP_PIXEL_FORMAT                                                                          0x25af

WARNING: line length of 105 exceeds 100 columns
#9602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9578:
+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9579:
+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x25b0

WARNING: line length of 105 exceeds 100 columns
#9604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9580:
+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9581:
+#define regDP4_DP_CONFIG                                                                                0x25b1

WARNING: line length of 105 exceeds 100 columns
#9606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9582:
+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#9607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9583:
+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x25b2

WARNING: line length of 105 exceeds 100 columns
#9608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9584:
+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9585:
+#define regDP4_DP_STEER_FIFO                                                                            0x25b3

WARNING: line length of 105 exceeds 100 columns
#9610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9586:
+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9587:
+#define regDP4_DP_MSA_MISC                                                                              0x25b4

WARNING: line length of 105 exceeds 100 columns
#9612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9588:
+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9589:
+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x25b5

WARNING: line length of 105 exceeds 100 columns
#9614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9590:
+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9591:
+#define regDP4_DP_VID_TIMING                                                                            0x25b6

WARNING: line length of 105 exceeds 100 columns
#9616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9592:
+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9593:
+#define regDP4_DP_VID_N                                                                                 0x25b7

WARNING: line length of 105 exceeds 100 columns
#9618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9594:
+#define regDP4_DP_VID_N_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9595:
+#define regDP4_DP_VID_M                                                                                 0x25b8

WARNING: line length of 105 exceeds 100 columns
#9620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9596:
+#define regDP4_DP_VID_M_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9597:
+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x25b9

WARNING: line length of 105 exceeds 100 columns
#9622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9598:
+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9599:
+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x25ba

WARNING: line length of 105 exceeds 100 columns
#9624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9600:
+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9601:
+#define regDP4_DP_VID_MSA_VBID                                                                          0x25bb

WARNING: line length of 105 exceeds 100 columns
#9626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9602:
+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9603:
+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x25bc

WARNING: line length of 105 exceeds 100 columns
#9628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9604:
+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9605:
+#define regDP4_DP_DPHY_CNTL                                                                             0x25bd

WARNING: line length of 105 exceeds 100 columns
#9630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9606:
+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9607:
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x25be

WARNING: line length of 105 exceeds 100 columns
#9632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9608:
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9609:
+#define regDP4_DP_DPHY_SYM0                                                                             0x25bf

WARNING: line length of 105 exceeds 100 columns
#9634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9610:
+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9611:
+#define regDP4_DP_DPHY_SYM1                                                                             0x25c0

WARNING: line length of 105 exceeds 100 columns
#9636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9612:
+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9613:
+#define regDP4_DP_DPHY_SYM2                                                                             0x25c1

WARNING: line length of 105 exceeds 100 columns
#9638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9614:
+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9615:
+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x25c2

WARNING: line length of 105 exceeds 100 columns
#9640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9616:
+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9617:
+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x25c3

WARNING: line length of 105 exceeds 100 columns
#9642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9618:
+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9619:
+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x25c4

WARNING: line length of 105 exceeds 100 columns
#9644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9620:
+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9621:
+#define regDP4_DP_DPHY_CRC_EN                                                                           0x25c5

WARNING: line length of 105 exceeds 100 columns
#9646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9622:
+#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9623:
+#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x25c6

WARNING: line length of 105 exceeds 100 columns
#9648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9624:
+#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9625:
+#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x25c7

WARNING: line length of 105 exceeds 100 columns
#9650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9626:
+#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9627:
+#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x25c8

WARNING: line length of 105 exceeds 100 columns
#9652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9628:
+#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9629:
+#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x25c9

WARNING: line length of 105 exceeds 100 columns
#9654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9630:
+#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#9655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9631:
+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x25ca

WARNING: line length of 105 exceeds 100 columns
#9656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9632:
+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9633:
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x25cb

WARNING: line length of 105 exceeds 100 columns
#9658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9634:
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9635:
+#define regDP4_DP_SEC_CNTL                                                                              0x25d1

WARNING: line length of 105 exceeds 100 columns
#9660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9636:
+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9637:
+#define regDP4_DP_SEC_CNTL1                                                                             0x25d2

WARNING: line length of 105 exceeds 100 columns
#9662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9638:
+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9639:
+#define regDP4_DP_SEC_FRAMING1                                                                          0x25d3

WARNING: line length of 105 exceeds 100 columns
#9664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9640:
+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9641:
+#define regDP4_DP_SEC_FRAMING2                                                                          0x25d4

WARNING: line length of 105 exceeds 100 columns
#9666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9642:
+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9643:
+#define regDP4_DP_SEC_FRAMING3                                                                          0x25d5

WARNING: line length of 105 exceeds 100 columns
#9668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9644:
+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9645:
+#define regDP4_DP_SEC_FRAMING4                                                                          0x25d6

WARNING: line length of 105 exceeds 100 columns
#9670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9646:
+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9647:
+#define regDP4_DP_SEC_AUD_N                                                                             0x25d7

WARNING: line length of 105 exceeds 100 columns
#9672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9648:
+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9649:
+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x25d8

WARNING: line length of 105 exceeds 100 columns
#9674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9650:
+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9651:
+#define regDP4_DP_SEC_AUD_M                                                                             0x25d9

WARNING: line length of 105 exceeds 100 columns
#9676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9652:
+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9653:
+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x25da

WARNING: line length of 105 exceeds 100 columns
#9678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9654:
+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9655:
+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x25db

WARNING: line length of 105 exceeds 100 columns
#9680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9656:
+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9657:
+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x25dc

WARNING: line length of 105 exceeds 100 columns
#9682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9658:
+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9659:
+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x25dd

WARNING: line length of 105 exceeds 100 columns
#9684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9660:
+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9661:
+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x25df

WARNING: line length of 105 exceeds 100 columns
#9686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9662:
+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9663:
+#define regDP4_DP_MSE_SAT0                                                                              0x25e0

WARNING: line length of 105 exceeds 100 columns
#9688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9664:
+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9665:
+#define regDP4_DP_MSE_SAT1                                                                              0x25e1

WARNING: line length of 105 exceeds 100 columns
#9690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9666:
+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9667:
+#define regDP4_DP_MSE_SAT2                                                                              0x25e2

WARNING: line length of 105 exceeds 100 columns
#9692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9668:
+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9669:
+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x25e3

WARNING: line length of 105 exceeds 100 columns
#9694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9670:
+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9671:
+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x25e4

WARNING: line length of 105 exceeds 100 columns
#9696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9672:
+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9673:
+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x25e5

WARNING: line length of 105 exceeds 100 columns
#9698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9674:
+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9675:
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x25ea

WARNING: line length of 105 exceeds 100 columns
#9700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9676:
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#9701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9677:
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x25eb

WARNING: line length of 105 exceeds 100 columns
#9702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9678:
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9679:
+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x25ed

WARNING: line length of 105 exceeds 100 columns
#9704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9680:
+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9681:
+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x25ee

WARNING: line length of 105 exceeds 100 columns
#9706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9682:
+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9683:
+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x25ef

WARNING: line length of 105 exceeds 100 columns
#9708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9684:
+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9685:
+#define regDP4_DP_DPIA_SPARE                                                                            0x25f0

WARNING: line length of 105 exceeds 100 columns
#9710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9686:
+#define regDP4_DP_DPIA_SPARE_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9687:
+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x25f2

WARNING: line length of 105 exceeds 100 columns
#9712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9688:
+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9689:
+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x25f3

WARNING: line length of 105 exceeds 100 columns
#9714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9690:
+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9691:
+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x25f4

WARNING: line length of 105 exceeds 100 columns
#9716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9692:
+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9693:
+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x25f5

WARNING: line length of 105 exceeds 100 columns
#9718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9694:
+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#9719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9695:
+#define regDP4_DP_MSO_CNTL                                                                              0x25f6

WARNING: line length of 105 exceeds 100 columns
#9720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9696:
+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9697:
+#define regDP4_DP_MSO_CNTL1                                                                             0x25f7

WARNING: line length of 105 exceeds 100 columns
#9722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9698:
+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9699:
+#define regDP4_DP_DSC_CNTL                                                                              0x25f8

WARNING: line length of 105 exceeds 100 columns
#9724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9700:
+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9701:
+#define regDP4_DP_SEC_CNTL2                                                                             0x25f9

WARNING: line length of 105 exceeds 100 columns
#9726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9702:
+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9703:
+#define regDP4_DP_SEC_CNTL3                                                                             0x25fa

WARNING: line length of 105 exceeds 100 columns
#9728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9704:
+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9705:
+#define regDP4_DP_SEC_CNTL4                                                                             0x25fb

WARNING: line length of 105 exceeds 100 columns
#9730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9706:
+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9707:
+#define regDP4_DP_SEC_CNTL5                                                                             0x25fc

WARNING: line length of 105 exceeds 100 columns
#9732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9708:
+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9709:
+#define regDP4_DP_SEC_CNTL6                                                                             0x25fd

WARNING: line length of 105 exceeds 100 columns
#9734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9710:
+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9711:
+#define regDP4_DP_SEC_CNTL7                                                                             0x25fe

WARNING: line length of 105 exceeds 100 columns
#9736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9712:
+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9713:
+#define regDP4_DP_DB_CNTL                                                                               0x25ff

WARNING: line length of 105 exceeds 100 columns
#9738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9714:
+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9715:
+#define regDP4_DP_MSA_VBID_MISC                                                                         0x2600

WARNING: line length of 105 exceeds 100 columns
#9740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9716:
+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9717:
+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x2601

WARNING: line length of 105 exceeds 100 columns
#9742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9718:
+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9719:
+#define regDP4_DP_ALPM_CNTL                                                                             0x2603

WARNING: line length of 105 exceeds 100 columns
#9744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9720:
+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9721:
+#define regDP4_DP_GSP8_CNTL                                                                             0x2604

WARNING: line length of 105 exceeds 100 columns
#9746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9722:
+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9723:
+#define regDP4_DP_GSP9_CNTL                                                                             0x2605

WARNING: line length of 105 exceeds 100 columns
#9748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9724:
+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9725:
+#define regDP4_DP_GSP10_CNTL                                                                            0x2606

WARNING: line length of 105 exceeds 100 columns
#9750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9726:
+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9727:
+#define regDP4_DP_GSP11_CNTL                                                                            0x2607

WARNING: line length of 105 exceeds 100 columns
#9752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9728:
+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9729:
+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2608

WARNING: line length of 105 exceeds 100 columns
#9754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9730:
+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9731:
+#define regDP4_DP_AUXLESS_ALPM_CNTL1                                                                    0x2609

WARNING: line length of 105 exceeds 100 columns
#9756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9732:
+#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9733:
+#define regDP4_DP_AUXLESS_ALPM_CNTL2                                                                    0x260a

WARNING: line length of 105 exceeds 100 columns
#9758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9734:
+#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9735:
+#define regDP4_DP_AUXLESS_ALPM_CNTL3                                                                    0x260b

WARNING: line length of 105 exceeds 100 columns
#9760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9736:
+#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9737:
+#define regDP4_DP_AUXLESS_ALPM_CNTL4                                                                    0x260c

WARNING: line length of 105 exceeds 100 columns
#9762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9738:
+#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9739:
+#define regDP4_DP_AUXLESS_ALPM_CNTL5                                                                    0x260d

WARNING: line length of 105 exceeds 100 columns
#9764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9740:
+#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9741:
+#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x260e

WARNING: line length of 105 exceeds 100 columns
#9766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9742:
+#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2

WARNING: line length of 110 exceeds 100 columns
#9767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9743:
+#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x260f

WARNING: line length of 105 exceeds 100 columns
#9768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9744:
+#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#9769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9745:
+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x2610

WARNING: line length of 105 exceeds 100 columns
#9770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9746:
+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9747:
+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x2611

WARNING: line length of 105 exceeds 100 columns
#9772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9748:
+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9749:
+#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x2612

WARNING: line length of 105 exceeds 100 columns
#9774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9750:
+#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9755:
+#define regDC_GENERICA                                                                                  0x2868

WARNING: line length of 105 exceeds 100 columns
#9780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9756:
+#define regDC_GENERICA_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#9781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9757:
+#define regDC_GENERICB                                                                                  0x2869

WARNING: line length of 105 exceeds 100 columns
#9782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9758:
+#define regDC_GENERICB_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#9783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9759:
+#define regDCIO_CLOCK_CNTL                                                                              0x286a

WARNING: line length of 105 exceeds 100 columns
#9784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9760:
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9761:
+#define regDC_REF_CLK_CNTL                                                                              0x286b

WARNING: line length of 105 exceeds 100 columns
#9786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9762:
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9763:
+#define regUNIPHYA_LINK_CNTL                                                                            0x286d

WARNING: line length of 105 exceeds 100 columns
#9788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9764:
+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9765:
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e

WARNING: line length of 105 exceeds 100 columns
#9790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9766:
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9767:
+#define regUNIPHYB_LINK_CNTL                                                                            0x286f

WARNING: line length of 105 exceeds 100 columns
#9792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9768:
+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9769:
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870

WARNING: line length of 105 exceeds 100 columns
#9794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9770:
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9771:
+#define regUNIPHYC_LINK_CNTL                                                                            0x2871

WARNING: line length of 105 exceeds 100 columns
#9796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9772:
+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9773:
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872

WARNING: line length of 105 exceeds 100 columns
#9798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9774:
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9775:
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874

WARNING: line length of 105 exceeds 100 columns
#9800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9776:
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9777:
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876

WARNING: line length of 105 exceeds 100 columns
#9802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9778:
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9779:
+#define regDCIO_WRCMD_DELAY                                                                             0x287e

WARNING: line length of 105 exceeds 100 columns
#9804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9780:
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9781:
+#define regDC_PINSTRAPS                                                                                 0x2880

WARNING: line length of 105 exceeds 100 columns
#9806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9782:
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9783:
+#define regDCIO_SPARE                                                                                   0x2882

WARNING: line length of 105 exceeds 100 columns
#9808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9784:
+#define regDCIO_SPARE_BASE_IDX                                                                          2

WARNING: line length of 110 exceeds 100 columns
#9809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9785:
+#define regINTERCEPT_STATE                                                                              0x2884

WARNING: line length of 105 exceeds 100 columns
#9810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9786:
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9787:
+#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886

WARNING: line length of 105 exceeds 100 columns
#9812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9788:
+#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9789:
+#define regDCIO_PATTERN_GEN_EN                                                                          0x2887

WARNING: line length of 105 exceeds 100 columns
#9814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9790:
+#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9791:
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b

WARNING: line length of 105 exceeds 100 columns
#9816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9792:
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#9817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9793:
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c

WARNING: line length of 105 exceeds 100 columns
#9818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9794:
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#9819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9795:
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d

WARNING: line length of 105 exceeds 100 columns
#9820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9796:
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#9821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9797:
+#define regDCIO_SOFT_RESET                                                                              0x289e

WARNING: line length of 105 exceeds 100 columns
#9822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9798:
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9803:
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8

WARNING: line length of 105 exceeds 100 columns
#9828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9804:
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#9829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9805:
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9

WARNING: line length of 105 exceeds 100 columns
#9830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9806:
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9807:
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca

WARNING: line length of 105 exceeds 100 columns
#9832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9808:
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9809:
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb

WARNING: line length of 105 exceeds 100 columns
#9834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9810:
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9811:
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0

WARNING: line length of 105 exceeds 100 columns
#9836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9812:
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9813:
+#define regDC_GPIO_DDC1_A                                                                               0x28d1

WARNING: line length of 105 exceeds 100 columns
#9838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9814:
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9815:
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2

WARNING: line length of 105 exceeds 100 columns
#9840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9816:
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9817:
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3

WARNING: line length of 105 exceeds 100 columns
#9842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9818:
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9819:
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4

WARNING: line length of 105 exceeds 100 columns
#9844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9820:
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9821:
+#define regDC_GPIO_DDC2_A                                                                               0x28d5

WARNING: line length of 105 exceeds 100 columns
#9846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9822:
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9823:
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6

WARNING: line length of 105 exceeds 100 columns
#9848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9824:
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9825:
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7

WARNING: line length of 105 exceeds 100 columns
#9850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9826:
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9827:
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8

WARNING: line length of 105 exceeds 100 columns
#9852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9828:
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9829:
+#define regDC_GPIO_DDC3_A                                                                               0x28d9

WARNING: line length of 105 exceeds 100 columns
#9854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9830:
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9831:
+#define regDC_GPIO_DDC3_EN                                                                              0x28da

WARNING: line length of 105 exceeds 100 columns
#9856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9832:
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9833:
+#define regDC_GPIO_DDC3_Y                                                                               0x28db

WARNING: line length of 105 exceeds 100 columns
#9858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9834:
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9835:
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc

WARNING: line length of 105 exceeds 100 columns
#9860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9836:
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9837:
+#define regDC_GPIO_DDC4_A                                                                               0x28dd

WARNING: line length of 105 exceeds 100 columns
#9862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9838:
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9839:
+#define regDC_GPIO_DDC4_EN                                                                              0x28de

WARNING: line length of 105 exceeds 100 columns
#9864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9840:
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9841:
+#define regDC_GPIO_DDC4_Y                                                                               0x28df

WARNING: line length of 105 exceeds 100 columns
#9866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9842:
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9843:
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0

WARNING: line length of 105 exceeds 100 columns
#9868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9844:
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9845:
+#define regDC_GPIO_DDC5_A                                                                               0x28e1

WARNING: line length of 105 exceeds 100 columns
#9870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9846:
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9847:
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2

WARNING: line length of 105 exceeds 100 columns
#9872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9848:
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9849:
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3

WARNING: line length of 105 exceeds 100 columns
#9874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9850:
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9851:
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8

WARNING: line length of 105 exceeds 100 columns
#9876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9852:
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#9877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9853:
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9

WARNING: line length of 105 exceeds 100 columns
#9878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9854:
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9855:
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea

WARNING: line length of 105 exceeds 100 columns
#9880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9856:
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#9881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9857:
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb

WARNING: line length of 105 exceeds 100 columns
#9882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9858:
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9859:
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0

WARNING: line length of 105 exceeds 100 columns
#9884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9860:
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9861:
+#define regDC_GPIO_GENLK_A                                                                              0x28f1

WARNING: line length of 105 exceeds 100 columns
#9886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9862:
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9863:
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2

WARNING: line length of 105 exceeds 100 columns
#9888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9864:
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9865:
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3

WARNING: line length of 105 exceeds 100 columns
#9890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9866:
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9867:
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4

WARNING: line length of 105 exceeds 100 columns
#9892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9868:
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9869:
+#define regDC_GPIO_HPD_A                                                                                0x28f5

WARNING: line length of 105 exceeds 100 columns
#9894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9870:
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#9895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9871:
+#define regDC_GPIO_HPD_EN                                                                               0x28f6

WARNING: line length of 105 exceeds 100 columns
#9896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9872:
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#9897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9873:
+#define regDC_GPIO_HPD_Y                                                                                0x28f7

WARNING: line length of 105 exceeds 100 columns
#9898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9874:
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2

WARNING: line length of 110 exceeds 100 columns
#9899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9875:
+#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8

WARNING: line length of 105 exceeds 100 columns
#9900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9876:
+#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9877:
+#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9

WARNING: line length of 105 exceeds 100 columns
#9902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9878:
+#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#9903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9879:
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa

WARNING: line length of 105 exceeds 100 columns
#9904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9880:
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9881:
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc

WARNING: line length of 105 exceeds 100 columns
#9906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9882:
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9883:
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd

WARNING: line length of 105 exceeds 100 columns
#9908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9884:
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9885:
+#define regPHY_AUX_CNTL                                                                                 0x28ff

WARNING: line length of 105 exceeds 100 columns
#9910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9886:
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9887:
+#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900

WARNING: line length of 105 exceeds 100 columns
#9912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9888:
+#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#9913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9889:
+#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902

WARNING: line length of 105 exceeds 100 columns
#9914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9890:
+#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9891:
+#define regDC_GPIO_TX12_EN                                                                              0x2915

WARNING: line length of 105 exceeds 100 columns
#9916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9892:
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#9917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9893:
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916

WARNING: line length of 105 exceeds 100 columns
#9918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9894:
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9895:
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917

WARNING: line length of 105 exceeds 100 columns
#9920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9896:
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9897:
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918

WARNING: line length of 105 exceeds 100 columns
#9922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9898:
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9899:
+#define regDC_GPIO_RXEN                                                                                 0x2919

WARNING: line length of 105 exceeds 100 columns
#9924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9900:
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#9925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9901:
+#define regDC_GPIO_PULLUPEN                                                                             0x291a

WARNING: line length of 105 exceeds 100 columns
#9926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9902:
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#9927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9903:
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b

WARNING: line length of 105 exceeds 100 columns
#9928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9904:
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9905:
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c

WARNING: line length of 105 exceeds 100 columns
#9930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9906:
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9907:
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d

WARNING: line length of 105 exceeds 100 columns
#9932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9908:
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#9933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9909:
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e

WARNING: line length of 105 exceeds 100 columns
#9934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9910:
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#9943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9919:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00

WARNING: line length of 105 exceeds 100 columns
#9944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9920:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9921:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01

WARNING: line length of 105 exceeds 100 columns
#9946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9922:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9923:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02

WARNING: line length of 105 exceeds 100 columns
#9948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9924:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9925:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03

WARNING: line length of 105 exceeds 100 columns
#9950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9926:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9927:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04

WARNING: line length of 105 exceeds 100 columns
#9952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9928:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9929:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05

WARNING: line length of 105 exceeds 100 columns
#9954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9930:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9931:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06

WARNING: line length of 105 exceeds 100 columns
#9956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9932:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9933:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07

WARNING: line length of 105 exceeds 100 columns
#9958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9934:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9935:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08

WARNING: line length of 105 exceeds 100 columns
#9960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9936:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9937:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09

WARNING: line length of 105 exceeds 100 columns
#9962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9938:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#9963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9939:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a

WARNING: line length of 105 exceeds 100 columns
#9964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9940:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9941:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b

WARNING: line length of 105 exceeds 100 columns
#9966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9942:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9943:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c

WARNING: line length of 105 exceeds 100 columns
#9968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9944:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9945:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d

WARNING: line length of 105 exceeds 100 columns
#9970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9946:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9947:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e

WARNING: line length of 105 exceeds 100 columns
#9972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9948:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9949:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f

WARNING: line length of 105 exceeds 100 columns
#9974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9950:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9951:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10

WARNING: line length of 105 exceeds 100 columns
#9976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9952:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9953:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11

WARNING: line length of 105 exceeds 100 columns
#9978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9954:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9955:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12

WARNING: line length of 105 exceeds 100 columns
#9980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9956:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9957:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13

WARNING: line length of 105 exceeds 100 columns
#9982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9958:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9959:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14

WARNING: line length of 105 exceeds 100 columns
#9984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9960:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9961:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15

WARNING: line length of 105 exceeds 100 columns
#9986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9962:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9963:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16

WARNING: line length of 105 exceeds 100 columns
#9988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9964:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9965:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17

WARNING: line length of 105 exceeds 100 columns
#9990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9966:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9967:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18

WARNING: line length of 105 exceeds 100 columns
#9992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9968:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9969:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19

WARNING: line length of 105 exceeds 100 columns
#9994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9970:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9971:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a

WARNING: line length of 105 exceeds 100 columns
#9996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9972:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9973:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b

WARNING: line length of 105 exceeds 100 columns
#9998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9974:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#9999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9975:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c

WARNING: line length of 105 exceeds 100 columns
#10000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9976:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9977:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d

WARNING: line length of 105 exceeds 100 columns
#10002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9978:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9979:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e

WARNING: line length of 105 exceeds 100 columns
#10004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9980:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9981:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f

WARNING: line length of 105 exceeds 100 columns
#10006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9982:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9983:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20

WARNING: line length of 105 exceeds 100 columns
#10008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9984:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9985:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21

WARNING: line length of 105 exceeds 100 columns
#10010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9986:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9987:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22

WARNING: line length of 105 exceeds 100 columns
#10012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9988:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9989:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23

WARNING: line length of 105 exceeds 100 columns
#10014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9990:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9991:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24

WARNING: line length of 105 exceeds 100 columns
#10016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9992:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9993:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25

WARNING: line length of 105 exceeds 100 columns
#10018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9994:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9995:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26

WARNING: line length of 105 exceeds 100 columns
#10020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9996:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9997:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27

WARNING: line length of 105 exceeds 100 columns
#10022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9998:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:9999:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28

WARNING: line length of 105 exceeds 100 columns
#10024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10000:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10001:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29

WARNING: line length of 105 exceeds 100 columns
#10026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10002:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10003:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a

WARNING: line length of 105 exceeds 100 columns
#10028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10004:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10005:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b

WARNING: line length of 105 exceeds 100 columns
#10030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10006:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10007:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c

WARNING: line length of 105 exceeds 100 columns
#10032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10008:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10009:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d

WARNING: line length of 105 exceeds 100 columns
#10034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10010:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10011:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e

WARNING: line length of 105 exceeds 100 columns
#10036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10012:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10013:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f

WARNING: line length of 105 exceeds 100 columns
#10038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10014:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10015:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30

WARNING: line length of 105 exceeds 100 columns
#10040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10016:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10017:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31

WARNING: line length of 105 exceeds 100 columns
#10042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10018:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10019:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32

WARNING: line length of 105 exceeds 100 columns
#10044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10020:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10021:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33

WARNING: line length of 105 exceeds 100 columns
#10046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10022:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10023:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34

WARNING: line length of 105 exceeds 100 columns
#10048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10024:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10025:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35

WARNING: line length of 105 exceeds 100 columns
#10050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10026:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10027:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36

WARNING: line length of 105 exceeds 100 columns
#10052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10028:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10029:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37

WARNING: line length of 105 exceeds 100 columns
#10054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10030:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10031:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38

WARNING: line length of 105 exceeds 100 columns
#10056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10032:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10033:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39

WARNING: line length of 105 exceeds 100 columns
#10058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10034:
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10039:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8

WARNING: line length of 105 exceeds 100 columns
#10064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10040:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10041:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9

WARNING: line length of 105 exceeds 100 columns
#10066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10042:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10043:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada

WARNING: line length of 105 exceeds 100 columns
#10068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10044:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10045:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb

WARNING: line length of 105 exceeds 100 columns
#10070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10046:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10047:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc

WARNING: line length of 105 exceeds 100 columns
#10072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10048:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10049:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add

WARNING: line length of 105 exceeds 100 columns
#10074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10050:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10051:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade

WARNING: line length of 105 exceeds 100 columns
#10076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10052:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10053:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf

WARNING: line length of 105 exceeds 100 columns
#10078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10054:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10055:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0

WARNING: line length of 105 exceeds 100 columns
#10080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10056:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10057:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1

WARNING: line length of 105 exceeds 100 columns
#10082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10058:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10059:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2

WARNING: line length of 105 exceeds 100 columns
#10084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10060:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10061:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3

WARNING: line length of 105 exceeds 100 columns
#10086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10062:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10063:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4

WARNING: line length of 105 exceeds 100 columns
#10088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10064:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10065:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5

WARNING: line length of 105 exceeds 100 columns
#10090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10066:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10067:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6

WARNING: line length of 105 exceeds 100 columns
#10092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10068:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10069:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7

WARNING: line length of 105 exceeds 100 columns
#10094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10070:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10071:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8

WARNING: line length of 105 exceeds 100 columns
#10096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10072:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10073:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9

WARNING: line length of 105 exceeds 100 columns
#10098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10074:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10075:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea

WARNING: line length of 105 exceeds 100 columns
#10100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10076:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10077:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb

WARNING: line length of 105 exceeds 100 columns
#10102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10078:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10079:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec

WARNING: line length of 105 exceeds 100 columns
#10104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10080:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10081:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed

WARNING: line length of 105 exceeds 100 columns
#10106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10082:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10083:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee

WARNING: line length of 105 exceeds 100 columns
#10108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10084:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10085:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef

WARNING: line length of 105 exceeds 100 columns
#10110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10086:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10087:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0

WARNING: line length of 105 exceeds 100 columns
#10112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10088:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10089:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1

WARNING: line length of 105 exceeds 100 columns
#10114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10090:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10091:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2

WARNING: line length of 105 exceeds 100 columns
#10116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10092:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10093:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3

WARNING: line length of 105 exceeds 100 columns
#10118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10094:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10095:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4

WARNING: line length of 105 exceeds 100 columns
#10120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10096:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10097:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5

WARNING: line length of 105 exceeds 100 columns
#10122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10098:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10099:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6

WARNING: line length of 105 exceeds 100 columns
#10124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10100:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10101:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7

WARNING: line length of 105 exceeds 100 columns
#10126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10102:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10103:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8

WARNING: line length of 105 exceeds 100 columns
#10128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10104:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10105:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9

WARNING: line length of 105 exceeds 100 columns
#10130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10106:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10107:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa

WARNING: line length of 105 exceeds 100 columns
#10132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10108:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10109:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb

WARNING: line length of 105 exceeds 100 columns
#10134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10110:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10111:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc

WARNING: line length of 105 exceeds 100 columns
#10136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10112:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10113:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd

WARNING: line length of 105 exceeds 100 columns
#10138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10114:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10115:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe

WARNING: line length of 105 exceeds 100 columns
#10140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10116:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10117:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff

WARNING: line length of 105 exceeds 100 columns
#10142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10118:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10119:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00

WARNING: line length of 105 exceeds 100 columns
#10144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10120:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10121:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01

WARNING: line length of 105 exceeds 100 columns
#10146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10122:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10123:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02

WARNING: line length of 105 exceeds 100 columns
#10148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10124:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10125:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03

WARNING: line length of 105 exceeds 100 columns
#10150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10126:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10127:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04

WARNING: line length of 105 exceeds 100 columns
#10152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10128:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10129:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05

WARNING: line length of 105 exceeds 100 columns
#10154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10130:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10131:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06

WARNING: line length of 105 exceeds 100 columns
#10156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10132:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10133:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07

WARNING: line length of 105 exceeds 100 columns
#10158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10134:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10135:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08

WARNING: line length of 105 exceeds 100 columns
#10160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10136:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10137:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09

WARNING: line length of 105 exceeds 100 columns
#10162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10138:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10139:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a

WARNING: line length of 105 exceeds 100 columns
#10164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10140:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10141:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b

WARNING: line length of 105 exceeds 100 columns
#10166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10142:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10143:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c

WARNING: line length of 105 exceeds 100 columns
#10168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10144:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10145:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d

WARNING: line length of 105 exceeds 100 columns
#10170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10146:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10147:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e

WARNING: line length of 105 exceeds 100 columns
#10172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10148:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10149:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f

WARNING: line length of 105 exceeds 100 columns
#10174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10150:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10151:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10

WARNING: line length of 105 exceeds 100 columns
#10176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10152:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10153:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11

WARNING: line length of 105 exceeds 100 columns
#10178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10154:
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10159:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0

WARNING: line length of 105 exceeds 100 columns
#10184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10160:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10161:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1

WARNING: line length of 105 exceeds 100 columns
#10186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10162:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10163:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2

WARNING: line length of 105 exceeds 100 columns
#10188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10164:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10165:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3

WARNING: line length of 105 exceeds 100 columns
#10190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10166:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10167:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4

WARNING: line length of 105 exceeds 100 columns
#10192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10168:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10169:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5

WARNING: line length of 105 exceeds 100 columns
#10194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10170:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10171:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6

WARNING: line length of 105 exceeds 100 columns
#10196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10172:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10173:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7

WARNING: line length of 105 exceeds 100 columns
#10198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10174:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10175:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8

WARNING: line length of 105 exceeds 100 columns
#10200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10176:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10177:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9

WARNING: line length of 105 exceeds 100 columns
#10202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10178:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10179:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba

WARNING: line length of 105 exceeds 100 columns
#10204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10180:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10181:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb

WARNING: line length of 105 exceeds 100 columns
#10206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10182:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10183:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc

WARNING: line length of 105 exceeds 100 columns
#10208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10184:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10185:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd

WARNING: line length of 105 exceeds 100 columns
#10210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10186:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10187:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe

WARNING: line length of 105 exceeds 100 columns
#10212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10188:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10189:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf

WARNING: line length of 105 exceeds 100 columns
#10214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10190:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10191:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0

WARNING: line length of 105 exceeds 100 columns
#10216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10192:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10193:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1

WARNING: line length of 105 exceeds 100 columns
#10218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10194:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10195:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2

WARNING: line length of 105 exceeds 100 columns
#10220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10196:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10197:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3

WARNING: line length of 105 exceeds 100 columns
#10222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10198:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10199:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4

WARNING: line length of 105 exceeds 100 columns
#10224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10200:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10201:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5

WARNING: line length of 105 exceeds 100 columns
#10226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10202:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10203:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6

WARNING: line length of 105 exceeds 100 columns
#10228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10204:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10205:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7

WARNING: line length of 105 exceeds 100 columns
#10230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10206:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10207:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8

WARNING: line length of 105 exceeds 100 columns
#10232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10208:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10209:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9

WARNING: line length of 105 exceeds 100 columns
#10234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10210:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10211:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca

WARNING: line length of 105 exceeds 100 columns
#10236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10212:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10213:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb

WARNING: line length of 105 exceeds 100 columns
#10238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10214:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10215:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc

WARNING: line length of 105 exceeds 100 columns
#10240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10216:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10217:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd

WARNING: line length of 105 exceeds 100 columns
#10242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10218:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10219:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce

WARNING: line length of 105 exceeds 100 columns
#10244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10220:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10221:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf

WARNING: line length of 105 exceeds 100 columns
#10246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10222:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10223:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0

WARNING: line length of 105 exceeds 100 columns
#10248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10224:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10225:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1

WARNING: line length of 105 exceeds 100 columns
#10250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10226:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10227:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2

WARNING: line length of 105 exceeds 100 columns
#10252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10228:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10229:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3

WARNING: line length of 105 exceeds 100 columns
#10254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10230:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10231:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4

WARNING: line length of 105 exceeds 100 columns
#10256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10232:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10233:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5

WARNING: line length of 105 exceeds 100 columns
#10258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10234:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10235:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6

WARNING: line length of 105 exceeds 100 columns
#10260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10236:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10237:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7

WARNING: line length of 105 exceeds 100 columns
#10262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10238:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10239:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8

WARNING: line length of 105 exceeds 100 columns
#10264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10240:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10241:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9

WARNING: line length of 105 exceeds 100 columns
#10266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10242:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10243:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda

WARNING: line length of 105 exceeds 100 columns
#10268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10244:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10245:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb

WARNING: line length of 105 exceeds 100 columns
#10270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10246:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10247:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc

WARNING: line length of 105 exceeds 100 columns
#10272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10248:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10249:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd

WARNING: line length of 105 exceeds 100 columns
#10274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10250:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10251:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde

WARNING: line length of 105 exceeds 100 columns
#10276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10252:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10253:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf

WARNING: line length of 105 exceeds 100 columns
#10278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10254:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10255:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0

WARNING: line length of 105 exceeds 100 columns
#10280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10256:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10257:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1

WARNING: line length of 105 exceeds 100 columns
#10282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10258:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10259:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2

WARNING: line length of 105 exceeds 100 columns
#10284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10260:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10261:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3

WARNING: line length of 105 exceeds 100 columns
#10286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10262:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10263:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4

WARNING: line length of 105 exceeds 100 columns
#10288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10264:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10265:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5

WARNING: line length of 105 exceeds 100 columns
#10290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10266:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10267:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6

WARNING: line length of 105 exceeds 100 columns
#10292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10268:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10269:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7

WARNING: line length of 105 exceeds 100 columns
#10294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10270:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10271:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8

WARNING: line length of 105 exceeds 100 columns
#10296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10272:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10273:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9

WARNING: line length of 105 exceeds 100 columns
#10298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10274:
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10279:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88

WARNING: line length of 105 exceeds 100 columns
#10304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10280:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10281:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89

WARNING: line length of 105 exceeds 100 columns
#10306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10282:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10283:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a

WARNING: line length of 105 exceeds 100 columns
#10308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10284:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10285:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b

WARNING: line length of 105 exceeds 100 columns
#10310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10286:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10287:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c

WARNING: line length of 105 exceeds 100 columns
#10312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10288:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10289:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d

WARNING: line length of 105 exceeds 100 columns
#10314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10290:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10291:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e

WARNING: line length of 105 exceeds 100 columns
#10316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10292:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10293:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f

WARNING: line length of 105 exceeds 100 columns
#10318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10294:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10295:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90

WARNING: line length of 105 exceeds 100 columns
#10320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10296:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10297:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91

WARNING: line length of 105 exceeds 100 columns
#10322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10298:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#10323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10299:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92

WARNING: line length of 105 exceeds 100 columns
#10324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10300:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10301:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93

WARNING: line length of 105 exceeds 100 columns
#10326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10302:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10303:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94

WARNING: line length of 105 exceeds 100 columns
#10328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10304:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10305:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95

WARNING: line length of 105 exceeds 100 columns
#10330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10306:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10307:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96

WARNING: line length of 105 exceeds 100 columns
#10332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10308:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10309:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97

WARNING: line length of 105 exceeds 100 columns
#10334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10310:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10311:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98

WARNING: line length of 105 exceeds 100 columns
#10336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10312:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10313:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99

WARNING: line length of 105 exceeds 100 columns
#10338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10314:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10315:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a

WARNING: line length of 105 exceeds 100 columns
#10340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10316:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10317:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b

WARNING: line length of 105 exceeds 100 columns
#10342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10318:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10319:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c

WARNING: line length of 105 exceeds 100 columns
#10344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10320:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10321:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d

WARNING: line length of 105 exceeds 100 columns
#10346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10322:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10323:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e

WARNING: line length of 105 exceeds 100 columns
#10348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10324:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10325:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f

WARNING: line length of 105 exceeds 100 columns
#10350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10326:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10327:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0

WARNING: line length of 105 exceeds 100 columns
#10352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10328:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10329:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1

WARNING: line length of 105 exceeds 100 columns
#10354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10330:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10331:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2

WARNING: line length of 105 exceeds 100 columns
#10356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10332:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10333:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3

WARNING: line length of 105 exceeds 100 columns
#10358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10334:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10335:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4

WARNING: line length of 105 exceeds 100 columns
#10360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10336:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10337:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5

WARNING: line length of 105 exceeds 100 columns
#10362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10338:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10339:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6

WARNING: line length of 105 exceeds 100 columns
#10364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10340:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10341:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7

WARNING: line length of 105 exceeds 100 columns
#10366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10342:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10343:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8

WARNING: line length of 105 exceeds 100 columns
#10368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10344:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10345:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9

WARNING: line length of 105 exceeds 100 columns
#10370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10346:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10347:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa

WARNING: line length of 105 exceeds 100 columns
#10372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10348:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10349:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab

WARNING: line length of 105 exceeds 100 columns
#10374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10350:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10351:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac

WARNING: line length of 105 exceeds 100 columns
#10376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10352:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10353:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad

WARNING: line length of 105 exceeds 100 columns
#10378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10354:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10355:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae

WARNING: line length of 105 exceeds 100 columns
#10380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10356:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10357:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf

WARNING: line length of 105 exceeds 100 columns
#10382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10358:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10359:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0

WARNING: line length of 105 exceeds 100 columns
#10384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10360:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10361:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1

WARNING: line length of 105 exceeds 100 columns
#10386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10362:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10363:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2

WARNING: line length of 105 exceeds 100 columns
#10388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10364:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10365:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3

WARNING: line length of 105 exceeds 100 columns
#10390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10366:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10367:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4

WARNING: line length of 105 exceeds 100 columns
#10392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10368:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10369:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5

WARNING: line length of 105 exceeds 100 columns
#10394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10370:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10371:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6

WARNING: line length of 105 exceeds 100 columns
#10396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10372:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10373:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7

WARNING: line length of 105 exceeds 100 columns
#10398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10374:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10375:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8

WARNING: line length of 105 exceeds 100 columns
#10400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10376:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10377:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9

WARNING: line length of 105 exceeds 100 columns
#10402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10378:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10379:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba

WARNING: line length of 105 exceeds 100 columns
#10404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10380:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10381:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb

WARNING: line length of 105 exceeds 100 columns
#10406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10382:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10383:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc

WARNING: line length of 105 exceeds 100 columns
#10408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10384:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10385:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd

WARNING: line length of 105 exceeds 100 columns
#10410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10386:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10387:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe

WARNING: line length of 105 exceeds 100 columns
#10412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10388:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10389:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf

WARNING: line length of 105 exceeds 100 columns
#10414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10390:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10391:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0

WARNING: line length of 105 exceeds 100 columns
#10416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10392:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10393:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1

WARNING: line length of 105 exceeds 100 columns
#10418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10394:
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#10423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10399:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10

WARNING: line length of 105 exceeds 100 columns
#10424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10400:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10401:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11

WARNING: line length of 105 exceeds 100 columns
#10426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10402:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10403:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12

WARNING: line length of 105 exceeds 100 columns
#10428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10404:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10405:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13

WARNING: line length of 105 exceeds 100 columns
#10430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10406:
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10407:
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14

WARNING: line length of 105 exceeds 100 columns
#10432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10408:
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10409:
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15

WARNING: line length of 105 exceeds 100 columns
#10434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10410:
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10411:
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16

WARNING: line length of 105 exceeds 100 columns
#10436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10412:
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10413:
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17

WARNING: line length of 105 exceeds 100 columns
#10438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10414:
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10415:
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18

WARNING: line length of 105 exceeds 100 columns
#10440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10416:
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10417:
+#define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19

WARNING: line length of 105 exceeds 100 columns
#10442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10418:
+#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#10443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10419:
+#define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a

WARNING: line length of 105 exceeds 100 columns
#10444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10420:
+#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#10445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10421:
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b

WARNING: line length of 105 exceeds 100 columns
#10446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10422:
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10423:
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c

WARNING: line length of 105 exceeds 100 columns
#10448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10424:
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#10449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10425:
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d

WARNING: line length of 105 exceeds 100 columns
#10450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10426:
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10427:
+#define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21

WARNING: line length of 105 exceeds 100 columns
#10452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10428:
+#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#10457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10433:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c

WARNING: line length of 105 exceeds 100 columns
#10458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10434:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10435:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d

WARNING: line length of 105 exceeds 100 columns
#10460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10436:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10437:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e

WARNING: line length of 105 exceeds 100 columns
#10462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10438:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10439:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f

WARNING: line length of 105 exceeds 100 columns
#10464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10440:
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10441:
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80

WARNING: line length of 105 exceeds 100 columns
#10466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10442:
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10443:
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81

WARNING: line length of 105 exceeds 100 columns
#10468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10444:
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10445:
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82

WARNING: line length of 105 exceeds 100 columns
#10470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10446:
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10447:
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83

WARNING: line length of 105 exceeds 100 columns
#10472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10448:
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#10473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10449:
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84

WARNING: line length of 105 exceeds 100 columns
#10474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10450:
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10451:
+#define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85

WARNING: line length of 105 exceeds 100 columns
#10476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10452:
+#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#10477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10453:
+#define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86

WARNING: line length of 105 exceeds 100 columns
#10478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10454:
+#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#10479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10455:
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87

WARNING: line length of 105 exceeds 100 columns
#10480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10456:
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10457:
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88

WARNING: line length of 105 exceeds 100 columns
#10482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10458:
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#10483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10459:
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89

WARNING: line length of 105 exceeds 100 columns
#10484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10460:
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10461:
+#define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d

WARNING: line length of 105 exceeds 100 columns
#10486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10462:
+#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#10491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10467:
+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000

WARNING: line length of 105 exceeds 100 columns
#10492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10468:
+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#10493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10469:
+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001

WARNING: line length of 105 exceeds 100 columns
#10494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10470:
+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10475:
+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005

WARNING: line length of 105 exceeds 100 columns
#10500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10476:
+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10477:
+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006

WARNING: line length of 105 exceeds 100 columns
#10502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10478:
+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10483:
+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a

WARNING: line length of 105 exceeds 100 columns
#10508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10484:
+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10485:
+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b

WARNING: line length of 105 exceeds 100 columns
#10510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10486:
+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10487:
+#define regDSCC0_DSCC_STATUS                                                                            0x300c

WARNING: line length of 105 exceeds 100 columns
#10512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10488:
+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#10513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10489:
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d

WARNING: line length of 105 exceeds 100 columns
#10514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10490:
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10491:
+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e

WARNING: line length of 105 exceeds 100 columns
#10516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10492:
+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10493:
+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f

WARNING: line length of 105 exceeds 100 columns
#10518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10494:
+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10495:
+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010

WARNING: line length of 105 exceeds 100 columns
#10520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10496:
+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10497:
+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011

WARNING: line length of 105 exceeds 100 columns
#10522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10498:
+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10499:
+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012

WARNING: line length of 105 exceeds 100 columns
#10524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10500:
+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10501:
+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013

WARNING: line length of 105 exceeds 100 columns
#10526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10502:
+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10503:
+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014

WARNING: line length of 105 exceeds 100 columns
#10528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10504:
+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10505:
+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015

WARNING: line length of 105 exceeds 100 columns
#10530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10506:
+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10507:
+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016

WARNING: line length of 105 exceeds 100 columns
#10532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10508:
+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10509:
+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017

WARNING: line length of 105 exceeds 100 columns
#10534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10510:
+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10511:
+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018

WARNING: line length of 105 exceeds 100 columns
#10536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10512:
+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10513:
+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019

WARNING: line length of 105 exceeds 100 columns
#10538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10514:
+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10515:
+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a

WARNING: line length of 105 exceeds 100 columns
#10540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10516:
+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10517:
+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b

WARNING: line length of 105 exceeds 100 columns
#10542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10518:
+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10519:
+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c

WARNING: line length of 105 exceeds 100 columns
#10544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10520:
+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10521:
+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d

WARNING: line length of 105 exceeds 100 columns
#10546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10522:
+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10523:
+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e

WARNING: line length of 105 exceeds 100 columns
#10548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10524:
+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10525:
+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f

WARNING: line length of 105 exceeds 100 columns
#10550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10526:
+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10527:
+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020

WARNING: line length of 105 exceeds 100 columns
#10552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10528:
+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10529:
+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021

WARNING: line length of 105 exceeds 100 columns
#10554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10530:
+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10531:
+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022

WARNING: line length of 105 exceeds 100 columns
#10556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10532:
+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10533:
+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023

WARNING: line length of 105 exceeds 100 columns
#10558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10534:
+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10535:
+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024

WARNING: line length of 105 exceeds 100 columns
#10560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10536:
+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10537:
+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025

WARNING: line length of 105 exceeds 100 columns
#10562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10538:
+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#10563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10539:
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026

WARNING: line length of 105 exceeds 100 columns
#10564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10540:
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10541:
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027

WARNING: line length of 105 exceeds 100 columns
#10566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10542:
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10543:
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028

WARNING: line length of 105 exceeds 100 columns
#10568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10544:
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10545:
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029

WARNING: line length of 105 exceeds 100 columns
#10570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10546:
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10547:
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a

WARNING: line length of 105 exceeds 100 columns
#10572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10548:
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10549:
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b

WARNING: line length of 105 exceeds 100 columns
#10574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10550:
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10551:
+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c

WARNING: line length of 105 exceeds 100 columns
#10576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10552:
+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10553:
+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d

WARNING: line length of 105 exceeds 100 columns
#10578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10554:
+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10555:
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e

WARNING: line length of 105 exceeds 100 columns
#10580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10556:
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10557:
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f

WARNING: line length of 105 exceeds 100 columns
#10582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10558:
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10559:
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030

WARNING: line length of 105 exceeds 100 columns
#10584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10560:
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10561:
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031

WARNING: line length of 105 exceeds 100 columns
#10586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10562:
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10563:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032

WARNING: line length of 105 exceeds 100 columns
#10588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10564:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10565:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033

WARNING: line length of 105 exceeds 100 columns
#10590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10566:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10567:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034

WARNING: line length of 105 exceeds 100 columns
#10592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10568:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10569:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035

WARNING: line length of 105 exceeds 100 columns
#10594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10570:
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10575:
+#define regDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050

WARNING: line length of 105 exceeds 100 columns
#10600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10576:
+#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10577:
+#define regDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051

WARNING: line length of 105 exceeds 100 columns
#10602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10578:
+#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10579:
+#define regDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052

WARNING: line length of 105 exceeds 100 columns
#10604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10580:
+#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10581:
+#define regDC_PERFMON19_PERFMON_CNTL                                                                    0x3053

WARNING: line length of 105 exceeds 100 columns
#10606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10582:
+#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10583:
+#define regDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054

WARNING: line length of 105 exceeds 100 columns
#10608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10584:
+#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10585:
+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055

WARNING: line length of 105 exceeds 100 columns
#10610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10586:
+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#10611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10587:
+#define regDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056

WARNING: line length of 105 exceeds 100 columns
#10612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10588:
+#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#10613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10589:
+#define regDC_PERFMON19_PERFMON_HI                                                                      0x3057

WARNING: line length of 105 exceeds 100 columns
#10614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10590:
+#define regDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10591:
+#define regDC_PERFMON19_PERFMON_LOW                                                                     0x3058

WARNING: line length of 105 exceeds 100 columns
#10616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10592:
+#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#10621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10597:
+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c

WARNING: line length of 105 exceeds 100 columns
#10622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10598:
+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#10623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10599:
+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d

WARNING: line length of 105 exceeds 100 columns
#10624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10600:
+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10604:
+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061

WARNING: line length of 105 exceeds 100 columns
#10629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10605:
+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10606:
+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062

WARNING: line length of 105 exceeds 100 columns
#10631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10607:
+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10612:
+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066

WARNING: line length of 105 exceeds 100 columns
#10637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10613:
+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10614:
+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067

WARNING: line length of 105 exceeds 100 columns
#10639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10615:
+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10616:
+#define regDSCC1_DSCC_STATUS                                                                            0x3068

WARNING: line length of 105 exceeds 100 columns
#10641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10617:
+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#10642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10618:
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069

WARNING: line length of 105 exceeds 100 columns
#10643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10619:
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10620:
+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a

WARNING: line length of 105 exceeds 100 columns
#10645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10621:
+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10622:
+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b

WARNING: line length of 105 exceeds 100 columns
#10647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10623:
+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10624:
+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c

WARNING: line length of 105 exceeds 100 columns
#10649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10625:
+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10626:
+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d

WARNING: line length of 105 exceeds 100 columns
#10651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10627:
+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10628:
+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e

WARNING: line length of 105 exceeds 100 columns
#10653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10629:
+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10630:
+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f

WARNING: line length of 105 exceeds 100 columns
#10655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10631:
+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10632:
+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070

WARNING: line length of 105 exceeds 100 columns
#10657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10633:
+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10634:
+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071

WARNING: line length of 105 exceeds 100 columns
#10659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10635:
+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10636:
+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072

WARNING: line length of 105 exceeds 100 columns
#10661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10637:
+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10638:
+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073

WARNING: line length of 105 exceeds 100 columns
#10663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10639:
+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10640:
+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074

WARNING: line length of 105 exceeds 100 columns
#10665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10641:
+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10642:
+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075

WARNING: line length of 105 exceeds 100 columns
#10667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10643:
+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10644:
+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076

WARNING: line length of 105 exceeds 100 columns
#10669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10645:
+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10646:
+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077

WARNING: line length of 105 exceeds 100 columns
#10671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10647:
+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10648:
+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078

WARNING: line length of 105 exceeds 100 columns
#10673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10649:
+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10650:
+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079

WARNING: line length of 105 exceeds 100 columns
#10675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10651:
+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10652:
+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a

WARNING: line length of 105 exceeds 100 columns
#10677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10653:
+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10654:
+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b

WARNING: line length of 105 exceeds 100 columns
#10679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10655:
+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10656:
+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c

WARNING: line length of 105 exceeds 100 columns
#10681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10657:
+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10658:
+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d

WARNING: line length of 105 exceeds 100 columns
#10683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10659:
+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10660:
+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e

WARNING: line length of 105 exceeds 100 columns
#10685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10661:
+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10662:
+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f

WARNING: line length of 105 exceeds 100 columns
#10687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10663:
+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10664:
+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080

WARNING: line length of 105 exceeds 100 columns
#10689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10665:
+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10666:
+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081

WARNING: line length of 105 exceeds 100 columns
#10691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10667:
+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#10692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10668:
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082

WARNING: line length of 105 exceeds 100 columns
#10693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10669:
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10670:
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083

WARNING: line length of 105 exceeds 100 columns
#10695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10671:
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10672:
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084

WARNING: line length of 105 exceeds 100 columns
#10697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10673:
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10674:
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085

WARNING: line length of 105 exceeds 100 columns
#10699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10675:
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10676:
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086

WARNING: line length of 105 exceeds 100 columns
#10701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10677:
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10678:
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087

WARNING: line length of 105 exceeds 100 columns
#10703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10679:
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10680:
+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088

WARNING: line length of 105 exceeds 100 columns
#10705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10681:
+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10682:
+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089

WARNING: line length of 105 exceeds 100 columns
#10707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10683:
+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10684:
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a

WARNING: line length of 105 exceeds 100 columns
#10709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10685:
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10686:
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b

WARNING: line length of 105 exceeds 100 columns
#10711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10687:
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10688:
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c

WARNING: line length of 105 exceeds 100 columns
#10713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10689:
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10690:
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d

WARNING: line length of 105 exceeds 100 columns
#10715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10691:
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10692:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e

WARNING: line length of 105 exceeds 100 columns
#10717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10693:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10694:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f

WARNING: line length of 105 exceeds 100 columns
#10719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10695:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10696:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090

WARNING: line length of 105 exceeds 100 columns
#10721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10697:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10698:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091

WARNING: line length of 105 exceeds 100 columns
#10723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10699:
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10704:
+#define regDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac

WARNING: line length of 105 exceeds 100 columns
#10729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10705:
+#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10706:
+#define regDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad

WARNING: line length of 105 exceeds 100 columns
#10731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10707:
+#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10708:
+#define regDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae

WARNING: line length of 105 exceeds 100 columns
#10733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10709:
+#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10710:
+#define regDC_PERFMON20_PERFMON_CNTL                                                                    0x30af

WARNING: line length of 105 exceeds 100 columns
#10735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10711:
+#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10712:
+#define regDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0

WARNING: line length of 105 exceeds 100 columns
#10737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10713:
+#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10714:
+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1

WARNING: line length of 105 exceeds 100 columns
#10739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10715:
+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#10740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10716:
+#define regDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2

WARNING: line length of 105 exceeds 100 columns
#10741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10717:
+#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#10742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10718:
+#define regDC_PERFMON20_PERFMON_HI                                                                      0x30b3

WARNING: line length of 105 exceeds 100 columns
#10743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10719:
+#define regDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10720:
+#define regDC_PERFMON20_PERFMON_LOW                                                                     0x30b4

WARNING: line length of 105 exceeds 100 columns
#10745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10721:
+#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#10750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10726:
+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8

WARNING: line length of 105 exceeds 100 columns
#10751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10727:
+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#10752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10728:
+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9

WARNING: line length of 105 exceeds 100 columns
#10753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10729:
+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10734:
+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd

WARNING: line length of 105 exceeds 100 columns
#10759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10735:
+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10736:
+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be

WARNING: line length of 105 exceeds 100 columns
#10761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10737:
+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10742:
+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2

WARNING: line length of 105 exceeds 100 columns
#10767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10743:
+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10744:
+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3

WARNING: line length of 105 exceeds 100 columns
#10769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10745:
+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10746:
+#define regDSCC2_DSCC_STATUS                                                                            0x30c4

WARNING: line length of 105 exceeds 100 columns
#10771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10747:
+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#10772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10748:
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5

WARNING: line length of 105 exceeds 100 columns
#10773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10749:
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10750:
+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6

WARNING: line length of 105 exceeds 100 columns
#10775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10751:
+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10752:
+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7

WARNING: line length of 105 exceeds 100 columns
#10777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10753:
+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10754:
+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8

WARNING: line length of 105 exceeds 100 columns
#10779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10755:
+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10756:
+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9

WARNING: line length of 105 exceeds 100 columns
#10781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10757:
+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10758:
+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca

WARNING: line length of 105 exceeds 100 columns
#10783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10759:
+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10760:
+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb

WARNING: line length of 105 exceeds 100 columns
#10785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10761:
+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10762:
+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc

WARNING: line length of 105 exceeds 100 columns
#10787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10763:
+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10764:
+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd

WARNING: line length of 105 exceeds 100 columns
#10789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10765:
+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10766:
+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce

WARNING: line length of 105 exceeds 100 columns
#10791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10767:
+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10768:
+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf

WARNING: line length of 105 exceeds 100 columns
#10793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10769:
+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10770:
+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0

WARNING: line length of 105 exceeds 100 columns
#10795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10771:
+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10772:
+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1

WARNING: line length of 105 exceeds 100 columns
#10797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10773:
+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10774:
+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2

WARNING: line length of 105 exceeds 100 columns
#10799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10775:
+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10776:
+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3

WARNING: line length of 105 exceeds 100 columns
#10801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10777:
+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10778:
+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4

WARNING: line length of 105 exceeds 100 columns
#10803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10779:
+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10780:
+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5

WARNING: line length of 105 exceeds 100 columns
#10805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10781:
+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10782:
+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6

WARNING: line length of 105 exceeds 100 columns
#10807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10783:
+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10784:
+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7

WARNING: line length of 105 exceeds 100 columns
#10809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10785:
+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10786:
+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8

WARNING: line length of 105 exceeds 100 columns
#10811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10787:
+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10788:
+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9

WARNING: line length of 105 exceeds 100 columns
#10813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10789:
+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10790:
+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da

WARNING: line length of 105 exceeds 100 columns
#10815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10791:
+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10792:
+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db

WARNING: line length of 105 exceeds 100 columns
#10817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10793:
+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10794:
+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc

WARNING: line length of 105 exceeds 100 columns
#10819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10795:
+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10796:
+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd

WARNING: line length of 105 exceeds 100 columns
#10821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10797:
+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#10822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10798:
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de

WARNING: line length of 105 exceeds 100 columns
#10823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10799:
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10800:
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df

WARNING: line length of 105 exceeds 100 columns
#10825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10801:
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10802:
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0

WARNING: line length of 105 exceeds 100 columns
#10827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10803:
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10804:
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1

WARNING: line length of 105 exceeds 100 columns
#10829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10805:
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10806:
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2

WARNING: line length of 105 exceeds 100 columns
#10831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10807:
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10808:
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3

WARNING: line length of 105 exceeds 100 columns
#10833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10809:
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10810:
+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4

WARNING: line length of 105 exceeds 100 columns
#10835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10811:
+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10812:
+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5

WARNING: line length of 105 exceeds 100 columns
#10837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10813:
+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10814:
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6

WARNING: line length of 105 exceeds 100 columns
#10839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10815:
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10816:
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7

WARNING: line length of 105 exceeds 100 columns
#10841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10817:
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10818:
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8

WARNING: line length of 105 exceeds 100 columns
#10843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10819:
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10820:
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9

WARNING: line length of 105 exceeds 100 columns
#10845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10821:
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10822:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea

WARNING: line length of 105 exceeds 100 columns
#10847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10823:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10824:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb

WARNING: line length of 105 exceeds 100 columns
#10849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10825:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10826:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec

WARNING: line length of 105 exceeds 100 columns
#10851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10827:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10828:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed

WARNING: line length of 105 exceeds 100 columns
#10853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10829:
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10834:
+#define regDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108

WARNING: line length of 105 exceeds 100 columns
#10859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10835:
+#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10836:
+#define regDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109

WARNING: line length of 105 exceeds 100 columns
#10861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10837:
+#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10838:
+#define regDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a

WARNING: line length of 105 exceeds 100 columns
#10863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10839:
+#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10840:
+#define regDC_PERFMON21_PERFMON_CNTL                                                                    0x310b

WARNING: line length of 105 exceeds 100 columns
#10865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10841:
+#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10842:
+#define regDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c

WARNING: line length of 105 exceeds 100 columns
#10867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10843:
+#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10844:
+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d

WARNING: line length of 105 exceeds 100 columns
#10869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10845:
+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#10870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10846:
+#define regDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e

WARNING: line length of 105 exceeds 100 columns
#10871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10847:
+#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#10872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10848:
+#define regDC_PERFMON21_PERFMON_HI                                                                      0x310f

WARNING: line length of 105 exceeds 100 columns
#10873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10849:
+#define regDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10850:
+#define regDC_PERFMON21_PERFMON_LOW                                                                     0x3110

WARNING: line length of 105 exceeds 100 columns
#10875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10851:
+#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#10880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10856:
+#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114

WARNING: line length of 105 exceeds 100 columns
#10881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10857:
+#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#10882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10858:
+#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115

WARNING: line length of 105 exceeds 100 columns
#10883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10859:
+#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10864:
+#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119

WARNING: line length of 105 exceeds 100 columns
#10889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10865:
+#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10866:
+#define regDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a

WARNING: line length of 105 exceeds 100 columns
#10891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10867:
+#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10872:
+#define regDSCC3_DSCC_CONFIG0                                                                           0x311e

WARNING: line length of 105 exceeds 100 columns
#10897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10873:
+#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10874:
+#define regDSCC3_DSCC_CONFIG1                                                                           0x311f

WARNING: line length of 105 exceeds 100 columns
#10899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10875:
+#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#10900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10876:
+#define regDSCC3_DSCC_STATUS                                                                            0x3120

WARNING: line length of 105 exceeds 100 columns
#10901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10877:
+#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#10902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10878:
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121

WARNING: line length of 105 exceeds 100 columns
#10903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10879:
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10880:
+#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122

WARNING: line length of 105 exceeds 100 columns
#10905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10881:
+#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10882:
+#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123

WARNING: line length of 105 exceeds 100 columns
#10907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10883:
+#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10884:
+#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124

WARNING: line length of 105 exceeds 100 columns
#10909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10885:
+#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10886:
+#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125

WARNING: line length of 105 exceeds 100 columns
#10911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10887:
+#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10888:
+#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126

WARNING: line length of 105 exceeds 100 columns
#10913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10889:
+#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10890:
+#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127

WARNING: line length of 105 exceeds 100 columns
#10915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10891:
+#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10892:
+#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128

WARNING: line length of 105 exceeds 100 columns
#10917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10893:
+#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10894:
+#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129

WARNING: line length of 105 exceeds 100 columns
#10919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10895:
+#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10896:
+#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a

WARNING: line length of 105 exceeds 100 columns
#10921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10897:
+#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10898:
+#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b

WARNING: line length of 105 exceeds 100 columns
#10923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10899:
+#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#10924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10900:
+#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c

WARNING: line length of 105 exceeds 100 columns
#10925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10901:
+#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10902:
+#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d

WARNING: line length of 105 exceeds 100 columns
#10927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10903:
+#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10904:
+#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e

WARNING: line length of 105 exceeds 100 columns
#10929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10905:
+#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10906:
+#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f

WARNING: line length of 105 exceeds 100 columns
#10931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10907:
+#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10908:
+#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130

WARNING: line length of 105 exceeds 100 columns
#10933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10909:
+#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10910:
+#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131

WARNING: line length of 105 exceeds 100 columns
#10935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10911:
+#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10912:
+#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132

WARNING: line length of 105 exceeds 100 columns
#10937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10913:
+#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10914:
+#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133

WARNING: line length of 105 exceeds 100 columns
#10939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10915:
+#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10916:
+#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134

WARNING: line length of 105 exceeds 100 columns
#10941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10917:
+#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10918:
+#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135

WARNING: line length of 105 exceeds 100 columns
#10943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10919:
+#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10920:
+#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136

WARNING: line length of 105 exceeds 100 columns
#10945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10921:
+#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10922:
+#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137

WARNING: line length of 105 exceeds 100 columns
#10947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10923:
+#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10924:
+#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138

WARNING: line length of 105 exceeds 100 columns
#10949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10925:
+#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#10950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10926:
+#define regDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139

WARNING: line length of 105 exceeds 100 columns
#10951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10927:
+#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#10952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10928:
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a

WARNING: line length of 105 exceeds 100 columns
#10953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10929:
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10930:
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b

WARNING: line length of 105 exceeds 100 columns
#10955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10931:
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#10956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10932:
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c

WARNING: line length of 105 exceeds 100 columns
#10957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10933:
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10934:
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d

WARNING: line length of 105 exceeds 100 columns
#10959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10935:
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10936:
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e

WARNING: line length of 105 exceeds 100 columns
#10961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10937:
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10938:
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f

WARNING: line length of 105 exceeds 100 columns
#10963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10939:
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#10964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10940:
+#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140

WARNING: line length of 105 exceeds 100 columns
#10965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10941:
+#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10942:
+#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141

WARNING: line length of 105 exceeds 100 columns
#10967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10943:
+#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10944:
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142

WARNING: line length of 105 exceeds 100 columns
#10969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10945:
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10946:
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143

WARNING: line length of 105 exceeds 100 columns
#10971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10947:
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10948:
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144

WARNING: line length of 105 exceeds 100 columns
#10973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10949:
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10950:
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145

WARNING: line length of 105 exceeds 100 columns
#10975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10951:
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#10976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10952:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146

WARNING: line length of 105 exceeds 100 columns
#10977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10953:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10954:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147

WARNING: line length of 105 exceeds 100 columns
#10979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10955:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10956:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148

WARNING: line length of 105 exceeds 100 columns
#10981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10957:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10958:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149

WARNING: line length of 105 exceeds 100 columns
#10983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10959:
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2

WARNING: line length of 110 exceeds 100 columns
#10988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10964:
+#define regDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x3164

WARNING: line length of 105 exceeds 100 columns
#10989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10965:
+#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#10990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10966:
+#define regDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x3165

WARNING: line length of 105 exceeds 100 columns
#10991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10967:
+#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10968:
+#define regDC_PERFMON22_PERFCOUNTER_STATE                                                               0x3166

WARNING: line length of 105 exceeds 100 columns
#10993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10969:
+#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#10994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10970:
+#define regDC_PERFMON22_PERFMON_CNTL                                                                    0x3167

WARNING: line length of 105 exceeds 100 columns
#10995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10971:
+#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#10996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10972:
+#define regDC_PERFMON22_PERFMON_CNTL2                                                                   0x3168

WARNING: line length of 105 exceeds 100 columns
#10997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10973:
+#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#10998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10974:
+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x3169

WARNING: line length of 105 exceeds 100 columns
#10999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10975:
+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10976:
+#define regDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x316a

WARNING: line length of 105 exceeds 100 columns
#11001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10977:
+#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#11002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10978:
+#define regDC_PERFMON22_PERFMON_HI                                                                      0x316b

WARNING: line length of 105 exceeds 100 columns
#11003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10979:
+#define regDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10980:
+#define regDC_PERFMON22_PERFMON_LOW                                                                     0x316c

WARNING: line length of 105 exceeds 100 columns
#11005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10981:
+#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10986:
+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228

WARNING: line length of 105 exceeds 100 columns
#11011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10987:
+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10988:
+#define regDWB_MEM_PWR_CTRL                                                                             0x3229

WARNING: line length of 105 exceeds 100 columns
#11013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10989:
+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10990:
+#define regFC_MODE_CTRL                                                                                 0x322a

WARNING: line length of 105 exceeds 100 columns
#11015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10991:
+#define regFC_MODE_CTRL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#11016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10992:
+#define regFC_FLOW_CTRL                                                                                 0x322b

WARNING: line length of 105 exceeds 100 columns
#11017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10993:
+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#11018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10994:
+#define regFC_WINDOW_START                                                                              0x322c

WARNING: line length of 105 exceeds 100 columns
#11019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10995:
+#define regFC_WINDOW_START_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#11020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10996:
+#define regFC_WINDOW_SIZE                                                                               0x322d

WARNING: line length of 105 exceeds 100 columns
#11021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10997:
+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10998:
+#define regFC_SOURCE_SIZE                                                                               0x322e

WARNING: line length of 105 exceeds 100 columns
#11023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:10999:
+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11000:
+#define regDWB_UPDATE_CTRL                                                                              0x322f

WARNING: line length of 105 exceeds 100 columns
#11025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11001:
+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#11026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11002:
+#define regDWB_CRC_CTRL                                                                                 0x3230

WARNING: line length of 105 exceeds 100 columns
#11027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11003:
+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#11028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11004:
+#define regDWB_CRC_MASK_R_G                                                                             0x3231

WARNING: line length of 105 exceeds 100 columns
#11029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11005:
+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11006:
+#define regDWB_CRC_MASK_B_A                                                                             0x3232

WARNING: line length of 105 exceeds 100 columns
#11031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11007:
+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11008:
+#define regDWB_CRC_VAL_R_G                                                                              0x3233

WARNING: line length of 105 exceeds 100 columns
#11033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11009:
+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#11034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11010:
+#define regDWB_CRC_VAL_B_A                                                                              0x3234

WARNING: line length of 105 exceeds 100 columns
#11035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11011:
+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#11036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11012:
+#define regDWB_OUT_CTRL                                                                                 0x3235

WARNING: line length of 105 exceeds 100 columns
#11037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11013:
+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2

WARNING: line length of 110 exceeds 100 columns
#11038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11014:
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236

WARNING: line length of 105 exceeds 100 columns
#11039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11015:
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11016:
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237

WARNING: line length of 105 exceeds 100 columns
#11041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11017:
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#11042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11018:
+#define regDWB_HOST_READ_CONTROL                                                                        0x3238

WARNING: line length of 105 exceeds 100 columns
#11043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11019:
+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#11044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11020:
+#define regDWB_OVERFLOW_STATUS                                                                          0x3239

WARNING: line length of 105 exceeds 100 columns
#11045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11021:
+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11022:
+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a

WARNING: line length of 105 exceeds 100 columns
#11047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11023:
+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#11048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11024:
+#define regDWB_SOFT_RESET                                                                               0x323b

WARNING: line length of 105 exceeds 100 columns
#11049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11025:
+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11030:
+#define regDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x3288

WARNING: line length of 105 exceeds 100 columns
#11055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11031:
+#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#11056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11032:
+#define regDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x3289

WARNING: line length of 105 exceeds 100 columns
#11057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11033:
+#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#11058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11034:
+#define regDC_PERFMON3_PERFCOUNTER_STATE                                                                0x328a

WARNING: line length of 105 exceeds 100 columns
#11059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11035:
+#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2

WARNING: line length of 110 exceeds 100 columns
#11060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11036:
+#define regDC_PERFMON3_PERFMON_CNTL                                                                     0x328b

WARNING: line length of 105 exceeds 100 columns
#11061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11037:
+#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11038:
+#define regDC_PERFMON3_PERFMON_CNTL2                                                                    0x328c

WARNING: line length of 105 exceeds 100 columns
#11063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11039:
+#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11040:
+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x328d

WARNING: line length of 105 exceeds 100 columns
#11065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11041:
+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11042:
+#define regDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x328e

WARNING: line length of 105 exceeds 100 columns
#11067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11043:
+#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#11068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11044:
+#define regDC_PERFMON3_PERFMON_HI                                                                       0x328f

WARNING: line length of 105 exceeds 100 columns
#11069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11045:
+#define regDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#11070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11046:
+#define regDC_PERFMON3_PERFMON_LOW                                                                      0x3290

WARNING: line length of 105 exceeds 100 columns
#11071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11047:
+#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11052:
+#define regDWB_HDR_MULT_COEF                                                                            0x3294

WARNING: line length of 105 exceeds 100 columns
#11077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11053:
+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#11078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11054:
+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295

WARNING: line length of 105 exceeds 100 columns
#11079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11055:
+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#11080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11056:
+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296

WARNING: line length of 105 exceeds 100 columns
#11081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11057:
+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#11082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11058:
+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297

WARNING: line length of 105 exceeds 100 columns
#11083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11059:
+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11060:
+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298

WARNING: line length of 105 exceeds 100 columns
#11085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11061:
+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11062:
+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299

WARNING: line length of 105 exceeds 100 columns
#11087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11063:
+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11064:
+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a

WARNING: line length of 105 exceeds 100 columns
#11089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11065:
+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11066:
+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b

WARNING: line length of 105 exceeds 100 columns
#11091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11067:
+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11068:
+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c

WARNING: line length of 105 exceeds 100 columns
#11093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11069:
+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11070:
+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d

WARNING: line length of 105 exceeds 100 columns
#11095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11071:
+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11072:
+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e

WARNING: line length of 105 exceeds 100 columns
#11097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11073:
+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11074:
+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f

WARNING: line length of 105 exceeds 100 columns
#11099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11075:
+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11076:
+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0

WARNING: line length of 105 exceeds 100 columns
#11101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11077:
+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11078:
+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1

WARNING: line length of 105 exceeds 100 columns
#11103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11079:
+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11080:
+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2

WARNING: line length of 105 exceeds 100 columns
#11105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11081:
+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11082:
+#define regDWB_OGAM_CONTROL                                                                             0x32a3

WARNING: line length of 105 exceeds 100 columns
#11107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11083:
+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11084:
+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4

WARNING: line length of 105 exceeds 100 columns
#11109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11085:
+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#11110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11086:
+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5

WARNING: line length of 105 exceeds 100 columns
#11111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11087:
+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#11112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11088:
+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6

WARNING: line length of 105 exceeds 100 columns
#11113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11089:
+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2

WARNING: line length of 110 exceeds 100 columns
#11114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11090:
+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7

WARNING: line length of 105 exceeds 100 columns
#11115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11091:
+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11092:
+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8

WARNING: line length of 105 exceeds 100 columns
#11117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11093:
+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11094:
+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9

WARNING: line length of 105 exceeds 100 columns
#11119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11095:
+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11096:
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa

WARNING: line length of 105 exceeds 100 columns
#11121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11097:
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#11122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11098:
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab

WARNING: line length of 105 exceeds 100 columns
#11123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11099:
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11100:
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac

WARNING: line length of 105 exceeds 100 columns
#11125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11101:
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#11126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11102:
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad

WARNING: line length of 105 exceeds 100 columns
#11127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11103:
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11104:
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae

WARNING: line length of 105 exceeds 100 columns
#11129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11105:
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#11130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11106:
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af

WARNING: line length of 105 exceeds 100 columns
#11131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11107:
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11108:
+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0

WARNING: line length of 105 exceeds 100 columns
#11133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11109:
+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11110:
+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1

WARNING: line length of 105 exceeds 100 columns
#11135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11111:
+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11112:
+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2

WARNING: line length of 105 exceeds 100 columns
#11137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11113:
+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11114:
+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3

WARNING: line length of 105 exceeds 100 columns
#11139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11115:
+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11116:
+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4

WARNING: line length of 105 exceeds 100 columns
#11141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11117:
+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11118:
+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5

WARNING: line length of 105 exceeds 100 columns
#11143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11119:
+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11120:
+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6

WARNING: line length of 105 exceeds 100 columns
#11145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11121:
+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#11146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11122:
+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7

WARNING: line length of 105 exceeds 100 columns
#11147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11123:
+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#11148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11124:
+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8

WARNING: line length of 105 exceeds 100 columns
#11149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11125:
+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#11150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11126:
+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9

WARNING: line length of 105 exceeds 100 columns
#11151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11127:
+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11128:
+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba

WARNING: line length of 105 exceeds 100 columns
#11153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11129:
+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11130:
+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb

WARNING: line length of 105 exceeds 100 columns
#11155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11131:
+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11132:
+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc

WARNING: line length of 105 exceeds 100 columns
#11157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11133:
+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11134:
+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd

WARNING: line length of 105 exceeds 100 columns
#11159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11135:
+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11136:
+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be

WARNING: line length of 105 exceeds 100 columns
#11161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11137:
+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11138:
+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf

WARNING: line length of 105 exceeds 100 columns
#11163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11139:
+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11140:
+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0

WARNING: line length of 105 exceeds 100 columns
#11165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11141:
+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11142:
+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1

WARNING: line length of 105 exceeds 100 columns
#11167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11143:
+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11144:
+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2

WARNING: line length of 105 exceeds 100 columns
#11169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11145:
+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11146:
+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3

WARNING: line length of 105 exceeds 100 columns
#11171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11147:
+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11148:
+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4

WARNING: line length of 105 exceeds 100 columns
#11173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11149:
+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11150:
+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5

WARNING: line length of 105 exceeds 100 columns
#11175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11151:
+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11152:
+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6

WARNING: line length of 105 exceeds 100 columns
#11177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11153:
+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11154:
+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7

WARNING: line length of 105 exceeds 100 columns
#11179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11155:
+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11156:
+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8

WARNING: line length of 105 exceeds 100 columns
#11181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11157:
+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11158:
+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9

WARNING: line length of 105 exceeds 100 columns
#11183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11159:
+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11160:
+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca

WARNING: line length of 105 exceeds 100 columns
#11185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11161:
+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11162:
+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb

WARNING: line length of 105 exceeds 100 columns
#11187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11163:
+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11164:
+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc

WARNING: line length of 105 exceeds 100 columns
#11189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11165:
+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11166:
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd

WARNING: line length of 105 exceeds 100 columns
#11191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11167:
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#11192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11168:
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce

WARNING: line length of 105 exceeds 100 columns
#11193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11169:
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11170:
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf

WARNING: line length of 105 exceeds 100 columns
#11195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11171:
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#11196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11172:
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0

WARNING: line length of 105 exceeds 100 columns
#11197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11173:
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11174:
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1

WARNING: line length of 105 exceeds 100 columns
#11199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11175:
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2

WARNING: line length of 110 exceeds 100 columns
#11200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11176:
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2

WARNING: line length of 105 exceeds 100 columns
#11201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11177:
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11178:
+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3

WARNING: line length of 105 exceeds 100 columns
#11203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11179:
+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11180:
+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4

WARNING: line length of 105 exceeds 100 columns
#11205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11181:
+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11182:
+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5

WARNING: line length of 105 exceeds 100 columns
#11207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11183:
+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11184:
+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6

WARNING: line length of 105 exceeds 100 columns
#11209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11185:
+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11186:
+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7

WARNING: line length of 105 exceeds 100 columns
#11211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11187:
+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11188:
+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8

WARNING: line length of 105 exceeds 100 columns
#11213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11189:
+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11190:
+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9

WARNING: line length of 105 exceeds 100 columns
#11215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11191:
+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#11216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11192:
+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da

WARNING: line length of 105 exceeds 100 columns
#11217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11193:
+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#11218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11194:
+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db

WARNING: line length of 105 exceeds 100 columns
#11219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11195:
+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2

WARNING: line length of 110 exceeds 100 columns
#11220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11196:
+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc

WARNING: line length of 105 exceeds 100 columns
#11221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11197:
+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11198:
+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd

WARNING: line length of 105 exceeds 100 columns
#11223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11199:
+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11200:
+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de

WARNING: line length of 105 exceeds 100 columns
#11225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11201:
+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11202:
+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df

WARNING: line length of 105 exceeds 100 columns
#11227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11203:
+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11204:
+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0

WARNING: line length of 105 exceeds 100 columns
#11229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11205:
+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11206:
+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1

WARNING: line length of 105 exceeds 100 columns
#11231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11207:
+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11208:
+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2

WARNING: line length of 105 exceeds 100 columns
#11233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11209:
+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11210:
+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3

WARNING: line length of 105 exceeds 100 columns
#11235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11211:
+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11212:
+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4

WARNING: line length of 105 exceeds 100 columns
#11237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11213:
+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11214:
+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5

WARNING: line length of 105 exceeds 100 columns
#11239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11215:
+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11216:
+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6

WARNING: line length of 105 exceeds 100 columns
#11241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11217:
+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11218:
+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7

WARNING: line length of 105 exceeds 100 columns
#11243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11219:
+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11220:
+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8

WARNING: line length of 105 exceeds 100 columns
#11245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11221:
+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11222:
+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9

WARNING: line length of 105 exceeds 100 columns
#11247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11223:
+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11224:
+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea

WARNING: line length of 105 exceeds 100 columns
#11249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11225:
+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11226:
+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb

WARNING: line length of 105 exceeds 100 columns
#11251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11227:
+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11228:
+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec

WARNING: line length of 105 exceeds 100 columns
#11253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11229:
+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11234:
+#define regDCHVM_CTRL0                                                                                  0x3603

WARNING: line length of 105 exceeds 100 columns
#11259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11235:
+#define regDCHVM_CTRL0_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#11260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11236:
+#define regDCHVM_CTRL1                                                                                  0x3604

WARNING: line length of 105 exceeds 100 columns
#11261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11237:
+#define regDCHVM_CTRL1_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#11262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11238:
+#define regDCHVM_CLK_CTRL                                                                               0x3605

WARNING: line length of 105 exceeds 100 columns
#11263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11239:
+#define regDCHVM_CLK_CTRL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11240:
+#define regDCHVM_MEM_CTRL                                                                               0x3606

WARNING: line length of 105 exceeds 100 columns
#11265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11241:
+#define regDCHVM_MEM_CTRL_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11242:
+#define regDCHVM_RIOMMU_CTRL0                                                                           0x3607

WARNING: line length of 105 exceeds 100 columns
#11267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11243:
+#define regDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#11268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11244:
+#define regDCHVM_RIOMMU_STAT0                                                                           0x3608

WARNING: line length of 105 exceeds 100 columns
#11269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11245:
+#define regDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#11274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11250:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623

WARNING: line length of 105 exceeds 100 columns
#11275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11251:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11252:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624

WARNING: line length of 105 exceeds 100 columns
#11277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11253:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#11278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11254:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625

WARNING: line length of 105 exceeds 100 columns
#11279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11255:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11256:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626

WARNING: line length of 105 exceeds 100 columns
#11281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11257:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11258:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627

WARNING: line length of 105 exceeds 100 columns
#11283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11259:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11260:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628

WARNING: line length of 105 exceeds 100 columns
#11285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11261:
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11266:
+#define regAPG0_APG_CONTROL                                                                             0x3630

WARNING: line length of 105 exceeds 100 columns
#11291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11267:
+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11268:
+#define regAPG0_APG_CONTROL2                                                                            0x3631

WARNING: line length of 105 exceeds 100 columns
#11293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11269:
+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#11294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11270:
+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632

WARNING: line length of 105 exceeds 100 columns
#11295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11271:
+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11272:
+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633

WARNING: line length of 105 exceeds 100 columns
#11297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11273:
+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11274:
+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a

WARNING: line length of 105 exceeds 100 columns
#11299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11275:
+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11276:
+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b

WARNING: line length of 105 exceeds 100 columns
#11301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11277:
+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#11302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11278:
+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c

WARNING: line length of 105 exceeds 100 columns
#11303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11279:
+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11280:
+#define regAPG0_APG_STATUS                                                                              0x3641

WARNING: line length of 105 exceeds 100 columns
#11305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11281:
+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#11306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11282:
+#define regAPG0_APG_STATUS2                                                                             0x3642

WARNING: line length of 105 exceeds 100 columns
#11307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11283:
+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11284:
+#define regAPG0_APG_MEM_PWR                                                                             0x3644

WARNING: line length of 105 exceeds 100 columns
#11309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11285:
+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11286:
+#define regAPG0_APG_SPARE                                                                               0x3646

WARNING: line length of 105 exceeds 100 columns
#11311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11287:
+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11292:
+#define regDME6_DME_CONTROL                                                                             0x364e

WARNING: line length of 105 exceeds 100 columns
#11317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11293:
+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11294:
+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f

WARNING: line length of 105 exceeds 100 columns
#11319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11295:
+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11300:
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651

WARNING: line length of 105 exceeds 100 columns
#11325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11301:
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11302:
+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652

WARNING: line length of 105 exceeds 100 columns
#11327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11303:
+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#11328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11304:
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653

WARNING: line length of 105 exceeds 100 columns
#11329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11305:
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#11330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11306:
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654

WARNING: line length of 105 exceeds 100 columns
#11331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11307:
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11308:
+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655

WARNING: line length of 105 exceeds 100 columns
#11333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11309:
+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11310:
+#define regVPG6_VPG_MEM_PWR                                                                             0x3656

WARNING: line length of 105 exceeds 100 columns
#11335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11311:
+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11312:
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657

WARNING: line length of 105 exceeds 100 columns
#11337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11313:
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#11338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11314:
+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658

WARNING: line length of 105 exceeds 100 columns
#11339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11315:
+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#11340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11316:
+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659

WARNING: line length of 105 exceeds 100 columns
#11341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11317:
+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11318:
+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a

WARNING: line length of 105 exceeds 100 columns
#11343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11319:
+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11324:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d

WARNING: line length of 105 exceeds 100 columns
#11349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11325:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11326:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e

WARNING: line length of 105 exceeds 100 columns
#11351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11327:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11328:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f

WARNING: line length of 105 exceeds 100 columns
#11353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11329:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2

WARNING: line length of 110 exceeds 100 columns
#11354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11330:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660

WARNING: line length of 105 exceeds 100 columns
#11355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11331:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2

WARNING: line length of 110 exceeds 100 columns
#11356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11332:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661

WARNING: line length of 105 exceeds 100 columns
#11357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11333:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11334:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662

WARNING: line length of 105 exceeds 100 columns
#11359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11335:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11336:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663

WARNING: line length of 105 exceeds 100 columns
#11361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11337:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11338:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664

WARNING: line length of 105 exceeds 100 columns
#11363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11339:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11340:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665

WARNING: line length of 105 exceeds 100 columns
#11365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11341:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11342:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666

WARNING: line length of 105 exceeds 100 columns
#11367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11343:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11344:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667

WARNING: line length of 105 exceeds 100 columns
#11369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11345:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11346:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668

WARNING: line length of 105 exceeds 100 columns
#11371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11347:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11348:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669

WARNING: line length of 105 exceeds 100 columns
#11373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11349:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11350:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a

WARNING: line length of 105 exceeds 100 columns
#11375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11351:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11352:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b

WARNING: line length of 105 exceeds 100 columns
#11377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11353:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11354:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c

WARNING: line length of 105 exceeds 100 columns
#11379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11355:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11356:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d

WARNING: line length of 105 exceeds 100 columns
#11381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11357:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11358:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e

WARNING: line length of 105 exceeds 100 columns
#11383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11359:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11360:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f

WARNING: line length of 105 exceeds 100 columns
#11385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11361:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11362:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670

WARNING: line length of 105 exceeds 100 columns
#11387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11363:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11364:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671

WARNING: line length of 105 exceeds 100 columns
#11389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11365:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11366:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672

WARNING: line length of 105 exceeds 100 columns
#11391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11367:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11368:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673

WARNING: line length of 105 exceeds 100 columns
#11393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11369:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11370:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674

WARNING: line length of 105 exceeds 100 columns
#11395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11371:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11372:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675

WARNING: line length of 105 exceeds 100 columns
#11397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11373:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11374:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676

WARNING: line length of 105 exceeds 100 columns
#11399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11375:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11376:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677

WARNING: line length of 105 exceeds 100 columns
#11401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11377:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11378:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678

WARNING: line length of 105 exceeds 100 columns
#11403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11379:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11380:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679

WARNING: line length of 105 exceeds 100 columns
#11405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11381:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11382:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a

WARNING: line length of 105 exceeds 100 columns
#11407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11383:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11384:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b

WARNING: line length of 105 exceeds 100 columns
#11409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11385:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11386:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c

WARNING: line length of 105 exceeds 100 columns
#11411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11387:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11388:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d

WARNING: line length of 105 exceeds 100 columns
#11413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11389:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11390:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e

WARNING: line length of 105 exceeds 100 columns
#11415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11391:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#11416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11392:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683

WARNING: line length of 105 exceeds 100 columns
#11417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11393:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11394:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684

WARNING: line length of 105 exceeds 100 columns
#11419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11395:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11396:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685

WARNING: line length of 105 exceeds 100 columns
#11421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11397:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11398:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686

WARNING: line length of 105 exceeds 100 columns
#11423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11399:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#11424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11400:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687

WARNING: line length of 105 exceeds 100 columns
#11425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11401:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11402:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688

WARNING: line length of 105 exceeds 100 columns
#11427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11403:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11404:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689

WARNING: line length of 105 exceeds 100 columns
#11429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11405:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11406:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a

WARNING: line length of 105 exceeds 100 columns
#11431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11407:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11408:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x368b

WARNING: line length of 105 exceeds 100 columns
#11433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11409:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#11434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11410:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x368c

WARNING: line length of 105 exceeds 100 columns
#11435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11411:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2

WARNING: line length of 110 exceeds 100 columns
#11436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11412:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368d

WARNING: line length of 105 exceeds 100 columns
#11437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11413:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11414:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368e

WARNING: line length of 105 exceeds 100 columns
#11439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11415:
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11420:
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697

WARNING: line length of 105 exceeds 100 columns
#11445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11421:
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11422:
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698

WARNING: line length of 105 exceeds 100 columns
#11447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11423:
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#11452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11428:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0

WARNING: line length of 105 exceeds 100 columns
#11453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11429:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11430:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1

WARNING: line length of 105 exceeds 100 columns
#11455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11431:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11432:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4

WARNING: line length of 105 exceeds 100 columns
#11457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11433:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11434:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5

WARNING: line length of 105 exceeds 100 columns
#11459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11435:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11436:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6

WARNING: line length of 105 exceeds 100 columns
#11461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11437:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11438:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7

WARNING: line length of 105 exceeds 100 columns
#11463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11439:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11440:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8

WARNING: line length of 105 exceeds 100 columns
#11465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11441:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11442:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb

WARNING: line length of 105 exceeds 100 columns
#11467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11443:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11444:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc

WARNING: line length of 105 exceeds 100 columns
#11469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11445:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11446:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd

WARNING: line length of 105 exceeds 100 columns
#11471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11447:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11448:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce

WARNING: line length of 105 exceeds 100 columns
#11473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11449:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11450:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1

WARNING: line length of 105 exceeds 100 columns
#11475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11451:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11452:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2

WARNING: line length of 105 exceeds 100 columns
#11477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11453:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11454:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3

WARNING: line length of 105 exceeds 100 columns
#11479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11455:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11456:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4

WARNING: line length of 105 exceeds 100 columns
#11481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11457:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11458:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7

WARNING: line length of 105 exceeds 100 columns
#11483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11459:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11460:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8

WARNING: line length of 105 exceeds 100 columns
#11485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11461:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11462:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9

WARNING: line length of 105 exceeds 100 columns
#11487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11463:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11464:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da

WARNING: line length of 105 exceeds 100 columns
#11489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11465:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11466:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db

WARNING: line length of 105 exceeds 100 columns
#11491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11467:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11468:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc

WARNING: line length of 105 exceeds 100 columns
#11493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11469:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11470:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd

WARNING: line length of 105 exceeds 100 columns
#11495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11471:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11472:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de

WARNING: line length of 105 exceeds 100 columns
#11497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11473:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11474:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df

WARNING: line length of 105 exceeds 100 columns
#11499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11475:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11476:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0

WARNING: line length of 105 exceeds 100 columns
#11501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11477:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11478:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1

WARNING: line length of 105 exceeds 100 columns
#11503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11479:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11480:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2

WARNING: line length of 105 exceeds 100 columns
#11505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11481:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11482:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3

WARNING: line length of 105 exceeds 100 columns
#11507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11483:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11484:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4

WARNING: line length of 105 exceeds 100 columns
#11509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11485:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11486:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5

WARNING: line length of 105 exceeds 100 columns
#11511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11487:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11488:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6

WARNING: line length of 105 exceeds 100 columns
#11513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11489:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11490:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7

WARNING: line length of 105 exceeds 100 columns
#11515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11491:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11492:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8

WARNING: line length of 105 exceeds 100 columns
#11517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11493:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11494:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea

WARNING: line length of 105 exceeds 100 columns
#11519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11495:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11496:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x36eb

WARNING: line length of 105 exceeds 100 columns
#11521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11497:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#11522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11498:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x36ec

WARNING: line length of 105 exceeds 100 columns
#11523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11499:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#11524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11500:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x36ed

WARNING: line length of 105 exceeds 100 columns
#11525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11501:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#11526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11502:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36ee

WARNING: line length of 105 exceeds 100 columns
#11527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11503:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11504:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ef

WARNING: line length of 105 exceeds 100 columns
#11529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11505:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11506:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36f0

WARNING: line length of 105 exceeds 100 columns
#11531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11507:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11508:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36f1

WARNING: line length of 105 exceeds 100 columns
#11533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11509:
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11514:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7

WARNING: line length of 105 exceeds 100 columns
#11539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11515:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11516:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8

WARNING: line length of 105 exceeds 100 columns
#11541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11517:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#11542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11518:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9

WARNING: line length of 105 exceeds 100 columns
#11543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11519:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11520:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa

WARNING: line length of 105 exceeds 100 columns
#11545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11521:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11522:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb

WARNING: line length of 105 exceeds 100 columns
#11547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11523:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11524:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc

WARNING: line length of 105 exceeds 100 columns
#11549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11525:
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11530:
+#define regAPG1_APG_CONTROL                                                                             0x3704

WARNING: line length of 105 exceeds 100 columns
#11555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11531:
+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11532:
+#define regAPG1_APG_CONTROL2                                                                            0x3705

WARNING: line length of 105 exceeds 100 columns
#11557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11533:
+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#11558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11534:
+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706

WARNING: line length of 105 exceeds 100 columns
#11559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11535:
+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11536:
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707

WARNING: line length of 110 exceeds 100 columns
#11561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11537:
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707

WARNING: line length of 105 exceeds 100 columns
#11562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11538:
+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11539:
+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e

WARNING: line length of 105 exceeds 100 columns
#11564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11540:
+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11541:
+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f

WARNING: line length of 105 exceeds 100 columns
#11566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11542:
+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#11567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11543:
+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710

WARNING: line length of 105 exceeds 100 columns
#11568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11544:
+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11545:
+#define regAPG1_APG_STATUS                                                                              0x3715

WARNING: line length of 105 exceeds 100 columns
#11570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11546:
+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#11571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11547:
+#define regAPG1_APG_STATUS2                                                                             0x3716

WARNING: line length of 105 exceeds 100 columns
#11572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11548:
+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11549:
+#define regAPG1_APG_MEM_PWR                                                                             0x3718

WARNING: line length of 105 exceeds 100 columns
#11574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11550:
+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11551:
+#define regAPG1_APG_SPARE                                                                               0x371a

WARNING: line length of 105 exceeds 100 columns
#11576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11552:
+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11557:
+#define regDME7_DME_CONTROL                                                                             0x3722

WARNING: line length of 105 exceeds 100 columns
#11582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11558:
+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11559:
+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723

WARNING: line length of 105 exceeds 100 columns
#11584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11560:
+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11565:
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725

WARNING: line length of 105 exceeds 100 columns
#11590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11566:
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11567:
+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726

WARNING: line length of 105 exceeds 100 columns
#11592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11568:
+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#11593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11569:
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727

WARNING: line length of 105 exceeds 100 columns
#11594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11570:
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#11595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11571:
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728

WARNING: line length of 105 exceeds 100 columns
#11596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11572:
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11573:
+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729

WARNING: line length of 105 exceeds 100 columns
#11598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11574:
+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11575:
+#define regVPG7_VPG_MEM_PWR                                                                             0x372a

WARNING: line length of 105 exceeds 100 columns
#11600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11576:
+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11577:
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b

WARNING: line length of 105 exceeds 100 columns
#11602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11578:
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#11603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11579:
+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c

WARNING: line length of 105 exceeds 100 columns
#11604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11580:
+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#11605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11581:
+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d

WARNING: line length of 105 exceeds 100 columns
#11606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11582:
+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11583:
+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e

WARNING: line length of 105 exceeds 100 columns
#11608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11584:
+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11589:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731

WARNING: line length of 105 exceeds 100 columns
#11614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11590:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11591:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732

WARNING: line length of 105 exceeds 100 columns
#11616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11592:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11593:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733

WARNING: line length of 105 exceeds 100 columns
#11618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11594:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2

WARNING: line length of 110 exceeds 100 columns
#11619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11595:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734

WARNING: line length of 105 exceeds 100 columns
#11620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11596:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2

WARNING: line length of 110 exceeds 100 columns
#11621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11597:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735

WARNING: line length of 105 exceeds 100 columns
#11622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11598:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11599:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736

WARNING: line length of 105 exceeds 100 columns
#11624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11600:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11601:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737

WARNING: line length of 105 exceeds 100 columns
#11626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11602:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11603:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738

WARNING: line length of 105 exceeds 100 columns
#11628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11604:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11605:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739

WARNING: line length of 105 exceeds 100 columns
#11630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11606:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11607:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a

WARNING: line length of 105 exceeds 100 columns
#11632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11608:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11609:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b

WARNING: line length of 105 exceeds 100 columns
#11634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11610:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11611:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c

WARNING: line length of 105 exceeds 100 columns
#11636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11612:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11613:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d

WARNING: line length of 105 exceeds 100 columns
#11638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11614:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11615:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e

WARNING: line length of 105 exceeds 100 columns
#11640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11616:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11617:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f

WARNING: line length of 105 exceeds 100 columns
#11642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11618:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11619:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740

WARNING: line length of 105 exceeds 100 columns
#11644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11620:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11621:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741

WARNING: line length of 105 exceeds 100 columns
#11646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11622:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11623:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742

WARNING: line length of 105 exceeds 100 columns
#11648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11624:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11625:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743

WARNING: line length of 105 exceeds 100 columns
#11650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11626:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11627:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744

WARNING: line length of 105 exceeds 100 columns
#11652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11628:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11629:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745

WARNING: line length of 105 exceeds 100 columns
#11654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11630:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11631:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746

WARNING: line length of 105 exceeds 100 columns
#11656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11632:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11633:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747

WARNING: line length of 105 exceeds 100 columns
#11658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11634:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11635:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748

WARNING: line length of 105 exceeds 100 columns
#11660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11636:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11637:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749

WARNING: line length of 105 exceeds 100 columns
#11662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11638:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11639:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a

WARNING: line length of 105 exceeds 100 columns
#11664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11640:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11641:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b

WARNING: line length of 105 exceeds 100 columns
#11666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11642:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11643:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c

WARNING: line length of 105 exceeds 100 columns
#11668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11644:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11645:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d

WARNING: line length of 105 exceeds 100 columns
#11670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11646:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11647:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e

WARNING: line length of 105 exceeds 100 columns
#11672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11648:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11649:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f

WARNING: line length of 105 exceeds 100 columns
#11674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11650:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11651:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750

WARNING: line length of 105 exceeds 100 columns
#11676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11652:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11653:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751

WARNING: line length of 105 exceeds 100 columns
#11678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11654:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11655:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752

WARNING: line length of 105 exceeds 100 columns
#11680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11656:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#11681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11657:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757

WARNING: line length of 105 exceeds 100 columns
#11682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11658:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11659:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758

WARNING: line length of 105 exceeds 100 columns
#11684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11660:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11661:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759

WARNING: line length of 105 exceeds 100 columns
#11686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11662:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11663:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a

WARNING: line length of 105 exceeds 100 columns
#11688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11664:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#11689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11665:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b

WARNING: line length of 105 exceeds 100 columns
#11690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11666:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11667:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c

WARNING: line length of 105 exceeds 100 columns
#11692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11668:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11669:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d

WARNING: line length of 105 exceeds 100 columns
#11694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11670:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11671:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e

WARNING: line length of 105 exceeds 100 columns
#11696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11672:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11673:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x375f

WARNING: line length of 105 exceeds 100 columns
#11698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11674:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#11699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11675:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3760

WARNING: line length of 105 exceeds 100 columns
#11700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11676:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2

WARNING: line length of 110 exceeds 100 columns
#11701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11677:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3761

WARNING: line length of 105 exceeds 100 columns
#11702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11678:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11679:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3762

WARNING: line length of 105 exceeds 100 columns
#11704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11680:
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11685:
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b

WARNING: line length of 105 exceeds 100 columns
#11710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11686:
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11687:
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c

WARNING: line length of 105 exceeds 100 columns
#11712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11688:
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#11717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11693:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794

WARNING: line length of 105 exceeds 100 columns
#11718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11694:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11695:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795

WARNING: line length of 105 exceeds 100 columns
#11720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11696:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11697:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798

WARNING: line length of 105 exceeds 100 columns
#11722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11698:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11699:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799

WARNING: line length of 105 exceeds 100 columns
#11724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11700:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11701:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a

WARNING: line length of 105 exceeds 100 columns
#11726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11702:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11703:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b

WARNING: line length of 105 exceeds 100 columns
#11728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11704:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11705:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c

WARNING: line length of 105 exceeds 100 columns
#11730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11706:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11707:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f

WARNING: line length of 105 exceeds 100 columns
#11732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11708:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11709:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0

WARNING: line length of 105 exceeds 100 columns
#11734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11710:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11711:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1

WARNING: line length of 105 exceeds 100 columns
#11736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11712:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11713:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2

WARNING: line length of 105 exceeds 100 columns
#11738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11714:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2

WARNING: line length of 110 exceeds 100 columns
#11739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11715:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5

WARNING: line length of 105 exceeds 100 columns
#11740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11716:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11717:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6

WARNING: line length of 105 exceeds 100 columns
#11742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11718:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11719:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7

WARNING: line length of 105 exceeds 100 columns
#11744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11720:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11721:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8

WARNING: line length of 105 exceeds 100 columns
#11746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11722:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11723:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab

WARNING: line length of 105 exceeds 100 columns
#11748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11724:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11725:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac

WARNING: line length of 105 exceeds 100 columns
#11750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11726:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11727:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad

WARNING: line length of 105 exceeds 100 columns
#11752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11728:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11729:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae

WARNING: line length of 105 exceeds 100 columns
#11754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11730:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11731:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af

WARNING: line length of 105 exceeds 100 columns
#11756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11732:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11733:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0

WARNING: line length of 105 exceeds 100 columns
#11758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11734:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11735:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1

WARNING: line length of 105 exceeds 100 columns
#11760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11736:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11737:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2

WARNING: line length of 105 exceeds 100 columns
#11762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11738:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11739:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3

WARNING: line length of 105 exceeds 100 columns
#11764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11740:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11741:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4

WARNING: line length of 105 exceeds 100 columns
#11766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11742:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11743:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5

WARNING: line length of 105 exceeds 100 columns
#11768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11744:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11745:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6

WARNING: line length of 105 exceeds 100 columns
#11770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11746:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11747:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7

WARNING: line length of 105 exceeds 100 columns
#11772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11748:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11749:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8

WARNING: line length of 105 exceeds 100 columns
#11774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11750:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11751:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9

WARNING: line length of 105 exceeds 100 columns
#11776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11752:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11753:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba

WARNING: line length of 105 exceeds 100 columns
#11778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11754:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11755:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb

WARNING: line length of 105 exceeds 100 columns
#11780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11756:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11757:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc

WARNING: line length of 105 exceeds 100 columns
#11782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11758:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11759:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be

WARNING: line length of 105 exceeds 100 columns
#11784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11760:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11761:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x37bf

WARNING: line length of 105 exceeds 100 columns
#11786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11762:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#11787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11763:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x37c0

WARNING: line length of 105 exceeds 100 columns
#11788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11764:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#11789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11765:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x37c1

WARNING: line length of 105 exceeds 100 columns
#11790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11766:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2

WARNING: line length of 110 exceeds 100 columns
#11791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11767:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37c2

WARNING: line length of 105 exceeds 100 columns
#11792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11768:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11769:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c3

WARNING: line length of 105 exceeds 100 columns
#11794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11770:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2

WARNING: line length of 110 exceeds 100 columns
#11795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11771:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c4

WARNING: line length of 105 exceeds 100 columns
#11796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11772:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2

WARNING: line length of 110 exceeds 100 columns
#11797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11773:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c5

WARNING: line length of 105 exceeds 100 columns
#11798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11774:
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11779:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb

WARNING: line length of 105 exceeds 100 columns
#11804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11780:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11781:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc

WARNING: line length of 105 exceeds 100 columns
#11806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11782:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#11807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11783:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd

WARNING: line length of 105 exceeds 100 columns
#11808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11784:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11785:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce

WARNING: line length of 105 exceeds 100 columns
#11810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11786:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11787:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf

WARNING: line length of 105 exceeds 100 columns
#11812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11788:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11789:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0

WARNING: line length of 105 exceeds 100 columns
#11814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11790:
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11795:
+#define regAPG2_APG_CONTROL                                                                             0x37d8

WARNING: line length of 105 exceeds 100 columns
#11820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11796:
+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11797:
+#define regAPG2_APG_CONTROL2                                                                            0x37d9

WARNING: line length of 105 exceeds 100 columns
#11822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11798:
+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#11823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11799:
+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da

WARNING: line length of 105 exceeds 100 columns
#11824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11800:
+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11801:
+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db

WARNING: line length of 105 exceeds 100 columns
#11826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11802:
+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11803:
+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2

WARNING: line length of 105 exceeds 100 columns
#11828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11804:
+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11805:
+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3

WARNING: line length of 105 exceeds 100 columns
#11830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11806:
+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#11831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11807:
+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4

WARNING: line length of 105 exceeds 100 columns
#11832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11808:
+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#11833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11809:
+#define regAPG2_APG_STATUS                                                                              0x37e9

WARNING: line length of 105 exceeds 100 columns
#11834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11810:
+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#11835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11811:
+#define regAPG2_APG_STATUS2                                                                             0x37ea

WARNING: line length of 105 exceeds 100 columns
#11836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11812:
+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11813:
+#define regAPG2_APG_MEM_PWR                                                                             0x37ec

WARNING: line length of 105 exceeds 100 columns
#11838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11814:
+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11815:
+#define regAPG2_APG_SPARE                                                                               0x37ee

WARNING: line length of 105 exceeds 100 columns
#11840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11816:
+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#11845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11821:
+#define regDME8_DME_CONTROL                                                                             0x37f6

WARNING: line length of 105 exceeds 100 columns
#11846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11822:
+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11823:
+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7

WARNING: line length of 105 exceeds 100 columns
#11848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11824:
+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11829:
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9

WARNING: line length of 105 exceeds 100 columns
#11854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11830:
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11831:
+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa

WARNING: line length of 105 exceeds 100 columns
#11856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11832:
+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#11857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11833:
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb

WARNING: line length of 105 exceeds 100 columns
#11858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11834:
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#11859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11835:
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc

WARNING: line length of 105 exceeds 100 columns
#11860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11836:
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11837:
+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd

WARNING: line length of 105 exceeds 100 columns
#11862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11838:
+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11839:
+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe

WARNING: line length of 105 exceeds 100 columns
#11864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11840:
+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11841:
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff

WARNING: line length of 105 exceeds 100 columns
#11866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11842:
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#11867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11843:
+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800

WARNING: line length of 105 exceeds 100 columns
#11868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11844:
+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#11869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11845:
+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801

WARNING: line length of 105 exceeds 100 columns
#11870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11846:
+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11847:
+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802

WARNING: line length of 105 exceeds 100 columns
#11872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11848:
+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#11877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11853:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805

WARNING: line length of 105 exceeds 100 columns
#11878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11854:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11855:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806

WARNING: line length of 105 exceeds 100 columns
#11880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11856:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11857:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807

WARNING: line length of 105 exceeds 100 columns
#11882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11858:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2

WARNING: line length of 110 exceeds 100 columns
#11883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11859:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808

WARNING: line length of 105 exceeds 100 columns
#11884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11860:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2

WARNING: line length of 110 exceeds 100 columns
#11885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11861:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809

WARNING: line length of 105 exceeds 100 columns
#11886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11862:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11863:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a

WARNING: line length of 105 exceeds 100 columns
#11888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11864:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11865:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b

WARNING: line length of 105 exceeds 100 columns
#11890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11866:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11867:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c

WARNING: line length of 105 exceeds 100 columns
#11892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11868:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11869:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d

WARNING: line length of 105 exceeds 100 columns
#11894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11870:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11871:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e

WARNING: line length of 105 exceeds 100 columns
#11896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11872:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11873:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f

WARNING: line length of 105 exceeds 100 columns
#11898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11874:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11875:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810

WARNING: line length of 105 exceeds 100 columns
#11900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11876:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11877:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811

WARNING: line length of 105 exceeds 100 columns
#11902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11878:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11879:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812

WARNING: line length of 105 exceeds 100 columns
#11904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11880:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#11905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11881:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813

WARNING: line length of 105 exceeds 100 columns
#11906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11882:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11883:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814

WARNING: line length of 105 exceeds 100 columns
#11908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11884:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11885:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815

WARNING: line length of 105 exceeds 100 columns
#11910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11886:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11887:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816

WARNING: line length of 105 exceeds 100 columns
#11912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11888:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11889:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817

WARNING: line length of 105 exceeds 100 columns
#11914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11890:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11891:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818

WARNING: line length of 105 exceeds 100 columns
#11916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11892:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11893:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819

WARNING: line length of 105 exceeds 100 columns
#11918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11894:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11895:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a

WARNING: line length of 105 exceeds 100 columns
#11920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11896:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11897:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b

WARNING: line length of 105 exceeds 100 columns
#11922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11898:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11899:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c

WARNING: line length of 105 exceeds 100 columns
#11924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11900:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11901:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d

WARNING: line length of 105 exceeds 100 columns
#11926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11902:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11903:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e

WARNING: line length of 105 exceeds 100 columns
#11928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11904:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11905:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f

WARNING: line length of 105 exceeds 100 columns
#11930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11906:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11907:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820

WARNING: line length of 105 exceeds 100 columns
#11932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11908:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11909:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821

WARNING: line length of 105 exceeds 100 columns
#11934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11910:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11911:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822

WARNING: line length of 105 exceeds 100 columns
#11936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11912:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11913:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823

WARNING: line length of 105 exceeds 100 columns
#11938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11914:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#11939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11915:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824

WARNING: line length of 105 exceeds 100 columns
#11940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11916:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11917:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825

WARNING: line length of 105 exceeds 100 columns
#11942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11918:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11919:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826

WARNING: line length of 105 exceeds 100 columns
#11944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11920:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#11945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11921:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b

WARNING: line length of 105 exceeds 100 columns
#11946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11922:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11923:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c

WARNING: line length of 105 exceeds 100 columns
#11948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11924:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#11949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11925:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d

WARNING: line length of 105 exceeds 100 columns
#11950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11926:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#11951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11927:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e

WARNING: line length of 105 exceeds 100 columns
#11952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11928:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#11953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11929:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f

WARNING: line length of 105 exceeds 100 columns
#11954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11930:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11931:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830

WARNING: line length of 105 exceeds 100 columns
#11956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11932:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11933:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831

WARNING: line length of 105 exceeds 100 columns
#11958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11934:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11935:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832

WARNING: line length of 105 exceeds 100 columns
#11960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11936:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#11961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11937:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3833

WARNING: line length of 105 exceeds 100 columns
#11962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11938:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#11963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11939:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3834

WARNING: line length of 105 exceeds 100 columns
#11964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11940:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2

WARNING: line length of 110 exceeds 100 columns
#11965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11941:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3835

WARNING: line length of 105 exceeds 100 columns
#11966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11942:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#11967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11943:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3836

WARNING: line length of 105 exceeds 100 columns
#11968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11944:
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#11973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11949:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f

WARNING: line length of 105 exceeds 100 columns
#11974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11950:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11951:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0

WARNING: line length of 105 exceeds 100 columns
#11976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11952:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#11977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11953:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1

WARNING: line length of 105 exceeds 100 columns
#11978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11954:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#11979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11955:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2

WARNING: line length of 105 exceeds 100 columns
#11980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11956:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11957:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3

WARNING: line length of 105 exceeds 100 columns
#11982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11958:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2

WARNING: line length of 110 exceeds 100 columns
#11983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11959:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4

WARNING: line length of 105 exceeds 100 columns
#11984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11960:
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#11989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11965:
+#define regAPG3_APG_CONTROL                                                                             0x38ac

WARNING: line length of 105 exceeds 100 columns
#11990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11966:
+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#11991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11967:
+#define regAPG3_APG_CONTROL2                                                                            0x38ad

WARNING: line length of 105 exceeds 100 columns
#11992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11968:
+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2

WARNING: line length of 110 exceeds 100 columns
#11993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11969:
+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae

WARNING: line length of 105 exceeds 100 columns
#11994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11970:
+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2

WARNING: line length of 110 exceeds 100 columns
#11995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11971:
+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af

WARNING: line length of 105 exceeds 100 columns
#11996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11972:
+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#11997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11973:
+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6

WARNING: line length of 105 exceeds 100 columns
#11998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11974:
+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#11999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11975:
+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7

WARNING: line length of 105 exceeds 100 columns
#12000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11976:
+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2

WARNING: line length of 110 exceeds 100 columns
#12001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11977:
+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8

WARNING: line length of 105 exceeds 100 columns
#12002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11978:
+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2

WARNING: line length of 110 exceeds 100 columns
#12003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11979:
+#define regAPG3_APG_STATUS                                                                              0x38bd

WARNING: line length of 105 exceeds 100 columns
#12004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11980:
+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#12005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11981:
+#define regAPG3_APG_STATUS2                                                                             0x38be

WARNING: line length of 105 exceeds 100 columns
#12006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11982:
+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#12007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11983:
+#define regAPG3_APG_MEM_PWR                                                                             0x38c0

WARNING: line length of 105 exceeds 100 columns
#12008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11984:
+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#12009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11985:
+#define regAPG3_APG_SPARE                                                                               0x38c2

WARNING: line length of 105 exceeds 100 columns
#12010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11986:
+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2

WARNING: line length of 110 exceeds 100 columns
#12015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11991:
+#define regDME9_DME_CONTROL                                                                             0x38ca

WARNING: line length of 105 exceeds 100 columns
#12016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11992:
+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#12017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11993:
+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb

WARNING: line length of 105 exceeds 100 columns
#12018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11994:
+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#12023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:11999:
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd

WARNING: line length of 105 exceeds 100 columns
#12024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12000:
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12001:
+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce

WARNING: line length of 105 exceeds 100 columns
#12026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12002:
+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#12027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12003:
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf

WARNING: line length of 105 exceeds 100 columns
#12028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12004:
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2

WARNING: line length of 110 exceeds 100 columns
#12029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12005:
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0

WARNING: line length of 105 exceeds 100 columns
#12030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12006:
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#12031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12007:
+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1

WARNING: line length of 105 exceeds 100 columns
#12032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12008:
+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#12033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12009:
+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2

WARNING: line length of 105 exceeds 100 columns
#12034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12010:
+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2

WARNING: line length of 110 exceeds 100 columns
#12035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12011:
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3

WARNING: line length of 105 exceeds 100 columns
#12036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12012:
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2

WARNING: line length of 110 exceeds 100 columns
#12037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12013:
+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4

WARNING: line length of 105 exceeds 100 columns
#12038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12014:
+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2

WARNING: line length of 110 exceeds 100 columns
#12039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12015:
+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5

WARNING: line length of 105 exceeds 100 columns
#12040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12016:
+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#12041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12017:
+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6

WARNING: line length of 105 exceeds 100 columns
#12042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12018:
+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2

WARNING: line length of 110 exceeds 100 columns
#12047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12023:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9

WARNING: line length of 105 exceeds 100 columns
#12048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12024:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#12049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12025:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da

WARNING: line length of 105 exceeds 100 columns
#12050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12026:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12027:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db

WARNING: line length of 105 exceeds 100 columns
#12052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12028:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2

WARNING: line length of 110 exceeds 100 columns
#12053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12029:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc

WARNING: line length of 105 exceeds 100 columns
#12054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12030:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2

WARNING: line length of 110 exceeds 100 columns
#12055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12031:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd

WARNING: line length of 105 exceeds 100 columns
#12056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12032:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12033:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de

WARNING: line length of 105 exceeds 100 columns
#12058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12034:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12035:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df

WARNING: line length of 105 exceeds 100 columns
#12060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12036:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12037:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0

WARNING: line length of 105 exceeds 100 columns
#12062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12038:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12039:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1

WARNING: line length of 105 exceeds 100 columns
#12064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12040:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12041:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2

WARNING: line length of 105 exceeds 100 columns
#12066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12042:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12043:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3

WARNING: line length of 105 exceeds 100 columns
#12068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12044:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12045:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4

WARNING: line length of 105 exceeds 100 columns
#12070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12046:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12047:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5

WARNING: line length of 105 exceeds 100 columns
#12072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12048:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12049:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6

WARNING: line length of 105 exceeds 100 columns
#12074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12050:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2

WARNING: line length of 110 exceeds 100 columns
#12075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12051:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7

WARNING: line length of 105 exceeds 100 columns
#12076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12052:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#12077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12053:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8

WARNING: line length of 105 exceeds 100 columns
#12078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12054:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12055:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9

WARNING: line length of 105 exceeds 100 columns
#12080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12056:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12057:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea

WARNING: line length of 105 exceeds 100 columns
#12082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12058:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12059:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb

WARNING: line length of 105 exceeds 100 columns
#12084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12060:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12061:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec

WARNING: line length of 105 exceeds 100 columns
#12086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12062:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12063:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed

WARNING: line length of 105 exceeds 100 columns
#12088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12064:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12065:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee

WARNING: line length of 105 exceeds 100 columns
#12090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12066:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12067:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef

WARNING: line length of 105 exceeds 100 columns
#12092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12068:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12069:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0

WARNING: line length of 105 exceeds 100 columns
#12094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12070:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12071:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1

WARNING: line length of 105 exceeds 100 columns
#12096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12072:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12073:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2

WARNING: line length of 105 exceeds 100 columns
#12098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12074:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#12099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12075:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3

WARNING: line length of 105 exceeds 100 columns
#12100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12076:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#12101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12077:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4

WARNING: line length of 105 exceeds 100 columns
#12102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12078:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#12103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12079:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5

WARNING: line length of 105 exceeds 100 columns
#12104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12080:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#12105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12081:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6

WARNING: line length of 105 exceeds 100 columns
#12106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12082:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#12107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12083:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7

WARNING: line length of 105 exceeds 100 columns
#12108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12084:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2

WARNING: line length of 110 exceeds 100 columns
#12109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12085:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8

WARNING: line length of 105 exceeds 100 columns
#12110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12086:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#12111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12087:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9

WARNING: line length of 105 exceeds 100 columns
#12112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12088:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#12113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12089:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa

WARNING: line length of 105 exceeds 100 columns
#12114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12090:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2

WARNING: line length of 110 exceeds 100 columns
#12115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12091:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff

WARNING: line length of 105 exceeds 100 columns
#12116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12092:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#12117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12093:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900

WARNING: line length of 105 exceeds 100 columns
#12118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12094:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2

WARNING: line length of 110 exceeds 100 columns
#12119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12095:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901

WARNING: line length of 105 exceeds 100 columns
#12120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12096:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2

WARNING: line length of 110 exceeds 100 columns
#12121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12097:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902

WARNING: line length of 105 exceeds 100 columns
#12122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12098:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2

WARNING: line length of 110 exceeds 100 columns
#12123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12099:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903

WARNING: line length of 105 exceeds 100 columns
#12124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12100:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#12125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12101:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904

WARNING: line length of 105 exceeds 100 columns
#12126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12102:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#12127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12103:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905

WARNING: line length of 105 exceeds 100 columns
#12128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12104:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2

WARNING: line length of 110 exceeds 100 columns
#12129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12105:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906

WARNING: line length of 105 exceeds 100 columns
#12130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12106:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2

WARNING: line length of 110 exceeds 100 columns
#12131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12107:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3907

WARNING: line length of 105 exceeds 100 columns
#12132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12108:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2

WARNING: line length of 110 exceeds 100 columns
#12133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12109:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3908

WARNING: line length of 105 exceeds 100 columns
#12134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12110:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2

WARNING: line length of 110 exceeds 100 columns
#12135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12111:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3909

WARNING: line length of 105 exceeds 100 columns
#12136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12112:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2

WARNING: line length of 110 exceeds 100 columns
#12137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12113:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x390a

WARNING: line length of 105 exceeds 100 columns
#12138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12114:
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2

WARNING: line length of 110 exceeds 100 columns
#12143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12119:
+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000

WARNING: line length of 105 exceeds 100 columns
#12144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12120:
+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12121:
+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001

WARNING: line length of 105 exceeds 100 columns
#12146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12122:
+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12123:
+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002

WARNING: line length of 105 exceeds 100 columns
#12148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12124:
+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12125:
+#define regMPCC0_MPCC_CONTROL                                                                           0x0003

WARNING: line length of 105 exceeds 100 columns
#12150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12126:
+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12127:
+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004

WARNING: line length of 105 exceeds 100 columns
#12152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12128:
+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#12153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12129:
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005

WARNING: line length of 105 exceeds 100 columns
#12154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12130:
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12131:
+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006

WARNING: line length of 105 exceeds 100 columns
#12156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12132:
+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#12157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12133:
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007

WARNING: line length of 105 exceeds 100 columns
#12158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12134:
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12135:
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008

WARNING: line length of 105 exceeds 100 columns
#12160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12136:
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#12161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12137:
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009

WARNING: line length of 105 exceeds 100 columns
#12162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12138:
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12139:
+#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a

WARNING: line length of 105 exceeds 100 columns
#12164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12140:
+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12141:
+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b

WARNING: line length of 105 exceeds 100 columns
#12166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12142:
+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12143:
+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c

WARNING: line length of 105 exceeds 100 columns
#12168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12144:
+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12145:
+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d

WARNING: line length of 105 exceeds 100 columns
#12170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12146:
+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#12171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12147:
+#define regMPCC0_MPCC_STATUS                                                                            0x000e

WARNING: line length of 105 exceeds 100 columns
#12172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12148:
+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12153:
+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015

WARNING: line length of 105 exceeds 100 columns
#12178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12154:
+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12155:
+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016

WARNING: line length of 105 exceeds 100 columns
#12180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12156:
+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12157:
+#define regMPCC1_MPCC_OPP_ID                                                                            0x0017

WARNING: line length of 105 exceeds 100 columns
#12182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12158:
+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12159:
+#define regMPCC1_MPCC_CONTROL                                                                           0x0018

WARNING: line length of 105 exceeds 100 columns
#12184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12160:
+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12161:
+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019

WARNING: line length of 105 exceeds 100 columns
#12186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12162:
+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#12187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12163:
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a

WARNING: line length of 105 exceeds 100 columns
#12188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12164:
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12165:
+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b

WARNING: line length of 105 exceeds 100 columns
#12190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12166:
+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#12191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12167:
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c

WARNING: line length of 105 exceeds 100 columns
#12192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12168:
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12169:
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d

WARNING: line length of 105 exceeds 100 columns
#12194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12170:
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#12195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12171:
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e

WARNING: line length of 105 exceeds 100 columns
#12196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12172:
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12173:
+#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f

WARNING: line length of 105 exceeds 100 columns
#12198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12174:
+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12175:
+#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020

WARNING: line length of 105 exceeds 100 columns
#12200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12176:
+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12177:
+#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021

WARNING: line length of 105 exceeds 100 columns
#12202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12178:
+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12179:
+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022

WARNING: line length of 105 exceeds 100 columns
#12204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12180:
+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#12205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12181:
+#define regMPCC1_MPCC_STATUS                                                                            0x0023

WARNING: line length of 105 exceeds 100 columns
#12206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12182:
+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12187:
+#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a

WARNING: line length of 105 exceeds 100 columns
#12212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12188:
+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12189:
+#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b

WARNING: line length of 105 exceeds 100 columns
#12214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12190:
+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12191:
+#define regMPCC2_MPCC_OPP_ID                                                                            0x002c

WARNING: line length of 105 exceeds 100 columns
#12216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12192:
+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12193:
+#define regMPCC2_MPCC_CONTROL                                                                           0x002d

WARNING: line length of 105 exceeds 100 columns
#12218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12194:
+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12195:
+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e

WARNING: line length of 105 exceeds 100 columns
#12220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12196:
+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#12221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12197:
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f

WARNING: line length of 105 exceeds 100 columns
#12222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12198:
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12199:
+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030

WARNING: line length of 105 exceeds 100 columns
#12224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12200:
+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#12225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12201:
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031

WARNING: line length of 105 exceeds 100 columns
#12226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12202:
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12203:
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032

WARNING: line length of 105 exceeds 100 columns
#12228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12204:
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#12229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12205:
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033

WARNING: line length of 105 exceeds 100 columns
#12230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12206:
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12207:
+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034

WARNING: line length of 105 exceeds 100 columns
#12232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12208:
+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12209:
+#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035

WARNING: line length of 105 exceeds 100 columns
#12234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12210:
+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12211:
+#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036

WARNING: line length of 105 exceeds 100 columns
#12236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12212:
+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12213:
+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037

WARNING: line length of 105 exceeds 100 columns
#12238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12214:
+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#12239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12215:
+#define regMPCC2_MPCC_STATUS                                                                            0x0038

WARNING: line length of 105 exceeds 100 columns
#12240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12216:
+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12221:
+#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f

WARNING: line length of 105 exceeds 100 columns
#12246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12222:
+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12223:
+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040

WARNING: line length of 105 exceeds 100 columns
#12248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12224:
+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12225:
+#define regMPCC3_MPCC_OPP_ID                                                                            0x0041

WARNING: line length of 105 exceeds 100 columns
#12250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12226:
+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12227:
+#define regMPCC3_MPCC_CONTROL                                                                           0x0042

WARNING: line length of 105 exceeds 100 columns
#12252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12228:
+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12229:
+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043

WARNING: line length of 105 exceeds 100 columns
#12254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12230:
+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#12255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12231:
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044

WARNING: line length of 105 exceeds 100 columns
#12256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12232:
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12233:
+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045

WARNING: line length of 105 exceeds 100 columns
#12258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12234:
+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#12259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12235:
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046

WARNING: line length of 105 exceeds 100 columns
#12260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12236:
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#12261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12237:
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047

WARNING: line length of 105 exceeds 100 columns
#12262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12238:
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#12263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12239:
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048

WARNING: line length of 105 exceeds 100 columns
#12264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12240:
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12241:
+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049

WARNING: line length of 105 exceeds 100 columns
#12266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12242:
+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12243:
+#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a

WARNING: line length of 105 exceeds 100 columns
#12268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12244:
+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12245:
+#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b

WARNING: line length of 105 exceeds 100 columns
#12270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12246:
+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#12271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12247:
+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c

WARNING: line length of 105 exceeds 100 columns
#12272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12248:
+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#12273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12249:
+#define regMPCC3_MPCC_STATUS                                                                            0x004d

WARNING: line length of 105 exceeds 100 columns
#12274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12250:
+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#12280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12256:
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8

WARNING: line length of 105 exceeds 100 columns
#12281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12257:
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#12282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12258:
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9

WARNING: line length of 105 exceeds 100 columns
#12283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12259:
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#12284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12260:
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa

WARNING: line length of 105 exceeds 100 columns
#12285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12261:
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#12286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12262:
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab

WARNING: line length of 105 exceeds 100 columns
#12287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12263:
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12264:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac

WARNING: line length of 105 exceeds 100 columns
#12289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12265:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12266:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad

WARNING: line length of 105 exceeds 100 columns
#12291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12267:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12268:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae

WARNING: line length of 105 exceeds 100 columns
#12293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12269:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12270:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af

WARNING: line length of 105 exceeds 100 columns
#12295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12271:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12272:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0

WARNING: line length of 105 exceeds 100 columns
#12297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12273:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12274:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1

WARNING: line length of 105 exceeds 100 columns
#12299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12275:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12276:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2

WARNING: line length of 105 exceeds 100 columns
#12301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12277:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12278:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3

WARNING: line length of 105 exceeds 100 columns
#12303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12279:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12280:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4

WARNING: line length of 105 exceeds 100 columns
#12305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12281:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12282:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5

WARNING: line length of 105 exceeds 100 columns
#12307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12283:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12284:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6

WARNING: line length of 105 exceeds 100 columns
#12309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12285:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12286:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7

WARNING: line length of 105 exceeds 100 columns
#12311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12287:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12288:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8

WARNING: line length of 105 exceeds 100 columns
#12313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12289:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12290:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9

WARNING: line length of 105 exceeds 100 columns
#12315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12291:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12292:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba

WARNING: line length of 105 exceeds 100 columns
#12317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12293:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12294:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb

WARNING: line length of 105 exceeds 100 columns
#12319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12295:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12296:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc

WARNING: line length of 105 exceeds 100 columns
#12321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12297:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12298:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd

WARNING: line length of 105 exceeds 100 columns
#12323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12299:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12300:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be

WARNING: line length of 105 exceeds 100 columns
#12325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12301:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12302:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf

WARNING: line length of 105 exceeds 100 columns
#12327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12303:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12304:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0

WARNING: line length of 105 exceeds 100 columns
#12329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12305:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12306:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1

WARNING: line length of 105 exceeds 100 columns
#12331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12307:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12308:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2

WARNING: line length of 105 exceeds 100 columns
#12333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12309:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12310:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3

WARNING: line length of 105 exceeds 100 columns
#12335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12311:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12312:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4

WARNING: line length of 105 exceeds 100 columns
#12337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12313:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12314:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5

WARNING: line length of 105 exceeds 100 columns
#12339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12315:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12316:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6

WARNING: line length of 105 exceeds 100 columns
#12341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12317:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12318:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7

WARNING: line length of 105 exceeds 100 columns
#12343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12319:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12320:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8

WARNING: line length of 105 exceeds 100 columns
#12345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12321:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12322:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9

WARNING: line length of 105 exceeds 100 columns
#12347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12323:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12324:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca

WARNING: line length of 105 exceeds 100 columns
#12349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12325:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12326:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb

WARNING: line length of 105 exceeds 100 columns
#12351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12327:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12328:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc

WARNING: line length of 105 exceeds 100 columns
#12353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12329:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12330:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd

WARNING: line length of 105 exceeds 100 columns
#12355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12331:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12332:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce

WARNING: line length of 105 exceeds 100 columns
#12357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12333:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12334:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf

WARNING: line length of 105 exceeds 100 columns
#12359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12335:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12336:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0

WARNING: line length of 105 exceeds 100 columns
#12361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12337:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12338:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1

WARNING: line length of 105 exceeds 100 columns
#12363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12339:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12340:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2

WARNING: line length of 105 exceeds 100 columns
#12365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12341:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12342:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3

WARNING: line length of 105 exceeds 100 columns
#12367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12343:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12344:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4

WARNING: line length of 105 exceeds 100 columns
#12369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12345:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12346:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5

WARNING: line length of 105 exceeds 100 columns
#12371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12347:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12348:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6

WARNING: line length of 105 exceeds 100 columns
#12373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12349:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12350:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7

WARNING: line length of 105 exceeds 100 columns
#12375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12351:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12352:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8

WARNING: line length of 105 exceeds 100 columns
#12377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12353:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12354:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9

WARNING: line length of 105 exceeds 100 columns
#12379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12355:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12356:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da

WARNING: line length of 105 exceeds 100 columns
#12381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12357:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12358:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db

WARNING: line length of 105 exceeds 100 columns
#12383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12359:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12360:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc

WARNING: line length of 105 exceeds 100 columns
#12385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12361:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12362:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd

WARNING: line length of 105 exceeds 100 columns
#12387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12363:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12364:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de

WARNING: line length of 105 exceeds 100 columns
#12389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12365:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12366:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df

WARNING: line length of 105 exceeds 100 columns
#12391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12367:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12368:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0

WARNING: line length of 105 exceeds 100 columns
#12393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12369:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12370:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1

WARNING: line length of 105 exceeds 100 columns
#12395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12371:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12372:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2

WARNING: line length of 105 exceeds 100 columns
#12397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12373:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12374:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3

WARNING: line length of 105 exceeds 100 columns
#12399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12375:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12376:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4

WARNING: line length of 105 exceeds 100 columns
#12401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12377:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12378:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5

WARNING: line length of 105 exceeds 100 columns
#12403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12379:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12380:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6

WARNING: line length of 105 exceeds 100 columns
#12405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12381:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12382:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7

WARNING: line length of 105 exceeds 100 columns
#12407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12383:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12384:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8

WARNING: line length of 105 exceeds 100 columns
#12409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12385:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12386:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9

WARNING: line length of 105 exceeds 100 columns
#12411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12387:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12388:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea

WARNING: line length of 105 exceeds 100 columns
#12413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12389:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12390:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb

WARNING: line length of 105 exceeds 100 columns
#12415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12391:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12392:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec

WARNING: line length of 105 exceeds 100 columns
#12417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12393:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12394:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed

WARNING: line length of 105 exceeds 100 columns
#12419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12395:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12396:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee

WARNING: line length of 105 exceeds 100 columns
#12421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12397:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12398:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef

WARNING: line length of 105 exceeds 100 columns
#12423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12399:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12400:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0

WARNING: line length of 105 exceeds 100 columns
#12425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12401:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12402:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1

WARNING: line length of 105 exceeds 100 columns
#12427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12403:
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12404:
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2

WARNING: line length of 105 exceeds 100 columns
#12429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12405:
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3

WARNING: line length of 110 exceeds 100 columns
#12430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12406:
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3

WARNING: line length of 105 exceeds 100 columns
#12431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12407:
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12408:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4

WARNING: line length of 105 exceeds 100 columns
#12433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12409:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12410:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5

WARNING: line length of 105 exceeds 100 columns
#12435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12411:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12412:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6

WARNING: line length of 105 exceeds 100 columns
#12437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12413:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12414:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7

WARNING: line length of 105 exceeds 100 columns
#12439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12415:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12416:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8

WARNING: line length of 105 exceeds 100 columns
#12441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12417:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12418:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9

WARNING: line length of 105 exceeds 100 columns
#12443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12419:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12420:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa

WARNING: line length of 105 exceeds 100 columns
#12445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12421:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12422:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb

WARNING: line length of 105 exceeds 100 columns
#12447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12423:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12424:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc

WARNING: line length of 105 exceeds 100 columns
#12449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12425:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12426:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd

WARNING: line length of 105 exceeds 100 columns
#12451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12427:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12428:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe

WARNING: line length of 105 exceeds 100 columns
#12453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12429:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12430:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff

WARNING: line length of 105 exceeds 100 columns
#12455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12431:
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12436:
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106

WARNING: line length of 105 exceeds 100 columns
#12461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12437:
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#12462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12438:
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107

WARNING: line length of 105 exceeds 100 columns
#12463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12439:
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#12464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12440:
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108

WARNING: line length of 105 exceeds 100 columns
#12465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12441:
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#12466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12442:
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109

WARNING: line length of 105 exceeds 100 columns
#12467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12443:
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12444:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a

WARNING: line length of 105 exceeds 100 columns
#12469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12445:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12446:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b

WARNING: line length of 105 exceeds 100 columns
#12471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12447:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12448:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c

WARNING: line length of 105 exceeds 100 columns
#12473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12449:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12450:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d

WARNING: line length of 105 exceeds 100 columns
#12475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12451:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12452:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e

WARNING: line length of 105 exceeds 100 columns
#12477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12453:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12454:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f

WARNING: line length of 105 exceeds 100 columns
#12479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12455:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12456:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110

WARNING: line length of 105 exceeds 100 columns
#12481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12457:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12458:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111

WARNING: line length of 105 exceeds 100 columns
#12483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12459:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12460:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112

WARNING: line length of 105 exceeds 100 columns
#12485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12461:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12462:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113

WARNING: line length of 105 exceeds 100 columns
#12487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12463:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12464:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114

WARNING: line length of 105 exceeds 100 columns
#12489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12465:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12466:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115

WARNING: line length of 105 exceeds 100 columns
#12491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12467:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12468:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116

WARNING: line length of 105 exceeds 100 columns
#12493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12469:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12470:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117

WARNING: line length of 105 exceeds 100 columns
#12495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12471:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12472:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118

WARNING: line length of 105 exceeds 100 columns
#12497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12473:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12474:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119

WARNING: line length of 105 exceeds 100 columns
#12499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12475:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12476:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a

WARNING: line length of 105 exceeds 100 columns
#12501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12477:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12478:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b

WARNING: line length of 105 exceeds 100 columns
#12503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12479:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12480:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c

WARNING: line length of 105 exceeds 100 columns
#12505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12481:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12482:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d

WARNING: line length of 105 exceeds 100 columns
#12507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12483:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12484:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e

WARNING: line length of 105 exceeds 100 columns
#12509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12485:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12486:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f

WARNING: line length of 105 exceeds 100 columns
#12511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12487:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12488:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120

WARNING: line length of 105 exceeds 100 columns
#12513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12489:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12490:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121

WARNING: line length of 105 exceeds 100 columns
#12515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12491:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12492:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122

WARNING: line length of 105 exceeds 100 columns
#12517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12493:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12494:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123

WARNING: line length of 105 exceeds 100 columns
#12519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12495:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12496:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124

WARNING: line length of 105 exceeds 100 columns
#12521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12497:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12498:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125

WARNING: line length of 105 exceeds 100 columns
#12523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12499:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12500:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126

WARNING: line length of 105 exceeds 100 columns
#12525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12501:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12502:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127

WARNING: line length of 105 exceeds 100 columns
#12527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12503:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12504:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128

WARNING: line length of 105 exceeds 100 columns
#12529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12505:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12506:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129

WARNING: line length of 105 exceeds 100 columns
#12531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12507:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12508:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a

WARNING: line length of 105 exceeds 100 columns
#12533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12509:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12510:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b

WARNING: line length of 105 exceeds 100 columns
#12535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12511:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12512:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c

WARNING: line length of 105 exceeds 100 columns
#12537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12513:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12514:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d

WARNING: line length of 105 exceeds 100 columns
#12539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12515:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12516:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e

WARNING: line length of 105 exceeds 100 columns
#12541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12517:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12518:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f

WARNING: line length of 105 exceeds 100 columns
#12543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12519:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12520:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130

WARNING: line length of 105 exceeds 100 columns
#12545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12521:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12522:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131

WARNING: line length of 105 exceeds 100 columns
#12547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12523:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12524:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132

WARNING: line length of 105 exceeds 100 columns
#12549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12525:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12526:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133

WARNING: line length of 105 exceeds 100 columns
#12551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12527:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12528:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134

WARNING: line length of 105 exceeds 100 columns
#12553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12529:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12530:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135

WARNING: line length of 105 exceeds 100 columns
#12555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12531:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12532:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136

WARNING: line length of 105 exceeds 100 columns
#12557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12533:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12534:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137

WARNING: line length of 105 exceeds 100 columns
#12559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12535:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12536:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138

WARNING: line length of 105 exceeds 100 columns
#12561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12537:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12538:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139

WARNING: line length of 105 exceeds 100 columns
#12563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12539:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12540:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a

WARNING: line length of 105 exceeds 100 columns
#12565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12541:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12542:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b

WARNING: line length of 105 exceeds 100 columns
#12567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12543:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12544:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c

WARNING: line length of 105 exceeds 100 columns
#12569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12545:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12546:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d

WARNING: line length of 105 exceeds 100 columns
#12571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12547:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12548:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e

WARNING: line length of 105 exceeds 100 columns
#12573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12549:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12550:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f

WARNING: line length of 105 exceeds 100 columns
#12575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12551:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12552:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140

WARNING: line length of 105 exceeds 100 columns
#12577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12553:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12554:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141

WARNING: line length of 105 exceeds 100 columns
#12579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12555:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12556:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142

WARNING: line length of 105 exceeds 100 columns
#12581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12557:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12558:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143

WARNING: line length of 105 exceeds 100 columns
#12583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12559:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12560:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144

WARNING: line length of 105 exceeds 100 columns
#12585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12561:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12562:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145

WARNING: line length of 105 exceeds 100 columns
#12587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12563:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12564:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146

WARNING: line length of 105 exceeds 100 columns
#12589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12565:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12566:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147

WARNING: line length of 105 exceeds 100 columns
#12591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12567:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12568:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148

WARNING: line length of 105 exceeds 100 columns
#12593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12569:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12570:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149

WARNING: line length of 105 exceeds 100 columns
#12595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12571:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12572:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a

WARNING: line length of 105 exceeds 100 columns
#12597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12573:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12574:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b

WARNING: line length of 105 exceeds 100 columns
#12599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12575:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12576:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c

WARNING: line length of 105 exceeds 100 columns
#12601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12577:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12578:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d

WARNING: line length of 105 exceeds 100 columns
#12603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12579:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12580:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e

WARNING: line length of 105 exceeds 100 columns
#12605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12581:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12582:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f

WARNING: line length of 105 exceeds 100 columns
#12607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12583:
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12584:
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150

WARNING: line length of 105 exceeds 100 columns
#12609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12585:
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3

WARNING: line length of 110 exceeds 100 columns
#12610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12586:
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151

WARNING: line length of 105 exceeds 100 columns
#12611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12587:
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12588:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152

WARNING: line length of 105 exceeds 100 columns
#12613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12589:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12590:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153

WARNING: line length of 105 exceeds 100 columns
#12615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12591:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12592:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154

WARNING: line length of 105 exceeds 100 columns
#12617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12593:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12594:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155

WARNING: line length of 105 exceeds 100 columns
#12619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12595:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12596:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156

WARNING: line length of 105 exceeds 100 columns
#12621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12597:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12598:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157

WARNING: line length of 105 exceeds 100 columns
#12623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12599:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12600:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158

WARNING: line length of 105 exceeds 100 columns
#12625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12601:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12602:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159

WARNING: line length of 105 exceeds 100 columns
#12627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12603:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12604:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a

WARNING: line length of 105 exceeds 100 columns
#12629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12605:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12606:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b

WARNING: line length of 105 exceeds 100 columns
#12631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12607:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12608:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c

WARNING: line length of 105 exceeds 100 columns
#12633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12609:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12610:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d

WARNING: line length of 105 exceeds 100 columns
#12635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12611:
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12616:
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164

WARNING: line length of 105 exceeds 100 columns
#12641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12617:
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#12642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12618:
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165

WARNING: line length of 105 exceeds 100 columns
#12643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12619:
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#12644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12620:
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166

WARNING: line length of 105 exceeds 100 columns
#12645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12621:
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#12646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12622:
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167

WARNING: line length of 105 exceeds 100 columns
#12647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12623:
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12624:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168

WARNING: line length of 105 exceeds 100 columns
#12649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12625:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12626:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169

WARNING: line length of 105 exceeds 100 columns
#12651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12627:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12628:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a

WARNING: line length of 105 exceeds 100 columns
#12653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12629:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12630:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b

WARNING: line length of 105 exceeds 100 columns
#12655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12631:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12632:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c

WARNING: line length of 105 exceeds 100 columns
#12657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12633:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12634:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d

WARNING: line length of 105 exceeds 100 columns
#12659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12635:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12636:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e

WARNING: line length of 105 exceeds 100 columns
#12661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12637:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12638:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f

WARNING: line length of 105 exceeds 100 columns
#12663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12639:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12640:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170

WARNING: line length of 105 exceeds 100 columns
#12665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12641:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12642:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171

WARNING: line length of 105 exceeds 100 columns
#12667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12643:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12644:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172

WARNING: line length of 105 exceeds 100 columns
#12669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12645:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12646:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173

WARNING: line length of 105 exceeds 100 columns
#12671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12647:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12648:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174

WARNING: line length of 105 exceeds 100 columns
#12673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12649:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12650:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175

WARNING: line length of 105 exceeds 100 columns
#12675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12651:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12652:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176

WARNING: line length of 105 exceeds 100 columns
#12677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12653:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12654:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177

WARNING: line length of 105 exceeds 100 columns
#12679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12655:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12656:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178

WARNING: line length of 105 exceeds 100 columns
#12681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12657:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12658:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179

WARNING: line length of 105 exceeds 100 columns
#12683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12659:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12660:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a

WARNING: line length of 105 exceeds 100 columns
#12685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12661:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12662:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b

WARNING: line length of 105 exceeds 100 columns
#12687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12663:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12664:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c

WARNING: line length of 105 exceeds 100 columns
#12689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12665:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12666:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d

WARNING: line length of 105 exceeds 100 columns
#12691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12667:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12668:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e

WARNING: line length of 105 exceeds 100 columns
#12693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12669:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12670:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f

WARNING: line length of 105 exceeds 100 columns
#12695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12671:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12672:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180

WARNING: line length of 105 exceeds 100 columns
#12697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12673:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12674:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181

WARNING: line length of 105 exceeds 100 columns
#12699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12675:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12676:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182

WARNING: line length of 105 exceeds 100 columns
#12701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12677:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12678:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183

WARNING: line length of 105 exceeds 100 columns
#12703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12679:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12680:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184

WARNING: line length of 105 exceeds 100 columns
#12705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12681:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12682:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185

WARNING: line length of 105 exceeds 100 columns
#12707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12683:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12684:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186

WARNING: line length of 105 exceeds 100 columns
#12709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12685:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12686:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187

WARNING: line length of 105 exceeds 100 columns
#12711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12687:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12688:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188

WARNING: line length of 105 exceeds 100 columns
#12713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12689:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12690:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189

WARNING: line length of 105 exceeds 100 columns
#12715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12691:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12692:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a

WARNING: line length of 105 exceeds 100 columns
#12717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12693:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12694:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b

WARNING: line length of 105 exceeds 100 columns
#12719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12695:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12696:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c

WARNING: line length of 105 exceeds 100 columns
#12721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12697:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12698:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d

WARNING: line length of 105 exceeds 100 columns
#12723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12699:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12700:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e

WARNING: line length of 105 exceeds 100 columns
#12725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12701:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12702:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f

WARNING: line length of 105 exceeds 100 columns
#12727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12703:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12704:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190

WARNING: line length of 105 exceeds 100 columns
#12729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12705:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12706:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191

WARNING: line length of 105 exceeds 100 columns
#12731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12707:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12708:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192

WARNING: line length of 105 exceeds 100 columns
#12733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12709:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12710:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193

WARNING: line length of 105 exceeds 100 columns
#12735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12711:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12712:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194

WARNING: line length of 105 exceeds 100 columns
#12737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12713:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12714:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195

WARNING: line length of 105 exceeds 100 columns
#12739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12715:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12716:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196

WARNING: line length of 105 exceeds 100 columns
#12741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12717:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12718:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197

WARNING: line length of 105 exceeds 100 columns
#12743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12719:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12720:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198

WARNING: line length of 105 exceeds 100 columns
#12745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12721:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12722:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199

WARNING: line length of 105 exceeds 100 columns
#12747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12723:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12724:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a

WARNING: line length of 105 exceeds 100 columns
#12749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12725:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12726:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b

WARNING: line length of 105 exceeds 100 columns
#12751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12727:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12728:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c

WARNING: line length of 105 exceeds 100 columns
#12753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12729:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12730:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d

WARNING: line length of 105 exceeds 100 columns
#12755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12731:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12732:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e

WARNING: line length of 105 exceeds 100 columns
#12757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12733:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12734:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f

WARNING: line length of 105 exceeds 100 columns
#12759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12735:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12736:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0

WARNING: line length of 105 exceeds 100 columns
#12761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12737:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12738:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1

WARNING: line length of 105 exceeds 100 columns
#12763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12739:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12740:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2

WARNING: line length of 105 exceeds 100 columns
#12765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12741:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12742:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3

WARNING: line length of 105 exceeds 100 columns
#12767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12743:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12744:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4

WARNING: line length of 105 exceeds 100 columns
#12769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12745:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12746:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5

WARNING: line length of 105 exceeds 100 columns
#12771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12747:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12748:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6

WARNING: line length of 105 exceeds 100 columns
#12773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12749:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12750:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7

WARNING: line length of 105 exceeds 100 columns
#12775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12751:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12752:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8

WARNING: line length of 105 exceeds 100 columns
#12777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12753:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12754:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9

WARNING: line length of 105 exceeds 100 columns
#12779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12755:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12756:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa

WARNING: line length of 105 exceeds 100 columns
#12781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12757:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12758:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab

WARNING: line length of 105 exceeds 100 columns
#12783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12759:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12760:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac

WARNING: line length of 105 exceeds 100 columns
#12785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12761:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12762:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad

WARNING: line length of 105 exceeds 100 columns
#12787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12763:
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12764:
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae

WARNING: line length of 105 exceeds 100 columns
#12789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12765:
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3

WARNING: line length of 110 exceeds 100 columns
#12790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12766:
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af

WARNING: line length of 105 exceeds 100 columns
#12791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12767:
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12768:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0

WARNING: line length of 105 exceeds 100 columns
#12793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12769:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12770:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1

WARNING: line length of 105 exceeds 100 columns
#12795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12771:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12772:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2

WARNING: line length of 105 exceeds 100 columns
#12797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12773:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12774:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3

WARNING: line length of 105 exceeds 100 columns
#12799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12775:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12776:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4

WARNING: line length of 105 exceeds 100 columns
#12801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12777:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12778:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5

WARNING: line length of 105 exceeds 100 columns
#12803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12779:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12780:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6

WARNING: line length of 105 exceeds 100 columns
#12805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12781:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12782:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7

WARNING: line length of 105 exceeds 100 columns
#12807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12783:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12784:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8

WARNING: line length of 105 exceeds 100 columns
#12809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12785:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12786:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9

WARNING: line length of 105 exceeds 100 columns
#12811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12787:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12788:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba

WARNING: line length of 105 exceeds 100 columns
#12813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12789:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12790:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb

WARNING: line length of 105 exceeds 100 columns
#12815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12791:
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12796:
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2

WARNING: line length of 105 exceeds 100 columns
#12821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12797:
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#12822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12798:
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3

WARNING: line length of 105 exceeds 100 columns
#12823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12799:
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#12824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12800:
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4

WARNING: line length of 105 exceeds 100 columns
#12825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12801:
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#12826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12802:
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5

WARNING: line length of 105 exceeds 100 columns
#12827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12803:
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12804:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6

WARNING: line length of 105 exceeds 100 columns
#12829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12805:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12806:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7

WARNING: line length of 105 exceeds 100 columns
#12831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12807:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12808:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8

WARNING: line length of 105 exceeds 100 columns
#12833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12809:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12810:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9

WARNING: line length of 105 exceeds 100 columns
#12835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12811:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12812:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca

WARNING: line length of 105 exceeds 100 columns
#12837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12813:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12814:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb

WARNING: line length of 105 exceeds 100 columns
#12839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12815:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12816:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc

WARNING: line length of 105 exceeds 100 columns
#12841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12817:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12818:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd

WARNING: line length of 105 exceeds 100 columns
#12843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12819:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12820:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce

WARNING: line length of 105 exceeds 100 columns
#12845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12821:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12822:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf

WARNING: line length of 105 exceeds 100 columns
#12847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12823:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12824:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0

WARNING: line length of 105 exceeds 100 columns
#12849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12825:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12826:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1

WARNING: line length of 105 exceeds 100 columns
#12851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12827:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12828:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2

WARNING: line length of 105 exceeds 100 columns
#12853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12829:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12830:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3

WARNING: line length of 105 exceeds 100 columns
#12855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12831:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12832:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4

WARNING: line length of 105 exceeds 100 columns
#12857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12833:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12834:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5

WARNING: line length of 105 exceeds 100 columns
#12859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12835:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12836:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6

WARNING: line length of 105 exceeds 100 columns
#12861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12837:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12838:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7

WARNING: line length of 105 exceeds 100 columns
#12863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12839:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12840:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8

WARNING: line length of 105 exceeds 100 columns
#12865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12841:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12842:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9

WARNING: line length of 105 exceeds 100 columns
#12867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12843:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12844:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da

WARNING: line length of 105 exceeds 100 columns
#12869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12845:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12846:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db

WARNING: line length of 105 exceeds 100 columns
#12871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12847:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12848:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc

WARNING: line length of 105 exceeds 100 columns
#12873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12849:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12850:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd

WARNING: line length of 105 exceeds 100 columns
#12875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12851:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12852:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de

WARNING: line length of 105 exceeds 100 columns
#12877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12853:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12854:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df

WARNING: line length of 105 exceeds 100 columns
#12879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12855:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12856:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0

WARNING: line length of 105 exceeds 100 columns
#12881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12857:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12858:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1

WARNING: line length of 105 exceeds 100 columns
#12883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12859:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12860:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2

WARNING: line length of 105 exceeds 100 columns
#12885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12861:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12862:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3

WARNING: line length of 105 exceeds 100 columns
#12887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12863:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12864:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4

WARNING: line length of 105 exceeds 100 columns
#12889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12865:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12866:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5

WARNING: line length of 105 exceeds 100 columns
#12891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12867:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12868:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6

WARNING: line length of 105 exceeds 100 columns
#12893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12869:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12870:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7

WARNING: line length of 105 exceeds 100 columns
#12895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12871:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12872:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8

WARNING: line length of 105 exceeds 100 columns
#12897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12873:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12874:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9

WARNING: line length of 105 exceeds 100 columns
#12899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12875:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12876:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea

WARNING: line length of 105 exceeds 100 columns
#12901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12877:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12878:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb

WARNING: line length of 105 exceeds 100 columns
#12903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12879:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12880:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec

WARNING: line length of 105 exceeds 100 columns
#12905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12881:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12882:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed

WARNING: line length of 105 exceeds 100 columns
#12907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12883:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12884:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee

WARNING: line length of 105 exceeds 100 columns
#12909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12885:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3

WARNING: line length of 110 exceeds 100 columns
#12910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12886:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef

WARNING: line length of 105 exceeds 100 columns
#12911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12887:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12888:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0

WARNING: line length of 105 exceeds 100 columns
#12913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12889:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12890:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1

WARNING: line length of 105 exceeds 100 columns
#12915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12891:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#12916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12892:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2

WARNING: line length of 105 exceeds 100 columns
#12917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12893:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12894:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3

WARNING: line length of 105 exceeds 100 columns
#12919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12895:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12896:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4

WARNING: line length of 105 exceeds 100 columns
#12921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12897:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12898:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5

WARNING: line length of 105 exceeds 100 columns
#12923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12899:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12900:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6

WARNING: line length of 105 exceeds 100 columns
#12925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12901:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12902:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7

WARNING: line length of 105 exceeds 100 columns
#12927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12903:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#12928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12904:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8

WARNING: line length of 105 exceeds 100 columns
#12929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12905:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12906:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9

WARNING: line length of 105 exceeds 100 columns
#12931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12907:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12908:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa

WARNING: line length of 105 exceeds 100 columns
#12933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12909:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#12934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12910:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb

WARNING: line length of 105 exceeds 100 columns
#12935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12911:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12912:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc

WARNING: line length of 105 exceeds 100 columns
#12937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12913:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12914:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd

WARNING: line length of 105 exceeds 100 columns
#12939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12915:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12916:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe

WARNING: line length of 105 exceeds 100 columns
#12941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12917:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12918:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff

WARNING: line length of 105 exceeds 100 columns
#12943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12919:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12920:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200

WARNING: line length of 105 exceeds 100 columns
#12945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12921:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12922:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201

WARNING: line length of 105 exceeds 100 columns
#12947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12923:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12924:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202

WARNING: line length of 105 exceeds 100 columns
#12949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12925:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12926:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203

WARNING: line length of 105 exceeds 100 columns
#12951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12927:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12928:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204

WARNING: line length of 105 exceeds 100 columns
#12953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12929:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12930:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205

WARNING: line length of 105 exceeds 100 columns
#12955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12931:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12932:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206

WARNING: line length of 105 exceeds 100 columns
#12957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12933:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12934:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207

WARNING: line length of 105 exceeds 100 columns
#12959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12935:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12936:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208

WARNING: line length of 105 exceeds 100 columns
#12961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12937:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12938:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209

WARNING: line length of 105 exceeds 100 columns
#12963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12939:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12940:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a

WARNING: line length of 105 exceeds 100 columns
#12965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12941:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12942:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b

WARNING: line length of 105 exceeds 100 columns
#12967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12943:
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#12968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12944:
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x020c

WARNING: line length of 105 exceeds 100 columns
#12969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12945:
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3

WARNING: line length of 110 exceeds 100 columns
#12970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12946:
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x020d

WARNING: line length of 105 exceeds 100 columns
#12971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12947:
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#12972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12948:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x020e

WARNING: line length of 105 exceeds 100 columns
#12973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12949:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12950:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x020f

WARNING: line length of 105 exceeds 100 columns
#12975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12951:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12952:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0210

WARNING: line length of 105 exceeds 100 columns
#12977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12953:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12954:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0211

WARNING: line length of 105 exceeds 100 columns
#12979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12955:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12956:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0212

WARNING: line length of 105 exceeds 100 columns
#12981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12957:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12958:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0213

WARNING: line length of 105 exceeds 100 columns
#12983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12959:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12960:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0214

WARNING: line length of 105 exceeds 100 columns
#12985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12961:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12962:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0215

WARNING: line length of 105 exceeds 100 columns
#12987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12963:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12964:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0216

WARNING: line length of 105 exceeds 100 columns
#12989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12965:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12966:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0217

WARNING: line length of 105 exceeds 100 columns
#12991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12967:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12968:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0218

WARNING: line length of 105 exceeds 100 columns
#12993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12969:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#12994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12970:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0219

WARNING: line length of 105 exceeds 100 columns
#12995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12971:
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12976:
+#define regMPC_CLOCK_CONTROL                                                                            0x0398

WARNING: line length of 105 exceeds 100 columns
#13001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12977:
+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12978:
+#define regMPC_SOFT_RESET                                                                               0x0399

WARNING: line length of 105 exceeds 100 columns
#13003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12979:
+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3

WARNING: line length of 110 exceeds 100 columns
#13004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12980:
+#define regMPC_CRC_CTRL                                                                                 0x039a

WARNING: line length of 105 exceeds 100 columns
#13005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12981:
+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3

WARNING: line length of 110 exceeds 100 columns
#13006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12982:
+#define regMPC_CRC_SEL_CONTROL                                                                          0x039b

WARNING: line length of 105 exceeds 100 columns
#13007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12983:
+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#13008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12984:
+#define regMPC_CRC_RESULT_AR                                                                            0x039c

WARNING: line length of 105 exceeds 100 columns
#13009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12985:
+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12986:
+#define regMPC_CRC_RESULT_GB                                                                            0x039d

WARNING: line length of 105 exceeds 100 columns
#13011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12987:
+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12988:
+#define regMPC_CRC_RESULT_C                                                                             0x039e

WARNING: line length of 105 exceeds 100 columns
#13013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12989:
+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3

WARNING: line length of 110 exceeds 100 columns
#13014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12990:
+#define regMPC_PERFMON_EVENT_CTRL                                                                       0x03a1

WARNING: line length of 105 exceeds 100 columns
#13015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12991:
+#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12992:
+#define regMPC_BYPASS_BG_AR                                                                             0x03a2

WARNING: line length of 105 exceeds 100 columns
#13017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12993:
+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3

WARNING: line length of 110 exceeds 100 columns
#13018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12994:
+#define regMPC_BYPASS_BG_GB                                                                             0x03a3

WARNING: line length of 105 exceeds 100 columns
#13019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12995:
+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3

WARNING: line length of 110 exceeds 100 columns
#13020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12996:
+#define regMPC_HOST_READ_CONTROL                                                                        0x03a4

WARNING: line length of 105 exceeds 100 columns
#13021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12997:
+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12998:
+#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5

WARNING: line length of 105 exceeds 100 columns
#13023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:12999:
+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13000:
+#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6

WARNING: line length of 105 exceeds 100 columns
#13025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13001:
+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13002:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7

WARNING: line length of 105 exceeds 100 columns
#13027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13003:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13004:
+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8

WARNING: line length of 105 exceeds 100 columns
#13029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13005:
+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13006:
+#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9

WARNING: line length of 105 exceeds 100 columns
#13031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13007:
+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13008:
+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa

WARNING: line length of 105 exceeds 100 columns
#13033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13009:
+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13010:
+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab

WARNING: line length of 105 exceeds 100 columns
#13035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13011:
+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13012:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac

WARNING: line length of 105 exceeds 100 columns
#13037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13013:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13014:
+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad

WARNING: line length of 105 exceeds 100 columns
#13039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13015:
+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13016:
+#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae

WARNING: line length of 105 exceeds 100 columns
#13041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13017:
+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13018:
+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af

WARNING: line length of 105 exceeds 100 columns
#13043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13019:
+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13020:
+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0

WARNING: line length of 105 exceeds 100 columns
#13045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13021:
+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13022:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1

WARNING: line length of 105 exceeds 100 columns
#13047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13023:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13024:
+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2

WARNING: line length of 105 exceeds 100 columns
#13049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13025:
+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13026:
+#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3

WARNING: line length of 105 exceeds 100 columns
#13051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13027:
+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13028:
+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4

WARNING: line length of 105 exceeds 100 columns
#13053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13029:
+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13030:
+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5

WARNING: line length of 105 exceeds 100 columns
#13055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13031:
+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13032:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6

WARNING: line length of 105 exceeds 100 columns
#13057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13033:
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13034:
+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7

WARNING: line length of 105 exceeds 100 columns
#13059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13035:
+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13036:
+#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8

WARNING: line length of 105 exceeds 100 columns
#13061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13037:
+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13038:
+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9

WARNING: line length of 105 exceeds 100 columns
#13063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13039:
+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13040:
+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba

WARNING: line length of 105 exceeds 100 columns
#13065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13041:
+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13042:
+#define regMPC_DWB0_MUX                                                                                 0x03c6

WARNING: line length of 105 exceeds 100 columns
#13067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13043:
+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3

WARNING: line length of 110 exceeds 100 columns
#13072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13048:
+#define regMPC_OUT0_MUX                                                                                 0x03d8

WARNING: line length of 105 exceeds 100 columns
#13073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13049:
+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3

WARNING: line length of 110 exceeds 100 columns
#13074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13050:
+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x03d9

WARNING: line length of 105 exceeds 100 columns
#13075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13051:
+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13052:
+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x03da

WARNING: line length of 105 exceeds 100 columns
#13077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13053:
+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13054:
+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x03db

WARNING: line length of 105 exceeds 100 columns
#13079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13055:
+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13056:
+#define regMPC_OUT1_MUX                                                                                 0x03dc

WARNING: line length of 105 exceeds 100 columns
#13081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13057:
+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3

WARNING: line length of 110 exceeds 100 columns
#13082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13058:
+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x03dd

WARNING: line length of 105 exceeds 100 columns
#13083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13059:
+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13060:
+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x03de

WARNING: line length of 105 exceeds 100 columns
#13085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13061:
+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13062:
+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x03df

WARNING: line length of 105 exceeds 100 columns
#13087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13063:
+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13064:
+#define regMPC_OUT2_MUX                                                                                 0x03e0

WARNING: line length of 105 exceeds 100 columns
#13089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13065:
+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3

WARNING: line length of 110 exceeds 100 columns
#13090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13066:
+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x03e1

WARNING: line length of 105 exceeds 100 columns
#13091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13067:
+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13068:
+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x03e2

WARNING: line length of 105 exceeds 100 columns
#13093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13069:
+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13070:
+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x03e3

WARNING: line length of 105 exceeds 100 columns
#13095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13071:
+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13072:
+#define regMPC_OUT3_MUX                                                                                 0x03e4

WARNING: line length of 105 exceeds 100 columns
#13097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13073:
+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3

WARNING: line length of 110 exceeds 100 columns
#13098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13074:
+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x03e5

WARNING: line length of 105 exceeds 100 columns
#13099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13075:
+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13076:
+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x03e6

WARNING: line length of 105 exceeds 100 columns
#13101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13077:
+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13078:
+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x03e7

WARNING: line length of 105 exceeds 100 columns
#13103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13079:
+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13080:
+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x03f0

WARNING: line length of 105 exceeds 100 columns
#13105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13081:
+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13082:
+#define regMPC_OUT0_CSC_MODE                                                                            0x03f1

WARNING: line length of 105 exceeds 100 columns
#13107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13083:
+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13084:
+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x03f2

WARNING: line length of 105 exceeds 100 columns
#13109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13085:
+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13086:
+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x03f3

WARNING: line length of 105 exceeds 100 columns
#13111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13087:
+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13088:
+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x03f4

WARNING: line length of 105 exceeds 100 columns
#13113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13089:
+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13090:
+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x03f5

WARNING: line length of 105 exceeds 100 columns
#13115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13091:
+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13092:
+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x03f6

WARNING: line length of 105 exceeds 100 columns
#13117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13093:
+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13094:
+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x03f7

WARNING: line length of 105 exceeds 100 columns
#13119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13095:
+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13096:
+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x03f8

WARNING: line length of 105 exceeds 100 columns
#13121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13097:
+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13098:
+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x03f9

WARNING: line length of 105 exceeds 100 columns
#13123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13099:
+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13100:
+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x03fa

WARNING: line length of 105 exceeds 100 columns
#13125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13101:
+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13102:
+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x03fb

WARNING: line length of 105 exceeds 100 columns
#13127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13103:
+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13104:
+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x03fc

WARNING: line length of 105 exceeds 100 columns
#13129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13105:
+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13106:
+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x03fd

WARNING: line length of 105 exceeds 100 columns
#13131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13107:
+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13108:
+#define regMPC_OUT1_CSC_MODE                                                                            0x03fe

WARNING: line length of 105 exceeds 100 columns
#13133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13109:
+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13110:
+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x03ff

WARNING: line length of 105 exceeds 100 columns
#13135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13111:
+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13112:
+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x0400

WARNING: line length of 105 exceeds 100 columns
#13137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13113:
+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13114:
+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x0401

WARNING: line length of 105 exceeds 100 columns
#13139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13115:
+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13116:
+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x0402

WARNING: line length of 105 exceeds 100 columns
#13141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13117:
+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13118:
+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x0403

WARNING: line length of 105 exceeds 100 columns
#13143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13119:
+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13120:
+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x0404

WARNING: line length of 105 exceeds 100 columns
#13145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13121:
+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13122:
+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x0405

WARNING: line length of 105 exceeds 100 columns
#13147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13123:
+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13124:
+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0406

WARNING: line length of 105 exceeds 100 columns
#13149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13125:
+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13126:
+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0407

WARNING: line length of 105 exceeds 100 columns
#13151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13127:
+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13128:
+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0408

WARNING: line length of 105 exceeds 100 columns
#13153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13129:
+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13130:
+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0409

WARNING: line length of 105 exceeds 100 columns
#13155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13131:
+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13132:
+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x040a

WARNING: line length of 105 exceeds 100 columns
#13157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13133:
+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13134:
+#define regMPC_OUT2_CSC_MODE                                                                            0x040b

WARNING: line length of 105 exceeds 100 columns
#13159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13135:
+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13136:
+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x040c

WARNING: line length of 105 exceeds 100 columns
#13161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13137:
+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13138:
+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x040d

WARNING: line length of 105 exceeds 100 columns
#13163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13139:
+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13140:
+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x040e

WARNING: line length of 105 exceeds 100 columns
#13165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13141:
+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13142:
+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x040f

WARNING: line length of 105 exceeds 100 columns
#13167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13143:
+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13144:
+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x0410

WARNING: line length of 105 exceeds 100 columns
#13169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13145:
+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13146:
+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x0411

WARNING: line length of 105 exceeds 100 columns
#13171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13147:
+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13148:
+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x0412

WARNING: line length of 105 exceeds 100 columns
#13173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13149:
+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13150:
+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x0413

WARNING: line length of 105 exceeds 100 columns
#13175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13151:
+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13152:
+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x0414

WARNING: line length of 105 exceeds 100 columns
#13177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13153:
+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13154:
+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x0415

WARNING: line length of 105 exceeds 100 columns
#13179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13155:
+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13156:
+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0416

WARNING: line length of 105 exceeds 100 columns
#13181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13157:
+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13158:
+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0417

WARNING: line length of 105 exceeds 100 columns
#13183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13159:
+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13160:
+#define regMPC_OUT3_CSC_MODE                                                                            0x0418

WARNING: line length of 105 exceeds 100 columns
#13185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13161:
+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13162:
+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0419

WARNING: line length of 105 exceeds 100 columns
#13187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13163:
+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13164:
+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x041a

WARNING: line length of 105 exceeds 100 columns
#13189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13165:
+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13166:
+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x041b

WARNING: line length of 105 exceeds 100 columns
#13191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13167:
+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13168:
+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x041c

WARNING: line length of 105 exceeds 100 columns
#13193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13169:
+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13170:
+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x041d

WARNING: line length of 105 exceeds 100 columns
#13195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13171:
+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13172:
+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x041e

WARNING: line length of 105 exceeds 100 columns
#13197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13173:
+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13174:
+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x041f

WARNING: line length of 105 exceeds 100 columns
#13199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13175:
+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13176:
+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x0420

WARNING: line length of 105 exceeds 100 columns
#13201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13177:
+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13178:
+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x0421

WARNING: line length of 105 exceeds 100 columns
#13203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13179:
+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13180:
+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x0422

WARNING: line length of 105 exceeds 100 columns
#13205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13181:
+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13182:
+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x0423

WARNING: line length of 105 exceeds 100 columns
#13207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13183:
+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13184:
+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x0424

WARNING: line length of 105 exceeds 100 columns
#13209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13185:
+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13190:
+#define regDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x0447

WARNING: line length of 105 exceeds 100 columns
#13215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13191:
+#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13192:
+#define regDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x0448

WARNING: line length of 105 exceeds 100 columns
#13217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13193:
+#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13194:
+#define regDC_PERFMON15_PERFCOUNTER_STATE                                                               0x0449

WARNING: line length of 105 exceeds 100 columns
#13219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13195:
+#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13196:
+#define regDC_PERFMON15_PERFMON_CNTL                                                                    0x044a

WARNING: line length of 105 exceeds 100 columns
#13221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13197:
+#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13198:
+#define regDC_PERFMON15_PERFMON_CNTL2                                                                   0x044b

WARNING: line length of 105 exceeds 100 columns
#13223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13199:
+#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13200:
+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x044c

WARNING: line length of 105 exceeds 100 columns
#13225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13201:
+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13202:
+#define regDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x044d

WARNING: line length of 105 exceeds 100 columns
#13227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13203:
+#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13204:
+#define regDC_PERFMON15_PERFMON_HI                                                                      0x044e

WARNING: line length of 105 exceeds 100 columns
#13229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13205:
+#define regDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13206:
+#define regDC_PERFMON15_PERFMON_LOW                                                                     0x044f

WARNING: line length of 105 exceeds 100 columns
#13231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13207:
+#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13212:
+#define regAFMT5_AFMT_ACP                                                                               0x091b

WARNING: line length of 105 exceeds 100 columns
#13237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13213:
+#define regAFMT5_AFMT_ACP_BASE_IDX                                                                      3

WARNING: line length of 110 exceeds 100 columns
#13238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13214:
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c

WARNING: line length of 105 exceeds 100 columns
#13239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13215:
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13216:
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d

WARNING: line length of 105 exceeds 100 columns
#13241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13217:
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#13242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13218:
+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e

WARNING: line length of 105 exceeds 100 columns
#13243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13219:
+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13220:
+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f

WARNING: line length of 105 exceeds 100 columns
#13245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13221:
+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13222:
+#define regAFMT5_AFMT_60958_0                                                                           0x0920

WARNING: line length of 105 exceeds 100 columns
#13247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13223:
+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#13248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13224:
+#define regAFMT5_AFMT_60958_1                                                                           0x0921

WARNING: line length of 105 exceeds 100 columns
#13249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13225:
+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#13250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13226:
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922

WARNING: line length of 105 exceeds 100 columns
#13251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13227:
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13228:
+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923

WARNING: line length of 105 exceeds 100 columns
#13253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13229:
+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13230:
+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924

WARNING: line length of 105 exceeds 100 columns
#13255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13231:
+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13232:
+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925

WARNING: line length of 105 exceeds 100 columns
#13257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13233:
+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13234:
+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926

WARNING: line length of 105 exceeds 100 columns
#13259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13235:
+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13236:
+#define regAFMT5_AFMT_60958_2                                                                           0x0927

WARNING: line length of 105 exceeds 100 columns
#13261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13237:
+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#13262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13238:
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928

WARNING: line length of 105 exceeds 100 columns
#13263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13239:
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13240:
+#define regAFMT5_AFMT_STATUS                                                                            0x0929

WARNING: line length of 105 exceeds 100 columns
#13265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13241:
+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13242:
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a

WARNING: line length of 105 exceeds 100 columns
#13267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13243:
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13244:
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b

WARNING: line length of 105 exceeds 100 columns
#13269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13245:
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13246:
+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c

WARNING: line length of 105 exceeds 100 columns
#13271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13247:
+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13248:
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d

WARNING: line length of 105 exceeds 100 columns
#13273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13249:
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13250:
+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f

WARNING: line length of 105 exceeds 100 columns
#13275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13251:
+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#13280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13256:
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931

WARNING: line length of 105 exceeds 100 columns
#13281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13257:
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13258:
+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932

WARNING: line length of 105 exceeds 100 columns
#13283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13259:
+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13260:
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933

WARNING: line length of 105 exceeds 100 columns
#13285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13261:
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13262:
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934

WARNING: line length of 105 exceeds 100 columns
#13287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13263:
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13264:
+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935

WARNING: line length of 105 exceeds 100 columns
#13289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13265:
+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13266:
+#define regVPG5_VPG_MEM_PWR                                                                             0x0936

WARNING: line length of 105 exceeds 100 columns
#13291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13267:
+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3

WARNING: line length of 110 exceeds 100 columns
#13292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13268:
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937

WARNING: line length of 105 exceeds 100 columns
#13293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13269:
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13270:
+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938

WARNING: line length of 105 exceeds 100 columns
#13295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13271:
+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13272:
+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939

WARNING: line length of 105 exceeds 100 columns
#13297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13273:
+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#13298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13274:
+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a

WARNING: line length of 105 exceeds 100 columns
#13299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13275:
+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#13304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13280:
+#define regDME5_DME_CONTROL                                                                             0x093c

WARNING: line length of 105 exceeds 100 columns
#13305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13281:
+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3

WARNING: line length of 110 exceeds 100 columns
#13306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13282:
+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d

WARNING: line length of 105 exceeds 100 columns
#13307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13283:
+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13288:
+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43

WARNING: line length of 105 exceeds 100 columns
#13313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13289:
+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13290:
+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a

WARNING: line length of 105 exceeds 100 columns
#13315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13291:
+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3

WARNING: line length of 110 exceeds 100 columns
#13320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13296:
+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56

WARNING: line length of 105 exceeds 100 columns
#13321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13297:
+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13298:
+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57

WARNING: line length of 105 exceeds 100 columns
#13323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13299:
+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13300:
+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58

WARNING: line length of 105 exceeds 100 columns
#13325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13301:
+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13302:
+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59

WARNING: line length of 105 exceeds 100 columns
#13327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13303:
+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13308:
+#define regDC_PERFMON23_PERFCOUNTER_CNTL                                                                0x0e66

WARNING: line length of 105 exceeds 100 columns
#13333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13309:
+#define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13310:
+#define regDC_PERFMON23_PERFCOUNTER_CNTL2                                                               0x0e67

WARNING: line length of 105 exceeds 100 columns
#13335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13311:
+#define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13312:
+#define regDC_PERFMON23_PERFCOUNTER_STATE                                                               0x0e68

WARNING: line length of 105 exceeds 100 columns
#13337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13313:
+#define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13314:
+#define regDC_PERFMON23_PERFMON_CNTL                                                                    0x0e69

WARNING: line length of 105 exceeds 100 columns
#13339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13315:
+#define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13316:
+#define regDC_PERFMON23_PERFMON_CNTL2                                                                   0x0e6a

WARNING: line length of 105 exceeds 100 columns
#13341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13317:
+#define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13318:
+#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC                                                         0x0e6b

WARNING: line length of 105 exceeds 100 columns
#13343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13319:
+#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13320:
+#define regDC_PERFMON23_PERFMON_CVALUE_LOW                                                              0x0e6c

WARNING: line length of 105 exceeds 100 columns
#13345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13321:
+#define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13322:
+#define regDC_PERFMON23_PERFMON_HI                                                                      0x0e6d

WARNING: line length of 105 exceeds 100 columns
#13347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13323:
+#define regDC_PERFMON23_PERFMON_HI_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13324:
+#define regDC_PERFMON23_PERFMON_LOW                                                                     0x0e6e

WARNING: line length of 105 exceeds 100 columns
#13349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13325:
+#define regDC_PERFMON23_PERFMON_LOW_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13331:
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a

WARNING: line length of 105 exceeds 100 columns
#13356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13332:
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#13357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13333:
+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b

WARNING: line length of 105 exceeds 100 columns
#13358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13334:
+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13335:
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c

WARNING: line length of 105 exceeds 100 columns
#13360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13336:
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13337:
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d

WARNING: line length of 105 exceeds 100 columns
#13362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13338:
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13339:
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e

WARNING: line length of 105 exceeds 100 columns
#13364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13340:
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13341:
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f

WARNING: line length of 105 exceeds 100 columns
#13366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13342:
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13343:
+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80

WARNING: line length of 105 exceeds 100 columns
#13368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13344:
+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13345:
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81

WARNING: line length of 105 exceeds 100 columns
#13370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13346:
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13347:
+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82

WARNING: line length of 105 exceeds 100 columns
#13372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13348:
+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13349:
+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83

WARNING: line length of 105 exceeds 100 columns
#13374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13350:
+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13351:
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84

WARNING: line length of 105 exceeds 100 columns
#13376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13352:
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13353:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85

WARNING: line length of 105 exceeds 100 columns
#13378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13354:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13355:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86

WARNING: line length of 105 exceeds 100 columns
#13380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13356:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13357:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87

WARNING: line length of 105 exceeds 100 columns
#13382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13358:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13359:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88

WARNING: line length of 105 exceeds 100 columns
#13384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13360:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13361:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89

WARNING: line length of 105 exceeds 100 columns
#13386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13362:
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13363:
+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a

WARNING: line length of 105 exceeds 100 columns
#13388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13364:
+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13365:
+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b

WARNING: line length of 105 exceeds 100 columns
#13390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13366:
+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13367:
+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c

WARNING: line length of 105 exceeds 100 columns
#13392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13368:
+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13369:
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e

WARNING: line length of 105 exceeds 100 columns
#13394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13370:
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13371:
+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f

WARNING: line length of 105 exceeds 100 columns
#13396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13372:
+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13373:
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90

WARNING: line length of 105 exceeds 100 columns
#13398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13374:
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13375:
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91

WARNING: line length of 105 exceeds 100 columns
#13400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13376:
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13377:
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92

WARNING: line length of 105 exceeds 100 columns
#13402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13378:
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13379:
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93

WARNING: line length of 105 exceeds 100 columns
#13404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13380:
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13381:
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94

WARNING: line length of 105 exceeds 100 columns
#13406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13382:
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13383:
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95

WARNING: line length of 105 exceeds 100 columns
#13408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13384:
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13385:
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96

WARNING: line length of 105 exceeds 100 columns
#13410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13386:
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13387:
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97

WARNING: line length of 105 exceeds 100 columns
#13412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13388:
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13389:
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98

WARNING: line length of 105 exceeds 100 columns
#13414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13390:
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13391:
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99

WARNING: line length of 105 exceeds 100 columns
#13416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13392:
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13393:
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a

WARNING: line length of 105 exceeds 100 columns
#13418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13394:
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13395:
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b

WARNING: line length of 105 exceeds 100 columns
#13420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13396:
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13397:
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c

WARNING: line length of 105 exceeds 100 columns
#13422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13398:
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13399:
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d

WARNING: line length of 105 exceeds 100 columns
#13424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13400:
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13401:
+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e

WARNING: line length of 105 exceeds 100 columns
#13426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13402:
+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13403:
+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f

WARNING: line length of 105 exceeds 100 columns
#13428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13404:
+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13405:
+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0

WARNING: line length of 105 exceeds 100 columns
#13430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13406:
+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13407:
+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1

WARNING: line length of 105 exceeds 100 columns
#13432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13408:
+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13409:
+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2

WARNING: line length of 105 exceeds 100 columns
#13434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13410:
+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13411:
+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3

WARNING: line length of 105 exceeds 100 columns
#13436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13412:
+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13413:
+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4

WARNING: line length of 105 exceeds 100 columns
#13438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13414:
+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13415:
+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5

WARNING: line length of 105 exceeds 100 columns
#13440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13416:
+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13417:
+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6

WARNING: line length of 105 exceeds 100 columns
#13442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13418:
+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13419:
+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7

WARNING: line length of 105 exceeds 100 columns
#13444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13420:
+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13421:
+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8

WARNING: line length of 105 exceeds 100 columns
#13446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13422:
+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13423:
+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9

WARNING: line length of 105 exceeds 100 columns
#13448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13424:
+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13425:
+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa

WARNING: line length of 105 exceeds 100 columns
#13450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13426:
+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13427:
+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab

WARNING: line length of 105 exceeds 100 columns
#13452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13428:
+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13429:
+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac

WARNING: line length of 105 exceeds 100 columns
#13454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13430:
+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13431:
+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead

WARNING: line length of 105 exceeds 100 columns
#13456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13432:
+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13433:
+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae

WARNING: line length of 105 exceeds 100 columns
#13458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13434:
+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13435:
+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf

WARNING: line length of 105 exceeds 100 columns
#13460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13436:
+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13437:
+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0

WARNING: line length of 105 exceeds 100 columns
#13462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13438:
+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13439:
+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1

WARNING: line length of 105 exceeds 100 columns
#13464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13440:
+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13441:
+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2

WARNING: line length of 105 exceeds 100 columns
#13466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13442:
+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13443:
+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3

WARNING: line length of 105 exceeds 100 columns
#13468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13444:
+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13445:
+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4

WARNING: line length of 105 exceeds 100 columns
#13470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13446:
+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13447:
+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5

WARNING: line length of 105 exceeds 100 columns
#13472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13448:
+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13449:
+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6

WARNING: line length of 105 exceeds 100 columns
#13474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13450:
+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13455:
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb

WARNING: line length of 105 exceeds 100 columns
#13480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13456:
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#13481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13457:
+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc

WARNING: line length of 105 exceeds 100 columns
#13482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13458:
+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13459:
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd

WARNING: line length of 105 exceeds 100 columns
#13484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13460:
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13461:
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe

WARNING: line length of 105 exceeds 100 columns
#13486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13462:
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13463:
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf

WARNING: line length of 105 exceeds 100 columns
#13488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13464:
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13465:
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0

WARNING: line length of 105 exceeds 100 columns
#13490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13466:
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13467:
+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1

WARNING: line length of 105 exceeds 100 columns
#13492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13468:
+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13469:
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2

WARNING: line length of 105 exceeds 100 columns
#13494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13470:
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13471:
+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3

WARNING: line length of 105 exceeds 100 columns
#13496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13472:
+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13473:
+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4

WARNING: line length of 105 exceeds 100 columns
#13498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13474:
+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13475:
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5

WARNING: line length of 105 exceeds 100 columns
#13500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13476:
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13477:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6

WARNING: line length of 105 exceeds 100 columns
#13502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13478:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13479:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7

WARNING: line length of 105 exceeds 100 columns
#13504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13480:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13481:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8

WARNING: line length of 105 exceeds 100 columns
#13506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13482:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13483:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9

WARNING: line length of 105 exceeds 100 columns
#13508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13484:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13485:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca

WARNING: line length of 105 exceeds 100 columns
#13510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13486:
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13487:
+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb

WARNING: line length of 105 exceeds 100 columns
#13512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13488:
+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13489:
+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc

WARNING: line length of 105 exceeds 100 columns
#13514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13490:
+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13491:
+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd

WARNING: line length of 105 exceeds 100 columns
#13516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13492:
+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13493:
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf

WARNING: line length of 105 exceeds 100 columns
#13518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13494:
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13495:
+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0

WARNING: line length of 105 exceeds 100 columns
#13520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13496:
+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13497:
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1

WARNING: line length of 105 exceeds 100 columns
#13522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13498:
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13499:
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2

WARNING: line length of 105 exceeds 100 columns
#13524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13500:
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13501:
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3

WARNING: line length of 105 exceeds 100 columns
#13526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13502:
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13503:
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4

WARNING: line length of 105 exceeds 100 columns
#13528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13504:
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13505:
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5

WARNING: line length of 105 exceeds 100 columns
#13530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13506:
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13507:
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6

WARNING: line length of 105 exceeds 100 columns
#13532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13508:
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13509:
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7

WARNING: line length of 105 exceeds 100 columns
#13534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13510:
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13511:
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8

WARNING: line length of 105 exceeds 100 columns
#13536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13512:
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13513:
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9

WARNING: line length of 105 exceeds 100 columns
#13538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13514:
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13515:
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda

WARNING: line length of 105 exceeds 100 columns
#13540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13516:
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13517:
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb

WARNING: line length of 105 exceeds 100 columns
#13542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13518:
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13519:
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc

WARNING: line length of 105 exceeds 100 columns
#13544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13520:
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13521:
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd

WARNING: line length of 105 exceeds 100 columns
#13546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13522:
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13523:
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede

WARNING: line length of 105 exceeds 100 columns
#13548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13524:
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13525:
+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf

WARNING: line length of 105 exceeds 100 columns
#13550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13526:
+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13527:
+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0

WARNING: line length of 105 exceeds 100 columns
#13552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13528:
+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13529:
+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1

WARNING: line length of 105 exceeds 100 columns
#13554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13530:
+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13531:
+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2

WARNING: line length of 105 exceeds 100 columns
#13556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13532:
+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13533:
+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3

WARNING: line length of 105 exceeds 100 columns
#13558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13534:
+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13535:
+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4

WARNING: line length of 105 exceeds 100 columns
#13560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13536:
+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13537:
+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5

WARNING: line length of 105 exceeds 100 columns
#13562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13538:
+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13539:
+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6

WARNING: line length of 105 exceeds 100 columns
#13564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13540:
+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13541:
+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7

WARNING: line length of 105 exceeds 100 columns
#13566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13542:
+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13543:
+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8

WARNING: line length of 105 exceeds 100 columns
#13568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13544:
+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13545:
+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9

WARNING: line length of 105 exceeds 100 columns
#13570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13546:
+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13547:
+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea

WARNING: line length of 105 exceeds 100 columns
#13572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13548:
+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13549:
+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb

WARNING: line length of 105 exceeds 100 columns
#13574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13550:
+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13551:
+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec

WARNING: line length of 105 exceeds 100 columns
#13576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13552:
+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13553:
+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed

WARNING: line length of 105 exceeds 100 columns
#13578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13554:
+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13555:
+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee

WARNING: line length of 105 exceeds 100 columns
#13580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13556:
+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13557:
+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef

WARNING: line length of 105 exceeds 100 columns
#13582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13558:
+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13559:
+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0

WARNING: line length of 105 exceeds 100 columns
#13584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13560:
+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13561:
+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1

WARNING: line length of 105 exceeds 100 columns
#13586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13562:
+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13563:
+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2

WARNING: line length of 105 exceeds 100 columns
#13588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13564:
+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13565:
+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3

WARNING: line length of 105 exceeds 100 columns
#13590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13566:
+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13567:
+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4

WARNING: line length of 105 exceeds 100 columns
#13592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13568:
+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13569:
+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5

WARNING: line length of 105 exceeds 100 columns
#13594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13570:
+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13571:
+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6

WARNING: line length of 105 exceeds 100 columns
#13596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13572:
+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13573:
+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7

WARNING: line length of 105 exceeds 100 columns
#13598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13574:
+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13579:
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc

WARNING: line length of 105 exceeds 100 columns
#13604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13580:
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#13605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13581:
+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd

WARNING: line length of 105 exceeds 100 columns
#13606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13582:
+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13583:
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe

WARNING: line length of 105 exceeds 100 columns
#13608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13584:
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13585:
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff

WARNING: line length of 105 exceeds 100 columns
#13610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13586:
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13587:
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00

WARNING: line length of 105 exceeds 100 columns
#13612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13588:
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13589:
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01

WARNING: line length of 105 exceeds 100 columns
#13614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13590:
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13591:
+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02

WARNING: line length of 105 exceeds 100 columns
#13616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13592:
+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13593:
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03

WARNING: line length of 105 exceeds 100 columns
#13618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13594:
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13595:
+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04

WARNING: line length of 105 exceeds 100 columns
#13620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13596:
+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13597:
+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05

WARNING: line length of 105 exceeds 100 columns
#13622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13598:
+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13599:
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06

WARNING: line length of 105 exceeds 100 columns
#13624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13600:
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13601:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07

WARNING: line length of 105 exceeds 100 columns
#13626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13602:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13603:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08

WARNING: line length of 105 exceeds 100 columns
#13628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13604:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13605:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09

WARNING: line length of 105 exceeds 100 columns
#13630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13606:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13607:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a

WARNING: line length of 105 exceeds 100 columns
#13632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13608:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13609:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b

WARNING: line length of 105 exceeds 100 columns
#13634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13610:
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13611:
+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c

WARNING: line length of 105 exceeds 100 columns
#13636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13612:
+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13613:
+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d

WARNING: line length of 105 exceeds 100 columns
#13638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13614:
+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13615:
+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e

WARNING: line length of 105 exceeds 100 columns
#13640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13616:
+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13617:
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10

WARNING: line length of 105 exceeds 100 columns
#13642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13618:
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13619:
+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11

WARNING: line length of 105 exceeds 100 columns
#13644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13620:
+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13621:
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12

WARNING: line length of 105 exceeds 100 columns
#13646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13622:
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13623:
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13

WARNING: line length of 105 exceeds 100 columns
#13648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13624:
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13625:
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14

WARNING: line length of 105 exceeds 100 columns
#13650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13626:
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13627:
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15

WARNING: line length of 105 exceeds 100 columns
#13652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13628:
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13629:
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16

WARNING: line length of 105 exceeds 100 columns
#13654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13630:
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13631:
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17

WARNING: line length of 105 exceeds 100 columns
#13656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13632:
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13633:
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18

WARNING: line length of 105 exceeds 100 columns
#13658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13634:
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13635:
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19

WARNING: line length of 105 exceeds 100 columns
#13660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13636:
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13637:
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a

WARNING: line length of 105 exceeds 100 columns
#13662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13638:
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13639:
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b

WARNING: line length of 105 exceeds 100 columns
#13664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13640:
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13641:
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c

WARNING: line length of 105 exceeds 100 columns
#13666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13642:
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13643:
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d

WARNING: line length of 105 exceeds 100 columns
#13668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13644:
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13645:
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e

WARNING: line length of 105 exceeds 100 columns
#13670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13646:
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13647:
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f

WARNING: line length of 105 exceeds 100 columns
#13672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13648:
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13649:
+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20

WARNING: line length of 105 exceeds 100 columns
#13674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13650:
+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13651:
+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21

WARNING: line length of 105 exceeds 100 columns
#13676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13652:
+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13653:
+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22

WARNING: line length of 105 exceeds 100 columns
#13678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13654:
+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13655:
+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23

WARNING: line length of 105 exceeds 100 columns
#13680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13656:
+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13657:
+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24

WARNING: line length of 105 exceeds 100 columns
#13682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13658:
+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13659:
+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25

WARNING: line length of 105 exceeds 100 columns
#13684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13660:
+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13661:
+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26

WARNING: line length of 105 exceeds 100 columns
#13686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13662:
+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13663:
+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27

WARNING: line length of 105 exceeds 100 columns
#13688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13664:
+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13665:
+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28

WARNING: line length of 105 exceeds 100 columns
#13690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13666:
+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13667:
+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29

WARNING: line length of 105 exceeds 100 columns
#13692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13668:
+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13669:
+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a

WARNING: line length of 105 exceeds 100 columns
#13694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13670:
+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13671:
+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b

WARNING: line length of 105 exceeds 100 columns
#13696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13672:
+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13673:
+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c

WARNING: line length of 105 exceeds 100 columns
#13698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13674:
+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13675:
+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d

WARNING: line length of 105 exceeds 100 columns
#13700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13676:
+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13677:
+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e

WARNING: line length of 105 exceeds 100 columns
#13702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13678:
+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13679:
+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f

WARNING: line length of 105 exceeds 100 columns
#13704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13680:
+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13681:
+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30

WARNING: line length of 105 exceeds 100 columns
#13706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13682:
+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13683:
+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31

WARNING: line length of 105 exceeds 100 columns
#13708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13684:
+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13685:
+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32

WARNING: line length of 105 exceeds 100 columns
#13710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13686:
+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13687:
+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33

WARNING: line length of 105 exceeds 100 columns
#13712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13688:
+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13689:
+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34

WARNING: line length of 105 exceeds 100 columns
#13714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13690:
+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13691:
+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35

WARNING: line length of 105 exceeds 100 columns
#13716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13692:
+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13693:
+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36

WARNING: line length of 105 exceeds 100 columns
#13718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13694:
+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13695:
+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37

WARNING: line length of 105 exceeds 100 columns
#13720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13696:
+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13697:
+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38

WARNING: line length of 105 exceeds 100 columns
#13722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13698:
+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13703:
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d

WARNING: line length of 105 exceeds 100 columns
#13728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13704:
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#13729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13705:
+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e

WARNING: line length of 105 exceeds 100 columns
#13730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13706:
+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3

WARNING: line length of 110 exceeds 100 columns
#13731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13707:
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f

WARNING: line length of 105 exceeds 100 columns
#13732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13708:
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13709:
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40

WARNING: line length of 105 exceeds 100 columns
#13734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13710:
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13711:
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41

WARNING: line length of 105 exceeds 100 columns
#13736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13712:
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13713:
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42

WARNING: line length of 105 exceeds 100 columns
#13738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13714:
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13715:
+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43

WARNING: line length of 105 exceeds 100 columns
#13740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13716:
+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13717:
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44

WARNING: line length of 105 exceeds 100 columns
#13742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13718:
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13719:
+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45

WARNING: line length of 105 exceeds 100 columns
#13744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13720:
+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13721:
+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46

WARNING: line length of 105 exceeds 100 columns
#13746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13722:
+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3

WARNING: line length of 110 exceeds 100 columns
#13747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13723:
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47

WARNING: line length of 105 exceeds 100 columns
#13748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13724:
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13725:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48

WARNING: line length of 105 exceeds 100 columns
#13750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13726:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13727:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49

WARNING: line length of 105 exceeds 100 columns
#13752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13728:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13729:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a

WARNING: line length of 105 exceeds 100 columns
#13754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13730:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13731:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b

WARNING: line length of 105 exceeds 100 columns
#13756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13732:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13733:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c

WARNING: line length of 105 exceeds 100 columns
#13758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13734:
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13735:
+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d

WARNING: line length of 105 exceeds 100 columns
#13760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13736:
+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13737:
+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e

WARNING: line length of 105 exceeds 100 columns
#13762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13738:
+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13739:
+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f

WARNING: line length of 105 exceeds 100 columns
#13764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13740:
+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13741:
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51

WARNING: line length of 105 exceeds 100 columns
#13766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13742:
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13743:
+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52

WARNING: line length of 105 exceeds 100 columns
#13768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13744:
+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13745:
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53

WARNING: line length of 105 exceeds 100 columns
#13770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13746:
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13747:
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54

WARNING: line length of 105 exceeds 100 columns
#13772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13748:
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3

WARNING: line length of 110 exceeds 100 columns
#13773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13749:
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55

WARNING: line length of 105 exceeds 100 columns
#13774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13750:
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13751:
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56

WARNING: line length of 105 exceeds 100 columns
#13776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13752:
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13753:
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57

WARNING: line length of 105 exceeds 100 columns
#13778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13754:
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13755:
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58

WARNING: line length of 105 exceeds 100 columns
#13780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13756:
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13757:
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59

WARNING: line length of 105 exceeds 100 columns
#13782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13758:
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13759:
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a

WARNING: line length of 105 exceeds 100 columns
#13784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13760:
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13761:
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b

WARNING: line length of 105 exceeds 100 columns
#13786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13762:
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13763:
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c

WARNING: line length of 105 exceeds 100 columns
#13788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13764:
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13765:
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d

WARNING: line length of 105 exceeds 100 columns
#13790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13766:
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13767:
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e

WARNING: line length of 105 exceeds 100 columns
#13792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13768:
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13769:
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f

WARNING: line length of 105 exceeds 100 columns
#13794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13770:
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13771:
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60

WARNING: line length of 105 exceeds 100 columns
#13796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13772:
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#13797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13773:
+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61

WARNING: line length of 105 exceeds 100 columns
#13798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13774:
+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13775:
+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62

WARNING: line length of 105 exceeds 100 columns
#13800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13776:
+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13777:
+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63

WARNING: line length of 105 exceeds 100 columns
#13802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13778:
+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13779:
+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64

WARNING: line length of 105 exceeds 100 columns
#13804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13780:
+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13781:
+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65

WARNING: line length of 105 exceeds 100 columns
#13806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13782:
+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13783:
+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66

WARNING: line length of 105 exceeds 100 columns
#13808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13784:
+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13785:
+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67

WARNING: line length of 105 exceeds 100 columns
#13810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13786:
+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13787:
+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68

WARNING: line length of 105 exceeds 100 columns
#13812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13788:
+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13789:
+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69

WARNING: line length of 105 exceeds 100 columns
#13814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13790:
+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13791:
+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a

WARNING: line length of 105 exceeds 100 columns
#13816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13792:
+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13793:
+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b

WARNING: line length of 105 exceeds 100 columns
#13818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13794:
+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13795:
+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c

WARNING: line length of 105 exceeds 100 columns
#13820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13796:
+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13797:
+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d

WARNING: line length of 105 exceeds 100 columns
#13822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13798:
+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13799:
+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e

WARNING: line length of 105 exceeds 100 columns
#13824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13800:
+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13801:
+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f

WARNING: line length of 105 exceeds 100 columns
#13826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13802:
+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13803:
+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70

WARNING: line length of 105 exceeds 100 columns
#13828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13804:
+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13805:
+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71

WARNING: line length of 105 exceeds 100 columns
#13830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13806:
+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13807:
+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72

WARNING: line length of 105 exceeds 100 columns
#13832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13808:
+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13809:
+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73

WARNING: line length of 105 exceeds 100 columns
#13834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13810:
+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13811:
+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74

WARNING: line length of 105 exceeds 100 columns
#13836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13812:
+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13813:
+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75

WARNING: line length of 105 exceeds 100 columns
#13838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13814:
+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13815:
+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76

WARNING: line length of 105 exceeds 100 columns
#13840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13816:
+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13817:
+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77

WARNING: line length of 105 exceeds 100 columns
#13842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13818:
+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13819:
+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78

WARNING: line length of 105 exceeds 100 columns
#13844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13820:
+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3

WARNING: line length of 110 exceeds 100 columns
#13845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13821:
+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79

WARNING: line length of 105 exceeds 100 columns
#13846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13822:
+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13827:
+#define regHDMI_LINK_ENC_CONTROL                                                                        0x095b

WARNING: line length of 105 exceeds 100 columns
#13852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13828:
+#define regHDMI_LINK_ENC_CONTROL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13829:
+#define regHDMI_LINK_ENC_CLK_CTRL                                                                       0x095c

WARNING: line length of 105 exceeds 100 columns
#13854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13830:
+#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13835:
+#define regHDMI_FRL_ENC_CONFIG                                                                          0x0965

WARNING: line length of 105 exceeds 100 columns
#13860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13836:
+#define regHDMI_FRL_ENC_CONFIG_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#13861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13837:
+#define regHDMI_FRL_ENC_CONFIG2                                                                         0x0966

WARNING: line length of 105 exceeds 100 columns
#13862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13838:
+#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13839:
+#define regHDMI_FRL_ENC_METER_BUFFER_STATUS                                                             0x0967

WARNING: line length of 105 exceeds 100 columns
#13864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13840:
+#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#13865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13841:
+#define regHDMI_FRL_ENC_MEM_CTRL                                                                        0x0968

WARNING: line length of 105 exceeds 100 columns
#13866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13842:
+#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX                                                               3

WARNING: line length of 110 exceeds 100 columns
#13871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13847:
+#define regHDMI_STREAM_ENC_CLOCK_CONTROL                                                                0x08d3

WARNING: line length of 105 exceeds 100 columns
#13872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13848:
+#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13849:
+#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL                                                            0x08d5

WARNING: line length of 105 exceeds 100 columns
#13874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13850:
+#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#13875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13851:
+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                                     0x08d6

WARNING: line length of 105 exceeds 100 columns
#13876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13852:
+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX                            3

WARNING: line length of 110 exceeds 100 columns
#13877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13853:
+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                                     0x08d7

WARNING: line length of 105 exceeds 100 columns
#13878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13854:
+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX                            3

WARNING: line length of 110 exceeds 100 columns
#13879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13855:
+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2                                     0x08d8

WARNING: line length of 105 exceeds 100 columns
#13880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13856:
+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX                            3

WARNING: line length of 110 exceeds 100 columns
#13885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13861:
+#define regHDMI_TB_ENC_CONTROL                                                                          0x08df

WARNING: line length of 105 exceeds 100 columns
#13886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13862:
+#define regHDMI_TB_ENC_CONTROL_BASE_IDX                                                                 3

WARNING: line length of 110 exceeds 100 columns
#13887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13863:
+#define regHDMI_TB_ENC_PIXEL_FORMAT                                                                     0x08e0

WARNING: line length of 105 exceeds 100 columns
#13888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13864:
+#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13865:
+#define regHDMI_TB_ENC_PACKET_CONTROL                                                                   0x08e1

WARNING: line length of 105 exceeds 100 columns
#13890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13866:
+#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13867:
+#define regHDMI_TB_ENC_ACR_PACKET_CONTROL                                                               0x08e2

WARNING: line length of 105 exceeds 100 columns
#13892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13868:
+#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13869:
+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1                                                              0x08e3

WARNING: line length of 105 exceeds 100 columns
#13894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13870:
+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13871:
+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2                                                              0x08e4

WARNING: line length of 105 exceeds 100 columns
#13896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13872:
+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#13897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13873:
+#define regHDMI_TB_ENC_GC_CONTROL                                                                       0x08e5

WARNING: line length of 105 exceeds 100 columns
#13898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13874:
+#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13875:
+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0                                                          0x08e6

WARNING: line length of 105 exceeds 100 columns
#13900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13876:
+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13877:
+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1                                                          0x08e7

WARNING: line length of 105 exceeds 100 columns
#13902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13878:
+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13879:
+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2                                                          0x08e8

WARNING: line length of 105 exceeds 100 columns
#13904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13880:
+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13881:
+#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE                                                           0x08e9

WARNING: line length of 105 exceeds 100 columns
#13906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13882:
+#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13883:
+#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE                                                           0x08ea

WARNING: line length of 105 exceeds 100 columns
#13908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13884:
+#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13885:
+#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE                                                           0x08eb

WARNING: line length of 105 exceeds 100 columns
#13910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13886:
+#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13887:
+#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE                                                           0x08ec

WARNING: line length of 105 exceeds 100 columns
#13912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13888:
+#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13889:
+#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE                                                           0x08ed

WARNING: line length of 105 exceeds 100 columns
#13914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13890:
+#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13891:
+#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE                                                         0x08ee

WARNING: line length of 105 exceeds 100 columns
#13916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13892:
+#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13893:
+#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE                                                         0x08ef

WARNING: line length of 105 exceeds 100 columns
#13918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13894:
+#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#13919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13895:
+#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE                                                            0x08f0

WARNING: line length of 105 exceeds 100 columns
#13920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13896:
+#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#13921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13897:
+#define regHDMI_TB_ENC_DB_CONTROL                                                                       0x08f1

WARNING: line length of 105 exceeds 100 columns
#13922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13898:
+#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX                                                              3

WARNING: line length of 110 exceeds 100 columns
#13923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13899:
+#define regHDMI_TB_ENC_ACR_32_0                                                                         0x08f2

WARNING: line length of 105 exceeds 100 columns
#13924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13900:
+#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13901:
+#define regHDMI_TB_ENC_ACR_32_1                                                                         0x08f3

WARNING: line length of 105 exceeds 100 columns
#13926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13902:
+#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13903:
+#define regHDMI_TB_ENC_ACR_44_0                                                                         0x08f4

WARNING: line length of 105 exceeds 100 columns
#13928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13904:
+#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13905:
+#define regHDMI_TB_ENC_ACR_44_1                                                                         0x08f5

WARNING: line length of 105 exceeds 100 columns
#13930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13906:
+#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13907:
+#define regHDMI_TB_ENC_ACR_48_0                                                                         0x08f6

WARNING: line length of 105 exceeds 100 columns
#13932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13908:
+#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13909:
+#define regHDMI_TB_ENC_ACR_48_1                                                                         0x08f7

WARNING: line length of 105 exceeds 100 columns
#13934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13910:
+#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13911:
+#define regHDMI_TB_ENC_ACR_STATUS_0                                                                     0x08f8

WARNING: line length of 105 exceeds 100 columns
#13936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13912:
+#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13913:
+#define regHDMI_TB_ENC_ACR_STATUS_1                                                                     0x08f9

WARNING: line length of 105 exceeds 100 columns
#13938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13914:
+#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13915:
+#define regHDMI_TB_ENC_BUFFER_CONTROL                                                                   0x08fb

WARNING: line length of 105 exceeds 100 columns
#13940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13916:
+#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13917:
+#define regHDMI_TB_ENC_MEM_CTRL                                                                         0x08fe

WARNING: line length of 105 exceeds 100 columns
#13942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13918:
+#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13919:
+#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL                                                          0x08ff

WARNING: line length of 105 exceeds 100 columns
#13944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13920:
+#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13921:
+#define regHDMI_TB_ENC_H_ACTIVE_BLANK                                                                   0x0900

WARNING: line length of 105 exceeds 100 columns
#13946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13922:
+#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX                                                          3

WARNING: line length of 110 exceeds 100 columns
#13947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13923:
+#define regHDMI_TB_ENC_HC_ACTIVE_BLANK                                                                  0x0901

WARNING: line length of 105 exceeds 100 columns
#13948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13924:
+#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX                                                         3

WARNING: line length of 110 exceeds 100 columns
#13949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13925:
+#define regHDMI_TB_ENC_CRC_CNTL                                                                         0x0903

WARNING: line length of 105 exceeds 100 columns
#13950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13926:
+#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX                                                                3

WARNING: line length of 110 exceeds 100 columns
#13951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13927:
+#define regHDMI_TB_ENC_CRC_RESULT_0                                                                     0x0904

WARNING: line length of 105 exceeds 100 columns
#13952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13928:
+#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13929:
+#define regHDMI_TB_ENC_ENCRYPTION_CONTROL                                                               0x0907

WARNING: line length of 105 exceeds 100 columns
#13954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13930:
+#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#13955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13931:
+#define regHDMI_TB_ENC_MODE                                                                             0x0908

WARNING: line length of 105 exceeds 100 columns
#13956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13932:
+#define regHDMI_TB_ENC_MODE_BASE_IDX                                                                    3

WARNING: line length of 110 exceeds 100 columns
#13957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13933:
+#define regHDMI_TB_ENC_INPUT_FIFO_STATUS                                                                0x0909

WARNING: line length of 105 exceeds 100 columns
#13958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13934:
+#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#13959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13935:
+#define regHDMI_TB_ENC_CRC_RESULT_1                                                                     0x090a

WARNING: line length of 105 exceeds 100 columns
#13960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13936:
+#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX                                                            3

WARNING: line length of 110 exceeds 100 columns
#13965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13941:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453

WARNING: line length of 105 exceeds 100 columns
#13966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13942:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#13967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13943:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454

WARNING: line length of 105 exceeds 100 columns
#13968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13944:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13945:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455

WARNING: line length of 105 exceeds 100 columns
#13970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13946:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13947:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456

WARNING: line length of 105 exceeds 100 columns
#13972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13948:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13949:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457

WARNING: line length of 105 exceeds 100 columns
#13974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13950:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#13975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13951:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458

WARNING: line length of 105 exceeds 100 columns
#13976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13952:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13953:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459

WARNING: line length of 105 exceeds 100 columns
#13978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13954:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#13979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13955:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a

WARNING: line length of 105 exceeds 100 columns
#13980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13956:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#13981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13957:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b

WARNING: line length of 105 exceeds 100 columns
#13982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13958:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#13983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13959:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c

WARNING: line length of 105 exceeds 100 columns
#13984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13960:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#13985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13961:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d

WARNING: line length of 105 exceeds 100 columns
#13986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13962:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#13987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13963:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e

WARNING: line length of 105 exceeds 100 columns
#13988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13964:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#13989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13965:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f

WARNING: line length of 105 exceeds 100 columns
#13990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13966:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13967:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460

WARNING: line length of 105 exceeds 100 columns
#13992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13968:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13969:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461

WARNING: line length of 105 exceeds 100 columns
#13994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13970:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13971:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462

WARNING: line length of 105 exceeds 100 columns
#13996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13972:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13973:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463

WARNING: line length of 105 exceeds 100 columns
#13998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13974:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#13999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13975:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464

WARNING: line length of 105 exceeds 100 columns
#14000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13976:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13977:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465

WARNING: line length of 105 exceeds 100 columns
#14002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13978:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13979:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466

WARNING: line length of 105 exceeds 100 columns
#14004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13980:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13981:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467

WARNING: line length of 105 exceeds 100 columns
#14006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13982:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13983:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468

WARNING: line length of 105 exceeds 100 columns
#14008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13984:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13985:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469

WARNING: line length of 105 exceeds 100 columns
#14010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13986:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13987:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a

WARNING: line length of 105 exceeds 100 columns
#14012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13988:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13989:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b

WARNING: line length of 105 exceeds 100 columns
#14014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13990:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13991:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c

WARNING: line length of 105 exceeds 100 columns
#14016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13992:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13993:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d

WARNING: line length of 105 exceeds 100 columns
#14018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13994:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13995:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e

WARNING: line length of 105 exceeds 100 columns
#14020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13996:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13997:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f

WARNING: line length of 105 exceeds 100 columns
#14022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13998:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:13999:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470

WARNING: line length of 105 exceeds 100 columns
#14024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14000:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14001:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471

WARNING: line length of 105 exceeds 100 columns
#14026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14002:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14003:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472

WARNING: line length of 105 exceeds 100 columns
#14028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14004:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14005:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473

WARNING: line length of 105 exceeds 100 columns
#14030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14006:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14007:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474

WARNING: line length of 105 exceeds 100 columns
#14032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14008:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14009:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475

WARNING: line length of 105 exceeds 100 columns
#14034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14010:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14011:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476

WARNING: line length of 105 exceeds 100 columns
#14036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14012:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14013:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477

WARNING: line length of 105 exceeds 100 columns
#14038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14014:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14015:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478

WARNING: line length of 105 exceeds 100 columns
#14040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14016:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14017:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479

WARNING: line length of 105 exceeds 100 columns
#14042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14018:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14019:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a

WARNING: line length of 105 exceeds 100 columns
#14044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14020:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14021:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b

WARNING: line length of 105 exceeds 100 columns
#14046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14022:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14023:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c

WARNING: line length of 105 exceeds 100 columns
#14048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14024:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14025:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d

WARNING: line length of 105 exceeds 100 columns
#14050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14026:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14027:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e

WARNING: line length of 105 exceeds 100 columns
#14052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14028:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14029:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f

WARNING: line length of 105 exceeds 100 columns
#14054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14030:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14031:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480

WARNING: line length of 105 exceeds 100 columns
#14056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14032:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14033:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481

WARNING: line length of 105 exceeds 100 columns
#14058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14034:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14035:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482

WARNING: line length of 105 exceeds 100 columns
#14060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14036:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14037:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483

WARNING: line length of 105 exceeds 100 columns
#14062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14038:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14039:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484

WARNING: line length of 105 exceeds 100 columns
#14064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14040:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14041:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485

WARNING: line length of 105 exceeds 100 columns
#14066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14042:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14043:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486

WARNING: line length of 105 exceeds 100 columns
#14068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14044:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14045:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487

WARNING: line length of 105 exceeds 100 columns
#14070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14046:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14047:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488

WARNING: line length of 105 exceeds 100 columns
#14072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14048:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14049:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489

WARNING: line length of 105 exceeds 100 columns
#14074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14050:
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14051:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a

WARNING: line length of 105 exceeds 100 columns
#14076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14052:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14053:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b

WARNING: line length of 105 exceeds 100 columns
#14078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14054:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#14079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14055:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c

WARNING: line length of 105 exceeds 100 columns
#14080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14056:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14057:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d

WARNING: line length of 105 exceeds 100 columns
#14082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14058:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14059:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e

WARNING: line length of 105 exceeds 100 columns
#14084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14060:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14061:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f

WARNING: line length of 105 exceeds 100 columns
#14086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14062:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14063:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490

WARNING: line length of 105 exceeds 100 columns
#14088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14064:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14065:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491

WARNING: line length of 105 exceeds 100 columns
#14090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14066:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14067:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492

WARNING: line length of 105 exceeds 100 columns
#14092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14068:
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14069:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493

WARNING: line length of 105 exceeds 100 columns
#14094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14070:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#14095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14071:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494

WARNING: line length of 105 exceeds 100 columns
#14096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14072:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14073:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495

WARNING: line length of 105 exceeds 100 columns
#14098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14074:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14075:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496

WARNING: line length of 105 exceeds 100 columns
#14100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14076:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#14101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14077:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497

WARNING: line length of 105 exceeds 100 columns
#14102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14078:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14079:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498

WARNING: line length of 105 exceeds 100 columns
#14104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14080:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14081:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499

WARNING: line length of 105 exceeds 100 columns
#14106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14082:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14083:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a

WARNING: line length of 105 exceeds 100 columns
#14108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14084:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14085:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b

WARNING: line length of 105 exceeds 100 columns
#14110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14086:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14087:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c

WARNING: line length of 105 exceeds 100 columns
#14112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14088:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14089:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d

WARNING: line length of 105 exceeds 100 columns
#14114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14090:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14091:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e

WARNING: line length of 105 exceeds 100 columns
#14116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14092:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14093:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f

WARNING: line length of 105 exceeds 100 columns
#14118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14094:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14095:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0

WARNING: line length of 105 exceeds 100 columns
#14120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14096:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14097:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1

WARNING: line length of 105 exceeds 100 columns
#14122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14098:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14099:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2

WARNING: line length of 105 exceeds 100 columns
#14124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14100:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14101:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3

WARNING: line length of 105 exceeds 100 columns
#14126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14102:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14103:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4

WARNING: line length of 105 exceeds 100 columns
#14128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14104:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14105:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5

WARNING: line length of 105 exceeds 100 columns
#14130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14106:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14107:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6

WARNING: line length of 105 exceeds 100 columns
#14132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14108:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14109:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7

WARNING: line length of 105 exceeds 100 columns
#14134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14110:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14111:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8

WARNING: line length of 105 exceeds 100 columns
#14136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14112:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14113:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9

WARNING: line length of 105 exceeds 100 columns
#14138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14114:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14115:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa

WARNING: line length of 105 exceeds 100 columns
#14140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14116:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14117:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab

WARNING: line length of 105 exceeds 100 columns
#14142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14118:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14119:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac

WARNING: line length of 105 exceeds 100 columns
#14144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14120:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14121:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad

WARNING: line length of 105 exceeds 100 columns
#14146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14122:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14123:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae

WARNING: line length of 105 exceeds 100 columns
#14148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14124:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14125:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af

WARNING: line length of 105 exceeds 100 columns
#14150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14126:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14127:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0

WARNING: line length of 105 exceeds 100 columns
#14152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14128:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14129:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1

WARNING: line length of 105 exceeds 100 columns
#14154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14130:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14131:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2

WARNING: line length of 105 exceeds 100 columns
#14156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14132:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14133:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3

WARNING: line length of 105 exceeds 100 columns
#14158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14134:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14135:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4

WARNING: line length of 105 exceeds 100 columns
#14160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14136:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14137:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5

WARNING: line length of 105 exceeds 100 columns
#14162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14138:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14139:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6

WARNING: line length of 105 exceeds 100 columns
#14164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14140:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14141:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7

WARNING: line length of 105 exceeds 100 columns
#14166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14142:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14143:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8

WARNING: line length of 105 exceeds 100 columns
#14168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14144:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14145:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9

WARNING: line length of 105 exceeds 100 columns
#14170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14146:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14147:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba

WARNING: line length of 105 exceeds 100 columns
#14172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14148:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14149:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb

WARNING: line length of 105 exceeds 100 columns
#14174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14150:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14151:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc

WARNING: line length of 105 exceeds 100 columns
#14176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14152:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14153:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd

WARNING: line length of 105 exceeds 100 columns
#14178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14154:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14155:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be

WARNING: line length of 105 exceeds 100 columns
#14180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14156:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14157:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf

WARNING: line length of 105 exceeds 100 columns
#14182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14158:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14159:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0

WARNING: line length of 105 exceeds 100 columns
#14184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14160:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14161:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1

WARNING: line length of 105 exceeds 100 columns
#14186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14162:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14163:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2

WARNING: line length of 105 exceeds 100 columns
#14188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14164:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14165:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3

WARNING: line length of 105 exceeds 100 columns
#14190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14166:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14167:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4

WARNING: line length of 105 exceeds 100 columns
#14192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14168:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14169:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5

WARNING: line length of 105 exceeds 100 columns
#14194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14170:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14171:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6

WARNING: line length of 105 exceeds 100 columns
#14196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14172:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14173:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7

WARNING: line length of 105 exceeds 100 columns
#14198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14174:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14175:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8

WARNING: line length of 105 exceeds 100 columns
#14200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14176:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14177:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9

WARNING: line length of 105 exceeds 100 columns
#14202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14178:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14179:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca

WARNING: line length of 105 exceeds 100 columns
#14204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14180:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14181:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb

WARNING: line length of 105 exceeds 100 columns
#14206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14182:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14183:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc

WARNING: line length of 105 exceeds 100 columns
#14208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14184:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14185:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd

WARNING: line length of 105 exceeds 100 columns
#14210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14186:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14187:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce

WARNING: line length of 105 exceeds 100 columns
#14212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14188:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14189:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf

WARNING: line length of 105 exceeds 100 columns
#14214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14190:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14191:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0

WARNING: line length of 105 exceeds 100 columns
#14216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14192:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14193:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1

WARNING: line length of 105 exceeds 100 columns
#14218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14194:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14195:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2

WARNING: line length of 105 exceeds 100 columns
#14220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14196:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14197:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3

WARNING: line length of 105 exceeds 100 columns
#14222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14198:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14199:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4

WARNING: line length of 105 exceeds 100 columns
#14224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14200:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14201:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5

WARNING: line length of 105 exceeds 100 columns
#14226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14202:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14203:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6

WARNING: line length of 105 exceeds 100 columns
#14228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14204:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14205:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7

WARNING: line length of 105 exceeds 100 columns
#14230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14206:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14207:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8

WARNING: line length of 105 exceeds 100 columns
#14232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14208:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14209:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9

WARNING: line length of 105 exceeds 100 columns
#14234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14210:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14211:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da

WARNING: line length of 105 exceeds 100 columns
#14236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14212:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14213:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db

WARNING: line length of 105 exceeds 100 columns
#14238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14214:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14215:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc

WARNING: line length of 105 exceeds 100 columns
#14240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14216:
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14217:
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04dd

WARNING: line length of 105 exceeds 100 columns
#14242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14218:
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#14247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14223:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x04e3

WARNING: line length of 105 exceeds 100 columns
#14248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14224:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14225:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x04e4

WARNING: line length of 105 exceeds 100 columns
#14250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14226:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14227:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x04e5

WARNING: line length of 105 exceeds 100 columns
#14252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14228:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14229:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x04e6

WARNING: line length of 105 exceeds 100 columns
#14254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14230:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14231:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x04e7

WARNING: line length of 105 exceeds 100 columns
#14256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14232:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14233:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x04e8

WARNING: line length of 105 exceeds 100 columns
#14258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14234:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14235:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x04e9

WARNING: line length of 105 exceeds 100 columns
#14260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14236:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14237:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x04ea

WARNING: line length of 105 exceeds 100 columns
#14262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14238:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14239:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x04eb

WARNING: line length of 105 exceeds 100 columns
#14264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14240:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14241:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x04ec

WARNING: line length of 105 exceeds 100 columns
#14266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14242:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14243:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x04ed

WARNING: line length of 105 exceeds 100 columns
#14268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14244:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14245:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x04ee

WARNING: line length of 105 exceeds 100 columns
#14270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14246:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14247:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x04ef

WARNING: line length of 105 exceeds 100 columns
#14272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14248:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14249:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x04f0

WARNING: line length of 105 exceeds 100 columns
#14274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14250:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14251:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x04f1

WARNING: line length of 105 exceeds 100 columns
#14276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14252:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14253:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x04f2

WARNING: line length of 105 exceeds 100 columns
#14278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14254:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14255:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x04f3

WARNING: line length of 105 exceeds 100 columns
#14280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14256:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14257:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x04f4

WARNING: line length of 105 exceeds 100 columns
#14282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14258:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14259:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x04f5

WARNING: line length of 105 exceeds 100 columns
#14284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14260:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14261:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x04f6

WARNING: line length of 105 exceeds 100 columns
#14286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14262:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14263:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x04f7

WARNING: line length of 105 exceeds 100 columns
#14288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14264:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14265:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x04f8

WARNING: line length of 105 exceeds 100 columns
#14290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14266:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14267:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x04f9

WARNING: line length of 105 exceeds 100 columns
#14292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14268:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14269:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x04fa

WARNING: line length of 105 exceeds 100 columns
#14294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14270:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14271:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x04fb

WARNING: line length of 105 exceeds 100 columns
#14296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14272:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14273:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x04fc

WARNING: line length of 105 exceeds 100 columns
#14298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14274:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14275:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x04fd

WARNING: line length of 105 exceeds 100 columns
#14300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14276:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14277:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x04fe

WARNING: line length of 105 exceeds 100 columns
#14302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14278:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14279:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x04ff

WARNING: line length of 105 exceeds 100 columns
#14304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14280:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14281:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0500

WARNING: line length of 105 exceeds 100 columns
#14306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14282:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14283:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0501

WARNING: line length of 105 exceeds 100 columns
#14308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14284:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14285:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0502

WARNING: line length of 105 exceeds 100 columns
#14310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14286:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14287:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0503

WARNING: line length of 105 exceeds 100 columns
#14312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14288:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14289:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0504

WARNING: line length of 105 exceeds 100 columns
#14314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14290:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14291:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0505

WARNING: line length of 105 exceeds 100 columns
#14316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14292:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14293:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0506

WARNING: line length of 105 exceeds 100 columns
#14318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14294:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14295:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0507

WARNING: line length of 105 exceeds 100 columns
#14320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14296:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14297:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0508

WARNING: line length of 105 exceeds 100 columns
#14322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14298:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14299:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0509

WARNING: line length of 105 exceeds 100 columns
#14324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14300:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14301:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x050a

WARNING: line length of 105 exceeds 100 columns
#14326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14302:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14303:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x050b

WARNING: line length of 105 exceeds 100 columns
#14328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14304:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14305:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x050c

WARNING: line length of 105 exceeds 100 columns
#14330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14306:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14307:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x050d

WARNING: line length of 105 exceeds 100 columns
#14332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14308:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14309:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x050e

WARNING: line length of 105 exceeds 100 columns
#14334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14310:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14311:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x050f

WARNING: line length of 105 exceeds 100 columns
#14336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14312:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14313:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0510

WARNING: line length of 105 exceeds 100 columns
#14338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14314:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14315:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0511

WARNING: line length of 105 exceeds 100 columns
#14340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14316:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14317:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0512

WARNING: line length of 105 exceeds 100 columns
#14342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14318:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14319:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0513

WARNING: line length of 105 exceeds 100 columns
#14344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14320:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14321:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0514

WARNING: line length of 105 exceeds 100 columns
#14346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14322:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14323:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0515

WARNING: line length of 105 exceeds 100 columns
#14348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14324:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14325:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0516

WARNING: line length of 105 exceeds 100 columns
#14350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14326:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14327:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0517

WARNING: line length of 105 exceeds 100 columns
#14352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14328:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14329:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0518

WARNING: line length of 105 exceeds 100 columns
#14354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14330:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14331:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0519

WARNING: line length of 105 exceeds 100 columns
#14356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14332:
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14333:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x051a

WARNING: line length of 105 exceeds 100 columns
#14358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14334:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14335:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x051b

WARNING: line length of 105 exceeds 100 columns
#14360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14336:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#14361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14337:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x051c

WARNING: line length of 105 exceeds 100 columns
#14362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14338:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14339:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x051d

WARNING: line length of 105 exceeds 100 columns
#14364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14340:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14341:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x051e

WARNING: line length of 105 exceeds 100 columns
#14366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14342:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14343:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x051f

WARNING: line length of 105 exceeds 100 columns
#14368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14344:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14345:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0520

WARNING: line length of 105 exceeds 100 columns
#14370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14346:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14347:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0521

WARNING: line length of 105 exceeds 100 columns
#14372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14348:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14349:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0522

WARNING: line length of 105 exceeds 100 columns
#14374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14350:
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14351:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0523

WARNING: line length of 105 exceeds 100 columns
#14376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14352:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#14377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14353:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0524

WARNING: line length of 105 exceeds 100 columns
#14378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14354:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14355:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0525

WARNING: line length of 105 exceeds 100 columns
#14380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14356:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14357:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0526

WARNING: line length of 105 exceeds 100 columns
#14382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14358:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#14383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14359:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0527

WARNING: line length of 105 exceeds 100 columns
#14384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14360:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14361:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0528

WARNING: line length of 105 exceeds 100 columns
#14386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14362:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14363:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0529

WARNING: line length of 105 exceeds 100 columns
#14388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14364:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14365:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x052a

WARNING: line length of 105 exceeds 100 columns
#14390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14366:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14367:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x052b

WARNING: line length of 105 exceeds 100 columns
#14392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14368:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14369:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x052c

WARNING: line length of 105 exceeds 100 columns
#14394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14370:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14371:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x052d

WARNING: line length of 105 exceeds 100 columns
#14396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14372:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14373:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x052e

WARNING: line length of 105 exceeds 100 columns
#14398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14374:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14375:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x052f

WARNING: line length of 105 exceeds 100 columns
#14400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14376:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14377:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0530

WARNING: line length of 105 exceeds 100 columns
#14402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14378:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14379:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0531

WARNING: line length of 105 exceeds 100 columns
#14404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14380:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14381:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0532

WARNING: line length of 105 exceeds 100 columns
#14406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14382:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14383:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0533

WARNING: line length of 105 exceeds 100 columns
#14408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14384:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14385:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0534

WARNING: line length of 105 exceeds 100 columns
#14410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14386:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14387:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0535

WARNING: line length of 105 exceeds 100 columns
#14412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14388:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14389:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0536

WARNING: line length of 105 exceeds 100 columns
#14414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14390:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14391:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0537

WARNING: line length of 105 exceeds 100 columns
#14416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14392:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14393:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0538

WARNING: line length of 105 exceeds 100 columns
#14418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14394:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14395:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0539

WARNING: line length of 105 exceeds 100 columns
#14420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14396:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14397:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x053a

WARNING: line length of 105 exceeds 100 columns
#14422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14398:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14399:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x053b

WARNING: line length of 105 exceeds 100 columns
#14424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14400:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14401:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x053c

WARNING: line length of 105 exceeds 100 columns
#14426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14402:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14403:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x053d

WARNING: line length of 105 exceeds 100 columns
#14428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14404:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14405:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x053e

WARNING: line length of 105 exceeds 100 columns
#14430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14406:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14407:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x053f

WARNING: line length of 105 exceeds 100 columns
#14432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14408:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14409:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0540

WARNING: line length of 105 exceeds 100 columns
#14434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14410:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14411:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0541

WARNING: line length of 105 exceeds 100 columns
#14436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14412:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14413:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0542

WARNING: line length of 105 exceeds 100 columns
#14438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14414:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14415:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0543

WARNING: line length of 105 exceeds 100 columns
#14440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14416:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14417:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0544

WARNING: line length of 105 exceeds 100 columns
#14442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14418:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14419:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0545

WARNING: line length of 105 exceeds 100 columns
#14444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14420:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14421:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0546

WARNING: line length of 105 exceeds 100 columns
#14446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14422:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14423:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0547

WARNING: line length of 105 exceeds 100 columns
#14448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14424:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14425:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0548

WARNING: line length of 105 exceeds 100 columns
#14450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14426:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14427:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0549

WARNING: line length of 105 exceeds 100 columns
#14452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14428:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14429:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x054a

WARNING: line length of 105 exceeds 100 columns
#14454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14430:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14431:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x054b

WARNING: line length of 105 exceeds 100 columns
#14456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14432:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14433:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x054c

WARNING: line length of 105 exceeds 100 columns
#14458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14434:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14435:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x054d

WARNING: line length of 105 exceeds 100 columns
#14460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14436:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14437:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x054e

WARNING: line length of 105 exceeds 100 columns
#14462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14438:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14439:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x054f

WARNING: line length of 105 exceeds 100 columns
#14464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14440:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14441:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0550

WARNING: line length of 105 exceeds 100 columns
#14466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14442:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14443:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0551

WARNING: line length of 105 exceeds 100 columns
#14468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14444:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14445:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0552

WARNING: line length of 105 exceeds 100 columns
#14470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14446:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14447:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0553

WARNING: line length of 105 exceeds 100 columns
#14472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14448:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14449:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0554

WARNING: line length of 105 exceeds 100 columns
#14474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14450:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14451:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0555

WARNING: line length of 105 exceeds 100 columns
#14476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14452:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14453:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0556

WARNING: line length of 105 exceeds 100 columns
#14478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14454:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14455:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0557

WARNING: line length of 105 exceeds 100 columns
#14480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14456:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14457:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0558

WARNING: line length of 105 exceeds 100 columns
#14482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14458:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14459:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0559

WARNING: line length of 105 exceeds 100 columns
#14484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14460:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14461:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x055a

WARNING: line length of 105 exceeds 100 columns
#14486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14462:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14463:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x055b

WARNING: line length of 105 exceeds 100 columns
#14488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14464:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14465:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x055c

WARNING: line length of 105 exceeds 100 columns
#14490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14466:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14467:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x055d

WARNING: line length of 105 exceeds 100 columns
#14492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14468:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14469:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x055e

WARNING: line length of 105 exceeds 100 columns
#14494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14470:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14471:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x055f

WARNING: line length of 105 exceeds 100 columns
#14496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14472:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14473:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0560

WARNING: line length of 105 exceeds 100 columns
#14498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14474:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14475:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0561

WARNING: line length of 105 exceeds 100 columns
#14500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14476:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14477:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0562

WARNING: line length of 105 exceeds 100 columns
#14502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14478:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14479:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0563

WARNING: line length of 105 exceeds 100 columns
#14504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14480:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14481:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0564

WARNING: line length of 105 exceeds 100 columns
#14506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14482:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14483:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0565

WARNING: line length of 105 exceeds 100 columns
#14508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14484:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14485:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0566

WARNING: line length of 105 exceeds 100 columns
#14510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14486:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14487:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0567

WARNING: line length of 105 exceeds 100 columns
#14512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14488:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14489:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0568

WARNING: line length of 105 exceeds 100 columns
#14514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14490:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14491:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0569

WARNING: line length of 105 exceeds 100 columns
#14516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14492:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14493:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x056a

WARNING: line length of 105 exceeds 100 columns
#14518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14494:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14495:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x056b

WARNING: line length of 105 exceeds 100 columns
#14520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14496:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14497:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x056c

WARNING: line length of 105 exceeds 100 columns
#14522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14498:
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14499:
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x056d

WARNING: line length of 105 exceeds 100 columns
#14524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14500:
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#14529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14505:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x0573

WARNING: line length of 105 exceeds 100 columns
#14530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14506:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14507:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0574

WARNING: line length of 105 exceeds 100 columns
#14532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14508:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14509:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0575

WARNING: line length of 105 exceeds 100 columns
#14534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14510:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14511:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0576

WARNING: line length of 105 exceeds 100 columns
#14536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14512:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14513:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x0577

WARNING: line length of 105 exceeds 100 columns
#14538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14514:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14515:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0578

WARNING: line length of 105 exceeds 100 columns
#14540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14516:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14517:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0579

WARNING: line length of 105 exceeds 100 columns
#14542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14518:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14519:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x057a

WARNING: line length of 105 exceeds 100 columns
#14544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14520:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14521:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x057b

WARNING: line length of 105 exceeds 100 columns
#14546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14522:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14523:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x057c

WARNING: line length of 105 exceeds 100 columns
#14548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14524:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14525:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x057d

WARNING: line length of 105 exceeds 100 columns
#14550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14526:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14527:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x057e

WARNING: line length of 105 exceeds 100 columns
#14552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14528:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14529:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x057f

WARNING: line length of 105 exceeds 100 columns
#14554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14530:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14531:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0580

WARNING: line length of 105 exceeds 100 columns
#14556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14532:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14533:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0581

WARNING: line length of 105 exceeds 100 columns
#14558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14534:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14535:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0582

WARNING: line length of 105 exceeds 100 columns
#14560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14536:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14537:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0583

WARNING: line length of 105 exceeds 100 columns
#14562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14538:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14539:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0584

WARNING: line length of 105 exceeds 100 columns
#14564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14540:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14541:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0585

WARNING: line length of 105 exceeds 100 columns
#14566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14542:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14543:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0586

WARNING: line length of 105 exceeds 100 columns
#14568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14544:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14545:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0587

WARNING: line length of 105 exceeds 100 columns
#14570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14546:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14547:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0588

WARNING: line length of 105 exceeds 100 columns
#14572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14548:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14549:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0589

WARNING: line length of 105 exceeds 100 columns
#14574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14550:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14551:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x058a

WARNING: line length of 105 exceeds 100 columns
#14576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14552:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14553:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x058b

WARNING: line length of 105 exceeds 100 columns
#14578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14554:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14555:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x058c

WARNING: line length of 105 exceeds 100 columns
#14580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14556:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14557:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x058d

WARNING: line length of 105 exceeds 100 columns
#14582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14558:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14559:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x058e

WARNING: line length of 105 exceeds 100 columns
#14584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14560:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14561:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x058f

WARNING: line length of 105 exceeds 100 columns
#14586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14562:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14563:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0590

WARNING: line length of 105 exceeds 100 columns
#14588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14564:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14565:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0591

WARNING: line length of 105 exceeds 100 columns
#14590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14566:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14567:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0592

WARNING: line length of 105 exceeds 100 columns
#14592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14568:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14569:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0593

WARNING: line length of 105 exceeds 100 columns
#14594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14570:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14571:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0594

WARNING: line length of 105 exceeds 100 columns
#14596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14572:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14573:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0595

WARNING: line length of 105 exceeds 100 columns
#14598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14574:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14575:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0596

WARNING: line length of 105 exceeds 100 columns
#14600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14576:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14577:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0597

WARNING: line length of 105 exceeds 100 columns
#14602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14578:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14579:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0598

WARNING: line length of 105 exceeds 100 columns
#14604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14580:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14581:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0599

WARNING: line length of 105 exceeds 100 columns
#14606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14582:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14583:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x059a

WARNING: line length of 105 exceeds 100 columns
#14608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14584:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14585:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x059b

WARNING: line length of 105 exceeds 100 columns
#14610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14586:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14587:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x059c

WARNING: line length of 105 exceeds 100 columns
#14612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14588:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14589:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x059d

WARNING: line length of 105 exceeds 100 columns
#14614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14590:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14591:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x059e

WARNING: line length of 105 exceeds 100 columns
#14616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14592:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14593:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x059f

WARNING: line length of 105 exceeds 100 columns
#14618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14594:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14595:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05a0

WARNING: line length of 105 exceeds 100 columns
#14620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14596:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14597:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05a1

WARNING: line length of 105 exceeds 100 columns
#14622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14598:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14599:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05a2

WARNING: line length of 105 exceeds 100 columns
#14624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14600:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14601:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05a3

WARNING: line length of 105 exceeds 100 columns
#14626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14602:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14603:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05a4

WARNING: line length of 105 exceeds 100 columns
#14628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14604:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14605:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05a5

WARNING: line length of 105 exceeds 100 columns
#14630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14606:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14607:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05a6

WARNING: line length of 105 exceeds 100 columns
#14632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14608:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14609:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05a7

WARNING: line length of 105 exceeds 100 columns
#14634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14610:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14611:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05a8

WARNING: line length of 105 exceeds 100 columns
#14636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14612:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14613:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05a9

WARNING: line length of 105 exceeds 100 columns
#14638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14614:
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14615:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05aa

WARNING: line length of 105 exceeds 100 columns
#14640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14616:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14617:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05ab

WARNING: line length of 105 exceeds 100 columns
#14642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14618:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#14643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14619:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ac

WARNING: line length of 105 exceeds 100 columns
#14644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14620:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14621:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ad

WARNING: line length of 105 exceeds 100 columns
#14646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14622:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14623:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ae

WARNING: line length of 105 exceeds 100 columns
#14648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14624:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14625:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05af

WARNING: line length of 105 exceeds 100 columns
#14650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14626:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14627:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05b0

WARNING: line length of 105 exceeds 100 columns
#14652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14628:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14629:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05b1

WARNING: line length of 105 exceeds 100 columns
#14654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14630:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14631:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05b2

WARNING: line length of 105 exceeds 100 columns
#14656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14632:
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14633:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05b3

WARNING: line length of 105 exceeds 100 columns
#14658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14634:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#14659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14635:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05b4

WARNING: line length of 105 exceeds 100 columns
#14660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14636:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14637:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05b5

WARNING: line length of 105 exceeds 100 columns
#14662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14638:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14639:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05b6

WARNING: line length of 105 exceeds 100 columns
#14664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14640:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#14665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14641:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05b7

WARNING: line length of 105 exceeds 100 columns
#14666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14642:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14643:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05b8

WARNING: line length of 105 exceeds 100 columns
#14668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14644:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14645:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05b9

WARNING: line length of 105 exceeds 100 columns
#14670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14646:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14647:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05ba

WARNING: line length of 105 exceeds 100 columns
#14672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14648:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14649:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05bb

WARNING: line length of 105 exceeds 100 columns
#14674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14650:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14651:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05bc

WARNING: line length of 105 exceeds 100 columns
#14676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14652:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14653:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05bd

WARNING: line length of 105 exceeds 100 columns
#14678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14654:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14655:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05be

WARNING: line length of 105 exceeds 100 columns
#14680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14656:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14657:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05bf

WARNING: line length of 105 exceeds 100 columns
#14682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14658:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14659:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x05c0

WARNING: line length of 105 exceeds 100 columns
#14684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14660:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14661:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x05c1

WARNING: line length of 105 exceeds 100 columns
#14686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14662:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14663:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x05c2

WARNING: line length of 105 exceeds 100 columns
#14688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14664:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14665:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x05c3

WARNING: line length of 105 exceeds 100 columns
#14690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14666:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14667:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x05c4

WARNING: line length of 105 exceeds 100 columns
#14692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14668:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14669:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x05c5

WARNING: line length of 105 exceeds 100 columns
#14694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14670:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14671:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x05c6

WARNING: line length of 105 exceeds 100 columns
#14696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14672:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14673:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x05c7

WARNING: line length of 105 exceeds 100 columns
#14698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14674:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14675:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x05c8

WARNING: line length of 105 exceeds 100 columns
#14700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14676:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14677:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x05c9

WARNING: line length of 105 exceeds 100 columns
#14702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14678:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14679:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x05ca

WARNING: line length of 105 exceeds 100 columns
#14704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14680:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14681:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x05cb

WARNING: line length of 105 exceeds 100 columns
#14706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14682:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14683:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x05cc

WARNING: line length of 105 exceeds 100 columns
#14708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14684:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14685:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x05cd

WARNING: line length of 105 exceeds 100 columns
#14710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14686:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14687:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x05ce

WARNING: line length of 105 exceeds 100 columns
#14712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14688:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14689:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x05cf

WARNING: line length of 105 exceeds 100 columns
#14714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14690:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14691:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x05d0

WARNING: line length of 105 exceeds 100 columns
#14716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14692:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14693:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x05d1

WARNING: line length of 105 exceeds 100 columns
#14718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14694:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14695:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x05d2

WARNING: line length of 105 exceeds 100 columns
#14720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14696:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14697:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x05d3

WARNING: line length of 105 exceeds 100 columns
#14722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14698:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14699:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x05d4

WARNING: line length of 105 exceeds 100 columns
#14724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14700:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14701:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x05d5

WARNING: line length of 105 exceeds 100 columns
#14726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14702:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14703:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x05d6

WARNING: line length of 105 exceeds 100 columns
#14728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14704:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14705:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x05d7

WARNING: line length of 105 exceeds 100 columns
#14730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14706:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14707:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x05d8

WARNING: line length of 105 exceeds 100 columns
#14732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14708:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14709:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x05d9

WARNING: line length of 105 exceeds 100 columns
#14734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14710:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14711:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x05da

WARNING: line length of 105 exceeds 100 columns
#14736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14712:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14713:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x05db

WARNING: line length of 105 exceeds 100 columns
#14738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14714:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14715:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x05dc

WARNING: line length of 105 exceeds 100 columns
#14740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14716:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14717:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x05dd

WARNING: line length of 105 exceeds 100 columns
#14742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14718:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14719:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x05de

WARNING: line length of 105 exceeds 100 columns
#14744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14720:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14721:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x05df

WARNING: line length of 105 exceeds 100 columns
#14746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14722:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14723:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x05e0

WARNING: line length of 105 exceeds 100 columns
#14748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14724:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14725:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x05e1

WARNING: line length of 105 exceeds 100 columns
#14750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14726:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14727:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x05e2

WARNING: line length of 105 exceeds 100 columns
#14752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14728:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14729:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x05e3

WARNING: line length of 105 exceeds 100 columns
#14754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14730:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14731:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x05e4

WARNING: line length of 105 exceeds 100 columns
#14756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14732:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14733:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x05e5

WARNING: line length of 105 exceeds 100 columns
#14758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14734:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14735:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x05e6

WARNING: line length of 105 exceeds 100 columns
#14760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14736:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14737:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x05e7

WARNING: line length of 105 exceeds 100 columns
#14762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14738:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14739:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x05e8

WARNING: line length of 105 exceeds 100 columns
#14764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14740:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14741:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x05e9

WARNING: line length of 105 exceeds 100 columns
#14766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14742:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14743:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x05ea

WARNING: line length of 105 exceeds 100 columns
#14768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14744:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14745:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x05eb

WARNING: line length of 105 exceeds 100 columns
#14770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14746:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14747:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x05ec

WARNING: line length of 105 exceeds 100 columns
#14772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14748:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14749:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x05ed

WARNING: line length of 105 exceeds 100 columns
#14774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14750:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14751:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x05ee

WARNING: line length of 105 exceeds 100 columns
#14776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14752:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14753:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x05ef

WARNING: line length of 105 exceeds 100 columns
#14778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14754:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14755:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x05f0

WARNING: line length of 105 exceeds 100 columns
#14780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14756:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14757:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x05f1

WARNING: line length of 105 exceeds 100 columns
#14782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14758:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14759:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x05f2

WARNING: line length of 105 exceeds 100 columns
#14784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14760:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14761:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x05f3

WARNING: line length of 105 exceeds 100 columns
#14786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14762:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14763:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x05f4

WARNING: line length of 105 exceeds 100 columns
#14788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14764:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14765:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x05f5

WARNING: line length of 105 exceeds 100 columns
#14790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14766:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14767:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x05f6

WARNING: line length of 105 exceeds 100 columns
#14792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14768:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14769:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x05f7

WARNING: line length of 105 exceeds 100 columns
#14794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14770:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14771:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x05f8

WARNING: line length of 105 exceeds 100 columns
#14796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14772:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14773:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x05f9

WARNING: line length of 105 exceeds 100 columns
#14798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14774:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14775:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x05fa

WARNING: line length of 105 exceeds 100 columns
#14800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14776:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14777:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x05fb

WARNING: line length of 105 exceeds 100 columns
#14802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14778:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14779:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x05fc

WARNING: line length of 105 exceeds 100 columns
#14804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14780:
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14781:
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x05fd

WARNING: line length of 105 exceeds 100 columns
#14806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14782:
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#14811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14787:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0603

WARNING: line length of 105 exceeds 100 columns
#14812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14788:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14789:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0604

WARNING: line length of 105 exceeds 100 columns
#14814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14790:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14791:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0605

WARNING: line length of 105 exceeds 100 columns
#14816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14792:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14793:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0606

WARNING: line length of 105 exceeds 100 columns
#14818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14794:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14795:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0607

WARNING: line length of 105 exceeds 100 columns
#14820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14796:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14797:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0608

WARNING: line length of 105 exceeds 100 columns
#14822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14798:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14799:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0609

WARNING: line length of 105 exceeds 100 columns
#14824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14800:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14801:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x060a

WARNING: line length of 105 exceeds 100 columns
#14826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14802:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14803:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x060b

WARNING: line length of 105 exceeds 100 columns
#14828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14804:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14805:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x060c

WARNING: line length of 105 exceeds 100 columns
#14830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14806:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14807:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x060d

WARNING: line length of 105 exceeds 100 columns
#14832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14808:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14809:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x060e

WARNING: line length of 105 exceeds 100 columns
#14834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14810:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14811:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x060f

WARNING: line length of 105 exceeds 100 columns
#14836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14812:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14813:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0610

WARNING: line length of 105 exceeds 100 columns
#14838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14814:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14815:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0611

WARNING: line length of 105 exceeds 100 columns
#14840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14816:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14817:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0612

WARNING: line length of 105 exceeds 100 columns
#14842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14818:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14819:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0613

WARNING: line length of 105 exceeds 100 columns
#14844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14820:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14821:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0614

WARNING: line length of 105 exceeds 100 columns
#14846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14822:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14823:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0615

WARNING: line length of 105 exceeds 100 columns
#14848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14824:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14825:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0616

WARNING: line length of 105 exceeds 100 columns
#14850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14826:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14827:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0617

WARNING: line length of 105 exceeds 100 columns
#14852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14828:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14829:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0618

WARNING: line length of 105 exceeds 100 columns
#14854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14830:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14831:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0619

WARNING: line length of 105 exceeds 100 columns
#14856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14832:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14833:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x061a

WARNING: line length of 105 exceeds 100 columns
#14858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14834:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14835:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x061b

WARNING: line length of 105 exceeds 100 columns
#14860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14836:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14837:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x061c

WARNING: line length of 105 exceeds 100 columns
#14862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14838:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14839:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x061d

WARNING: line length of 105 exceeds 100 columns
#14864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14840:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14841:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x061e

WARNING: line length of 105 exceeds 100 columns
#14866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14842:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14843:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x061f

WARNING: line length of 105 exceeds 100 columns
#14868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14844:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14845:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0620

WARNING: line length of 105 exceeds 100 columns
#14870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14846:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14847:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0621

WARNING: line length of 105 exceeds 100 columns
#14872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14848:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14849:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0622

WARNING: line length of 105 exceeds 100 columns
#14874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14850:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14851:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0623

WARNING: line length of 105 exceeds 100 columns
#14876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14852:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14853:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0624

WARNING: line length of 105 exceeds 100 columns
#14878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14854:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14855:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0625

WARNING: line length of 105 exceeds 100 columns
#14880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14856:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14857:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0626

WARNING: line length of 105 exceeds 100 columns
#14882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14858:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14859:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0627

WARNING: line length of 105 exceeds 100 columns
#14884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14860:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14861:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0628

WARNING: line length of 105 exceeds 100 columns
#14886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14862:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14863:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0629

WARNING: line length of 105 exceeds 100 columns
#14888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14864:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14865:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x062a

WARNING: line length of 105 exceeds 100 columns
#14890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14866:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14867:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x062b

WARNING: line length of 105 exceeds 100 columns
#14892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14868:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14869:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x062c

WARNING: line length of 105 exceeds 100 columns
#14894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14870:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14871:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x062d

WARNING: line length of 105 exceeds 100 columns
#14896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14872:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14873:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x062e

WARNING: line length of 105 exceeds 100 columns
#14898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14874:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14875:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x062f

WARNING: line length of 105 exceeds 100 columns
#14900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14876:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14877:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0630

WARNING: line length of 105 exceeds 100 columns
#14902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14878:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14879:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0631

WARNING: line length of 105 exceeds 100 columns
#14904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14880:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14881:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0632

WARNING: line length of 105 exceeds 100 columns
#14906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14882:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14883:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0633

WARNING: line length of 105 exceeds 100 columns
#14908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14884:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14885:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0634

WARNING: line length of 105 exceeds 100 columns
#14910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14886:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14887:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0635

WARNING: line length of 105 exceeds 100 columns
#14912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14888:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14889:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0636

WARNING: line length of 105 exceeds 100 columns
#14914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14890:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14891:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0637

WARNING: line length of 105 exceeds 100 columns
#14916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14892:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14893:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0638

WARNING: line length of 105 exceeds 100 columns
#14918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14894:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14895:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0639

WARNING: line length of 105 exceeds 100 columns
#14920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14896:
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14897:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x063a

WARNING: line length of 105 exceeds 100 columns
#14922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14898:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14899:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x063b

WARNING: line length of 105 exceeds 100 columns
#14924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14900:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3

WARNING: line length of 110 exceeds 100 columns
#14925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14901:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x063c

WARNING: line length of 105 exceeds 100 columns
#14926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14902:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3

WARNING: line length of 110 exceeds 100 columns
#14927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14903:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x063d

WARNING: line length of 105 exceeds 100 columns
#14928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14904:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3

WARNING: line length of 110 exceeds 100 columns
#14929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14905:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x063e

WARNING: line length of 105 exceeds 100 columns
#14930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14906:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3

WARNING: line length of 110 exceeds 100 columns
#14931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14907:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x063f

WARNING: line length of 105 exceeds 100 columns
#14932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14908:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14909:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0640

WARNING: line length of 105 exceeds 100 columns
#14934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14910:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14911:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0641

WARNING: line length of 105 exceeds 100 columns
#14936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14912:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14913:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0642

WARNING: line length of 105 exceeds 100 columns
#14938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14914:
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3

WARNING: line length of 110 exceeds 100 columns
#14939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14915:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x0643

WARNING: line length of 105 exceeds 100 columns
#14940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14916:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3

WARNING: line length of 110 exceeds 100 columns
#14941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14917:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0644

WARNING: line length of 105 exceeds 100 columns
#14942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14918:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3

WARNING: line length of 110 exceeds 100 columns
#14943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14919:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0645

WARNING: line length of 105 exceeds 100 columns
#14944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14920:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3

WARNING: line length of 110 exceeds 100 columns
#14945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14921:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0646

WARNING: line length of 105 exceeds 100 columns
#14946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14922:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3

WARNING: line length of 110 exceeds 100 columns
#14947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14923:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0647

WARNING: line length of 105 exceeds 100 columns
#14948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14924:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14925:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0648

WARNING: line length of 105 exceeds 100 columns
#14950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14926:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14927:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0649

WARNING: line length of 105 exceeds 100 columns
#14952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14928:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14929:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x064a

WARNING: line length of 105 exceeds 100 columns
#14954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14930:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14931:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x064b

WARNING: line length of 105 exceeds 100 columns
#14956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14932:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14933:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x064c

WARNING: line length of 105 exceeds 100 columns
#14958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14934:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#14959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14935:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x064d

WARNING: line length of 105 exceeds 100 columns
#14960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14936:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14937:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x064e

WARNING: line length of 105 exceeds 100 columns
#14962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14938:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14939:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x064f

WARNING: line length of 105 exceeds 100 columns
#14964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14940:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#14965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14941:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0650

WARNING: line length of 105 exceeds 100 columns
#14966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14942:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14943:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0651

WARNING: line length of 105 exceeds 100 columns
#14968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14944:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14945:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0652

WARNING: line length of 105 exceeds 100 columns
#14970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14946:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14947:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0653

WARNING: line length of 105 exceeds 100 columns
#14972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14948:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14949:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0654

WARNING: line length of 105 exceeds 100 columns
#14974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14950:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14951:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0655

WARNING: line length of 105 exceeds 100 columns
#14976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14952:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#14977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14953:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0656

WARNING: line length of 105 exceeds 100 columns
#14978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14954:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14955:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0657

WARNING: line length of 105 exceeds 100 columns
#14980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14956:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14957:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0658

WARNING: line length of 105 exceeds 100 columns
#14982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14958:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#14983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14959:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0659

WARNING: line length of 105 exceeds 100 columns
#14984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14960:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14961:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x065a

WARNING: line length of 105 exceeds 100 columns
#14986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14962:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14963:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x065b

WARNING: line length of 105 exceeds 100 columns
#14988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14964:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14965:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x065c

WARNING: line length of 105 exceeds 100 columns
#14990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14966:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14967:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x065d

WARNING: line length of 105 exceeds 100 columns
#14992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14968:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#14993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14969:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x065e

WARNING: line length of 105 exceeds 100 columns
#14994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14970:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14971:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x065f

WARNING: line length of 105 exceeds 100 columns
#14996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14972:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14973:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0660

WARNING: line length of 105 exceeds 100 columns
#14998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14974:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#14999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14975:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0661

WARNING: line length of 105 exceeds 100 columns
#15000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14976:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14977:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0662

WARNING: line length of 105 exceeds 100 columns
#15002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14978:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14979:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0663

WARNING: line length of 105 exceeds 100 columns
#15004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14980:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14981:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0664

WARNING: line length of 105 exceeds 100 columns
#15006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14982:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14983:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0665

WARNING: line length of 105 exceeds 100 columns
#15008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14984:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14985:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0666

WARNING: line length of 105 exceeds 100 columns
#15010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14986:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14987:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0667

WARNING: line length of 105 exceeds 100 columns
#15012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14988:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14989:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0668

WARNING: line length of 105 exceeds 100 columns
#15014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14990:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14991:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0669

WARNING: line length of 105 exceeds 100 columns
#15016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14992:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14993:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x066a

WARNING: line length of 105 exceeds 100 columns
#15018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14994:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14995:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x066b

WARNING: line length of 105 exceeds 100 columns
#15020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14996:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14997:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x066c

WARNING: line length of 105 exceeds 100 columns
#15022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14998:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:14999:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x066d

WARNING: line length of 105 exceeds 100 columns
#15024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15000:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#15025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15001:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x066e

WARNING: line length of 105 exceeds 100 columns
#15026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15002:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#15027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15003:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x066f

WARNING: line length of 105 exceeds 100 columns
#15028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15004:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3

WARNING: line length of 110 exceeds 100 columns
#15029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15005:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0670

WARNING: line length of 105 exceeds 100 columns
#15030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15006:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#15031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15007:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0671

WARNING: line length of 105 exceeds 100 columns
#15032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15008:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#15033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15009:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0672

WARNING: line length of 105 exceeds 100 columns
#15034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15010:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3

WARNING: line length of 110 exceeds 100 columns
#15035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15011:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0673

WARNING: line length of 105 exceeds 100 columns
#15036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15012:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#15037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15013:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0674

WARNING: line length of 105 exceeds 100 columns
#15038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15014:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#15039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15015:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0675

WARNING: line length of 105 exceeds 100 columns
#15040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15016:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#15041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15017:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0676

WARNING: line length of 105 exceeds 100 columns
#15042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15018:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#15043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15019:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0677

WARNING: line length of 105 exceeds 100 columns
#15044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15020:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#15045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15021:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0678

WARNING: line length of 105 exceeds 100 columns
#15046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15022:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3

WARNING: line length of 110 exceeds 100 columns
#15047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15023:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0679

WARNING: line length of 105 exceeds 100 columns
#15048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15024:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#15049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15025:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x067a

WARNING: line length of 105 exceeds 100 columns
#15050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15026:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#15051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15027:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x067b

WARNING: line length of 105 exceeds 100 columns
#15052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15028:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3

WARNING: line length of 110 exceeds 100 columns
#15053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15029:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x067c

WARNING: line length of 105 exceeds 100 columns
#15054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15030:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#15055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15031:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x067d

WARNING: line length of 105 exceeds 100 columns
#15056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15032:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#15057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15033:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x067e

WARNING: line length of 105 exceeds 100 columns
#15058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15034:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#15059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15035:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x067f

WARNING: line length of 105 exceeds 100 columns
#15060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15036:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#15061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15037:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0680

WARNING: line length of 105 exceeds 100 columns
#15062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15038:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3

WARNING: line length of 110 exceeds 100 columns
#15063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15039:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0681

WARNING: line length of 105 exceeds 100 columns
#15064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15040:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15041:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0682

WARNING: line length of 105 exceeds 100 columns
#15066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15042:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15043:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0683

WARNING: line length of 105 exceeds 100 columns
#15068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15044:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15045:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0684

WARNING: line length of 105 exceeds 100 columns
#15070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15046:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15047:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0685

WARNING: line length of 105 exceeds 100 columns
#15072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15048:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15049:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0686

WARNING: line length of 105 exceeds 100 columns
#15074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15050:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15051:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0687

WARNING: line length of 105 exceeds 100 columns
#15076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15052:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15053:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0688

WARNING: line length of 105 exceeds 100 columns
#15078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15054:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15055:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0689

WARNING: line length of 105 exceeds 100 columns
#15080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15056:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15057:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x068a

WARNING: line length of 105 exceeds 100 columns
#15082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15058:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15059:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x068b

WARNING: line length of 105 exceeds 100 columns
#15084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15060:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15061:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x068c

WARNING: line length of 105 exceeds 100 columns
#15086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15062:
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3

WARNING: line length of 110 exceeds 100 columns
#15087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15063:
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x068d

WARNING: line length of 105 exceeds 100 columns
#15088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15064:
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3

WARNING: line length of 110 exceeds 100 columns
#15093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15069:
+#define regDLPC_ENABLE                                                                                  0x2fe8

WARNING: line length of 105 exceeds 100 columns
#15094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15070:
+#define regDLPC_ENABLE_BASE_IDX                                                                         2

WARNING: line length of 110 exceeds 100 columns
#15095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15071:
+#define regDLPC_CURRENT_COUNT                                                                           0x2fe9

WARNING: line length of 105 exceeds 100 columns
#15096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15072:
+#define regDLPC_CURRENT_COUNT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#15097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15073:
+#define regDLPC_OPTC_SNAPSHOT                                                                           0x2fea

WARNING: line length of 105 exceeds 100 columns
#15098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15074:
+#define regDLPC_OPTC_SNAPSHOT_BASE_IDX                                                                  2

WARNING: line length of 110 exceeds 100 columns
#15099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15075:
+#define regDLPC_PWRUP                                                                                   0x2feb

WARNING: line length of 105 exceeds 100 columns
#15100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15076:
+#define regDLPC_PWRUP_BASE_IDX                                                                          2

WARNING: line length of 110 exceeds 100 columns
#15101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15077:
+#define regDLPC_OTG_RESYNC                                                                              0x2fec

WARNING: line length of 105 exceeds 100 columns
#15102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15078:
+#define regDLPC_OTG_RESYNC_BASE_IDX                                                                     2

WARNING: line length of 110 exceeds 100 columns
#15103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15079:
+#define regDLPC_DCN_ZSC_LONO_PWRUP                                                                      0x2fed

WARNING: line length of 105 exceeds 100 columns
#15104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15080:
+#define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX                                                             2

WARNING: line length of 110 exceeds 100 columns
#15105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15081:
+#define regDLPC_SPARE                                                                                   0x2fee

WARNING: line length of 105 exceeds 100 columns
#15106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15082:
+#define regDLPC_SPARE_BASE_IDX                                                                          2

WARNING: line length of 110 exceeds 100 columns
#15107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15083:
+#define regDLPC_COUNTER_INIT_VALUE                                                                      0x2fef

WARNING: line length of 105 exceeds 100 columns
#15108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15084:
+#define regDLPC_COUNTER_INIT_VALUE_BASE_IDX                                                             2

WARNING: line length of 111 exceeds 100 columns
#15113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15089:
+#define regDPIA_MU_CLOCK_CTRL                                                                           0x13800

WARNING: line length of 105 exceeds 100 columns
#15114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15090:
+#define regDPIA_MU_CLOCK_CTRL_BASE_IDX                                                                  3

WARNING: line length of 111 exceeds 100 columns
#15115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15091:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0                                                                0x13801

WARNING: line length of 105 exceeds 100 columns
#15116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15092:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15093:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT0                                                                0x13802

WARNING: line length of 105 exceeds 100 columns
#15118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15094:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15095:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1                                                                0x13803

WARNING: line length of 105 exceeds 100 columns
#15120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15096:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15097:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT1                                                                0x13804

WARNING: line length of 105 exceeds 100 columns
#15122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15098:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15099:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2                                                                0x13805

WARNING: line length of 105 exceeds 100 columns
#15124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15100:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15101:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT2                                                                0x13806

WARNING: line length of 105 exceeds 100 columns
#15126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15102:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15103:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3                                                                0x13807

WARNING: line length of 105 exceeds 100 columns
#15128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15104:
+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15105:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT3                                                                0x13808

WARNING: line length of 105 exceeds 100 columns
#15130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15106:
+#define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15107:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT0                                                                0x13811

WARNING: line length of 105 exceeds 100 columns
#15132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15108:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15109:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT1                                                                0x13812

WARNING: line length of 105 exceeds 100 columns
#15134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15110:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15111:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT2                                                                0x13813

WARNING: line length of 105 exceeds 100 columns
#15136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15112:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15113:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT3                                                                0x13814

WARNING: line length of 105 exceeds 100 columns
#15138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15114:
+#define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX                                                       3

WARNING: line length of 111 exceeds 100 columns
#15139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15115:
+#define regDPIA_MU_TPI_MAX_CREDIT_COUNT                                                                 0x13819

WARNING: line length of 105 exceeds 100 columns
#15140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15116:
+#define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX                                                        3

WARNING: line length of 111 exceeds 100 columns
#15141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15117:
+#define regDPIA_MU_INTERRUPT_STATUS                                                                     0x1381a

WARNING: line length of 105 exceeds 100 columns
#15142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15118:
+#define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX                                                            3

WARNING: line length of 111 exceeds 100 columns
#15143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15119:
+#define regDPIA_MU_INTERRUPT_CTRL                                                                       0x1381b

WARNING: line length of 105 exceeds 100 columns
#15144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15120:
+#define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX                                                              3

WARNING: line length of 111 exceeds 100 columns
#15145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15121:
+#define regDPIA_MU_LOCAL_INTERRUPT_CTRL                                                                 0x1381c

WARNING: line length of 105 exceeds 100 columns
#15146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15122:
+#define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX                                                        3

WARNING: line length of 111 exceeds 100 columns
#15147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15123:
+#define regDPIA_MU_LOCAL_INTERRUPT_ACK                                                                  0x1381d

WARNING: line length of 105 exceeds 100 columns
#15148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15124:
+#define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX                                                         3

WARNING: line length of 111 exceeds 100 columns
#15149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15125:
+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL                                                                  0x1381e

WARNING: line length of 105 exceeds 100 columns
#15150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15126:
+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX                                                         3

WARNING: line length of 111 exceeds 100 columns
#15151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15127:
+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2                                                                 0x1381f

WARNING: line length of 105 exceeds 100 columns
#15152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15128:
+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX                                                        3

WARNING: line length of 111 exceeds 100 columns
#15153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15129:
+#define regDPIA_MU_RBBMIF_STATUS                                                                        0x13820

WARNING: line length of 105 exceeds 100 columns
#15154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15130:
+#define regDPIA_MU_RBBMIF_STATUS_BASE_IDX                                                               3

WARNING: line length of 111 exceeds 100 columns
#15155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15131:
+#define regDPIA_MU_MICROSECOND_REF_CTRL                                                                 0x13821

WARNING: line length of 105 exceeds 100 columns
#15156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15132:
+#define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX                                                        3

WARNING: line length of 111 exceeds 100 columns
#15157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15133:
+#define regDPIA_MU_PORT_ADP_STATUS                                                                      0x13822

WARNING: line length of 105 exceeds 100 columns
#15158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15134:
+#define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX                                                             3

WARNING: line length of 111 exceeds 100 columns
#15159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15135:
+#define regDPIA_GLUE_CTRL                                                                               0x13823

WARNING: line length of 105 exceeds 100 columns
#15160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15136:
+#define regDPIA_GLUE_CTRL_BASE_IDX                                                                      3

WARNING: line length of 111 exceeds 100 columns
#15161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15137:
+#define regDPIA_PERF_COUNT_CONTROL0                                                                     0x13825

WARNING: line length of 105 exceeds 100 columns
#15162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15138:
+#define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX                                                            3

WARNING: line length of 111 exceeds 100 columns
#15163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15139:
+#define regDPIA_PERF_COUNT_CONTROL1                                                                     0x13826

WARNING: line length of 105 exceeds 100 columns
#15164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15140:
+#define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX                                                            3

WARNING: line length of 111 exceeds 100 columns
#15165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15141:
+#define regDPIA_PERF_COUNT_CONTROL2                                                                     0x13827

WARNING: line length of 105 exceeds 100 columns
#15166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15142:
+#define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX                                                            3

WARNING: line length of 111 exceeds 100 columns
#15167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15143:
+#define regDPIA_PERF_COUNT_CONTROL3                                                                     0x13828

WARNING: line length of 105 exceeds 100 columns
#15168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15144:
+#define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX                                                            3

WARNING: line length of 111 exceeds 100 columns
#15169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15145:
+#define regDPIA_PERF_COUNT_CONTROL4                                                                     0x13829

WARNING: line length of 105 exceeds 100 columns
#15170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15146:
+#define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX                                                            3

WARNING: line length of 111 exceeds 100 columns
#15171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15147:
+#define regDPIA_PERF_COUNT_CONTROL5                                                                     0x1382a

WARNING: line length of 105 exceeds 100 columns
#15172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15148:
+#define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX                                                            3

WARNING: line length of 111 exceeds 100 columns
#15173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15149:
+#define regDPIA_PERF_COUNT_INDEX                                                                        0x1382b

WARNING: line length of 105 exceeds 100 columns
#15174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15150:
+#define regDPIA_PERF_COUNT_INDEX_BASE_IDX                                                               3

WARNING: line length of 111 exceeds 100 columns
#15175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15151:
+#define regDPIA_PERF_COUNT_DATA_LO                                                                      0x1382c

WARNING: line length of 105 exceeds 100 columns
#15176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15152:
+#define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX                                                             3

WARNING: line length of 111 exceeds 100 columns
#15177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15153:
+#define regDPIA_MU_SPARE                                                                                0x1382d

WARNING: line length of 105 exceeds 100 columns
#15178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15154:
+#define regDPIA_MU_SPARE_BASE_IDX                                                                       3

WARNING: line length of 110 exceeds 100 columns
#15183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15159:
+#define regAZCONTROLLER1_CORB_WRITE_POINTER                                                             0x0000

WARNING: line length of 105 exceeds 100 columns
#15184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15160:
+#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX                                                    0

WARNING: line length of 110 exceeds 100 columns
#15185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15161:
+#define regAZCONTROLLER1_CORB_READ_POINTER                                                              0x0000

WARNING: line length of 105 exceeds 100 columns
#15186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15162:
+#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX                                                     0

WARNING: line length of 110 exceeds 100 columns
#15187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15163:
+#define regAZCONTROLLER1_CORB_CONTROL                                                                   0x0001

WARNING: line length of 105 exceeds 100 columns
#15188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15164:
+#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX                                                          0

WARNING: line length of 110 exceeds 100 columns
#15189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15165:
+#define regAZCONTROLLER1_CORB_STATUS                                                                    0x0001

WARNING: line length of 105 exceeds 100 columns
#15190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15166:
+#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX                                                           0

WARNING: line length of 110 exceeds 100 columns
#15191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15167:
+#define regAZCONTROLLER1_CORB_SIZE                                                                      0x0001

WARNING: line length of 105 exceeds 100 columns
#15192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15168:
+#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX                                                             0

WARNING: line length of 110 exceeds 100 columns
#15193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15169:
+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS                                                        0x0002

WARNING: line length of 105 exceeds 100 columns
#15194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15170:
+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               0

WARNING: line length of 110 exceeds 100 columns
#15195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15171:
+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS                                                        0x0003

WARNING: line length of 105 exceeds 100 columns
#15196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15172:
+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               0

WARNING: line length of 110 exceeds 100 columns
#15197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15173:
+#define regAZCONTROLLER1_RIRB_WRITE_POINTER                                                             0x0004

WARNING: line length of 105 exceeds 100 columns
#15198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15174:
+#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX                                                    0

WARNING: line length of 110 exceeds 100 columns
#15199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15175:
+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT                                                       0x0004

WARNING: line length of 105 exceeds 100 columns
#15200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15176:
+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              0

WARNING: line length of 110 exceeds 100 columns
#15201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15177:
+#define regAZCONTROLLER1_RIRB_CONTROL                                                                   0x0005

WARNING: line length of 105 exceeds 100 columns
#15202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15178:
+#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX                                                          0

WARNING: line length of 110 exceeds 100 columns
#15203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15179:
+#define regAZCONTROLLER1_RIRB_STATUS                                                                    0x0005

WARNING: line length of 105 exceeds 100 columns
#15204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15180:
+#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX                                                           0

WARNING: line length of 110 exceeds 100 columns
#15205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15181:
+#define regAZCONTROLLER1_RIRB_SIZE                                                                      0x0005

WARNING: line length of 105 exceeds 100 columns
#15206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15182:
+#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX                                                             0

WARNING: line length of 110 exceeds 100 columns
#15207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15183:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x0006

WARNING: line length of 105 exceeds 100 columns
#15208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15184:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    0

WARNING: line length of 110 exceeds 100 columns
#15209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15185:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x0006

WARNING: line length of 105 exceeds 100 columns
#15210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15186:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               0

WARNING: line length of 110 exceeds 100 columns
#15211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15187:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x0006

WARNING: line length of 105 exceeds 100 columns
#15212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15188:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              0

WARNING: line length of 110 exceeds 100 columns
#15213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15189:
+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x0007

WARNING: line length of 105 exceeds 100 columns
#15214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15190:
+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    0

WARNING: line length of 110 exceeds 100 columns
#15215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15191:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS                                                       0x0008

WARNING: line length of 105 exceeds 100 columns
#15216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15192:
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              0

WARNING: line length of 110 exceeds 100 columns
#15217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15193:
+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x000a

WARNING: line length of 105 exceeds 100 columns
#15218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15194:
+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       0

WARNING: line length of 110 exceeds 100 columns
#15219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15195:
+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x000b

WARNING: line length of 105 exceeds 100 columns
#15220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15196:
+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       0

WARNING: line length of 110 exceeds 100 columns
#15221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15197:
+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS                                                       0x074c

WARNING: line length of 105 exceeds 100 columns
#15222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15198:
+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              1

WARNING: line length of 110 exceeds 100 columns
#15227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15203:
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x0006

WARNING: line length of 105 exceeds 100 columns
#15228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15204:
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      0

WARNING: line length of 110 exceeds 100 columns
#15229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15205:
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x0006

WARNING: line length of 105 exceeds 100 columns
#15230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15206:
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     0

WARNING: line length of 110 exceeds 100 columns
#15235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15211:
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x0006

WARNING: line length of 105 exceeds 100 columns
#15236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15212:
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  0

WARNING: line length of 110 exceeds 100 columns
#15237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15213:
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x0006

WARNING: line length of 105 exceeds 100 columns
#15238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15214:
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 0

WARNING: line length of 110 exceeds 100 columns
#15243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15219:
+#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL                                                           0x1eb8

WARNING: line length of 105 exceeds 100 columns
#15244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15220:
+#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#15249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15225:
+#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL                                                           0x1eb9

WARNING: line length of 105 exceeds 100 columns
#15250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15226:
+#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#15255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15231:
+#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL                                                           0x1eba

WARNING: line length of 105 exceeds 100 columns
#15256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15232:
+#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#15261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15237:
+#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL                                                           0x1ebb

WARNING: line length of 105 exceeds 100 columns
#15262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15238:
+#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2

WARNING: line length of 110 exceeds 100 columns
#15267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15243:
+#define regDIG0_STREAM_MAPPER_CONTROL                                                                   0x1f0d

WARNING: line length of 105 exceeds 100 columns
#15268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15244:
+#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#15269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15245:
+#define regDIG1_STREAM_MAPPER_CONTROL                                                                   0x1f0e

WARNING: line length of 105 exceeds 100 columns
#15270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15246:
+#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#15271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15247:
+#define regDIG2_STREAM_MAPPER_CONTROL                                                                   0x1f0f

WARNING: line length of 105 exceeds 100 columns
#15272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15248:
+#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#15273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15249:
+#define regDIG3_STREAM_MAPPER_CONTROL                                                                   0x1f10

WARNING: line length of 105 exceeds 100 columns
#15274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15250:
+#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2

WARNING: line length of 110 exceeds 100 columns
#15275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15251:
+#define regDIG4_STREAM_MAPPER_CONTROL                                                                   0x1f11

WARNING: line length of 105 exceeds 100 columns
#15276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h:15252:
+#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2

WARNING: line length of 113 exceeds 100 columns
#15312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27:
+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0

WARNING: line length of 117 exceeds 100 columns
#15313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28:
+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL

WARNING: line length of 113 exceeds 100 columns
#15314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29:
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#15315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30:
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf

WARNING: line length of 117 exceeds 100 columns
#15316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31:
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL

WARNING: line length of 117 exceeds 100 columns
#15317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32:
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L

WARNING: line length of 113 exceeds 100 columns
#15318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33:
+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#15319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34:
+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1

WARNING: line length of 115 exceeds 100 columns
#15320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35:
+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L

WARNING: line length of 115 exceeds 100 columns
#15321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36:
+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L

WARNING: line length of 113 exceeds 100 columns
#15322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37:
+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0

WARNING: line length of 115 exceeds 100 columns
#15323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38:
+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L

WARNING: line length of 113 exceeds 100 columns
#15324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39:
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#15325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40:
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4

WARNING: line length of 117 exceeds 100 columns
#15326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41:
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L

WARNING: line length of 117 exceeds 100 columns
#15327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42:
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L

WARNING: line length of 113 exceeds 100 columns
#15328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43:
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44:
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7

WARNING: line length of 121 exceeds 100 columns
#15330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45:
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46:
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L

WARNING: line length of 113 exceeds 100 columns
#15332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47:
+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48:
+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49:
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#15335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50:
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf

WARNING: line length of 117 exceeds 100 columns
#15336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51:
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL

WARNING: line length of 117 exceeds 100 columns
#15337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52:
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L

WARNING: line length of 113 exceeds 100 columns
#15338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53:
+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0

WARNING: line length of 117 exceeds 100 columns
#15339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:54:
+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL

WARNING: line length of 113 exceeds 100 columns
#15340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:55:
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#15341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:56:
+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#15342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:57:
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2

WARNING: line length of 115 exceeds 100 columns
#15343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:58:
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L

WARNING: line length of 115 exceeds 100 columns
#15344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:59:
+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L

WARNING: line length of 115 exceeds 100 columns
#15345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:60:
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L

WARNING: line length of 113 exceeds 100 columns
#15346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:61:
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#15347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:62:
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2

WARNING: line length of 115 exceeds 100 columns
#15348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:63:
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L

WARNING: line length of 115 exceeds 100 columns
#15349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:64:
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L

WARNING: line length of 113 exceeds 100 columns
#15350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:65:
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#15351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:66:
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4

WARNING: line length of 117 exceeds 100 columns
#15352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:67:
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L

WARNING: line length of 117 exceeds 100 columns
#15353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:68:
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L

WARNING: line length of 113 exceeds 100 columns
#15354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:69:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0

WARNING: line length of 114 exceeds 100 columns
#15355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:70:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c

WARNING: line length of 121 exceeds 100 columns
#15356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:71:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#15357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:72:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#15358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:73:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#15359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:74:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:75:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0

WARNING: line length of 121 exceeds 100 columns
#15361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:76:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#15362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:77:
+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#15363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:78:
+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:79:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#15365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:80:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1

WARNING: line length of 121 exceeds 100 columns
#15366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:81:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:82:
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L

WARNING: line length of 113 exceeds 100 columns
#15368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:83:
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:84:
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1

WARNING: line length of 113 exceeds 100 columns
#15370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:85:
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7

WARNING: line length of 121 exceeds 100 columns
#15371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:86:
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:87:
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL

WARNING: line length of 121 exceeds 100 columns
#15373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:88:
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L

WARNING: line length of 113 exceeds 100 columns
#15374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:89:
+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#15375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:90:
+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:91:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#15377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:92:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#15378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:93:
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:94:
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#15380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:95:
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#15381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:96:
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:97:
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#15383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:98:
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:99:
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#15385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:100:
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:101:
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:102:
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:103:
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:104:
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:105:
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:106:
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:107:
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:108:
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:109:
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:110:
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:111:
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:112:
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:113:
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:114:
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:115:
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:116:
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:117:
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:118:
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:119:
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:120:
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:121:
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:122:
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:123:
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:124:
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:125:
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:126:
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:127:
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:128:
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:129:
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:130:
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:131:
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:132:
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:133:
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:134:
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:135:
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#15421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:136:
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:137:
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:138:
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:139:
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:140:
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:141:
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:142:
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:143:
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:144:
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:145:
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:146:
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:147:
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:148:
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:149:
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:150:
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:151:
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:152:
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:153:
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:154:
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:155:
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:156:
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:157:
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:158:
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:159:
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:160:
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:161:
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:162:
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:163:
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:164:
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:165:
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:166:
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:167:
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:168:
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:169:
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:170:
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:171:
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:172:
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:173:
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:174:
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:175:
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:176:
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:177:
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:178:
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:179:
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:180:
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:181:
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:182:
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:183:
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:184:
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:185:
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:186:
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:187:
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:188:
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:189:
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:190:
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:191:
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:192:
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:193:
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:194:
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:195:
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:196:
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:197:
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:198:
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:199:
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#15485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:200:
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:201:
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:202:
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:203:
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:204:
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:205:
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:206:
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:207:
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:208:
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:209:
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:210:
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:211:
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:212:
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:213:
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:214:
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:215:
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:216:
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:217:
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:218:
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:219:
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:220:
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:221:
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:222:
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:223:
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:224:
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:225:
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:226:
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:227:
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:228:
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:229:
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:230:
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:231:
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:232:
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:233:
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:234:
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:235:
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:236:
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:237:
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:238:
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:239:
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:240:
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:241:
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:242:
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:243:
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:244:
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:245:
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:246:
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:247:
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:248:
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:249:
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:250:
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:251:
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:252:
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:253:
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:254:
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:255:
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:256:
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:257:
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:258:
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:259:
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:260:
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:261:
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:262:
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:263:
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:264:
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:265:
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:266:
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:267:
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:268:
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:269:
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:270:
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:271:
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:272:
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:273:
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:274:
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:275:
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:276:
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:277:
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:278:
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:279:
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:280:
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:281:
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:282:
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:283:
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:284:
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:285:
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:286:
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:287:
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:288:
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:289:
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:290:
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:291:
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:292:
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:293:
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:294:
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:295:
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:296:
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:297:
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:298:
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:299:
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:300:
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:301:
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:302:
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:303:
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:304:
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:305:
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:306:
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:307:
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:308:
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:309:
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:310:
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:311:
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:312:
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:313:
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:314:
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:315:
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:316:
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:317:
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:318:
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:319:
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:320:
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:321:
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:322:
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:323:
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:324:
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:325:
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:326:
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:327:
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#15613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:328:
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#15614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:329:
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#15615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:330:
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:331:
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:332:
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:333:
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#15619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:334:
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:335:
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:336:
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:337:
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:338:
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:339:
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:340:
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:341:
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#15627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:342:
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#15628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:343:
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#15629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:344:
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:345:
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:346:
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:347:
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#15633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:348:
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:349:
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#15635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:350:
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:351:
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:352:
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:353:
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:354:
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:355:
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#15641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:356:
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#15642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:357:
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#15643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:358:
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:359:
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:360:
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:361:
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#15647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:362:
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:363:
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#15649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:364:
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:365:
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:366:
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:367:
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:368:
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:369:
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#15655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:370:
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#15656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:371:
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#15657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:372:
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:373:
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:374:
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:375:
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#15661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:376:
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:377:
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#15663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:378:
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:379:
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:380:
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:381:
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:382:
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:383:
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#15669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:384:
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#15670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:385:
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#15671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:386:
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:387:
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:388:
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:389:
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#15675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:390:
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:391:
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#15677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:392:
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:393:
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:394:
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:395:
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:396:
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:397:
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#15683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:398:
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#15684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:399:
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#15685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:400:
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:401:
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:402:
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:403:
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#15689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:404:
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:405:
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#15691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:406:
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:407:
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:408:
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:409:
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:410:
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:411:
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#15697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:412:
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#15698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:413:
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#15699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:414:
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:415:
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:416:
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:417:
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#15703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:418:
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L

WARNING: line length of 113 exceeds 100 columns
#15704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:419:
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#15705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:420:
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:421:
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:422:
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:423:
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:424:
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL

WARNING: line length of 123 exceeds 100 columns
#15710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:425:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#15711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:426:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#15712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:427:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#15713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:428:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#15714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:429:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#15715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:430:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#15716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:431:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#15717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:432:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#15718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:433:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#15719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:434:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#15720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:435:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#15721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:436:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#15722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:437:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#15723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:438:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#15724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:439:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#15725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:440:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#15726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:441:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#15727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:442:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#15728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:443:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#15729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:444:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#15730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:445:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#15731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:446:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#15732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:447:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#15733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:448:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#15734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:449:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#15735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:450:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#15736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:451:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#15737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:452:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#15738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:453:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#15739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:454:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#15740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:455:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#15741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:456:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#15742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:457:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#15743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:458:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#15744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:459:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#15745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:460:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#15746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:461:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#15747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:462:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#15748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:463:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#15749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:464:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#15750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:465:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#15751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:466:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#15752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:467:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#15753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:468:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#15754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:469:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#15755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:470:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#15756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:471:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#15757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:472:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#15758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:473:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#15759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:474:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#15760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:475:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#15761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:476:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#15762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:477:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#15763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:478:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#15764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:479:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:480:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#15766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:481:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#15767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:482:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#15768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:483:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#15769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:484:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#15770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:485:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#15771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:486:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#15772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:487:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#15773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:488:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#15774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:489:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#15775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:490:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#15776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:491:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#15777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:492:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#15778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:493:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#15779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:494:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#15780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:495:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#15781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:496:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#15782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:497:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#15783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:498:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#15784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:499:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#15785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:500:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#15786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:501:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#15787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:502:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#15788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:503:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#15789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:504:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#15790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:505:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:506:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#15792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:507:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#15793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:508:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#15794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:509:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#15795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:510:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:511:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#15797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:512:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:513:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#15799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:514:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#15800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:515:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#15801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:516:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#15802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:517:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#15803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:518:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#15804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:519:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#15805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:520:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#15806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:521:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#15807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:522:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#15808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:523:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#15809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:524:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#15810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:525:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#15811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:526:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#15812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:527:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#15813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:528:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:529:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#15815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:530:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#15816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:531:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#15817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:532:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#15818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:533:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#15819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:534:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#15820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:535:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#15821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:536:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#15822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:537:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#15823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:538:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#15824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:539:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#15825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:540:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#15826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:541:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#15827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:542:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#15828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:543:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#15829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:544:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#15830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:545:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#15831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:546:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#15832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:547:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#15833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:548:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#15834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:549:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#15835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:550:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#15836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:551:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#15837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:552:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:553:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#15839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:554:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#15840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:555:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#15841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:556:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#15842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:557:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#15843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:558:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#15844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:559:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#15845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:560:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:561:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#15847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:562:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#15848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:563:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#15849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:564:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#15850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:565:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#15851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:566:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#15852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:567:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#15853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:568:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:569:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#15855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:570:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#15856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:571:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#15857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:572:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#15858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:573:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#15859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:574:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#15860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:575:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#15861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:576:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#15862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:577:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#15863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:578:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#15864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:579:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#15865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:580:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:581:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#15867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:582:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#15868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:583:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#15869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:584:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#15870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:585:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#15871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:586:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#15872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:587:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:588:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:589:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#15875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:590:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#15876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:591:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:592:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:593:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#15879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:594:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#15880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:595:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:596:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:597:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:598:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:599:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:600:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:601:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:602:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:603:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:604:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:605:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:606:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:607:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:608:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:609:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:610:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:611:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:612:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:613:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:614:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:615:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:616:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:617:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:618:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:619:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:620:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:621:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:622:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:623:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:624:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:625:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:626:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:627:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:628:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:629:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:630:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:631:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:632:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:633:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:634:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:635:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:636:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:637:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:638:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:639:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:640:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:641:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:642:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:643:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:644:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#15930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:645:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#15931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:646:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:647:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:648:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:649:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#15935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:650:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#15936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:651:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#15937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:652:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:653:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:654:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:655:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#15941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:656:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#15942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:657:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#15943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:658:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:659:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:660:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:661:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#15947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:662:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#15948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:663:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#15949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:664:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:665:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:666:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:667:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#15953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:668:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#15954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:669:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#15955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:670:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#15956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:671:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#15957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:672:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#15958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:673:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#15959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:674:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#15960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:675:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#15961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:676:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#15962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:677:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#15963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:678:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#15964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:679:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#15965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:680:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#15966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:681:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#15967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:682:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#15968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:683:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#15969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:684:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#15970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:685:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:686:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#15972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:687:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#15973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:688:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#15974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:689:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#15975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:690:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#15976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:691:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#15977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:692:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#15978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:693:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#15979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:694:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#15980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:695:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#15981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:696:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#15982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:697:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#15983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:698:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#15984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:699:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#15985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:700:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#15986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:701:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#15987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:702:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#15988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:703:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#15989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:704:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#15990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:705:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#15991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:706:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#15992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:707:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#15993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:708:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#15994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:709:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#15995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:710:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#15996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:711:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:712:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#15998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:713:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#15999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:714:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:715:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:716:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:717:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#16003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:718:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#16004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:719:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:720:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:721:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:722:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:723:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:724:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:725:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#16011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:726:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#16012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:727:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:728:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:729:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:730:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:731:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:732:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:733:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#16019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:734:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#16020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:735:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:736:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:737:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:738:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:739:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:740:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#16026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:741:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#16027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:742:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#16028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:743:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:744:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:745:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:746:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:747:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:748:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#16034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:749:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:750:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#16036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:751:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#16037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:752:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#16038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:753:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#16039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:754:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:755:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:756:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#16042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:757:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#16043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:758:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#16044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:759:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#16045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:760:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#16046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:761:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#16047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:762:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#16048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:763:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#16049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:764:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#16050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:765:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#16051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:766:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#16052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:767:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#16053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:768:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#16054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:769:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:770:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#16056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:771:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#16057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:772:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#16058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:773:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#16059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:774:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#16060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:775:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#16061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:776:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#16062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:777:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:778:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#16064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:779:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#16065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:780:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#16066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:781:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#16067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:782:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#16068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:783:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#16069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:784:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#16070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:785:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#16071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:786:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#16072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:787:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#16073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:788:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#16074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:789:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:790:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:791:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#16077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:792:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:793:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:794:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#16080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:795:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:796:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#16082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:797:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#16083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:798:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#16084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:799:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#16085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:800:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#16086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:801:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#16087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:802:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#16088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:803:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:804:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#16090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:805:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#16091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:806:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#16092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:807:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:808:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#16094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:809:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#16095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:810:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#16096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:811:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#16097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:812:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#16098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:813:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#16099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:814:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#16100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:815:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#16101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:816:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#16102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:817:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#16103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:818:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#16104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:819:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#16105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:820:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#16106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:821:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#16107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:822:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#16108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:823:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#16109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:824:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#16110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:825:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#16111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:826:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#16112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:827:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:828:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:829:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#16115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:830:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#16116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:831:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:832:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:833:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:834:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:835:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:836:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:837:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:838:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:839:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:840:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:841:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:842:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:843:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:844:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:845:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:846:
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:847:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#16133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:848:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:849:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#16135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:850:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#16136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:851:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#16137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:852:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#16138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:853:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:854:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#16140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:855:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#16141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:856:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:857:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#16143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:858:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:859:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#16145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:860:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#16146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:861:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#16147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:862:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#16148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:863:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#16149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:864:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#16150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:865:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:866:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:867:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:868:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#16154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:869:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#16155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:870:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#16156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:871:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:872:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#16158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:873:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:874:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#16160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:875:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#16161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:876:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#16162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:877:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#16163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:878:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#16164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:879:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#16165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:880:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:881:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:882:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#16168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:883:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#16169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:884:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#16170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:885:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#16171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:886:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:887:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:888:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#16174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:889:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#16175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:890:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#16176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:891:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#16177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:892:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:893:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:894:
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 123 exceeds 100 columns
#16180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:895:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#16181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:896:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#16182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:897:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#16183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:898:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#16184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:899:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#16185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:900:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#16186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:901:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#16187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:902:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#16188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:903:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#16189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:904:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#16190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:905:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#16191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:906:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#16192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:907:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#16193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:908:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#16194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:909:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#16195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:910:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#16196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:911:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#16197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:912:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:913:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:914:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:915:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#16201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:916:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:917:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:918:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:919:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#16205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:920:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#16206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:921:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#16207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:922:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#16208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:923:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:924:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#16210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:925:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#16211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:926:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#16212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:927:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#16213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:928:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#16214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:929:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:930:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#16216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:931:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#16217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:932:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#16218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:933:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#16219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:934:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#16220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:935:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#16221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:936:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#16222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:937:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:938:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:939:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#16225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:940:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#16226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:941:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#16227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:942:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#16228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:943:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#16229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:944:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#16230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:945:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#16231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:946:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#16232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:947:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#16233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:948:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#16234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:949:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:950:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:951:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#16237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:952:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:953:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:954:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:955:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#16241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:956:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:957:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#16243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:958:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#16244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:959:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#16245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:960:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#16246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:961:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#16247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:962:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#16248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:963:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#16249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:964:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#16250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:965:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#16251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:966:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#16252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:967:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#16253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:968:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#16254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:969:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#16255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:970:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#16256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:971:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#16257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:972:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#16258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:973:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#16259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:974:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#16260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:975:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:976:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:977:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#16263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:978:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#16264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:979:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#16265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:980:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:981:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#16267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:982:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:983:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#16269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:984:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#16270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:985:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#16271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:986:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#16272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:987:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#16273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:988:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#16274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:989:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#16275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:990:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#16276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:991:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#16277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:992:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#16278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:993:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#16279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:994:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#16280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:995:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#16281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:996:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#16282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:997:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#16283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:998:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:999:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1000:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#16286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1001:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1002:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1003:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#16289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1004:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1005:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1006:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1007:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#16293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1008:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#16294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1009:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#16295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1010:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#16296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1011:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#16297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1012:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#16298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1013:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#16299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1014:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#16300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1015:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#16301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1016:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#16302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1017:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#16303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1018:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#16304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1019:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#16305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1020:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#16306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1021:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#16307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1022:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1023:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1024:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#16310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1025:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1026:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1027:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1028:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#16314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1029:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1030:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1031:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1032:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#16318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1033:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1034:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#16320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1035:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#16321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1036:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#16322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1037:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#16323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1038:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1039:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#16325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1040:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#16326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1041:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#16327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1042:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#16328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1043:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#16329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1044:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#16330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1045:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#16331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1046:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#16332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1047:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#16333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1048:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#16334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1049:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#16335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1050:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1051:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1052:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#16338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1053:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#16339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1054:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#16340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1055:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#16341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1056:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#16342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1057:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1058:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1059:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#16345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1060:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#16346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1061:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1062:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1063:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1064:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1065:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1066:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1067:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1068:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1069:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1070:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1071:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1072:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1073:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1074:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1075:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1076:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1077:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1078:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1079:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1080:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1081:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1082:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1083:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1084:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1085:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1086:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1087:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1088:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1089:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1090:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1091:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1092:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1093:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1094:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1095:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1096:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1097:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1098:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1099:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1100:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1101:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1102:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1103:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1104:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1105:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1106:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1107:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1108:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1109:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1110:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1111:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1112:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1113:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1114:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1115:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1116:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1117:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1118:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1119:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1120:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1121:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1122:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1123:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1124:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1125:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1126:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1127:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1128:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1129:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1130:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1131:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1132:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1133:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1134:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1135:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1136:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1137:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1138:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1139:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1140:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1141:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1142:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1143:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1144:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#16430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1145:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#16431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1146:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#16432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1147:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#16433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1148:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#16434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1149:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#16435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1150:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#16436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1151:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#16437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1152:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#16438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1153:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#16439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1154:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#16440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1155:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1156:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1157:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#16443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1158:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1159:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1160:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#16446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1161:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1162:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#16448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1163:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#16449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1164:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#16450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1165:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#16451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1166:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#16452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1167:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1168:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#16454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1169:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1170:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#16456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1171:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1172:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#16458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1173:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1174:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#16460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1175:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#16461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1176:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#16462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1177:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#16463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1178:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#16464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1179:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#16465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1180:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#16466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1181:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#16467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1182:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1183:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#16469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1184:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1185:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1186:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1187:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#16473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1188:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#16474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1189:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1190:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1191:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1192:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1193:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1194:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1195:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#16481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1196:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#16482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1197:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1198:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1199:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1200:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1201:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1202:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1203:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#16489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1204:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#16490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1205:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1206:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1207:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1208:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1209:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1210:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#16496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1211:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#16497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1212:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#16498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1213:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1214:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1215:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1216:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1217:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1218:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#16504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1219:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1220:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#16506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1221:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#16507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1222:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#16508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1223:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#16509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1224:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1225:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1226:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#16512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1227:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#16513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1228:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#16514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1229:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#16515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1230:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#16516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1231:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#16517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1232:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#16518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1233:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#16519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1234:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#16520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1235:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#16521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1236:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#16522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1237:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#16523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1238:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#16524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1239:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1240:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#16526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1241:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#16527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1242:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#16528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1243:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#16529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1244:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#16530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1245:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#16531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1246:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#16532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1247:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1248:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#16534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1249:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#16535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1250:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#16536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1251:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#16537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1252:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#16538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1253:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#16539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1254:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#16540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1255:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#16541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1256:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#16542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1257:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#16543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1258:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#16544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1259:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1260:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1261:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#16547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1262:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1263:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1264:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#16550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1265:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1266:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#16552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1267:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#16553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1268:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#16554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1269:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#16555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1270:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#16556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1271:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#16557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1272:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#16558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1273:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1274:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#16560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1275:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#16561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1276:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#16562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1277:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1278:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#16564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1279:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#16565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1280:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#16566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1281:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#16567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1282:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#16568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1283:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#16569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1284:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#16570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1285:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#16571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1286:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#16572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1287:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#16573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1288:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#16574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1289:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#16575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1290:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#16576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1291:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#16577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1292:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#16578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1293:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#16579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1294:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#16580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1295:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#16581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1296:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#16582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1297:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1298:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1299:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#16585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1300:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#16586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1301:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1302:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1303:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1304:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1305:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1306:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1307:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1308:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1309:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1310:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1311:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1312:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1313:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#16599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1314:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#16600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1315:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1316:
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1317:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#16603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1318:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1319:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#16605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1320:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#16606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1321:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#16607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1322:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#16608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1323:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1324:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#16610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1325:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#16611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1326:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1327:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#16613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1328:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1329:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#16615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1330:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#16616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1331:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#16617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1332:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#16618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1333:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#16619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1334:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#16620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1335:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1336:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1337:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1338:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#16624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1339:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#16625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1340:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#16626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1341:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1342:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#16628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1343:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1344:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#16630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1345:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#16631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1346:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#16632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1347:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#16633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1348:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#16634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1349:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#16635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1350:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1351:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1352:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#16638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1353:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#16639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1354:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#16640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1355:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#16641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1356:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1357:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1358:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#16644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1359:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#16645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1360:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#16646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1361:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#16647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1362:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1363:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1364:
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 123 exceeds 100 columns
#16650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1365:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#16651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1366:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#16652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1367:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#16653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1368:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#16654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1369:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#16655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1370:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#16656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1371:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#16657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1372:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#16658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1373:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#16659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1374:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#16660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1375:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#16661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1376:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#16662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1377:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#16663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1378:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#16664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1379:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#16665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1380:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#16666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1381:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#16667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1382:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1383:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1384:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1385:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#16671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1386:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1387:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1388:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1389:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#16675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1390:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#16676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1391:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#16677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1392:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#16678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1393:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1394:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#16680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1395:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#16681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1396:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#16682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1397:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#16683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1398:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#16684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1399:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1400:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#16686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1401:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#16687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1402:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#16688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1403:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#16689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1404:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#16690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1405:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#16691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1406:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#16692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1407:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1408:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#16694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1409:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#16695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1410:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#16696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1411:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#16697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1412:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#16698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1413:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#16699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1414:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#16700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1415:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#16701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1416:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#16702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1417:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#16703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1418:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#16704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1419:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1420:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1421:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#16707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1422:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1423:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1424:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1425:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#16711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1426:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1427:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#16713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1428:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#16714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1429:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#16715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1430:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#16716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1431:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#16717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1432:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#16718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1433:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#16719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1434:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#16720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1435:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#16721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1436:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#16722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1437:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#16723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1438:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#16724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1439:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#16725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1440:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#16726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1441:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#16727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1442:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#16728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1443:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#16729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1444:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#16730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1445:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1446:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1447:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#16733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1448:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#16734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1449:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#16735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1450:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1451:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#16737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1452:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1453:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#16739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1454:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#16740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1455:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#16741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1456:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#16742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1457:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#16743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1458:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#16744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1459:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#16745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1460:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#16746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1461:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#16747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1462:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#16748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1463:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#16749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1464:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#16750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1465:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#16751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1466:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#16752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1467:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#16753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1468:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1469:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1470:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#16756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1471:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1472:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1473:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#16759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1474:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1475:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1476:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1477:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#16763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1478:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#16764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1479:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#16765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1480:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#16766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1481:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#16767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1482:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#16768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1483:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#16769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1484:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#16770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1485:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#16771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1486:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#16772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1487:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#16773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1488:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#16774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1489:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#16775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1490:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#16776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1491:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#16777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1492:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1493:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1494:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#16780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1495:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#16781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1496:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1497:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#16783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1498:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#16784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1499:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#16785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1500:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1501:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1502:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#16788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1503:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1504:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#16790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1505:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#16791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1506:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#16792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1507:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#16793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1508:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1509:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#16795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1510:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#16796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1511:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#16797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1512:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#16798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1513:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#16799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1514:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#16800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1515:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#16801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1516:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#16802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1517:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#16803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1518:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#16804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1519:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#16805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1520:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1521:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1522:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#16808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1523:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#16809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1524:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#16810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1525:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#16811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1526:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#16812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1527:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1528:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1529:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#16815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1530:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#16816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1531:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1532:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1533:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1534:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1535:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1536:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1537:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1538:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1539:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1540:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1541:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1542:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1543:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1544:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1545:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1546:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1547:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1548:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1549:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1550:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1551:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1552:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1553:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1554:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1555:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1556:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1557:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1558:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1559:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1560:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1561:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1562:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1563:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1564:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1565:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1566:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1567:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1568:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1569:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1570:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1571:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1572:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1573:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1574:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1575:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1576:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1577:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1578:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1579:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1580:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1581:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1582:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1583:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1584:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#16870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1585:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#16871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1586:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1587:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1588:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1589:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1590:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1591:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1592:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1593:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1594:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1595:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1596:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1597:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1598:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1599:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1600:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1601:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1602:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1603:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1604:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1605:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1606:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1607:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#16893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1608:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#16894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1609:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#16895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1610:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#16896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1611:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1612:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#16898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1613:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#16899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1614:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#16900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1615:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#16901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1616:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#16902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1617:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#16903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1618:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#16904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1619:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#16905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1620:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#16906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1621:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#16907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1622:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#16908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1623:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#16909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1624:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#16910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1625:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1626:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#16912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1627:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#16913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1628:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#16914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1629:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#16915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1630:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#16916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1631:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#16917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1632:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#16918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1633:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#16919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1634:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#16920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1635:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#16921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1636:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#16922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1637:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#16923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1638:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#16924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1639:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1640:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#16926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1641:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1642:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#16928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1643:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1644:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#16930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1645:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#16931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1646:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#16932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1647:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#16933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1648:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#16934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1649:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#16935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1650:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#16936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1651:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#16937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1652:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1653:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#16939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1654:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#16940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1655:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1656:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1657:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#16943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1658:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#16944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1659:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1660:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1661:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1662:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1663:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1664:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1665:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#16951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1666:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#16952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1667:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1668:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1669:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1670:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1671:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#16957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1672:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#16958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1673:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#16959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1674:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#16960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1675:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1676:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1677:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1678:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1679:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1680:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#16966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1681:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#16967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1682:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#16968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1683:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1684:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#16970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1685:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#16971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1686:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#16972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1687:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#16973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1688:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#16974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1689:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#16975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1690:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#16976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1691:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#16977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1692:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#16978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1693:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#16979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1694:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#16980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1695:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#16981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1696:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#16982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1697:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#16983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1698:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#16984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1699:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#16985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1700:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#16986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1701:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#16987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1702:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#16988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1703:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#16989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1704:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#16990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1705:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#16991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1706:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#16992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1707:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#16993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1708:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#16994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1709:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#16995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1710:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#16996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1711:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#16997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1712:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#16998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1713:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#16999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1714:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1715:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#17001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1716:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#17002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1717:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1718:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#17004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1719:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1720:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#17006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1721:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#17007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1722:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#17008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1723:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#17009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1724:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#17010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1725:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#17011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1726:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#17012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1727:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#17013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1728:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#17014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1729:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1730:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1731:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#17017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1732:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1733:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1734:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#17020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1735:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1736:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#17022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1737:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1738:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#17024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1739:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#17025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1740:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#17026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1741:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#17027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1742:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#17028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1743:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1744:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#17030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1745:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1746:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#17032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1747:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1748:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#17034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1749:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#17035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1750:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#17036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1751:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1752:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#17038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1753:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#17039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1754:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1755:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#17041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1756:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#17042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1757:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#17043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1758:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#17044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1759:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#17045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1760:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#17046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1761:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#17047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1762:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#17048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1763:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#17049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1764:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1765:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#17051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1766:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#17052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1767:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1768:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1769:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#17055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1770:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1771:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1772:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1773:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1774:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1775:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1776:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1777:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1778:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1779:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1780:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1781:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1782:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1783:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1784:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1785:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1786:
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1787:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#17073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1788:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1789:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#17075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1790:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#17076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1791:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#17077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1792:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#17078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1793:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1794:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#17080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1795:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#17081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1796:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1797:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#17083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1798:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1799:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#17085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1800:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#17086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1801:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#17087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1802:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#17088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1803:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#17089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1804:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#17090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1805:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1806:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1807:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1808:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#17094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1809:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#17095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1810:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#17096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1811:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1812:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#17098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1813:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1814:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#17100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1815:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#17101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1816:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#17102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1817:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#17103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1818:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#17104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1819:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#17105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1820:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1821:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1822:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#17108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1823:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#17109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1824:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#17110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1825:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#17111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1826:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1827:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1828:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#17114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1829:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#17115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1830:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#17116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1831:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#17117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1832:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1833:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1834:
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 123 exceeds 100 columns
#17120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1835:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#17121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1836:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#17122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1837:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#17123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1838:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#17124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1839:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#17125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1840:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#17126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1841:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#17127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1842:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#17128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1843:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#17129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1844:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#17130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1845:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#17131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1846:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#17132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1847:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#17133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1848:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#17134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1849:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#17135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1850:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#17136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1851:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#17137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1852:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1853:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1854:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1855:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#17141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1856:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1857:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1858:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1859:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#17145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1860:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#17146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1861:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#17147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1862:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#17148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1863:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1864:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#17150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1865:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#17151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1866:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#17152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1867:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#17153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1868:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#17154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1869:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1870:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#17156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1871:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#17157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1872:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#17158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1873:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#17159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1874:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#17160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1875:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#17161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1876:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#17162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1877:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1878:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1879:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#17165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1880:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#17166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1881:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#17167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1882:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#17168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1883:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#17169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1884:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#17170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1885:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#17171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1886:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#17172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1887:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#17173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1888:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#17174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1889:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1890:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1891:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#17177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1892:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1893:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1894:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1895:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#17181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1896:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1897:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#17183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1898:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#17184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1899:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#17185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1900:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#17186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1901:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#17187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1902:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#17188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1903:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#17189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1904:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#17190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1905:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#17191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1906:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#17192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1907:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1908:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#17194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1909:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#17195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1910:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#17196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1911:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#17197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1912:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#17198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1913:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#17199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1914:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#17200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1915:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1916:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1917:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#17203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1918:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#17204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1919:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#17205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1920:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1921:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#17207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1922:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1923:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#17209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1924:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#17210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1925:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#17211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1926:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#17212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1927:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#17213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1928:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#17214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1929:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#17215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1930:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#17216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1931:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#17217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1932:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#17218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1933:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#17219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1934:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#17220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1935:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#17221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1936:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#17222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1937:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#17223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1938:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1939:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1940:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#17226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1941:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1942:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1943:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#17229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1944:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1945:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1946:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1947:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#17233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1948:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#17234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1949:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#17235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1950:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#17236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1951:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#17237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1952:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#17238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1953:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#17239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1954:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#17240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1955:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#17241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1956:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#17242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1957:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#17243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1958:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#17244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1959:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#17245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1960:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#17246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1961:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#17247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1962:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1963:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1964:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#17250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1965:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1966:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1967:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1968:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#17254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1969:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1970:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1971:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1972:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#17258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1973:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1974:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#17260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1975:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#17261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1976:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1977:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#17263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1978:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1979:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#17265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1980:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#17266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1981:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#17267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1982:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#17268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1983:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#17269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1984:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#17270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1985:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#17271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1986:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#17272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1987:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#17273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1988:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#17274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1989:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#17275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1990:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1991:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1992:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#17278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1993:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#17279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1994:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#17280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1995:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#17281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1996:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#17282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1997:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1998:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:1999:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#17285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2000:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#17286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2001:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2002:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2003:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2004:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2005:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2006:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2007:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2008:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2009:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2010:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2011:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2012:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2013:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2014:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2015:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2016:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2017:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2018:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2019:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2020:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2021:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2022:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2023:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2024:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2025:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2026:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2027:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2028:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2029:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2030:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2031:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2032:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2033:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2034:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2035:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2036:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2037:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2038:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2039:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2040:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2041:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2042:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2043:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2044:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2045:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2046:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2047:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2048:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2049:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2050:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2051:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2052:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2053:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2054:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2055:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2056:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2057:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2058:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2059:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2060:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2061:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2062:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2063:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2064:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2065:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2066:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2067:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2068:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2069:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2070:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2071:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2072:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2073:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2074:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2075:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2076:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2077:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2078:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2079:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2080:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2081:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2082:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2083:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2084:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#17370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2085:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2086:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#17372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2087:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#17373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2088:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#17374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2089:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#17375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2090:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#17376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2091:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#17377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2092:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#17378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2093:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#17379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2094:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#17380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2095:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2096:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2097:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#17383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2098:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2099:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2100:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#17386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2101:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2102:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#17388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2103:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2104:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#17390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2105:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#17391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2106:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#17392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2107:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2108:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#17394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2109:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2110:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#17396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2111:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2112:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#17398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2113:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2114:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#17400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2115:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#17401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2116:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#17402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2117:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#17403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2118:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#17404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2119:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#17405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2120:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#17406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2121:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#17407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2122:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2123:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#17409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2124:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2125:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#17411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2126:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#17412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2127:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#17413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2128:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#17414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2129:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2130:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2131:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2132:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2133:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#17419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2134:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#17420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2135:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#17421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2136:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#17422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2137:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2138:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2139:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2140:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2141:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#17427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2142:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#17428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2143:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#17429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2144:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#17430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2145:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2146:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2147:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2148:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2149:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2150:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#17436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2151:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#17437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2152:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#17438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2153:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2154:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2155:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2156:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2157:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2158:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#17444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2159:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2160:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#17446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2161:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#17447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2162:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#17448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2163:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#17449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2164:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2165:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2166:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#17452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2167:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#17453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2168:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#17454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2169:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#17455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2170:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#17456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2171:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#17457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2172:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#17458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2173:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#17459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2174:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#17460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2175:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#17461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2176:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#17462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2177:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#17463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2178:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#17464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2179:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2180:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#17466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2181:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#17467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2182:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#17468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2183:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#17469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2184:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2185:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#17471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2186:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#17472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2187:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2188:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#17474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2189:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2190:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#17476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2191:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#17477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2192:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#17478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2193:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#17479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2194:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#17480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2195:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#17481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2196:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#17482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2197:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#17483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2198:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#17484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2199:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2200:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2201:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#17487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2202:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2203:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2204:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#17490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2205:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2206:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#17492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2207:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2208:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#17494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2209:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#17495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2210:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#17496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2211:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#17497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2212:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#17498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2213:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2214:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#17500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2215:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2216:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#17502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2217:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2218:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#17504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2219:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#17505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2220:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#17506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2221:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2222:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#17508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2223:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#17509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2224:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2225:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#17511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2226:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#17512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2227:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#17513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2228:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#17514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2229:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#17515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2230:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#17516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2231:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#17517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2232:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#17518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2233:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#17519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2234:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2235:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#17521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2236:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#17522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2237:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2238:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2239:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#17525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2240:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2241:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2242:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2243:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2244:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2245:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2246:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2247:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2248:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2249:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2250:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2251:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2252:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2253:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2254:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2255:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2256:
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2257:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#17543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2258:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2259:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#17545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2260:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#17546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2261:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#17547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2262:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#17548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2263:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2264:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#17550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2265:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#17551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2266:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2267:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#17553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2268:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2269:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#17555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2270:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#17556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2271:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#17557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2272:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#17558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2273:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#17559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2274:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#17560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2275:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2276:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2277:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2278:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#17564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2279:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#17565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2280:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#17566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2281:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2282:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#17568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2283:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2284:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#17570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2285:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#17571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2286:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#17572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2287:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#17573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2288:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#17574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2289:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#17575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2290:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2291:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2292:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#17578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2293:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#17579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2294:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#17580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2295:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#17581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2296:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2297:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2298:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#17584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2299:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#17585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2300:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#17586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2301:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#17587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2302:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2303:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2304:
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 123 exceeds 100 columns
#17590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2305:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#17591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2306:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#17592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2307:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#17593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2308:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#17594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2309:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#17595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2310:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#17596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2311:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#17597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2312:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#17598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2313:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#17599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2314:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#17600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2315:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#17601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2316:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#17602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2317:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#17603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2318:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#17604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2319:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#17605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2320:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#17606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2321:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#17607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2322:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2323:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2324:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2325:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#17611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2326:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2327:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2328:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2329:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#17615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2330:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#17616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2331:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#17617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2332:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#17618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2333:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2334:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#17620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2335:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#17621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2336:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#17622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2337:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#17623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2338:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#17624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2339:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2340:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#17626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2341:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#17627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2342:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#17628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2343:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#17629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2344:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#17630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2345:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#17631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2346:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#17632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2347:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2348:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#17634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2349:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#17635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2350:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#17636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2351:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#17637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2352:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#17638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2353:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#17639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2354:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#17640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2355:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#17641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2356:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#17642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2357:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#17643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2358:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#17644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2359:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2360:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2361:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#17647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2362:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2363:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2364:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2365:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#17651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2366:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2367:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#17653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2368:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#17654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2369:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#17655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2370:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#17656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2371:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#17657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2372:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#17658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2373:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#17659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2374:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#17660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2375:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#17661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2376:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#17662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2377:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2378:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#17664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2379:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#17665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2380:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#17666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2381:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#17667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2382:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#17668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2383:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#17669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2384:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#17670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2385:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2386:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2387:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#17673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2388:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#17674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2389:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#17675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2390:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2391:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#17677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2392:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2393:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#17679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2394:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#17680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2395:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#17681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2396:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#17682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2397:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#17683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2398:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#17684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2399:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#17685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2400:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#17686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2401:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#17687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2402:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#17688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2403:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#17689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2404:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#17690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2405:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#17691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2406:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#17692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2407:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#17693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2408:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2409:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2410:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#17696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2411:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2412:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2413:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#17699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2414:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2415:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2416:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2417:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#17703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2418:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#17704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2419:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#17705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2420:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#17706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2421:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#17707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2422:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#17708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2423:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#17709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2424:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#17710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2425:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#17711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2426:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#17712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2427:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#17713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2428:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#17714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2429:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#17715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2430:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#17716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2431:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#17717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2432:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2433:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2434:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#17720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2435:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#17721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2436:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2437:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#17723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2438:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#17724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2439:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#17725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2440:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2441:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2442:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#17728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2443:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2444:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#17730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2445:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#17731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2446:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2447:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#17733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2448:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2449:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#17735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2450:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#17736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2451:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#17737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2452:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#17738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2453:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#17739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2454:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#17740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2455:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#17741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2456:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#17742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2457:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#17743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2458:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#17744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2459:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#17745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2460:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2461:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2462:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#17748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2463:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#17749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2464:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#17750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2465:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#17751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2466:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#17752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2467:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2468:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2469:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#17755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2470:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#17756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2471:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2472:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2473:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2474:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2475:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2476:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2477:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2478:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2479:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2480:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2481:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2482:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2483:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2484:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2485:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2486:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2487:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2488:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2489:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2490:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2491:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2492:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2493:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2494:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2495:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2496:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2497:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2498:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2499:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2500:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2501:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2502:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2503:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2504:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2505:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2506:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2507:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2508:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2509:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2510:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2511:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2512:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2513:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2514:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2515:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2516:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2517:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2518:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2519:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2520:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2521:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2522:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2523:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2524:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#17810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2525:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#17811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2526:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2527:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2528:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2529:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2530:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2531:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2532:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2533:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2534:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2535:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2536:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2537:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2538:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2539:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2540:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2541:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2542:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2543:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2544:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2545:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2546:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2547:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2548:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#17834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2549:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#17835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2550:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#17836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2551:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2552:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#17838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2553:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2554:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#17840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2555:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2556:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#17842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2557:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#17843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2558:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#17844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2559:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#17845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2560:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#17846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2561:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#17847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2562:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#17848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2563:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#17849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2564:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#17850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2565:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2566:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2567:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#17853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2568:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2569:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2570:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#17856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2571:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2572:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#17858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2573:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2574:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#17860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2575:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#17861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2576:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#17862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2577:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#17863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2578:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#17864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2579:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2580:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#17866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2581:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2582:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#17868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2583:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2584:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#17870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2585:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#17871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2586:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#17872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2587:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#17873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2588:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#17874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2589:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#17875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2590:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#17876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2591:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#17877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2592:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2593:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#17879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2594:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#17880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2595:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#17881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2596:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#17882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2597:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#17883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2598:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#17884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2599:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2600:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2601:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2602:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2603:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#17889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2604:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#17890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2605:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#17891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2606:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#17892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2607:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2608:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2609:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2610:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2611:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#17897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2612:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#17898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2613:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#17899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2614:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#17900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2615:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2616:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2617:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2618:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2619:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2620:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#17906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2621:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#17907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2622:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#17908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2623:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2624:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#17910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2625:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#17911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2626:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#17912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2627:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#17913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2628:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#17914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2629:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#17915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2630:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#17916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2631:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#17917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2632:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#17918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2633:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#17919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2634:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2635:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2636:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#17922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2637:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#17923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2638:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#17924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2639:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#17925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2640:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#17926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2641:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#17927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2642:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#17928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2643:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#17929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2644:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#17930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2645:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#17931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2646:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#17932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2647:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#17933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2648:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#17934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2649:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2650:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#17936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2651:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#17937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2652:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#17938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2653:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#17939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2654:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2655:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#17941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2656:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#17942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2657:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2658:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#17944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2659:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2660:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#17946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2661:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#17947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2662:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#17948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2663:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#17949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2664:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#17950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2665:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#17951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2666:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#17952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2667:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#17953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2668:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#17954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2669:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#17955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2670:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#17956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2671:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#17957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2672:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#17958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2673:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#17959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2674:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#17960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2675:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#17961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2676:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#17962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2677:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#17963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2678:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#17964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2679:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#17965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2680:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#17966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2681:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#17967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2682:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#17968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2683:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#17969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2684:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#17970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2685:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2686:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#17972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2687:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#17973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2688:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#17974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2689:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#17975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2690:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#17976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2691:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#17977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2692:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#17978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2693:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#17979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2694:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2695:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#17981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2696:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#17982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2697:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#17983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2698:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#17984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2699:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#17985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2700:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#17986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2701:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#17987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2702:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#17988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2703:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#17989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2704:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#17990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2705:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#17991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2706:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#17992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2707:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2708:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#17994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2709:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#17995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2710:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#17996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2711:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#17997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2712:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#17998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2713:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#17999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2714:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2715:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2716:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2717:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2718:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2719:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2720:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2721:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2722:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2723:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2724:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2725:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2726:
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2727:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#18013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2728:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2729:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#18015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2730:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2731:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#18017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2732:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#18018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2733:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2734:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#18020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2735:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#18021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2736:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2737:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#18023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2738:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2739:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#18025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2740:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#18026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2741:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#18027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2742:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#18028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2743:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#18029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2744:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#18030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2745:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2746:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2747:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2748:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#18034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2749:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#18035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2750:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#18036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2751:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2752:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#18038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2753:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2754:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#18040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2755:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#18041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2756:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2757:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#18043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2758:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#18044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2759:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#18045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2760:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2761:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2762:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#18048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2763:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#18049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2764:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#18050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2765:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#18051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2766:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2767:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2768:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#18054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2769:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#18055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2770:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#18056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2771:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#18057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2772:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2773:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2774:
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 123 exceeds 100 columns
#18060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2775:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#18061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2776:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#18062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2777:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#18063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2778:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#18064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2779:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#18065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2780:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#18066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2781:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#18067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2782:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#18068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2783:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#18069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2784:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#18070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2785:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#18071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2786:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#18072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2787:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#18073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2788:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#18074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2789:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#18075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2790:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#18076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2791:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#18077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2792:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2793:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2794:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2795:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#18081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2796:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2797:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2798:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2799:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#18085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2800:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#18086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2801:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#18087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2802:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#18088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2803:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2804:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#18090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2805:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#18091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2806:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#18092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2807:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#18093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2808:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#18094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2809:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2810:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#18096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2811:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#18097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2812:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#18098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2813:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#18099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2814:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#18100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2815:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#18101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2816:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#18102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2817:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2818:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2819:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#18105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2820:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#18106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2821:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#18107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2822:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#18108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2823:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#18109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2824:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#18110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2825:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#18111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2826:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#18112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2827:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#18113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2828:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#18114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2829:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2830:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2831:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#18117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2832:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2833:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2834:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2835:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#18121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2836:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2837:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#18123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2838:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#18124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2839:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#18125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2840:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#18126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2841:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#18127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2842:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#18128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2843:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#18129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2844:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#18130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2845:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#18131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2846:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#18132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2847:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#18133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2848:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#18134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2849:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#18135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2850:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#18136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2851:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#18137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2852:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#18138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2853:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#18139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2854:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#18140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2855:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2856:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2857:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#18143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2858:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#18144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2859:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#18145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2860:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2861:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#18147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2862:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2863:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#18149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2864:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#18150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2865:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#18151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2866:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#18152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2867:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#18153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2868:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#18154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2869:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#18155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2870:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#18156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2871:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#18157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2872:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#18158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2873:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#18159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2874:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#18160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2875:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#18161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2876:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#18162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2877:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#18163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2878:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2879:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2880:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#18166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2881:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2882:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2883:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#18169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2884:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2885:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2886:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2887:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#18173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2888:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#18174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2889:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#18175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2890:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#18176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2891:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#18177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2892:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#18178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2893:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#18179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2894:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#18180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2895:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#18181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2896:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#18182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2897:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#18183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2898:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#18184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2899:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#18185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2900:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#18186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2901:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#18187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2902:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2903:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2904:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#18190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2905:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2906:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2907:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2908:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#18194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2909:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2910:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2911:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2912:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#18198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2913:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2914:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#18200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2915:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#18201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2916:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#18202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2917:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#18203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2918:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2919:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#18205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2920:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#18206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2921:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#18207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2922:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#18208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2923:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#18209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2924:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#18210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2925:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#18211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2926:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#18212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2927:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#18213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2928:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#18214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2929:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#18215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2930:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2931:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2932:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#18218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2933:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#18219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2934:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#18220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2935:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#18221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2936:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#18222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2937:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2938:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2939:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#18225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2940:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#18226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2941:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2942:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2943:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2944:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2945:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2946:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2947:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2948:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2949:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2950:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2951:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2952:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2953:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2954:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2955:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2956:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2957:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2958:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2959:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2960:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2961:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2962:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2963:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2964:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2965:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2966:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2967:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2968:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2969:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2970:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2971:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2972:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2973:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2974:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2975:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2976:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2977:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2978:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2979:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2980:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2981:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2982:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2983:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2984:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2985:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2986:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2987:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2988:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2989:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2990:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2991:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2992:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2993:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2994:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2995:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2996:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2997:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2998:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:2999:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3000:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3001:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3002:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3003:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3004:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3005:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3006:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3007:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3008:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3009:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3010:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3011:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3012:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3013:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3014:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3015:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3016:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3017:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3018:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3019:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3020:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3021:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3022:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3023:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3024:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#18310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3025:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#18311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3026:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#18312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3027:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#18313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3028:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#18314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3029:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#18315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3030:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#18316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3031:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#18317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3032:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#18318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3033:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#18319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3034:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#18320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3035:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3036:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3037:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#18323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3038:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3039:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3040:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#18326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3041:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3042:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#18328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3043:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#18329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3044:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#18330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3045:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#18331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3046:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#18332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3047:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3048:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#18334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3049:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3050:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#18336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3051:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3052:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#18338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3053:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3054:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#18340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3055:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#18341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3056:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#18342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3057:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#18343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3058:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#18344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3059:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#18345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3060:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#18346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3061:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#18347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3062:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3063:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#18349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3064:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3065:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#18351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3066:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#18352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3067:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#18353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3068:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#18354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3069:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3070:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3071:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3072:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3073:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#18359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3074:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#18360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3075:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#18361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3076:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#18362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3077:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3078:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3079:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3080:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3081:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#18367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3082:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#18368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3083:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#18369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3084:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#18370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3085:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3086:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3087:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3088:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3089:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3090:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#18376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3091:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#18377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3092:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#18378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3093:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3094:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3095:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3096:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3097:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3098:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#18384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3099:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3100:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#18386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3101:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#18387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3102:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#18388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3103:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#18389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3104:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3105:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3106:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#18392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3107:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#18393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3108:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#18394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3109:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#18395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3110:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#18396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3111:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#18397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3112:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#18398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3113:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#18399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3114:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#18400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3115:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#18401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3116:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#18402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3117:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#18403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3118:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#18404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3119:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3120:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#18406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3121:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#18407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3122:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#18408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3123:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#18409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3124:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#18410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3125:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#18411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3126:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#18412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3127:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3128:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#18414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3129:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#18415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3130:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#18416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3131:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#18417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3132:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#18418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3133:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#18419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3134:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#18420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3135:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#18421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3136:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#18422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3137:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#18423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3138:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#18424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3139:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3140:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3141:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#18427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3142:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3143:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3144:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#18430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3145:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3146:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#18432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3147:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#18433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3148:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#18434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3149:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#18435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3150:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#18436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3151:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#18437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3152:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3153:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3154:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#18440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3155:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#18441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3156:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#18442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3157:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3158:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#18444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3159:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#18445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3160:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#18446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3161:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#18447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3162:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#18448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3163:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#18449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3164:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#18450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3165:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#18451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3166:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#18452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3167:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#18453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3168:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#18454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3169:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#18455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3170:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#18456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3171:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#18457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3172:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#18458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3173:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#18459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3174:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#18460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3175:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#18461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3176:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#18462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3177:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3178:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3179:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#18465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3180:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#18466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3181:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3182:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3183:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3184:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3185:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3186:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3187:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3188:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3189:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3190:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3191:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3192:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3193:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3194:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3195:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3196:
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3197:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#18483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3198:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3199:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#18485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3200:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3201:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#18487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3202:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#18488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3203:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3204:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#18490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3205:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#18491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3206:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3207:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#18493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3208:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3209:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#18495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3210:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#18496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3211:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#18497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3212:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#18498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3213:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#18499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3214:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#18500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3215:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3216:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3217:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3218:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#18504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3219:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#18505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3220:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#18506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3221:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3222:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#18508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3223:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3224:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#18510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3225:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#18511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3226:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3227:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#18513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3228:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#18514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3229:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#18515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3230:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3231:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3232:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#18518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3233:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#18519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3234:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#18520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3235:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#18521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3236:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3237:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3238:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#18524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3239:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#18525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3240:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#18526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3241:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#18527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3242:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3243:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3244:
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 123 exceeds 100 columns
#18530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3245:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#18531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3246:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#18532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3247:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#18533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3248:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#18534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3249:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#18535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3250:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#18536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3251:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#18537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3252:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#18538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3253:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#18539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3254:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#18540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3255:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#18541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3256:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#18542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3257:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#18543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3258:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#18544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3259:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#18545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3260:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#18546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3261:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#18547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3262:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3263:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3264:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3265:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#18551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3266:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3267:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3268:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3269:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#18555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3270:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#18556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3271:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#18557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3272:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#18558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3273:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3274:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#18560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3275:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#18561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3276:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#18562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3277:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#18563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3278:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#18564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3279:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3280:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#18566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3281:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#18567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3282:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#18568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3283:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#18569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3284:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#18570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3285:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#18571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3286:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#18572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3287:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3288:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3289:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#18575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3290:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#18576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3291:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#18577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3292:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#18578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3293:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#18579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3294:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#18580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3295:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#18581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3296:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#18582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3297:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#18583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3298:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#18584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3299:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3300:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3301:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#18587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3302:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3303:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3304:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3305:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#18591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3306:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3307:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#18593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3308:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#18594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3309:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#18595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3310:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#18596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3311:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#18597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3312:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#18598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3313:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#18599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3314:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#18600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3315:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#18601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3316:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#18602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3317:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#18603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3318:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#18604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3319:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#18605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3320:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#18606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3321:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#18607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3322:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#18608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3323:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#18609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3324:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#18610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3325:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3326:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3327:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#18613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3328:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#18614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3329:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#18615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3330:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3331:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#18617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3332:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3333:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#18619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3334:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#18620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3335:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#18621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3336:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#18622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3337:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#18623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3338:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#18624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3339:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#18625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3340:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#18626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3341:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#18627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3342:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#18628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3343:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#18629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3344:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#18630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3345:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#18631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3346:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#18632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3347:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#18633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3348:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3349:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3350:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#18636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3351:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3352:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3353:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#18639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3354:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3355:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3356:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3357:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#18643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3358:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#18644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3359:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#18645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3360:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#18646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3361:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#18647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3362:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#18648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3363:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#18649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3364:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#18650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3365:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#18651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3366:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#18652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3367:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#18653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3368:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#18654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3369:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#18655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3370:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#18656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3371:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#18657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3372:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3373:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3374:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#18660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3375:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#18661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3376:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3377:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#18663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3378:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#18664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3379:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#18665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3380:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3381:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3382:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#18668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3383:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3384:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#18670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3385:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#18671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3386:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#18672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3387:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#18673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3388:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3389:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#18675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3390:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#18676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3391:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#18677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3392:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#18678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3393:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#18679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3394:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#18680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3395:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#18681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3396:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#18682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3397:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#18683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3398:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#18684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3399:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#18685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3400:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3401:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3402:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#18688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3403:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#18689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3404:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#18690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3405:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#18691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3406:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#18692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3407:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3408:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3409:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#18695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3410:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#18696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3411:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3412:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3413:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3414:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3415:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3416:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3417:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3418:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3419:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3420:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3421:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3422:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3423:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3424:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3425:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3426:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3427:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3428:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3429:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3430:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3431:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3432:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3433:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3434:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3435:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3436:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3437:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3438:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3439:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3440:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3441:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3442:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3443:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3444:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3445:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3446:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3447:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3448:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3449:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3450:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3451:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3452:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3453:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3454:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3455:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3456:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3457:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3458:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3459:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3460:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3461:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3462:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3463:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3464:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#18750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3465:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#18751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3466:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3467:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3468:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3469:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3470:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3471:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3472:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3473:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3474:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3475:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3476:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3477:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3478:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3479:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3480:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3481:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3482:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3483:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3484:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3485:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3486:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3487:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3488:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#18774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3489:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#18775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3490:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#18776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3491:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3492:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#18778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3493:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3494:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#18780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3495:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#18781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3496:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#18782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3497:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#18783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3498:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#18784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3499:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#18785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3500:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#18786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3501:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#18787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3502:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#18788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3503:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#18789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3504:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#18790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3505:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3506:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3507:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#18793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3508:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3509:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3510:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#18796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3511:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3512:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#18798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3513:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#18799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3514:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#18800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3515:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#18801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3516:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#18802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3517:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#18803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3518:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#18804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3519:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3520:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#18806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3521:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3522:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#18808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3523:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3524:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#18810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3525:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#18811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3526:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#18812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3527:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#18813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3528:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#18814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3529:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#18815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3530:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#18816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3531:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#18817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3532:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3533:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#18819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3534:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3535:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#18821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3536:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#18822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3537:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#18823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3538:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#18824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3539:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3540:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3541:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3542:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3543:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#18829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3544:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#18830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3545:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#18831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3546:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#18832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3547:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3548:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3549:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3550:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3551:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#18837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3552:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#18838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3553:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#18839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3554:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#18840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3555:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3556:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3557:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3558:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3559:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3560:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#18846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3561:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#18847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3562:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#18848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3563:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3564:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3565:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#18851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3566:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#18852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3567:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#18853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3568:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#18854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3569:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#18855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3570:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#18856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3571:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#18857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3572:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#18858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3573:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#18859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3574:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3575:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3576:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#18862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3577:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#18863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3578:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#18864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3579:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#18865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3580:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#18866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3581:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#18867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3582:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#18868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3583:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#18869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3584:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#18870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3585:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#18871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3586:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#18872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3587:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#18873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3588:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#18874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3589:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3590:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#18876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3591:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#18877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3592:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#18878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3593:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#18879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3594:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#18880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3595:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#18881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3596:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#18882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3597:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3598:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#18884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3599:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#18885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3600:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#18886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3601:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#18887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3602:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#18888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3603:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#18889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3604:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#18890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3605:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#18891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3606:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#18892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3607:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#18893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3608:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#18894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3609:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3610:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3611:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#18897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3612:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#18898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3613:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#18899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3614:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#18900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3615:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#18901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3616:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#18902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3617:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#18903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3618:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#18904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3619:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#18905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3620:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#18906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3621:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#18907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3622:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3623:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#18909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3624:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#18910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3625:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#18911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3626:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#18912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3627:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3628:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#18914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3629:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#18915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3630:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#18916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3631:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#18917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3632:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#18918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3633:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#18919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3634:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#18920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3635:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#18921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3636:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#18922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3637:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#18923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3638:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#18924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3639:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#18925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3640:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#18926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3641:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#18927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3642:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#18928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3643:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#18929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3644:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#18930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3645:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#18931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3646:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#18932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3647:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3648:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3649:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#18935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3650:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#18936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3651:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3652:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3653:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3654:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3655:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3656:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3657:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3658:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3659:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3660:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3661:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3662:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3663:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#18949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3664:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#18950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3665:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#18951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3666:
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#18952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3667:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#18953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3668:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3669:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#18955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3670:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3671:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#18957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3672:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#18958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3673:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3674:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#18960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3675:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#18961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3676:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3677:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#18963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3678:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#18964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3679:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#18965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3680:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#18966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3681:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#18967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3682:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#18968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3683:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#18969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3684:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#18970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3685:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3686:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#18972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3687:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#18973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3688:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#18974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3689:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#18975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3690:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#18976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3691:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#18977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3692:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#18978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3693:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3694:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#18980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3695:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#18981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3696:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#18982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3697:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#18983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3698:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#18984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3699:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#18985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3700:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3701:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3702:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#18988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3703:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#18989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3704:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#18990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3705:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#18991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3706:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3707:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3708:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#18994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3709:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#18995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3710:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#18996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3711:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#18997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3712:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#18998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3713:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#18999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3714:
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 123 exceeds 100 columns
#19000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3715:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#19001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3716:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 121 exceeds 100 columns
#19002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3717:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 125 exceeds 100 columns
#19003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3718:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#19004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3719:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4

WARNING: line length of 113 exceeds 100 columns
#19005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3720:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5

WARNING: line length of 114 exceeds 100 columns
#19006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3721:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 128 exceeds 100 columns
#19007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3722:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#19008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3723:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8

WARNING: line length of 113 exceeds 100 columns
#19009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3724:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9

WARNING: line length of 113 exceeds 100 columns
#19010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3725:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa

WARNING: line length of 113 exceeds 100 columns
#19011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3726:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb

WARNING: line length of 129 exceeds 100 columns
#19012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3727:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3728:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14

WARNING: line length of 129 exceeds 100 columns
#19014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3729:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 126 exceeds 100 columns
#19015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3730:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 127 exceeds 100 columns
#19016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3731:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 131 exceeds 100 columns
#19017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3732:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3733:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3734:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3735:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L

WARNING: line length of 134 exceeds 100 columns
#19021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3736:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3737:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3738:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#19024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3739:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#19025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3740:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L

WARNING: line length of 134 exceeds 100 columns
#19026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3741:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3742:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#19028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3743:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#19029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3744:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#19030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3745:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#19031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3746:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb

WARNING: line length of 113 exceeds 100 columns
#19032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3747:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe

WARNING: line length of 113 exceeds 100 columns
#19033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3748:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf

WARNING: line length of 121 exceeds 100 columns
#19034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3749:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3750:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#19036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3751:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#19037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3752:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L

WARNING: line length of 121 exceeds 100 columns
#19038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3753:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#19039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3754:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L

WARNING: line length of 113 exceeds 100 columns
#19040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3755:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#19041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3756:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#19042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3757:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3758:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3759:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#19045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3760:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#19046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3761:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#19047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3762:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#19048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3763:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#19049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3764:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#19050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3765:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#19051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3766:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#19052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3767:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8

WARNING: line length of 114 exceeds 100 columns
#19053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3768:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17

WARNING: line length of 121 exceeds 100 columns
#19054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3769:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3770:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3771:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3772:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3773:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3774:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3775:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#19061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3776:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3777:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#19063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3778:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#19064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3779:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#19065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3780:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL

WARNING: line length of 115 exceeds 100 columns
#19066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3781:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#19067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3782:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#19068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3783:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#19069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3784:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#19070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3785:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#19071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3786:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#19072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3787:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#19073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3788:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#19074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3789:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#19075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3790:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL

WARNING: line length of 117 exceeds 100 columns
#19076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3791:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#19077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3792:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1

WARNING: line length of 114 exceeds 100 columns
#19078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3793:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2

WARNING: line length of 116 exceeds 100 columns
#19079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3794:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#19080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3795:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3796:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3797:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L

WARNING: line length of 122 exceeds 100 columns
#19083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3798:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#19084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3799:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#19085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3800:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3801:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#19087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3802:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3803:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#19089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3804:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL

WARNING: line length of 117 exceeds 100 columns
#19090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3805:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#19091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3806:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#19092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3807:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 119 exceeds 100 columns
#19093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3808:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#19094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3809:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#19095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3810:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6

WARNING: line length of 122 exceeds 100 columns
#19096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3811:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#19097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3812:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#19098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3813:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#19099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3814:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa

WARNING: line length of 113 exceeds 100 columns
#19100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3815:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb

WARNING: line length of 123 exceeds 100 columns
#19101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3816:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3817:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14

WARNING: line length of 123 exceeds 100 columns
#19103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3818:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3819:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3820:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 125 exceeds 100 columns
#19106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3821:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3822:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3823:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L

WARNING: line length of 128 exceeds 100 columns
#19109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3824:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3825:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3826:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#19112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3827:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#19113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3828:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L

WARNING: line length of 128 exceeds 100 columns
#19114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3829:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3830:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#19116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3831:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0

WARNING: line length of 113 exceeds 100 columns
#19117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3832:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#19118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3833:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2

WARNING: line length of 113 exceeds 100 columns
#19119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3834:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#19120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3835:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#19121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3836:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#19122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3837:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#19123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3838:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#19124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3839:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8

WARNING: line length of 114 exceeds 100 columns
#19125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3840:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10

WARNING: line length of 114 exceeds 100 columns
#19126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3841:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18

WARNING: line length of 121 exceeds 100 columns
#19127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3842:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3843:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3844:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3845:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3846:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3847:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3848:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#19134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3849:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3850:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3851:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3852:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#19138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3853:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#19139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3854:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7

WARNING: line length of 121 exceeds 100 columns
#19140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3855:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#19141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3856:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#19142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3857:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0

WARNING: line length of 121 exceeds 100 columns
#19143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3858:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3859:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6

WARNING: line length of 121 exceeds 100 columns
#19145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3860:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L

WARNING: line length of 113 exceeds 100 columns
#19146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3861:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#19147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3862:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8

WARNING: line length of 114 exceeds 100 columns
#19148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3863:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#19149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3864:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#19150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3865:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12

WARNING: line length of 114 exceeds 100 columns
#19151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3866:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#19152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3867:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b

WARNING: line length of 114 exceeds 100 columns
#19153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3868:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f

WARNING: line length of 121 exceeds 100 columns
#19154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3869:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#19155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3870:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3871:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3872:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#19158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3873:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L

WARNING: line length of 121 exceeds 100 columns
#19159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3874:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#19160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3875:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L

WARNING: line length of 121 exceeds 100 columns
#19161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3876:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#19162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3877:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3878:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3879:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#19165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3880:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18

WARNING: line length of 121 exceeds 100 columns
#19166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3881:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3882:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3883:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#19169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3884:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#19170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3885:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3886:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3887:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3888:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3889:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3890:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3891:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3892:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3893:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3894:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3895:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3896:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3897:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3898:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3899:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3900:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3901:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3902:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3903:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3904:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3905:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3906:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3907:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3908:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3909:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3910:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3911:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3912:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3913:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3914:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3915:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3916:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3917:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3918:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3919:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3920:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3921:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3922:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3923:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3924:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3925:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3926:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3927:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3928:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3929:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3930:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3931:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3932:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3933:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3934:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3935:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10

WARNING: line length of 121 exceeds 100 columns
#19221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3936:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3937:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3938:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3939:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#19225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3940:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#19226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3941:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#19227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3942:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3943:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3944:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3945:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#19231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3946:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#19232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3947:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#19233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3948:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3949:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3950:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3951:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#19237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3952:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#19238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3953:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#19239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3954:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3955:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3956:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3957:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#19243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3958:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8

WARNING: line length of 114 exceeds 100 columns
#19244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3959:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#19245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3960:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3961:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3962:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#19248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3963:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#19249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3964:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#19250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3965:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#19251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3966:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#19252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3967:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#19253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3968:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#19254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3969:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#19255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3970:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#19256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3971:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#19257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3972:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#19258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3973:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#19259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3974:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#19260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3975:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3976:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3977:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3978:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3979:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#19265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3980:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#19266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3981:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3982:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#19268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3983:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3984:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#19270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3985:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#19271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3986:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#19272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3987:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#19273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3988:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#19274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3989:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#19275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3990:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#19276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3991:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#19277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3992:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4

WARNING: line length of 121 exceeds 100 columns
#19278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3993:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3994:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L

WARNING: line length of 113 exceeds 100 columns
#19280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3995:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#19281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3996:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#19282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3997:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#19283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3998:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#19284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:3999:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#19285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4000:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#19286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4001:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#19287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4002:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4003:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#19289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4004:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4005:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#19291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4006:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#19292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4007:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#19293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4008:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#19294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4009:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#19295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4010:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4011:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#19297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4012:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#19298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4013:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#19299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4014:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#19300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4015:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#19301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4016:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18

WARNING: line length of 121 exceeds 100 columns
#19302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4017:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#19303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4018:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4019:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#19305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4020:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#19306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4021:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#19307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4022:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8

WARNING: line length of 114 exceeds 100 columns
#19308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4023:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#19309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4024:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#19310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4025:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#19311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4026:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4027:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#19313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4028:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#19314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4029:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#19315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4030:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#19316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4031:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#19317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4032:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#19318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4033:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#19319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4034:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4035:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#19321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4036:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#19322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4037:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#19323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4038:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#19324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4039:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#19325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4040:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#19326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4041:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#19327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4042:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4

WARNING: line length of 114 exceeds 100 columns
#19328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4043:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#19329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4044:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4045:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4046:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L

WARNING: line length of 118 exceeds 100 columns
#19332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4047:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 117 exceeds 100 columns
#19333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4048:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 124 exceeds 100 columns
#19334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4049:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 122 exceeds 100 columns
#19335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4050:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#19336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4051:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#19337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4052:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#19338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4053:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#19339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4054:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#19340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4055:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#19341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4056:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#19342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4057:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#19343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4058:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e

WARNING: line length of 121 exceeds 100 columns
#19344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4059:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4060:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4061:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#19347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4062:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#19348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4063:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4064:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4065:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#19351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4066:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#19352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4067:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#19353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4068:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#19354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4069:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#19355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4070:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#19356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4071:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9

WARNING: line length of 113 exceeds 100 columns
#19357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4072:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#19358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4073:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#19359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4074:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11

WARNING: line length of 114 exceeds 100 columns
#19360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4075:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14

WARNING: line length of 114 exceeds 100 columns
#19361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4076:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18

WARNING: line length of 114 exceeds 100 columns
#19362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4077:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19

WARNING: line length of 114 exceeds 100 columns
#19363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4078:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#19364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4079:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4080:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4081:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4082:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4083:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#19369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4084:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#19370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4085:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4086:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#19372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4087:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4088:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#19374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4089:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#19375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4090:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#19376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4091:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#19377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4092:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#19378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4093:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#19379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4094:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2

WARNING: line length of 121 exceeds 100 columns
#19380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4095:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#19381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4096:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#19382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4097:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#19383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4098:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#19384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4099:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#19385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4100:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7

WARNING: line length of 121 exceeds 100 columns
#19386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4101:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#19387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4102:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4103:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L

WARNING: line length of 121 exceeds 100 columns
#19389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4104:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#19390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4105:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0

WARNING: line length of 117 exceeds 100 columns
#19391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4106:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6

WARNING: line length of 121 exceeds 100 columns
#19392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4107:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL

WARNING: line length of 123 exceeds 100 columns
#19393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4108:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L

WARNING: line length of 117 exceeds 100 columns
#19394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4109:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#19395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4110:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4

WARNING: line length of 123 exceeds 100 columns
#19396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4111:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL

WARNING: line length of 132 exceeds 100 columns
#19397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4112:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#19398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4113:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4114:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#19400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4115:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5

WARNING: line length of 113 exceeds 100 columns
#19401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4116:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7

WARNING: line length of 121 exceeds 100 columns
#19402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4117:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4118:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4119:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#19405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4120:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L

WARNING: line length of 113 exceeds 100 columns
#19406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4121:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#19407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4122:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#19408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4123:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4124:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4125:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#19411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4126:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#19412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4127:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4128:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4129:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#19415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4130:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#19416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4131:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4132:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4133:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#19419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4134:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4

WARNING: line length of 121 exceeds 100 columns
#19420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4135:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4136:
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4137:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#19423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4138:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4139:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#19425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4140:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#19426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4141:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#19427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4142:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8

WARNING: line length of 121 exceeds 100 columns
#19428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4143:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4144:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#19430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4145:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#19431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4146:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4147:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#19433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4148:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4149:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#19435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4150:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#19436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4151:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#19437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4152:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#19438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4153:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8

WARNING: line length of 114 exceeds 100 columns
#19439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4154:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#19440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4155:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4156:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4157:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4158:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L

WARNING: line length of 126 exceeds 100 columns
#19444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4159:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0

WARNING: line length of 132 exceeds 100 columns
#19445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4160:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L

WARNING: line length of 113 exceeds 100 columns
#19446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4161:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#19447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4162:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4

WARNING: line length of 121 exceeds 100 columns
#19448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4163:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4164:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L

WARNING: line length of 113 exceeds 100 columns
#19450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4165:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#19451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4166:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#19452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4167:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#19453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4168:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#19454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4169:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8

WARNING: line length of 121 exceeds 100 columns
#19455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4170:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4171:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4172:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#19458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4173:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#19459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4174:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#19460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4175:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8

WARNING: line length of 121 exceeds 100 columns
#19461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4176:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4177:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4178:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#19464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4179:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#19465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4180:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#19466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4181:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8

WARNING: line length of 121 exceeds 100 columns
#19467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4182:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4183:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4184:
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L

WARNING: line length of 134 exceeds 100 columns
#19470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4185:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#19471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4186:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#19472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4187:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#19473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4188:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#19474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4189:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#19475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4190:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#19476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4191:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#19477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4192:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#19478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4193:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#19479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4194:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#19480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4195:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#19481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4196:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#19482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4197:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4198:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#19484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4199:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#19485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4200:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#19486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4201:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#19487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4202:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#19488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4203:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4204:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#19490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4205:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#19491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4206:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#19492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4207:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4208:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#19494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4209:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#19495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4210:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#19496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4211:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4212:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#19498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4213:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4214:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#19500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4215:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#19501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4216:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#19502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4217:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#19503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4218:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#19504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4219:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4220:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#19506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4221:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#19507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4222:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#19508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4223:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#19509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4224:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#19510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4225:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#19511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4226:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#19512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4227:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4228:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4229:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#19515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4230:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#19516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4231:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#19517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4232:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#19518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4233:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#19519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4234:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#19520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4235:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#19521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4236:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#19522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4237:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#19523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4238:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#19524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4239:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4240:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4241:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4242:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4243:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4244:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4245:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#19531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4246:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4247:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#19533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4248:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#19534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4249:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#19535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4250:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#19536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4251:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#19537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4252:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#19538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4253:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#19539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4254:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#19540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4255:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#19541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4256:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#19542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4257:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#19543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4258:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#19544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4259:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#19545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4260:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#19546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4261:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#19547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4262:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#19548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4263:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#19549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4264:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#19550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4265:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#19551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4266:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4267:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#19553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4268:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#19554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4269:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#19555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4270:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#19556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4271:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4272:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#19558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4273:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#19559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4274:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#19560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4275:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4276:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#19562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4277:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#19563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4278:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#19564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4279:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4280:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#19566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4281:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#19567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4282:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#19568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4283:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#19569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4284:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#19570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4285:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#19571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4286:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#19572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4287:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#19573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4288:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#19574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4289:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#19575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4290:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#19576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4291:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#19577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4292:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4293:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4294:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4295:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4296:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4297:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4298:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#19584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4299:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4300:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4301:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4302:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#19588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4303:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#19589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4304:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#19590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4305:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#19591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4306:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#19592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4307:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#19593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4308:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#19594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4309:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#19595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4310:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#19596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4311:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#19597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4312:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#19598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4313:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4314:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#19600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4315:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#19601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4316:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#19602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4317:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#19603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4318:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#19604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4319:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4320:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#19606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4321:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#19607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4322:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#19608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4323:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#19609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4324:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#19610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4325:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4326:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#19612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4327:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4328:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4329:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#19615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4330:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#19616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4331:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4332:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#19618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4333:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4334:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#19620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4335:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#19621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4336:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#19622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4337:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4338:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#19624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4339:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#19625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4340:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#19626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4341:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#19627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4342:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#19628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4343:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4344:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#19630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4345:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#19631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4346:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#19632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4347:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#19633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4348:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#19634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4349:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4350:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#19636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4351:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4352:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4353:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#19639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4354:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#19640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4355:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4356:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#19642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4357:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4358:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#19644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4359:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#19645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4360:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#19646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4361:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#19647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4362:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#19648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4363:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4364:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#19650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4365:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#19651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4366:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#19652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4367:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#19653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4368:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#19654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4369:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#19655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4370:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4371:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4372:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#19658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4373:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#19659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4374:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#19660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4375:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#19661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4376:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#19662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4377:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#19663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4378:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#19664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4379:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#19665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4380:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#19666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4381:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#19667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4382:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#19668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4383:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#19669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4384:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#19670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4385:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#19671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4386:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4387:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#19673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4388:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#19674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4389:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#19675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4390:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4391:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#19677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4392:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#19678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4393:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#19679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4394:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#19680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4395:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#19681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4396:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#19682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4397:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#19683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4398:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4399:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#19685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4400:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4401:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#19687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4402:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#19688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4403:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#19689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4404:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#19690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4405:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4406:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#19692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4407:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#19693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4408:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#19694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4409:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#19695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4410:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4411:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#19697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4412:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#19698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4413:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4414:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4415:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#19701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4416:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 134 exceeds 100 columns
#19702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4417:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#19703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4418:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#19704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4419:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#19705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4420:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#19706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4421:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#19707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4422:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#19708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4423:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#19709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4424:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#19710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4425:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#19711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4426:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#19712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4427:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#19713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4428:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#19714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4429:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4430:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#19716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4431:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#19717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4432:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#19718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4433:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#19719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4434:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#19720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4435:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4436:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#19722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4437:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#19723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4438:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#19724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4439:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4440:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#19726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4441:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#19727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4442:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#19728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4443:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4444:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#19730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4445:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4446:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#19732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4447:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#19733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4448:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#19734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4449:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#19735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4450:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#19736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4451:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4452:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#19738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4453:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#19739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4454:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#19740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4455:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#19741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4456:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#19742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4457:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#19743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4458:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#19744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4459:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4460:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4461:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#19747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4462:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#19748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4463:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#19749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4464:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#19750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4465:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#19751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4466:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#19752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4467:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#19753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4468:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#19754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4469:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#19755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4470:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#19756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4471:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4472:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4473:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4474:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4475:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4476:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4477:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#19763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4478:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4479:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#19765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4480:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#19766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4481:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#19767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4482:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#19768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4483:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#19769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4484:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#19770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4485:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#19771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4486:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#19772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4487:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#19773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4488:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#19774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4489:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#19775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4490:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#19776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4491:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#19777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4492:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#19778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4493:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#19779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4494:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#19780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4495:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#19781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4496:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#19782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4497:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#19783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4498:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4499:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#19785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4500:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#19786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4501:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#19787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4502:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#19788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4503:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4504:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#19790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4505:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#19791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4506:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#19792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4507:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4508:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#19794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4509:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#19795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4510:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#19796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4511:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4512:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#19798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4513:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#19799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4514:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#19800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4515:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#19801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4516:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#19802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4517:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#19803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4518:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#19804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4519:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#19805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4520:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#19806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4521:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#19807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4522:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#19808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4523:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#19809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4524:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4525:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4526:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4527:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4528:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4529:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4530:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#19816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4531:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4532:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4533:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4534:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#19820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4535:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#19821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4536:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#19822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4537:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#19823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4538:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#19824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4539:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#19825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4540:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#19826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4541:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#19827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4542:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#19828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4543:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#19829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4544:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#19830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4545:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4546:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#19832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4547:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#19833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4548:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#19834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4549:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#19835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4550:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#19836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4551:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4552:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#19838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4553:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#19839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4554:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#19840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4555:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#19841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4556:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#19842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4557:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4558:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#19844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4559:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4560:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4561:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#19847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4562:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#19848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4563:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4564:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#19850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4565:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4566:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#19852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4567:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#19853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4568:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#19854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4569:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4570:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#19856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4571:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#19857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4572:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#19858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4573:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#19859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4574:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#19860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4575:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4576:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#19862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4577:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#19863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4578:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#19864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4579:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#19865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4580:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#19866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4581:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4582:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#19868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4583:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4584:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4585:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#19871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4586:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#19872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4587:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#19873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4588:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#19874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4589:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4590:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#19876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4591:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#19877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4592:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#19878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4593:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#19879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4594:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#19880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4595:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4596:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#19882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4597:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#19883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4598:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#19884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4599:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#19885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4600:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#19886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4601:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#19887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4602:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4603:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4604:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#19890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4605:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#19891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4606:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#19892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4607:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#19893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4608:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#19894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4609:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#19895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4610:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#19896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4611:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#19897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4612:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#19898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4613:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#19899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4614:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#19900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4615:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#19901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4616:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#19902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4617:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#19903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4618:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#19904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4619:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#19905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4620:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#19906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4621:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#19907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4622:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#19908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4623:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#19909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4624:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#19910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4625:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#19911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4626:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#19912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4627:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#19913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4628:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#19914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4629:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#19915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4630:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4631:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#19917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4632:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#19918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4633:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#19919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4634:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#19920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4635:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#19921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4636:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#19922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4637:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4638:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#19924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4639:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#19925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4640:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#19926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4641:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#19927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4642:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#19928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4643:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#19929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4644:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#19930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4645:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#19931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4646:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#19932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4647:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#19933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4648:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 134 exceeds 100 columns
#19934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4649:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#19935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4650:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#19936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4651:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#19937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4652:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#19938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4653:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#19939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4654:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#19940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4655:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#19941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4656:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#19942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4657:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#19943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4658:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#19944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4659:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#19945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4660:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#19946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4661:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#19947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4662:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#19948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4663:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#19949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4664:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#19950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4665:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#19951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4666:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#19952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4667:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4668:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#19954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4669:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#19955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4670:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#19956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4671:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#19957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4672:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#19958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4673:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#19959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4674:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#19960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4675:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#19961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4676:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#19962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4677:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#19963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4678:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#19964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4679:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#19965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4680:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#19966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4681:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#19967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4682:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#19968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4683:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4684:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#19970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4685:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#19971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4686:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#19972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4687:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#19973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4688:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#19974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4689:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#19975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4690:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#19976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4691:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#19977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4692:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#19978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4693:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#19979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4694:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#19980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4695:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#19981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4696:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#19982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4697:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#19983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4698:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#19984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4699:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#19985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4700:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#19986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4701:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#19987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4702:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#19988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4703:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#19989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4704:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#19990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4705:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#19991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4706:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#19992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4707:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#19993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4708:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#19994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4709:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#19995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4710:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#19996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4711:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#19997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4712:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#19998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4713:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#19999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4714:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#20000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4715:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#20001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4716:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#20002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4717:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#20003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4718:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#20004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4719:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#20005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4720:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#20006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4721:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#20007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4722:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#20008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4723:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#20009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4724:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#20010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4725:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#20011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4726:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4727:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#20013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4728:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#20014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4729:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#20015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4730:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4731:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#20017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4732:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#20018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4733:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#20019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4734:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#20020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4735:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4736:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#20022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4737:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#20023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4738:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#20024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4739:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4740:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#20026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4741:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4742:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#20028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4743:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4744:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#20030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4745:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#20031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4746:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#20032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4747:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#20033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4748:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#20034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4749:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#20035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4750:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#20036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4751:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#20037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4752:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#20038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4753:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#20039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4754:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#20040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4755:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#20041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4756:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4757:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4758:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4759:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4760:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4761:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4762:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4763:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4764:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4765:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4766:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#20052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4767:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4768:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#20054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4769:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#20055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4770:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#20056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4771:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#20057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4772:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#20058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4773:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#20059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4774:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#20060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4775:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#20061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4776:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#20062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4777:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4778:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#20064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4779:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4780:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4781:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#20067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4782:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#20068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4783:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4784:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#20070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4785:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#20071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4786:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4787:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#20073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4788:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4789:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4790:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#20076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4791:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4792:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4793:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#20079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4794:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4795:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4796:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#20082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4797:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4798:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4799:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#20085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4800:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#20086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4801:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4802:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#20088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4803:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#20089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4804:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4805:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#20091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4806:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#20092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4807:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4808:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#20094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4809:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#20095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4810:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4811:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#20097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4812:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4813:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4814:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#20100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4815:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4816:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4817:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#20103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4818:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4819:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4820:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#20106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4821:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4822:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4823:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#20109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4824:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#20110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4825:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4826:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#20112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4827:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4828:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#20114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4829:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4830:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#20116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4831:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#20117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4832:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#20118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4833:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#20119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4834:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4835:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4836:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#20122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4837:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#20123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4838:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#20124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4839:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#20125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4840:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#20126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4841:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#20127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4842:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#20128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4843:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#20129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4844:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#20130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4845:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#20131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4846:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#20132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4847:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#20133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4848:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#20134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4849:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#20135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4850:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4851:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#20137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4852:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#20138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4853:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#20139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4854:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4855:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#20141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4856:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#20142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4857:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#20143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4858:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#20144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4859:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#20145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4860:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#20146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4861:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#20147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4862:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4863:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#20149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4864:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4865:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#20151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4866:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#20152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4867:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#20153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4868:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#20154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4869:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4870:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#20156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4871:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#20157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4872:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#20158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4873:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#20159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4874:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#20160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4875:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#20161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4876:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#20162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4877:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#20163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4878:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4879:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#20165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4880:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 134 exceeds 100 columns
#20166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4881:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#20167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4882:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#20168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4883:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#20169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4884:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#20170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4885:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4886:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#20172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4887:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#20173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4888:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#20174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4889:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#20175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4890:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#20176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4891:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#20177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4892:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#20178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4893:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4894:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#20180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4895:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#20181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4896:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#20182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4897:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#20183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4898:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#20184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4899:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4900:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#20186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4901:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#20187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4902:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#20188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4903:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4904:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#20190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4905:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4906:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#20192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4907:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4908:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#20194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4909:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4910:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#20196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4911:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#20197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4912:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#20198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4913:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#20199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4914:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#20200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4915:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4916:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#20202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4917:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#20203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4918:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#20204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4919:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#20205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4920:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#20206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4921:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#20207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4922:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#20208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4923:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4924:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#20210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4925:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#20211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4926:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#20212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4927:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#20213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4928:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#20214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4929:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#20215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4930:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#20216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4931:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#20217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4932:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#20218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4933:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#20219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4934:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#20220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4935:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4936:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4937:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4938:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4939:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4940:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4941:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4942:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4943:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#20229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4944:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#20230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4945:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4946:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#20232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4947:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#20233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4948:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#20234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4949:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#20235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4950:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#20236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4951:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#20237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4952:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#20238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4953:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#20239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4954:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#20240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4955:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#20241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4956:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#20242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4957:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#20243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4958:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4959:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#20245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4960:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#20246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4961:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#20247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4962:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4963:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#20249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4964:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#20250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4965:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#20251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4966:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#20252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4967:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4968:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#20254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4969:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#20255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4970:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#20256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4971:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4972:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#20258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4973:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4974:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#20260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4975:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4976:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#20262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4977:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#20263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4978:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#20264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4979:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#20265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4980:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#20266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4981:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#20267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4982:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#20268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4983:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#20269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4984:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#20270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4985:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#20271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4986:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#20272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4987:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#20273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4988:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4989:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4990:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4991:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4992:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4993:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4994:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4995:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4996:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4997:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4998:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#20284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:4999:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5000:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#20286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5001:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#20287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5002:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#20288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5003:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#20289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5004:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#20290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5005:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#20291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5006:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#20292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5007:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#20293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5008:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#20294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5009:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5010:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#20296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5011:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5012:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5013:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#20299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5014:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#20300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5015:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5016:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#20302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5017:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#20303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5018:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5019:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#20305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5020:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5021:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5022:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#20308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5023:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5024:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5025:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#20311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5026:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5027:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5028:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#20314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5029:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5030:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5031:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#20317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5032:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#20318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5033:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5034:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#20320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5035:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#20321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5036:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5037:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#20323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5038:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#20324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5039:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5040:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#20326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5041:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#20327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5042:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5043:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#20329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5044:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5045:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5046:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#20332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5047:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5048:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5049:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#20335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5050:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5051:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5052:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#20338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5053:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5054:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5055:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#20341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5056:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#20342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5057:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5058:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#20344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5059:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5060:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#20346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5061:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5062:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#20348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5063:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#20349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5064:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#20350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5065:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#20351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5066:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5067:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5068:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#20354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5069:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#20355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5070:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#20356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5071:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#20357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5072:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#20358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5073:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#20359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5074:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#20360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5075:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#20361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5076:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#20362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5077:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#20363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5078:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#20364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5079:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#20365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5080:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#20366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5081:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#20367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5082:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5083:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#20369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5084:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#20370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5085:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#20371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5086:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5087:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#20373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5088:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#20374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5089:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#20375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5090:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#20376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5091:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#20377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5092:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#20378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5093:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#20379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5094:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5095:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#20381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5096:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5097:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#20383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5098:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#20384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5099:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#20385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5100:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#20386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5101:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5102:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#20388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5103:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#20389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5104:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#20390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5105:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#20391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5106:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#20392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5107:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#20393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5108:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#20394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5109:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#20395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5110:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5111:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#20397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5112:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 134 exceeds 100 columns
#20398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5113:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#20399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5114:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#20400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5115:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#20401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5116:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#20402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5117:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5118:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#20404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5119:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#20405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5120:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#20406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5121:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#20407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5122:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#20408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5123:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#20409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5124:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#20410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5125:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5126:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#20412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5127:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#20413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5128:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#20414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5129:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#20415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5130:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#20416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5131:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5132:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#20418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5133:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#20419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5134:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#20420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5135:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5136:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#20422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5137:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5138:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#20424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5139:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5140:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#20426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5141:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5142:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#20428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5143:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#20429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5144:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#20430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5145:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#20431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5146:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#20432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5147:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5148:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#20434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5149:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#20435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5150:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#20436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5151:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#20437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5152:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#20438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5153:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#20439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5154:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#20440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5155:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5156:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#20442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5157:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#20443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5158:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#20444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5159:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#20445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5160:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#20446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5161:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#20447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5162:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#20448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5163:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#20449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5164:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#20450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5165:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#20451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5166:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#20452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5167:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5168:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5169:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5170:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5171:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5172:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5173:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5174:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5175:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#20461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5176:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#20462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5177:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5178:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#20464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5179:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#20465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5180:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#20466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5181:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#20467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5182:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#20468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5183:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#20469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5184:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#20470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5185:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#20471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5186:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#20472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5187:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#20473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5188:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#20474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5189:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#20475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5190:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5191:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#20477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5192:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#20478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5193:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#20479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5194:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5195:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#20481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5196:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#20482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5197:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#20483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5198:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#20484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5199:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5200:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#20486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5201:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#20487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5202:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#20488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5203:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5204:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#20490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5205:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5206:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#20492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5207:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5208:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#20494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5209:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#20495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5210:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#20496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5211:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#20497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5212:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#20498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5213:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#20499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5214:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#20500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5215:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#20501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5216:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#20502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5217:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#20503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5218:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#20504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5219:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#20505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5220:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5221:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5222:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5223:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5224:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5225:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5226:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5227:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5228:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5229:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5230:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#20516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5231:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5232:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#20518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5233:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#20519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5234:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#20520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5235:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#20521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5236:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#20522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5237:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#20523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5238:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#20524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5239:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#20525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5240:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#20526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5241:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5242:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#20528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5243:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5244:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5245:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#20531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5246:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#20532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5247:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5248:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#20534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5249:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#20535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5250:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5251:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#20537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5252:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5253:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5254:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#20540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5255:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5256:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5257:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#20543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5258:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5259:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5260:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#20546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5261:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5262:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5263:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#20549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5264:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#20550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5265:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5266:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#20552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5267:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#20553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5268:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5269:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#20555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5270:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#20556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5271:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5272:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#20558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5273:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#20559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5274:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5275:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#20561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5276:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5277:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5278:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#20564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5279:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5280:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5281:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#20567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5282:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5283:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5284:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#20570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5285:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5286:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5287:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#20573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5288:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#20574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5289:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5290:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#20576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5291:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5292:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#20578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5293:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5294:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#20580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5295:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#20581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5296:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#20582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5297:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#20583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5298:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5299:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5300:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#20586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5301:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#20587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5302:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#20588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5303:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#20589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5304:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#20590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5305:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#20591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5306:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#20592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5307:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#20593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5308:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#20594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5309:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#20595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5310:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#20596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5311:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#20597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5312:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#20598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5313:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#20599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5314:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5315:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#20601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5316:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#20602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5317:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#20603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5318:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5319:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#20605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5320:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#20606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5321:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#20607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5322:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#20608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5323:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#20609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5324:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#20610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5325:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#20611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5326:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5327:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#20613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5328:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5329:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#20615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5330:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#20616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5331:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#20617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5332:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#20618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5333:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5334:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#20620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5335:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#20621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5336:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#20622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5337:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#20623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5338:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#20624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5339:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#20625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5340:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#20626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5341:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#20627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5342:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5343:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#20629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5344:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 134 exceeds 100 columns
#20630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5345:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#20631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5346:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#20632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5347:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#20633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5348:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#20634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5349:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5350:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#20636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5351:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#20637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5352:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#20638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5353:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#20639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5354:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#20640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5355:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#20641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5356:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#20642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5357:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5358:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#20644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5359:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#20645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5360:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#20646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5361:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#20647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5362:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#20648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5363:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5364:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#20650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5365:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#20651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5366:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#20652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5367:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5368:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#20654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5369:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5370:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#20656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5371:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5372:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#20658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5373:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5374:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#20660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5375:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#20661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5376:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#20662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5377:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#20663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5378:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#20664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5379:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5380:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#20666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5381:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#20667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5382:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#20668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5383:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#20669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5384:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#20670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5385:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#20671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5386:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#20672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5387:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5388:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#20674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5389:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#20675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5390:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#20676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5391:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#20677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5392:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#20678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5393:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#20679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5394:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#20680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5395:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#20681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5396:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#20682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5397:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#20683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5398:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#20684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5399:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5400:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5401:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5402:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5403:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5404:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5405:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5406:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5407:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#20693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5408:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#20694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5409:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5410:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#20696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5411:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#20697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5412:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#20698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5413:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#20699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5414:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#20700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5415:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#20701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5416:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#20702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5417:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#20703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5418:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#20704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5419:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#20705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5420:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#20706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5421:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#20707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5422:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5423:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#20709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5424:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#20710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5425:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#20711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5426:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5427:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#20713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5428:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#20714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5429:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#20715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5430:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#20716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5431:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5432:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#20718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5433:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#20719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5434:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#20720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5435:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5436:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#20722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5437:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5438:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#20724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5439:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5440:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#20726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5441:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#20727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5442:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#20728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5443:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#20729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5444:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#20730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5445:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#20731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5446:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#20732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5447:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#20733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5448:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#20734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5449:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#20735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5450:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#20736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5451:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#20737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5452:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5453:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5454:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5455:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5456:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5457:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5458:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5459:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5460:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5461:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5462:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#20748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5463:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5464:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#20750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5465:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#20751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5466:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#20752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5467:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#20753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5468:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#20754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5469:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#20755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5470:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#20756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5471:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#20757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5472:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#20758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5473:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5474:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#20760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5475:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5476:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5477:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#20763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5478:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#20764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5479:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5480:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#20766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5481:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#20767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5482:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5483:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#20769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5484:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5485:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5486:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#20772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5487:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5488:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5489:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#20775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5490:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5491:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5492:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#20778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5493:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5494:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5495:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#20781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5496:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#20782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5497:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5498:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#20784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5499:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#20785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5500:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5501:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#20787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5502:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#20788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5503:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5504:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#20790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5505:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#20791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5506:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#20792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5507:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#20793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5508:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#20794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5509:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5510:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#20796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5511:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5512:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5513:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#20799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5514:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#20800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5515:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5516:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#20802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5517:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5518:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#20804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5519:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#20805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5520:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#20806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5521:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5522:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#20808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5523:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5524:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#20810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5525:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5526:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#20812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5527:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#20813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5528:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#20814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5529:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#20815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5530:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5531:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5532:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#20818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5533:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#20819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5534:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#20820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5535:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#20821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5536:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#20822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5537:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#20823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5538:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#20824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5539:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#20825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5540:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#20826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5541:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#20827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5542:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#20828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5543:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#20829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5544:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#20830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5545:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#20831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5546:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#20832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5547:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#20833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5548:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#20834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5549:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#20835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5550:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#20836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5551:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#20837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5552:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#20838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5553:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#20839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5554:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#20840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5555:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#20841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5556:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#20842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5557:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#20843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5558:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5559:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#20845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5560:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#20846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5561:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#20847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5562:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#20848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5563:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#20849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5564:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#20850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5565:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5566:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#20852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5567:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#20853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5568:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#20854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5569:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#20855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5570:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#20856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5571:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#20857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5572:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#20858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5573:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#20859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5574:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5575:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#20861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5576:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 134 exceeds 100 columns
#20862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5577:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#20863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5578:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#20864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5579:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#20865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5580:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#20866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5581:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5582:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#20868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5583:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#20869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5584:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#20870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5585:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#20871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5586:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#20872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5587:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#20873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5588:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#20874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5589:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5590:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#20876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5591:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#20877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5592:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#20878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5593:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#20879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5594:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#20880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5595:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5596:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#20882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5597:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#20883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5598:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#20884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5599:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5600:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#20886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5601:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5602:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#20888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5603:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5604:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#20890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5605:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5606:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#20892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5607:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#20893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5608:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#20894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5609:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#20895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5610:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#20896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5611:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5612:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#20898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5613:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#20899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5614:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#20900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5615:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#20901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5616:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#20902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5617:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#20903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5618:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#20904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5619:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#20905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5620:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#20906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5621:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#20907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5622:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#20908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5623:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#20909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5624:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#20910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5625:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#20911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5626:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#20912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5627:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#20913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5628:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#20914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5629:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#20915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5630:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#20916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5631:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5632:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5633:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5634:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5635:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5636:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5637:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5638:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5639:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#20925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5640:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#20926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5641:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#20927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5642:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#20928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5643:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#20929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5644:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#20930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5645:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#20931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5646:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#20932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5647:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#20933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5648:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#20934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5649:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#20935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5650:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#20936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5651:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#20937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5652:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#20938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5653:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#20939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5654:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5655:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#20941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5656:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#20942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5657:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#20943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5658:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5659:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#20945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5660:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#20946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5661:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#20947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5662:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#20948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5663:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5664:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#20950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5665:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#20951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5666:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#20952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5667:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#20953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5668:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#20954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5669:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#20955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5670:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#20956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5671:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#20957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5672:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#20958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5673:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#20959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5674:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#20960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5675:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#20961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5676:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#20962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5677:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#20963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5678:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#20964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5679:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#20965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5680:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#20966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5681:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#20967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5682:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#20968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5683:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#20969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5684:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#20970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5685:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#20971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5686:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#20972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5687:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#20973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5688:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#20974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5689:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#20975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5690:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#20976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5691:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#20977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5692:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#20978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5693:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#20979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5694:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#20980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5695:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#20981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5696:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#20982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5697:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#20983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5698:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#20984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5699:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#20985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5700:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#20986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5701:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#20987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5702:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#20988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5703:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#20989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5704:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#20990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5705:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#20991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5706:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#20992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5707:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#20993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5708:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#20994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5709:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#20995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5710:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#20996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5711:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#20997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5712:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#20998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5713:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#20999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5714:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#21000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5715:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#21001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5716:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#21002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5717:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5718:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#21004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5719:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#21005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5720:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5721:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#21007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5722:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#21008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5723:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#21009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5724:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#21010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5725:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#21011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5726:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#21012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5727:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#21013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5728:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#21014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5729:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#21015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5730:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#21016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5731:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#21017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5732:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#21018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5733:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#21019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5734:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#21020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5735:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#21021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5736:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#21022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5737:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#21023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5738:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#21024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5739:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#21025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5740:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#21026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5741:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5742:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#21028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5743:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#21029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5744:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5745:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#21031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5746:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#21032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5747:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#21033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5748:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#21034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5749:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#21035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5750:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#21036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5751:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#21037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5752:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#21038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5753:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#21039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5754:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#21040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5755:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5756:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#21042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5757:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#21043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5758:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#21044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5759:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#21045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5760:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#21046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5761:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#21047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5762:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5763:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5764:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#21050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5765:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#21051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5766:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#21052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5767:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#21053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5768:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#21054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5769:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#21055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5770:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#21056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5771:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#21057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5772:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#21058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5773:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#21059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5774:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#21060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5775:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#21061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5776:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#21062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5777:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#21063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5778:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#21064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5779:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#21065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5780:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#21066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5781:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#21067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5782:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#21068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5783:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#21069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5784:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#21070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5785:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#21071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5786:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#21072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5787:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#21073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5788:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#21074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5789:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#21075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5790:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5791:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#21077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5792:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5793:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#21079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5794:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#21080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5795:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#21081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5796:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#21082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5797:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5798:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#21084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5799:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#21085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5800:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#21086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5801:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#21087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5802:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#21088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5803:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#21089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5804:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#21090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5805:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5806:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5807:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5808:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 134 exceeds 100 columns
#21094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5809:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#21095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5810:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 132 exceeds 100 columns
#21096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5811:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 136 exceeds 100 columns
#21097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5812:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 123 exceeds 100 columns
#21098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5813:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#21099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5814:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5

WARNING: line length of 125 exceeds 100 columns
#21100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5815:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 139 exceeds 100 columns
#21101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5816:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 123 exceeds 100 columns
#21102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5817:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 115 exceeds 100 columns
#21103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5818:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9

WARNING: line length of 121 exceeds 100 columns
#21104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5819:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 115 exceeds 100 columns
#21105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5820:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb

WARNING: line length of 140 exceeds 100 columns
#21106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5821:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#21107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5822:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14

WARNING: line length of 140 exceeds 100 columns
#21108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5823:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 137 exceeds 100 columns
#21109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5824:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 138 exceeds 100 columns
#21110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5825:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 142 exceeds 100 columns
#21111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5826:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 129 exceeds 100 columns
#21112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5827:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5828:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L

WARNING: line length of 131 exceeds 100 columns
#21114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5829:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 145 exceeds 100 columns
#21115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5830:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 129 exceeds 100 columns
#21116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5831:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5832:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L

WARNING: line length of 127 exceeds 100 columns
#21118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5833:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#21119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5834:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L

WARNING: line length of 145 exceeds 100 columns
#21120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5835:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#21121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5836:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L

WARNING: line length of 115 exceeds 100 columns
#21122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5837:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#21123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5838:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4

WARNING: line length of 116 exceeds 100 columns
#21124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5839:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8

WARNING: line length of 117 exceeds 100 columns
#21125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5840:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb

WARNING: line length of 113 exceeds 100 columns
#21126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5841:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe

WARNING: line length of 113 exceeds 100 columns
#21127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5842:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf

WARNING: line length of 121 exceeds 100 columns
#21128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5843:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5844:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L

WARNING: line length of 122 exceeds 100 columns
#21130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5845:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L

WARNING: line length of 123 exceeds 100 columns
#21131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5846:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L

WARNING: line length of 121 exceeds 100 columns
#21132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5847:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#21133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5848:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L

WARNING: line length of 113 exceeds 100 columns
#21134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5849:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0

WARNING: line length of 113 exceeds 100 columns
#21135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5850:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4

WARNING: line length of 121 exceeds 100 columns
#21136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5851:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5852:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#21138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5853:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#21139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5854:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1

WARNING: line length of 113 exceeds 100 columns
#21140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5855:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#21141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5856:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3

WARNING: line length of 113 exceeds 100 columns
#21142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5857:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4

WARNING: line length of 113 exceeds 100 columns
#21143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5858:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#21144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5859:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6

WARNING: line length of 113 exceeds 100 columns
#21145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5860:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7

WARNING: line length of 113 exceeds 100 columns
#21146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5861:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8

WARNING: line length of 114 exceeds 100 columns
#21147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5862:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17

WARNING: line length of 121 exceeds 100 columns
#21148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5863:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5864:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5865:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5866:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5867:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5868:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5869:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5870:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5871:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#21157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5872:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#21158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5873:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#21159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5874:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL

WARNING: line length of 126 exceeds 100 columns
#21160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5875:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0

WARNING: line length of 126 exceeds 100 columns
#21161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5876:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10

WARNING: line length of 132 exceeds 100 columns
#21162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5877:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL

WARNING: line length of 131 exceeds 100 columns
#21163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5878:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L

WARNING: line length of 128 exceeds 100 columns
#21164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5879:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 125 exceeds 100 columns
#21165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5880:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1

WARNING: line length of 126 exceeds 100 columns
#21166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5881:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 130 exceeds 100 columns
#21167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5882:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#21168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5883:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5

WARNING: line length of 119 exceeds 100 columns
#21169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5884:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6

WARNING: line length of 133 exceeds 100 columns
#21170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5885:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 117 exceeds 100 columns
#21171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5886:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#21172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5887:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9

WARNING: line length of 115 exceeds 100 columns
#21173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5888:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa

WARNING: line length of 113 exceeds 100 columns
#21174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5889:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb

WARNING: line length of 134 exceeds 100 columns
#21175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5890:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#21176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5891:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14

WARNING: line length of 134 exceeds 100 columns
#21177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5892:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 131 exceeds 100 columns
#21178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5893:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L

WARNING: line length of 132 exceeds 100 columns
#21179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5894:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L

WARNING: line length of 136 exceeds 100 columns
#21180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5895:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5896:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L

WARNING: line length of 125 exceeds 100 columns
#21182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5897:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L

WARNING: line length of 139 exceeds 100 columns
#21183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5898:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 123 exceeds 100 columns
#21184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5899:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5900:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5901:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#21187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5902:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L

WARNING: line length of 139 exceeds 100 columns
#21188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5903:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#21189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5904:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#21190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5905:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0

WARNING: line length of 113 exceeds 100 columns
#21191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5906:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1

WARNING: line length of 114 exceeds 100 columns
#21192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5907:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#21193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5908:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3

WARNING: line length of 113 exceeds 100 columns
#21194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5909:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4

WARNING: line length of 113 exceeds 100 columns
#21195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5910:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5

WARNING: line length of 113 exceeds 100 columns
#21196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5911:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6

WARNING: line length of 113 exceeds 100 columns
#21197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5912:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#21198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5913:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8

WARNING: line length of 114 exceeds 100 columns
#21199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5914:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#21200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5915:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#21201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5916:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5917:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5918:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5919:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5920:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5921:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5922:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5923:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5924:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5925:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#21211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5926:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#21212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5927:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#21213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5928:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7

WARNING: line length of 121 exceeds 100 columns
#21214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5929:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#21215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5930:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L

WARNING: line length of 114 exceeds 100 columns
#21216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5931:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#21217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5932:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f

WARNING: line length of 121 exceeds 100 columns
#21218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5933:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#21219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5934:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#21220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5935:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5

WARNING: line length of 121 exceeds 100 columns
#21221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5936:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#21222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5937:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#21223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5938:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1

WARNING: line length of 118 exceeds 100 columns
#21224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5939:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 114 exceeds 100 columns
#21225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5940:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#21226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5941:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9

WARNING: line length of 118 exceeds 100 columns
#21227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5942:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 115 exceeds 100 columns
#21228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5943:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#21229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5944:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11

WARNING: line length of 119 exceeds 100 columns
#21230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5945:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 115 exceeds 100 columns
#21231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5946:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#21232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5947:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19

WARNING: line length of 119 exceeds 100 columns
#21233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5948:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#21234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5949:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5950:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L

WARNING: line length of 124 exceeds 100 columns
#21236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5951:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#21237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5952:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5953:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L

WARNING: line length of 124 exceeds 100 columns
#21239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5954:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#21240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5955:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#21241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5956:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L

WARNING: line length of 124 exceeds 100 columns
#21242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5957:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#21243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5958:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#21244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5959:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L

WARNING: line length of 124 exceeds 100 columns
#21245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5960:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 115 exceeds 100 columns
#21246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5961:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#21247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5962:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1

WARNING: line length of 119 exceeds 100 columns
#21248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5963:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4

WARNING: line length of 115 exceeds 100 columns
#21249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5964:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#21250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5965:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9

WARNING: line length of 119 exceeds 100 columns
#21251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5966:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc

WARNING: line length of 116 exceeds 100 columns
#21252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5967:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#21253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5968:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11

WARNING: line length of 120 exceeds 100 columns
#21254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5969:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14

WARNING: line length of 116 exceeds 100 columns
#21255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5970:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#21256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5971:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19

WARNING: line length of 120 exceeds 100 columns
#21257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5972:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c

WARNING: line length of 121 exceeds 100 columns
#21258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5973:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5974:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L

WARNING: line length of 125 exceeds 100 columns
#21260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5975:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#21261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5976:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5977:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L

WARNING: line length of 125 exceeds 100 columns
#21263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5978:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#21264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5979:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#21265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5980:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L

WARNING: line length of 125 exceeds 100 columns
#21266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5981:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#21267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5982:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#21268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5983:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L

WARNING: line length of 125 exceeds 100 columns
#21269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5984:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#21270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5985:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#21271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5986:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#21272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5987:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5988:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#21274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5989:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#21275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5990:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#21276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5991:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0

WARNING: line length of 113 exceeds 100 columns
#21277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5992:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4

WARNING: line length of 114 exceeds 100 columns
#21278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5993:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f

WARNING: line length of 121 exceeds 100 columns
#21279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5994:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5995:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5996:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L

WARNING: line length of 129 exceeds 100 columns
#21282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5997:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0

WARNING: line length of 128 exceeds 100 columns
#21283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5998:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c

WARNING: line length of 135 exceeds 100 columns
#21284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:5999:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL

WARNING: line length of 133 exceeds 100 columns
#21285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6000:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L

WARNING: line length of 113 exceeds 100 columns
#21286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6001:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0

WARNING: line length of 124 exceeds 100 columns
#21287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6002:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#21288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6003:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8

WARNING: line length of 113 exceeds 100 columns
#21289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6004:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc

WARNING: line length of 121 exceeds 100 columns
#21290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6005:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10

WARNING: line length of 120 exceeds 100 columns
#21291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6006:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14

WARNING: line length of 114 exceeds 100 columns
#21292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6007:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18

WARNING: line length of 123 exceeds 100 columns
#21293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6008:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e

WARNING: line length of 121 exceeds 100 columns
#21294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6009:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL

WARNING: line length of 130 exceeds 100 columns
#21295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6010:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#21296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6011:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#21297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6012:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L

WARNING: line length of 126 exceeds 100 columns
#21298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6013:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L

WARNING: line length of 125 exceeds 100 columns
#21299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6014:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#21300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6015:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L

WARNING: line length of 128 exceeds 100 columns
#21301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6016:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L

WARNING: line length of 114 exceeds 100 columns
#21302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6017:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0

WARNING: line length of 120 exceeds 100 columns
#21303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6018:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8

WARNING: line length of 121 exceeds 100 columns
#21304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6019:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L

WARNING: line length of 126 exceeds 100 columns
#21305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6020:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#21306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6021:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0

WARNING: line length of 121 exceeds 100 columns
#21307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6022:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6023:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#21309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6024:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6025:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#21311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6026:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1

WARNING: line length of 119 exceeds 100 columns
#21312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6027:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4

WARNING: line length of 133 exceeds 100 columns
#21313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6028:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#21314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6029:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6030:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L

WARNING: line length of 125 exceeds 100 columns
#21316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6031:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L

WARNING: line length of 139 exceeds 100 columns
#21317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6032:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L

WARNING: line length of 113 exceeds 100 columns
#21318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6033:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#21319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6034:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8

WARNING: line length of 114 exceeds 100 columns
#21320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6035:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10

WARNING: line length of 114 exceeds 100 columns
#21321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6036:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f

WARNING: line length of 121 exceeds 100 columns
#21322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6037:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6038:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6039:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6040:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#21326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6041:
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6042:
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6043:
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6044:
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6045:
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6046:
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6047:
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6048:
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6049:
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6050:
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6051:
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6052:
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6053:
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6054:
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6055:
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6056:
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6057:
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6058:
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6059:
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6060:
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6061:
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6062:
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6063:
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6064:
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6065:
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6066:
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6067:
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6068:
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6069:
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6070:
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6071:
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6072:
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6073:
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6074:
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6075:
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6076:
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6077:
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6078:
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6079:
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6080:
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6081:
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6082:
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6083:
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6084:
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6085:
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6086:
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6087:
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6088:
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6089:
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6090:
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6091:
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6092:
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6093:
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6094:
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6095:
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6096:
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6097:
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6098:
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6099:
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6100:
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6101:
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6102:
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6103:
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6104:
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6105:
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6106:
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6107:
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6108:
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6109:
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6110:
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6111:
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6112:
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6113:
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6114:
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#21400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6115:
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#21401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6116:
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#21402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6117:
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6118:
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6119:
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6120:
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6121:
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#21407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6122:
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#21408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6123:
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#21409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6124:
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#21410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6125:
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6126:
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6127:
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6128:
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6129:
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#21415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6130:
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#21416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6131:
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#21417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6132:
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#21418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6133:
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6134:
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6135:
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6136:
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6137:
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#21423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6138:
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#21424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6139:
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#21425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6140:
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#21426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6141:
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6142:
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6143:
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6144:
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6145:
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#21431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6146:
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#21432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6147:
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#21433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6148:
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#21434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6149:
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6150:
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#21436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6151:
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#21437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6152:
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#21438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6153:
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#21439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6154:
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6155:
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#21441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6156:
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#21442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6157:
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#21443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6158:
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6159:
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#21445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6160:
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#21446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6161:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#21447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6162:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#21448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6163:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#21449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6164:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#21450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6165:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6166:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6167:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#21453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6168:
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#21454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6169:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#21455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6170:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#21456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6171:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#21457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6172:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#21458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6173:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6174:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6175:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#21461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6176:
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#21462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6177:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#21463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6178:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#21464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6179:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#21465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6180:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#21466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6181:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6182:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6183:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#21469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6184:
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#21470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6185:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#21471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6186:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#21472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6187:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#21473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6188:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#21474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6189:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6190:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6191:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#21477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6192:
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#21478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6193:
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6194:
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1

WARNING: line length of 113 exceeds 100 columns
#21480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6195:
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2

WARNING: line length of 113 exceeds 100 columns
#21481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6196:
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3

WARNING: line length of 113 exceeds 100 columns
#21482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6197:
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4

WARNING: line length of 113 exceeds 100 columns
#21483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6198:
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5

WARNING: line length of 113 exceeds 100 columns
#21484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6199:
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6

WARNING: line length of 113 exceeds 100 columns
#21485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6200:
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7

WARNING: line length of 121 exceeds 100 columns
#21486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6201:
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6202:
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6203:
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6204:
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6205:
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6206:
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6207:
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6208:
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L

WARNING: line length of 113 exceeds 100 columns
#21494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6209:
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6210:
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6211:
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6212:
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6213:
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#21499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6214:
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#21500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6215:
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6216:
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#21502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6217:
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#21503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6218:
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#21504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6219:
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#21505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6220:
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3

WARNING: line length of 113 exceeds 100 columns
#21506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6221:
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4

WARNING: line length of 114 exceeds 100 columns
#21507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6222:
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11

WARNING: line length of 121 exceeds 100 columns
#21508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6223:
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6224:
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6225:
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6226:
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6227:
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6228:
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L

WARNING: line length of 113 exceeds 100 columns
#21514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6229:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#21515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6230:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3

WARNING: line length of 113 exceeds 100 columns
#21516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6231:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#21517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6232:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT                                                              0x7

WARNING: line length of 113 exceeds 100 columns
#21518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6233:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#21519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6234:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT                                                              0xb

WARNING: line length of 113 exceeds 100 columns
#21520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6235:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#21521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6236:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT                                                              0xf

WARNING: line length of 121 exceeds 100 columns
#21522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6237:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6238:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK                                                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6239:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK                                                           0x00000070L

WARNING: line length of 121 exceeds 100 columns
#21525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6240:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK                                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6241:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK                                                           0x00000700L

WARNING: line length of 121 exceeds 100 columns
#21527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6242:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK                                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#21528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6243:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK                                                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#21529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6244:
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK                                                                0x00008000L

WARNING: line length of 113 exceeds 100 columns
#21530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6245:
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#21531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6246:
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#21532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6247:
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6248:
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#21534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6249:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#21535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6250:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#21536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6251:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#21537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6252:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#21538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6253:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6254:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6255:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#21541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6256:
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#21542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6257:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#21543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6258:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#21544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6259:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#21545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6260:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#21546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6261:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#21547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6262:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5

WARNING: line length of 113 exceeds 100 columns
#21548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6263:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6

WARNING: line length of 113 exceeds 100 columns
#21549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6264:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7

WARNING: line length of 113 exceeds 100 columns
#21550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6265:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#21551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6266:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE__SHIFT                                                   0x9

WARNING: line length of 121 exceeds 100 columns
#21552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6267:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6268:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6269:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6270:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6271:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6272:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6273:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6274:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6275:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6276:
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE_MASK                                                     0x00000200L

WARNING: line length of 113 exceeds 100 columns
#21562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6277:
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#21563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6278:
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#21564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6279:
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#21565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6280:
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6281:
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#21567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6282:
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6283:
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#21569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6284:
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#21570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6285:
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#21571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6286:
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9

WARNING: line length of 114 exceeds 100 columns
#21572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6287:
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#21573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6288:
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#21574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6289:
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19

WARNING: line length of 121 exceeds 100 columns
#21575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6290:
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6291:
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#21577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6292:
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6293:
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6294:
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#21580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6295:
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#21581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6296:
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L

WARNING: line length of 113 exceeds 100 columns
#21582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6297:
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#21583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6298:
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6299:
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#21585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6300:
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L

WARNING: line length of 113 exceeds 100 columns
#21586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6301:
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#21587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6302:
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#21588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6303:
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#21589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6304:
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6305:
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#21591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6306:
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6307:
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#21593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6308:
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6309:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#21595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6310:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3

WARNING: line length of 113 exceeds 100 columns
#21596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6311:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#21597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6312:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7

WARNING: line length of 113 exceeds 100 columns
#21598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6313:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#21599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6314:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb

WARNING: line length of 113 exceeds 100 columns
#21600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6315:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#21601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6316:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf

WARNING: line length of 121 exceeds 100 columns
#21602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6317:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6318:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6319:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L

WARNING: line length of 121 exceeds 100 columns
#21605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6320:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6321:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L

WARNING: line length of 121 exceeds 100 columns
#21607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6322:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#21608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6323:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#21609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6324:
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L

WARNING: line length of 113 exceeds 100 columns
#21610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6325:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#21611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6326:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3

WARNING: line length of 113 exceeds 100 columns
#21612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6327:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#21613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6328:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7

WARNING: line length of 121 exceeds 100 columns
#21614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6329:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6330:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6331:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L

WARNING: line length of 121 exceeds 100 columns
#21617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6332:
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L

WARNING: line length of 113 exceeds 100 columns
#21618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6333:
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#21619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6334:
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT                                                                    0x2

WARNING: line length of 113 exceeds 100 columns
#21620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6335:
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT                                                               0x3

WARNING: line length of 113 exceeds 100 columns
#21621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6336:
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT                                                                    0x5

WARNING: line length of 113 exceeds 100 columns
#21622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6337:
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT                                                               0x6

WARNING: line length of 113 exceeds 100 columns
#21623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6338:
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT                                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#21624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6339:
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT                                                               0x9

WARNING: line length of 113 exceeds 100 columns
#21625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6340:
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT                                                                    0xb

WARNING: line length of 121 exceeds 100 columns
#21626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6341:
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#21627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6342:
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK                                                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6343:
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK                                                                 0x00000018L

WARNING: line length of 121 exceeds 100 columns
#21629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6344:
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK                                                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6345:
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK                                                                 0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#21631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6346:
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK                                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6347:
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK                                                                 0x00000600L

WARNING: line length of 121 exceeds 100 columns
#21633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6348:
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK                                                                      0x00000800L

WARNING: line length of 113 exceeds 100 columns
#21634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6349:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#21635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6350:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT                                                0x1

WARNING: line length of 113 exceeds 100 columns
#21636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6351:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#21637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6352:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT                                                0x3

WARNING: line length of 113 exceeds 100 columns
#21638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6353:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x6

WARNING: line length of 113 exceeds 100 columns
#21639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6354:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#21640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6355:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#21641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6356:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#21642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6357:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT                                        0xa

WARNING: line length of 113 exceeds 100 columns
#21643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6358:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT                                             0xb

WARNING: line length of 113 exceeds 100 columns
#21644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6359:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT                                        0xc

WARNING: line length of 113 exceeds 100 columns
#21645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6360:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT                                             0xd

WARNING: line length of 121 exceeds 100 columns
#21646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6361:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6362:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK                                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6363:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6364:
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK                                                  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6365:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6366:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6367:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6368:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6369:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK                                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#21655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6370:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#21656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6371:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK                                          0x00001000L

WARNING: line length of 121 exceeds 100 columns
#21657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6372:
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK                                               0x00002000L

WARNING: line length of 113 exceeds 100 columns
#21658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6373:
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6374:
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6375:
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6376:
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6377:
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6378:
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6379:
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6380:
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6381:
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6382:
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6383:
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6384:
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6385:
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#21671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6386:
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#21672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6387:
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1__SHIFT                                                      0x3

WARNING: line length of 113 exceeds 100 columns
#21673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6388:
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#21674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6389:
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1__SHIFT                                                      0x6

WARNING: line length of 113 exceeds 100 columns
#21675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6390:
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2__SHIFT                                                      0x7

WARNING: line length of 113 exceeds 100 columns
#21676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6391:
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1__SHIFT                                                      0x9

WARNING: line length of 113 exceeds 100 columns
#21677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6392:
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT                                                      0xa

WARNING: line length of 121 exceeds 100 columns
#21678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6393:
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6394:
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2_MASK                                                        0x00000006L

WARNING: line length of 121 exceeds 100 columns
#21680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6395:
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1_MASK                                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6396:
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2_MASK                                                        0x00000030L

WARNING: line length of 121 exceeds 100 columns
#21682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6397:
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1_MASK                                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6398:
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2_MASK                                                        0x00000180L

WARNING: line length of 121 exceeds 100 columns
#21684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6399:
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1_MASK                                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6400:
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2_MASK                                                        0x00000C00L

WARNING: line length of 113 exceeds 100 columns
#21686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6401:
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6402:
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14

WARNING: line length of 121 exceeds 100 columns
#21688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6403:
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL

WARNING: line length of 121 exceeds 100 columns
#21689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6404:
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L

WARNING: line length of 113 exceeds 100 columns
#21690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6405:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#21691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6406:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#21692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6407:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#21693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6408:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#21694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6409:
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#21695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6410:
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#21696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6411:
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e

WARNING: line length of 114 exceeds 100 columns
#21697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6412:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#21698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6413:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#21699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6414:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#21700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6415:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#21701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6416:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L

WARNING: line length of 121 exceeds 100 columns
#21702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6417:
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#21703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6418:
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#21704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6419:
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L

WARNING: line length of 121 exceeds 100 columns
#21705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6420:
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#21706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6421:
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#21707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6422:
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#21708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6423:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#21709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6424:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#21710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6425:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#21711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6426:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#21712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6427:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#21713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6428:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5

WARNING: line length of 113 exceeds 100 columns
#21714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6429:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#21715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6430:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7

WARNING: line length of 113 exceeds 100 columns
#21716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6431:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#21717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6432:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb

WARNING: line length of 121 exceeds 100 columns
#21718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6433:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6434:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6435:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6436:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6437:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6438:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6439:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6440:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6441:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L

WARNING: line length of 121 exceeds 100 columns
#21727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6442:
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L

WARNING: line length of 113 exceeds 100 columns
#21728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6443:
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#21729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6444:
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#21730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6445:
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2

WARNING: line length of 113 exceeds 100 columns
#21731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6446:
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#21732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6447:
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#21733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6448:
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#21734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6449:
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#21735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6450:
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9

WARNING: line length of 113 exceeds 100 columns
#21736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6451:
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#21737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6452:
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb

WARNING: line length of 114 exceeds 100 columns
#21738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6453:
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11

WARNING: line length of 114 exceeds 100 columns
#21739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6454:
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#21740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6455:
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13

WARNING: line length of 114 exceeds 100 columns
#21741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6456:
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16

WARNING: line length of 114 exceeds 100 columns
#21742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6457:
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#21743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6458:
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#21744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6459:
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#21745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6460:
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#21746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6461:
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#21747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6462:
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6463:
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6464:
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6465:
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6466:
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6467:
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6468:
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6469:
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6470:
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#21756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6471:
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#21757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6472:
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L

WARNING: line length of 121 exceeds 100 columns
#21758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6473:
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#21759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6474:
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#21760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6475:
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#21761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6476:
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#21762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6477:
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#21763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6478:
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#21764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6479:
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#21765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6480:
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#21766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6481:
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#21767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6482:
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#21768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6483:
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6484:
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#21770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6485:
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#21771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6486:
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#21772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6487:
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6488:
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#21774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6489:
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#21775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6490:
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6491:
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#21777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6492:
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#21778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6493:
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#21779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6494:
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11

WARNING: line length of 114 exceeds 100 columns
#21780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6495:
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14

WARNING: line length of 121 exceeds 100 columns
#21781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6496:
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#21782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6497:
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#21783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6498:
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#21784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6499:
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L

WARNING: line length of 121 exceeds 100 columns
#21785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6500:
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L

WARNING: line length of 113 exceeds 100 columns
#21786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6501:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#21787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6502:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#21788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6503:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#21789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6504:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#21790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6505:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#21791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6506:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5

WARNING: line length of 113 exceeds 100 columns
#21792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6507:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6

WARNING: line length of 113 exceeds 100 columns
#21793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6508:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#21794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6509:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#21795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6510:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#21796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6511:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb

WARNING: line length of 113 exceeds 100 columns
#21797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6512:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#21798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6513:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd

WARNING: line length of 114 exceeds 100 columns
#21799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6514:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#21800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6515:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11

WARNING: line length of 114 exceeds 100 columns
#21801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6516:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12

WARNING: line length of 114 exceeds 100 columns
#21802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6517:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13

WARNING: line length of 114 exceeds 100 columns
#21803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6518:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#21804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6519:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15

WARNING: line length of 114 exceeds 100 columns
#21805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6520:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16

WARNING: line length of 121 exceeds 100 columns
#21806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6521:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6522:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#21808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6523:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#21809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6524:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6525:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6526:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6527:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6528:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6529:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6530:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#21816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6531:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#21817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6532:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#21818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6533:
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#21819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6534:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#21820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6535:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L

WARNING: line length of 121 exceeds 100 columns
#21821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6536:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#21822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6537:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#21823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6538:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#21824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6539:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L

WARNING: line length of 121 exceeds 100 columns
#21825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6540:
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L

WARNING: line length of 113 exceeds 100 columns
#21826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6541:
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#21827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6542:
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#21828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6543:
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6544:
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#21830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6545:
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#21831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6546:
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#21832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6547:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#21833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6548:
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT                                                       0x3

WARNING: line length of 113 exceeds 100 columns
#21834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6549:
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#21835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6550:
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#21836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6551:
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#21837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6552:
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#21838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6553:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#21839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6554:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9

WARNING: line length of 113 exceeds 100 columns
#21840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6555:
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc

WARNING: line length of 113 exceeds 100 columns
#21841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6556:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe

WARNING: line length of 114 exceeds 100 columns
#21842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6557:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#21843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6558:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#21844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6559:
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6560:
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6561:
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6562:
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6563:
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6564:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6565:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6566:
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00003000L

WARNING: line length of 121 exceeds 100 columns
#21852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6567:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#21853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6568:
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#21854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6569:
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#21855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6570:
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6571:
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#21857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6572:
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6573:
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6574:
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#21860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6575:
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6576:
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#21862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6577:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#21863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6578:
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT                                                       0x3

WARNING: line length of 113 exceeds 100 columns
#21864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6579:
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#21865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6580:
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#21866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6581:
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#21867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6582:
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#21868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6583:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#21869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6584:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9

WARNING: line length of 113 exceeds 100 columns
#21870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6585:
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc

WARNING: line length of 113 exceeds 100 columns
#21871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6586:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe

WARNING: line length of 114 exceeds 100 columns
#21872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6587:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#21873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6588:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#21874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6589:
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6590:
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6591:
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6592:
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6593:
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6594:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6595:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6596:
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00003000L

WARNING: line length of 121 exceeds 100 columns
#21882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6597:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#21883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6598:
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#21884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6599:
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#21885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6600:
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6601:
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#21887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6602:
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6603:
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6604:
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#21890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6605:
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6606:
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#21892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6607:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#21893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6608:
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT                                                       0x3

WARNING: line length of 113 exceeds 100 columns
#21894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6609:
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#21895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6610:
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#21896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6611:
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#21897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6612:
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#21898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6613:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#21899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6614:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9

WARNING: line length of 113 exceeds 100 columns
#21900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6615:
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc

WARNING: line length of 113 exceeds 100 columns
#21901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6616:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe

WARNING: line length of 114 exceeds 100 columns
#21902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6617:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#21903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6618:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#21904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6619:
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6620:
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6621:
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6622:
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6623:
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6624:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6625:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6626:
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00003000L

WARNING: line length of 121 exceeds 100 columns
#21912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6627:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#21913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6628:
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#21914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6629:
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#21915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6630:
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6631:
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#21917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6632:
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6633:
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6634:
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#21920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6635:
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6636:
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#21922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6637:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#21923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6638:
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT                                                       0x3

WARNING: line length of 113 exceeds 100 columns
#21924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6639:
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#21925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6640:
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#21926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6641:
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#21927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6642:
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#21928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6643:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#21929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6644:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9

WARNING: line length of 113 exceeds 100 columns
#21930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6645:
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc

WARNING: line length of 113 exceeds 100 columns
#21931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6646:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe

WARNING: line length of 114 exceeds 100 columns
#21932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6647:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#21933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6648:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#21934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6649:
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#21935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6650:
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#21936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6651:
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#21937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6652:
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#21938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6653:
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#21939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6654:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#21940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6655:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#21941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6656:
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00003000L

WARNING: line length of 121 exceeds 100 columns
#21942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6657:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#21943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6658:
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#21944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6659:
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#21945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6660:
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6661:
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#21947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6662:
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#21948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6663:
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6664:
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#21950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6665:
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#21951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6666:
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#21952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6667:
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#21953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6668:
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#21954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6669:
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#21955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6670:
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#21956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6671:
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6672:
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6673:
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6674:
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6675:
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6676:
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6677:
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6678:
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6679:
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6680:
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6681:
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6682:
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6683:
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#21969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6684:
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#21970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6685:
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#21971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6686:
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#21972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6687:
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#21973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6688:
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#21974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6689:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6690:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL__SHIFT                                                          0x5

WARNING: line length of 121 exceeds 100 columns
#21976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6691:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6692:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL_MASK                                                            0x000000E0L

WARNING: line length of 113 exceeds 100 columns
#21978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6693:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6694:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL__SHIFT                                                          0x5

WARNING: line length of 121 exceeds 100 columns
#21980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6695:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6696:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL_MASK                                                            0x000000E0L

WARNING: line length of 113 exceeds 100 columns
#21982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6697:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6698:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL__SHIFT                                                          0x5

WARNING: line length of 121 exceeds 100 columns
#21984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6699:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6700:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL_MASK                                                            0x000000E0L

WARNING: line length of 113 exceeds 100 columns
#21986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6701:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6702:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL__SHIFT                                                          0x5

WARNING: line length of 121 exceeds 100 columns
#21988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6703:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6704:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL_MASK                                                            0x000000E0L

WARNING: line length of 113 exceeds 100 columns
#21990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6705:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#21991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6706:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL__SHIFT                                                          0x5

WARNING: line length of 121 exceeds 100 columns
#21992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6707:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#21993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6708:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL_MASK                                                            0x000000E0L

WARNING: line length of 113 exceeds 100 columns
#21994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6709:
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#21995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6710:
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2

WARNING: line length of 113 exceeds 100 columns
#21996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6711:
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3

WARNING: line length of 113 exceeds 100 columns
#21997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6712:
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#21998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6713:
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#21999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6714:
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#22000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6715:
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd

WARNING: line length of 113 exceeds 100 columns
#22001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6716:
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe

WARNING: line length of 113 exceeds 100 columns
#22002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6717:
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf

WARNING: line length of 114 exceeds 100 columns
#22003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6718:
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#22004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6719:
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11

WARNING: line length of 114 exceeds 100 columns
#22005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6720:
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12

WARNING: line length of 114 exceeds 100 columns
#22006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6721:
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13

WARNING: line length of 114 exceeds 100 columns
#22007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6722:
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#22008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6723:
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15

WARNING: line length of 121 exceeds 100 columns
#22009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6724:
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6725:
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6726:
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6727:
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6728:
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6729:
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#22015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6730:
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#22016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6731:
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#22017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6732:
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#22018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6733:
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#22019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6734:
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#22020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6735:
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L

WARNING: line length of 121 exceeds 100 columns
#22021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6736:
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L

WARNING: line length of 121 exceeds 100 columns
#22022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6737:
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#22023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6738:
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L

WARNING: line length of 113 exceeds 100 columns
#22024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6739:
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#22025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6740:
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9

WARNING: line length of 113 exceeds 100 columns
#22026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6741:
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#22027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6742:
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb

WARNING: line length of 113 exceeds 100 columns
#22028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6743:
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#22029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6744:
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd

WARNING: line length of 121 exceeds 100 columns
#22030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6745:
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6746:
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6747:
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6748:
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#22034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6749:
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#22035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6750:
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L

WARNING: line length of 113 exceeds 100 columns
#22036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6751:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#22037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6752:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4

WARNING: line length of 114 exceeds 100 columns
#22038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6753:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#22039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6754:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#22040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6755:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#22041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6756:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT                                    0x1d

WARNING: line length of 121 exceeds 100 columns
#22042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6757:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#22043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6758:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000070L

WARNING: line length of 121 exceeds 100 columns
#22044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6759:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#22045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6760:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#22046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6761:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#22047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6762:
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK                                      0x20000000L

WARNING: line length of 113 exceeds 100 columns
#22048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6763:
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6764:
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6765:
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#22051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6766:
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6767:
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6768:
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6769:
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#22055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6770:
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6771:
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6772:
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6773:
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6774:
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6775:
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6776:
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6777:
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6778:
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6779:
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6780:
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6781:
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6782:
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6783:
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1

WARNING: line length of 113 exceeds 100 columns
#22069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6784:
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5

WARNING: line length of 113 exceeds 100 columns
#22070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6785:
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9

WARNING: line length of 113 exceeds 100 columns
#22071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6786:
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd

WARNING: line length of 114 exceeds 100 columns
#22072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6787:
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11

WARNING: line length of 114 exceeds 100 columns
#22073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6788:
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15

WARNING: line length of 121 exceeds 100 columns
#22074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6789:
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6790:
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6791:
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6792:
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#22078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6793:
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#22079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6794:
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L

WARNING: line length of 113 exceeds 100 columns
#22080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6795:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#22081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6796:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#22082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6797:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#22083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6798:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#22084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6799:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#22085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6800:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#22086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6801:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11

WARNING: line length of 114 exceeds 100 columns
#22087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6802:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12

WARNING: line length of 114 exceeds 100 columns
#22088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6803:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13

WARNING: line length of 114 exceeds 100 columns
#22089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6804:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#22090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6805:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15

WARNING: line length of 114 exceeds 100 columns
#22091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6806:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18

WARNING: line length of 114 exceeds 100 columns
#22092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6807:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#22093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6808:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#22094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6809:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b

WARNING: line length of 114 exceeds 100 columns
#22095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6810:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#22096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6811:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#22097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6812:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6813:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6814:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6815:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#22101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6816:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#22102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6817:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#22103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6818:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L

WARNING: line length of 121 exceeds 100 columns
#22104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6819:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#22105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6820:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#22106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6821:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#22107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6822:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L

WARNING: line length of 121 exceeds 100 columns
#22108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6823:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#22109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6824:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#22110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6825:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L

WARNING: line length of 121 exceeds 100 columns
#22111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6826:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L

WARNING: line length of 121 exceeds 100 columns
#22112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6827:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#22113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6828:
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L

WARNING: line length of 113 exceeds 100 columns
#22114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6829:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#22115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6830:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#22116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6831:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#22117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6832:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1

WARNING: line length of 113 exceeds 100 columns
#22118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6833:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#22119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6834:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2

WARNING: line length of 113 exceeds 100 columns
#22120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6835:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#22121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6836:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3

WARNING: line length of 113 exceeds 100 columns
#22122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6837:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#22123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6838:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#22124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6839:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#22125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6840:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5

WARNING: line length of 113 exceeds 100 columns
#22126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6841:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#22127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6842:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#22128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6843:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa

WARNING: line length of 113 exceeds 100 columns
#22129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6844:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb

WARNING: line length of 113 exceeds 100 columns
#22130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6845:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc

WARNING: line length of 113 exceeds 100 columns
#22131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6846:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd

WARNING: line length of 121 exceeds 100 columns
#22132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6847:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6848:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6849:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6850:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6851:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6852:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6853:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6854:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6855:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6856:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6857:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6858:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6859:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6860:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6861:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6862:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#22148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6863:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L

WARNING: line length of 121 exceeds 100 columns
#22149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6864:
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L

WARNING: line length of 113 exceeds 100 columns
#22150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6865:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#22151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6866:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#22152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6867:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2

WARNING: line length of 113 exceeds 100 columns
#22153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6868:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#22154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6869:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#22155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6870:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5

WARNING: line length of 113 exceeds 100 columns
#22156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6871:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6

WARNING: line length of 121 exceeds 100 columns
#22157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6872:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6873:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6874:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6875:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6876:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6877:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6878:
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L

WARNING: line length of 113 exceeds 100 columns
#22164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6879:
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#22165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6880:
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6881:
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#22167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6882:
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6883:
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#22169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6884:
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6885:
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#22171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6886:
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6887:
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#22173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6888:
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6889:
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#22175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6890:
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6891:
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#22177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6892:
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6893:
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#22179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6894:
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6895:
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#22181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6896:
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4

WARNING: line length of 121 exceeds 100 columns
#22182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6897:
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6898:
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L

WARNING: line length of 113 exceeds 100 columns
#22184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6899:
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#22185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6900:
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT                                                          0x3

WARNING: line length of 121 exceeds 100 columns
#22186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6901:
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#22187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6902:
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK                                                            0x00000008L

WARNING: line length of 113 exceeds 100 columns
#22188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6903:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#22189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6904:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#22190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6905:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#22191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6906:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3

WARNING: line length of 113 exceeds 100 columns
#22192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6907:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#22193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6908:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#22194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6909:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#22195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6910:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#22196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6911:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa

WARNING: line length of 113 exceeds 100 columns
#22197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6912:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb

WARNING: line length of 113 exceeds 100 columns
#22198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6913:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc

WARNING: line length of 113 exceeds 100 columns
#22199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6914:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd

WARNING: line length of 113 exceeds 100 columns
#22200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6915:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe

WARNING: line length of 113 exceeds 100 columns
#22201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6916:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf

WARNING: line length of 114 exceeds 100 columns
#22202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6917:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#22203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6918:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15

WARNING: line length of 114 exceeds 100 columns
#22204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6919:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16

WARNING: line length of 114 exceeds 100 columns
#22205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6920:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17

WARNING: line length of 121 exceeds 100 columns
#22206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6921:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6922:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6923:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6924:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6925:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6926:
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6927:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6928:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6929:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6930:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#22216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6931:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L

WARNING: line length of 121 exceeds 100 columns
#22217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6932:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#22218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6933:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#22219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6934:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#22220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6935:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#22221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6936:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L

WARNING: line length of 121 exceeds 100 columns
#22222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6937:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L

WARNING: line length of 121 exceeds 100 columns
#22223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6938:
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L

WARNING: line length of 113 exceeds 100 columns
#22224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6939:
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#22225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6940:
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#22226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6941:
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#22227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6942:
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#22228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6943:
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#22229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6944:
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L

WARNING: line length of 113 exceeds 100 columns
#22230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6945:
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#22231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6946:
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6947:
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#22233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6948:
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6949:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#22235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6950:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#22236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6951:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT                                                        0x2

WARNING: line length of 113 exceeds 100 columns
#22237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6952:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT                                                        0x3

WARNING: line length of 121 exceeds 100 columns
#22238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6953:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6954:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK                                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6955:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK                                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6956:
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK                                                          0x00000008L

WARNING: line length of 113 exceeds 100 columns
#22242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6957:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#22243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6958:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#22244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6959:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#22245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6960:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11

WARNING: line length of 114 exceeds 100 columns
#22246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6961:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12

WARNING: line length of 114 exceeds 100 columns
#22247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6962:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#22248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6963:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#22249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6964:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#22250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6965:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#22251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6966:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#22252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6967:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#22253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6968:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#22254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6969:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L

WARNING: line length of 121 exceeds 100 columns
#22255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6970:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L

WARNING: line length of 121 exceeds 100 columns
#22256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6971:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#22257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6972:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#22258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6973:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#22259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6974:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#22260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6975:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#22261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6976:
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L

WARNING: line length of 121 exceeds 100 columns
#22262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6977:
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0

WARNING: line length of 127 exceeds 100 columns
#22263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6978:
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6979:
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#22265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6980:
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL

WARNING: line length of 125 exceeds 100 columns
#22266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6981:
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0

WARNING: line length of 131 exceeds 100 columns
#22267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6982:
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6983:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#22269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6984:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#22270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6985:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#22271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6986:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa

WARNING: line length of 121 exceeds 100 columns
#22272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6987:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6988:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#22274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6989:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6990:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L

WARNING: line length of 113 exceeds 100 columns
#22276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6991:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#22277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6992:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8

WARNING: line length of 114 exceeds 100 columns
#22278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6993:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#22279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6994:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18

WARNING: line length of 121 exceeds 100 columns
#22280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6995:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#22281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6996:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#22282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6997:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#22283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6998:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#22284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:6999:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#22285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7000:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7001:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#22287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7002:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7003:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#22289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7004:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7005:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#22291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7006:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7007:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#22293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7008:
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L

WARNING: line length of 133 exceeds 100 columns
#22294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7009:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0

WARNING: line length of 139 exceeds 100 columns
#22295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7010:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7011:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0

WARNING: line length of 121 exceeds 100 columns
#22297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7012:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7013:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#22299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7014:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#22300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7015:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#22301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7016:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L

WARNING: line length of 117 exceeds 100 columns
#22302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7017:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0

WARNING: line length of 123 exceeds 100 columns
#22303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7018:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7019:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#22305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7020:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e

WARNING: line length of 114 exceeds 100 columns
#22306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7021:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#22307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7022:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#22308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7023:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L

WARNING: line length of 121 exceeds 100 columns
#22309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7024:
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#22310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7025:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7026:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#22312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7027:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8

WARNING: line length of 113 exceeds 100 columns
#22313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7028:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb

WARNING: line length of 113 exceeds 100 columns
#22314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7029:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe

WARNING: line length of 113 exceeds 100 columns
#22315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7030:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf

WARNING: line length of 113 exceeds 100 columns
#22316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7031:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf

WARNING: line length of 121 exceeds 100 columns
#22317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7032:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7033:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L

WARNING: line length of 121 exceeds 100 columns
#22319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7034:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L

WARNING: line length of 121 exceeds 100 columns
#22320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7035:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L

WARNING: line length of 121 exceeds 100 columns
#22321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7036:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#22322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7037:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#22323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7038:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L

WARNING: line length of 113 exceeds 100 columns
#22324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7039:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#22325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7040:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4

WARNING: line length of 121 exceeds 100 columns
#22326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7041:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7042:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7043:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#22329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7044:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#22330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7045:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#22331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7046:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#22332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7047:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#22333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7048:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#22334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7049:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#22335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7050:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#22336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7051:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8

WARNING: line length of 114 exceeds 100 columns
#22337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7052:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17

WARNING: line length of 121 exceeds 100 columns
#22338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7053:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7054:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7055:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7056:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7057:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7058:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7059:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7060:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7061:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#22347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7062:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L

WARNING: line length of 113 exceeds 100 columns
#22348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7063:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#22349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7064:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL

WARNING: line length of 113 exceeds 100 columns
#22350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7065:
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#22351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7066:
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14

WARNING: line length of 121 exceeds 100 columns
#22352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7067:
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#22353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7068:
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L

WARNING: line length of 113 exceeds 100 columns
#22354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7069:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7

WARNING: line length of 121 exceeds 100 columns
#22355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7070:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L

WARNING: line length of 113 exceeds 100 columns
#22356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7071:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#22357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7072:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7073:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#22359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7074:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1

WARNING: line length of 113 exceeds 100 columns
#22360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7075:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4

WARNING: line length of 121 exceeds 100 columns
#22361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7076:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7077:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7078:
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L

WARNING: line length of 113 exceeds 100 columns
#22364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7079:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#22365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7080:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#22366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7081:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2

WARNING: line length of 113 exceeds 100 columns
#22367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7082:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3

WARNING: line length of 113 exceeds 100 columns
#22368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7083:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4

WARNING: line length of 113 exceeds 100 columns
#22369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7084:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5

WARNING: line length of 113 exceeds 100 columns
#22370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7085:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6

WARNING: line length of 114 exceeds 100 columns
#22371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7086:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#22372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7087:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#22373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7088:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9

WARNING: line length of 113 exceeds 100 columns
#22374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7089:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa

WARNING: line length of 113 exceeds 100 columns
#22375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7090:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb

WARNING: line length of 115 exceeds 100 columns
#22376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7091:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#22377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7092:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14

WARNING: line length of 121 exceeds 100 columns
#22378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7093:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7094:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7095:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7096:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7097:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7098:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7099:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7100:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7101:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7102:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7103:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7104:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#22390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7105:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#22391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7106:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#22392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7107:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0

WARNING: line length of 114 exceeds 100 columns
#22393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7108:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10

WARNING: line length of 121 exceeds 100 columns
#22394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7109:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#22395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7110:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#22396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7111:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#22397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7112:
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7113:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#22399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7114:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7115:
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6

WARNING: line length of 121 exceeds 100 columns
#22401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7116:
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L

WARNING: line length of 113 exceeds 100 columns
#22402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7117:
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#22403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7118:
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7

WARNING: line length of 121 exceeds 100 columns
#22404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7119:
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#22405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7120:
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L

WARNING: line length of 113 exceeds 100 columns
#22406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7121:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#22407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7122:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f

WARNING: line length of 121 exceeds 100 columns
#22408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7123:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#22409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7124:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#22410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7125:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#22411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7126:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4

WARNING: line length of 113 exceeds 100 columns
#22412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7127:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#22413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7128:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#22414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7129:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#22415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7130:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#22416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7131:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18

WARNING: line length of 114 exceeds 100 columns
#22417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7132:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e

WARNING: line length of 121 exceeds 100 columns
#22418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7133:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7134:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#22420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7135:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#22421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7136:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#22422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7137:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#22423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7138:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#22424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7139:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#22425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7140:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#22426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7141:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#22427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7142:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4

WARNING: line length of 121 exceeds 100 columns
#22428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7143:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7144:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7145:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#22431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7146:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#22432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7147:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7148:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7149:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7150:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6

WARNING: line length of 121 exceeds 100 columns
#22436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7151:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#22437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7152:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#22438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7153:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#22439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7154:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#22440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7155:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9

WARNING: line length of 113 exceeds 100 columns
#22441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7156:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa

WARNING: line length of 121 exceeds 100 columns
#22442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7157:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#22443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7158:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7159:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7160:
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L

WARNING: line length of 113 exceeds 100 columns
#22446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7161:
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#22447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7162:
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7163:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#22449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7164:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3

WARNING: line length of 113 exceeds 100 columns
#22450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7165:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7

WARNING: line length of 121 exceeds 100 columns
#22451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7166:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#22452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7167:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L

WARNING: line length of 121 exceeds 100 columns
#22453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7168:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L

WARNING: line length of 113 exceeds 100 columns
#22454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7169:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#22455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7170:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#22456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7171:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8

WARNING: line length of 114 exceeds 100 columns
#22457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7172:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#22458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7173:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18

WARNING: line length of 121 exceeds 100 columns
#22459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7174:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#22460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7175:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L

WARNING: line length of 121 exceeds 100 columns
#22461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7176:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#22462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7177:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#22463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7178:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#22464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7179:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#22465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7180:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7181:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7182:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1

WARNING: line length of 113 exceeds 100 columns
#22468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7183:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#22469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7184:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7185:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7186:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7187:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7188:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1

WARNING: line length of 113 exceeds 100 columns
#22474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7189:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#22475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7190:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7191:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7192:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7193:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7194:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1

WARNING: line length of 113 exceeds 100 columns
#22480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7195:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#22481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7196:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7197:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7198:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7199:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7200:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1

WARNING: line length of 113 exceeds 100 columns
#22486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7201:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4

WARNING: line length of 121 exceeds 100 columns
#22487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7202:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7203:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7204:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7205:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#22491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7206:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#22492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7207:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#22493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7208:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#22494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7209:
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#22495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7210:
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#22496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7211:
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7212:
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#22498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7213:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#22499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7214:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7215:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#22501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7216:
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7217:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7218:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#22504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7219:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#22505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7220:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7221:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7222:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7223:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7224:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#22510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7225:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#22511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7226:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7227:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7228:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7229:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7230:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#22516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7231:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#22517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7232:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7233:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7234:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7235:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7236:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#22522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7237:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#22523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7238:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7239:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7240:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7241:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#22527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7242:
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#22528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7243:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#22529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7244:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2

WARNING: line length of 121 exceeds 100 columns
#22530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7245:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#22531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7246:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL

WARNING: line length of 113 exceeds 100 columns
#22532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7247:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7248:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2

WARNING: line length of 113 exceeds 100 columns
#22534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7249:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3

WARNING: line length of 113 exceeds 100 columns
#22535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7250:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7

WARNING: line length of 121 exceeds 100 columns
#22536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7251:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#22537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7252:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7253:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L

WARNING: line length of 121 exceeds 100 columns
#22539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7254:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L

WARNING: line length of 113 exceeds 100 columns
#22540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7255:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#22541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7256:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6

WARNING: line length of 121 exceeds 100 columns
#22542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7257:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#22543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7258:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L

WARNING: line length of 113 exceeds 100 columns
#22544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7259:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#22545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7260:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4

WARNING: line length of 121 exceeds 100 columns
#22546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7261:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7262:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L

WARNING: line length of 113 exceeds 100 columns
#22548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7263:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0

WARNING: line length of 113 exceeds 100 columns
#22549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7264:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4

WARNING: line length of 113 exceeds 100 columns
#22550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7265:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#22551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7266:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7

WARNING: line length of 121 exceeds 100 columns
#22552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7267:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7268:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7269:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#22555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7270:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#22556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7271:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7272:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4

WARNING: line length of 121 exceeds 100 columns
#22558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7273:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7274:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7275:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7276:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4

WARNING: line length of 121 exceeds 100 columns
#22562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7277:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7278:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7279:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7280:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4

WARNING: line length of 121 exceeds 100 columns
#22566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7281:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7282:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7283:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7284:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4

WARNING: line length of 121 exceeds 100 columns
#22570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7285:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7286:
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7287:
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#22573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7288:
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7289:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#22575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7290:
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#22576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7291:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#22577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7292:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8

WARNING: line length of 121 exceeds 100 columns
#22578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7293:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7294:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#22580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7295:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#22581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7296:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7297:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#22583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7298:
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7299:
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#22585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7300:
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7301:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#22587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7302:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1

WARNING: line length of 113 exceeds 100 columns
#22588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7303:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8

WARNING: line length of 114 exceeds 100 columns
#22589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7304:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10

WARNING: line length of 121 exceeds 100 columns
#22590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7305:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7306:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7307:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#22593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7308:
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#22594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7309:
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#22595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7310:
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L

WARNING: line length of 113 exceeds 100 columns
#22596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7311:
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7312:
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#22598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7313:
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7314:
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L

WARNING: line length of 113 exceeds 100 columns
#22600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7315:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#22601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7316:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1

WARNING: line length of 113 exceeds 100 columns
#22602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7317:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2

WARNING: line length of 113 exceeds 100 columns
#22603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7318:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3

WARNING: line length of 113 exceeds 100 columns
#22604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7319:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#22605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7320:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6

WARNING: line length of 113 exceeds 100 columns
#22606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7321:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7

WARNING: line length of 113 exceeds 100 columns
#22607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7322:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#22608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7323:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9

WARNING: line length of 113 exceeds 100 columns
#22609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7324:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa

WARNING: line length of 113 exceeds 100 columns
#22610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7325:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb

WARNING: line length of 114 exceeds 100 columns
#22611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7326:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10

WARNING: line length of 114 exceeds 100 columns
#22612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7327:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14

WARNING: line length of 121 exceeds 100 columns
#22613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7328:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7329:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7330:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7331:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7332:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7333:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7334:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7335:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7336:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7337:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7338:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L

WARNING: line length of 121 exceeds 100 columns
#22624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7339:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#22625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7340:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#22626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7341:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#22627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7342:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#22628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7343:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2

WARNING: line length of 113 exceeds 100 columns
#22629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7344:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3

WARNING: line length of 113 exceeds 100 columns
#22630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7345:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#22631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7346:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#22632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7347:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#22633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7348:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#22634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7349:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8

WARNING: line length of 114 exceeds 100 columns
#22635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7350:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#22636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7351:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#22637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7352:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7353:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7354:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7355:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7356:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7357:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7358:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7359:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7360:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#22646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7361:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#22647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7362:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L

WARNING: line length of 113 exceeds 100 columns
#22648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7363:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#22649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7364:
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7365:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7366:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4

WARNING: line length of 113 exceeds 100 columns
#22652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7367:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8

WARNING: line length of 113 exceeds 100 columns
#22653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7368:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb

WARNING: line length of 113 exceeds 100 columns
#22654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7369:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe

WARNING: line length of 113 exceeds 100 columns
#22655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7370:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf

WARNING: line length of 121 exceeds 100 columns
#22656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7371:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7372:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L

WARNING: line length of 121 exceeds 100 columns
#22658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7373:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L

WARNING: line length of 121 exceeds 100 columns
#22659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7374:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L

WARNING: line length of 121 exceeds 100 columns
#22660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7375:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#22661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7376:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L

WARNING: line length of 113 exceeds 100 columns
#22662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7377:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#22663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7378:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4

WARNING: line length of 121 exceeds 100 columns
#22664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7379:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7380:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7381:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#22667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7382:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#22668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7383:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#22669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7384:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3

WARNING: line length of 113 exceeds 100 columns
#22670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7385:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#22671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7386:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5

WARNING: line length of 113 exceeds 100 columns
#22672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7387:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6

WARNING: line length of 113 exceeds 100 columns
#22673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7388:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#22674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7389:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8

WARNING: line length of 114 exceeds 100 columns
#22675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7390:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17

WARNING: line length of 121 exceeds 100 columns
#22676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7391:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7392:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7393:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7394:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7395:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7396:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7397:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7398:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7399:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#22685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7400:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L

WARNING: line length of 115 exceeds 100 columns
#22686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7401:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#22687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7402:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1

WARNING: line length of 113 exceeds 100 columns
#22688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7403:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2

WARNING: line length of 117 exceeds 100 columns
#22689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7404:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3

WARNING: line length of 113 exceeds 100 columns
#22690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7405:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4

WARNING: line length of 113 exceeds 100 columns
#22691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7406:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5

WARNING: line length of 113 exceeds 100 columns
#22692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7407:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6

WARNING: line length of 120 exceeds 100 columns
#22693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7408:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#22694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7409:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8

WARNING: line length of 113 exceeds 100 columns
#22695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7410:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9

WARNING: line length of 113 exceeds 100 columns
#22696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7411:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa

WARNING: line length of 113 exceeds 100 columns
#22697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7412:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb

WARNING: line length of 121 exceeds 100 columns
#22698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7413:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#22699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7414:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#22700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7415:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7416:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7417:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L

WARNING: line length of 123 exceeds 100 columns
#22703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7418:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7419:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7420:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7421:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L

WARNING: line length of 126 exceeds 100 columns
#22707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7422:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7423:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7424:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7425:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7426:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L

WARNING: line length of 126 exceeds 100 columns
#22712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7427:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#22713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7428:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#22714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7429:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0

WARNING: line length of 114 exceeds 100 columns
#22715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7430:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10

WARNING: line length of 121 exceeds 100 columns
#22716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7431:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#22717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7432:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#22718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7433:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#22719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7434:
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7435:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5

WARNING: line length of 121 exceeds 100 columns
#22721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7436:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L

WARNING: line length of 113 exceeds 100 columns
#22722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7437:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#22723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7438:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7

WARNING: line length of 121 exceeds 100 columns
#22724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7439:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#22725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7440:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L

WARNING: line length of 113 exceeds 100 columns
#22726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7441:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0

WARNING: line length of 114 exceeds 100 columns
#22727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7442:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f

WARNING: line length of 121 exceeds 100 columns
#22728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7443:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#22729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7444:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#22730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7445:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#22731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7446:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4

WARNING: line length of 113 exceeds 100 columns
#22732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7447:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8

WARNING: line length of 113 exceeds 100 columns
#22733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7448:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc

WARNING: line length of 114 exceeds 100 columns
#22734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7449:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10

WARNING: line length of 114 exceeds 100 columns
#22735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7450:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14

WARNING: line length of 114 exceeds 100 columns
#22736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7451:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18

WARNING: line length of 114 exceeds 100 columns
#22737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7452:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e

WARNING: line length of 121 exceeds 100 columns
#22738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7453:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7454:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#22740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7455:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#22741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7456:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#22742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7457:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#22743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7458:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#22744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7459:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#22745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7460:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#22746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7461:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#22747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7462:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4

WARNING: line length of 121 exceeds 100 columns
#22748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7463:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7464:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7465:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0

WARNING: line length of 113 exceeds 100 columns
#22751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7466:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4

WARNING: line length of 121 exceeds 100 columns
#22752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7467:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#22753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7468:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7469:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7470:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6

WARNING: line length of 121 exceeds 100 columns
#22756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7471:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#22757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7472:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#22758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7473:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#22759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7474:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#22760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7475:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7476:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7477:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7478:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7479:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7480:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7481:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7482:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7483:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7484:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7485:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7486:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7487:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7488:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7489:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7490:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7491:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7492:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7493:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7494:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7495:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7496:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7497:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7498:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7499:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#22785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7500:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#22786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7501:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7502:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#22788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7503:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7504:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7505:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7506:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7507:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7508:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7509:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7510:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7511:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7512:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7513:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7514:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7515:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7516:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7517:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7518:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7519:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7520:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7521:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0

WARNING: line length of 113 exceeds 100 columns
#22807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7522:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#22808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7523:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#22809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7524:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7525:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7526:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#22812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7527:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#22813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7528:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8

WARNING: line length of 121 exceeds 100 columns
#22814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7529:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7530:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#22816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7531:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#22817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7532:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7533:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#22819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7534:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7535:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#22821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7536:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1

WARNING: line length of 113 exceeds 100 columns
#22822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7537:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4

WARNING: line length of 114 exceeds 100 columns
#22823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7538:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5

WARNING: line length of 121 exceeds 100 columns
#22824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7539:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7540:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L

WARNING: line length of 121 exceeds 100 columns
#22826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7541:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7542:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L

WARNING: line length of 113 exceeds 100 columns
#22828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7543:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#22829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7544:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8

WARNING: line length of 114 exceeds 100 columns
#22830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7545:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#22831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7546:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#22832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7547:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#22833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7548:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#22834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7549:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#22835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7550:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#22836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7551:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#22837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7552:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7553:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#22839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7554:
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#22840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7555:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#22841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7556:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1

WARNING: line length of 113 exceeds 100 columns
#22842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7557:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2

WARNING: line length of 113 exceeds 100 columns
#22843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7558:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3

WARNING: line length of 113 exceeds 100 columns
#22844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7559:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5

WARNING: line length of 113 exceeds 100 columns
#22845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7560:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6

WARNING: line length of 114 exceeds 100 columns
#22846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7561:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7

WARNING: line length of 113 exceeds 100 columns
#22847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7562:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#22848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7563:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9

WARNING: line length of 113 exceeds 100 columns
#22849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7564:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa

WARNING: line length of 113 exceeds 100 columns
#22850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7565:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb

WARNING: line length of 115 exceeds 100 columns
#22851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7566:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#22852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7567:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14

WARNING: line length of 121 exceeds 100 columns
#22853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7568:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7569:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7570:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7571:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7572:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7573:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7574:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7575:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7576:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7577:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7578:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#22864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7579:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#22865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7580:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#22866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7581:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#22867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7582:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1

WARNING: line length of 113 exceeds 100 columns
#22868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7583:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2

WARNING: line length of 113 exceeds 100 columns
#22869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7584:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3

WARNING: line length of 113 exceeds 100 columns
#22870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7585:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#22871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7586:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#22872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7587:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6

WARNING: line length of 113 exceeds 100 columns
#22873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7588:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#22874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7589:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#22875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7590:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#22876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7591:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#22877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7592:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7593:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7594:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7595:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7596:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7597:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7598:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7599:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7600:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#22886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7601:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#22887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7602:
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#22888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7603:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#22889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7604:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#22890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7605:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#22891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7606:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#22892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7607:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#22893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7608:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#22894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7609:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#22895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7610:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#22896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7611:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#22897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7612:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#22898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7613:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#22899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7614:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#22900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7615:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#22901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7616:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#22902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7617:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#22903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7618:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#22904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7619:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#22905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7620:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#22906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7621:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#22907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7622:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#22908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7623:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#22909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7624:
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#22910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7625:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#22911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7626:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#22912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7627:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#22913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7628:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#22914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7629:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#22915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7630:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#22916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7631:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7632:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7633:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#22919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7634:
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#22920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7635:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#22921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7636:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#22922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7637:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#22923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7638:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#22924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7639:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#22925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7640:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#22926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7641:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#22927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7642:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#22928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7643:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#22929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7644:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#22930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7645:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#22931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7646:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#22932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7647:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#22933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7648:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#22934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7649:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#22935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7650:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#22936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7651:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#22937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7652:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7653:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#22939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7654:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7655:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#22941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7656:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#22942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7657:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#22943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7658:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#22944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7659:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#22945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7660:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#22946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7661:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#22947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7662:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#22948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7663:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#22949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7664:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#22950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7665:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#22951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7666:
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#22952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7667:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#22953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7668:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#22954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7669:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#22955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7670:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#22956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7671:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#22957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7672:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#22958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7673:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#22959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7674:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#22960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7675:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#22961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7676:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#22962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7677:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#22963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7678:
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#22964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7679:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#22965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7680:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#22966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7681:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#22967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7682:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#22968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7683:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7684:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7685:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#22971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7686:
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#22972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7687:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#22973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7688:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#22974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7689:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#22975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7690:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#22976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7691:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#22977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7692:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#22978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7693:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#22979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7694:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#22980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7695:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#22981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7696:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#22982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7697:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#22983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7698:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#22984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7699:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#22985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7700:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#22986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7701:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#22987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7702:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#22988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7703:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#22989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7704:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#22990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7705:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#22991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7706:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#22992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7707:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#22993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7708:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#22994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7709:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#22995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7710:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#22996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7711:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#22997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7712:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#22998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7713:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#22999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7714:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7715:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#23001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7716:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7717:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7718:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7719:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7720:
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#23006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7721:
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#23007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7722:
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#23008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7723:
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#23009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7724:
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#23010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7725:
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#23011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7726:
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#23012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7727:
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#23013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7728:
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#23014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7729:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#23015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7730:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#23016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7731:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#23017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7732:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#23018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7733:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#23019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7734:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#23020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7735:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#23021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7736:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#23022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7737:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#23023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7738:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#23024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7739:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#23025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7740:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#23026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7741:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#23027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7742:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#23028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7743:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7744:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7745:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7746:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#23032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7747:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#23033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7748:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#23034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7749:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7750:
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#23036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7751:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#23037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7752:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#23038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7753:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#23039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7754:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#23040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7755:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#23041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7756:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#23042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7757:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7758:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7759:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#23045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7760:
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#23046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7761:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#23047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7762:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#23048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7763:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#23049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7764:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#23050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7765:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#23051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7766:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#23052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7767:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#23053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7768:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#23054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7769:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#23055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7770:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#23056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7771:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#23057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7772:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#23058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7773:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#23059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7774:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#23060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7775:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#23061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7776:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#23062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7777:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#23063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7778:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7779:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#23065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7780:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7781:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#23067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7782:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7783:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#23069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7784:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7785:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#23071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7786:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7787:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#23073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7788:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7789:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#23075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7790:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7791:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#23077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7792:
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#23078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7793:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#23079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7794:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#23080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7795:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#23081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7796:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#23082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7797:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#23083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7798:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7799:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#23085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7800:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#23086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7801:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7802:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7803:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7804:
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7805:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#23091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7806:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#23092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7807:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#23093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7808:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#23094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7809:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7810:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7811:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#23097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7812:
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#23098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7813:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#23099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7814:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#23100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7815:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#23101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7816:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#23102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7817:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#23103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7818:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#23104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7819:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#23105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7820:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#23106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7821:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#23107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7822:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#23108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7823:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#23109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7824:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#23110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7825:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#23111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7826:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#23112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7827:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#23113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7828:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#23114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7829:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#23115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7830:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7831:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7832:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7833:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7834:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7835:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7836:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7837:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7838:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7839:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7840:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7841:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#23127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7842:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7843:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7844:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7845:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7846:
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#23132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7847:
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#23133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7848:
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#23134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7849:
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#23135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7850:
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#23136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7851:
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#23137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7852:
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#23138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7853:
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#23139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7854:
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#23140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7855:
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#23141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7856:
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#23142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7857:
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7858:
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7859:
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#23145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7860:
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e

WARNING: line length of 121 exceeds 100 columns
#23146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7861:
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7862:
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7863:
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#23149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7864:
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#23150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7865:
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7866:
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7867:
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#23153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7868:
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e

WARNING: line length of 121 exceeds 100 columns
#23154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7869:
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7870:
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7871:
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#23157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7872:
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#23158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7873:
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7874:
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7875:
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#23161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7876:
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e

WARNING: line length of 121 exceeds 100 columns
#23162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7877:
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7878:
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7879:
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#23165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7880:
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#23166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7881:
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7882:
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7883:
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#23169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7884:
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e

WARNING: line length of 121 exceeds 100 columns
#23170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7885:
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7886:
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7887:
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#23173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7888:
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#23174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7889:
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7890:
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7891:
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#23177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7892:
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#23178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7893:
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7894:
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7895:
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#23181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7896:
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#23182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7897:
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7898:
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7899:
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#23185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7900:
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#23186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7901:
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7902:
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7903:
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#23189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7904:
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#23190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7905:
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7906:
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7907:
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#23193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7908:
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#23194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7909:
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7910:
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7911:
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#23197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7912:
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#23198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7913:
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7914:
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#23200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7915:
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#23201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7916:
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#23202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7917:
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7918:
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#23204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7919:
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#23205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7920:
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#23206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7921:
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#23207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7922:
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3

WARNING: line length of 113 exceeds 100 columns
#23208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7923:
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#23209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7924:
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5

WARNING: line length of 113 exceeds 100 columns
#23210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7925:
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#23211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7926:
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7

WARNING: line length of 121 exceeds 100 columns
#23212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7927:
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7928:
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7929:
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7930:
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7931:
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7932:
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7933:
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7934:
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L

WARNING: line length of 113 exceeds 100 columns
#23220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7935:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#23221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7936:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#23222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7937:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#23223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7938:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#23224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7939:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#23225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7940:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#23226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7941:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6

WARNING: line length of 113 exceeds 100 columns
#23227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7942:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7

WARNING: line length of 121 exceeds 100 columns
#23228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7943:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7944:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7945:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7946:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7947:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7948:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7949:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7950:
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L

WARNING: line length of 113 exceeds 100 columns
#23236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7951:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#23237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7952:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#23238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7953:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#23239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7954:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3

WARNING: line length of 113 exceeds 100 columns
#23240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7955:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#23241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7956:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#23242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7957:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#23243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7958:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#23244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7959:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#23245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7960:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#23246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7961:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#23247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7962:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#23248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7963:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#23249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7964:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd

WARNING: line length of 113 exceeds 100 columns
#23250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7965:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe

WARNING: line length of 113 exceeds 100 columns
#23251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7966:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf

WARNING: line length of 121 exceeds 100 columns
#23252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7967:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7968:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7969:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7970:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7971:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7972:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7973:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7974:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7975:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7976:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7977:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7978:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#23264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7979:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7980:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7981:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7982:
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L

WARNING: line length of 113 exceeds 100 columns
#23268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7983:
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#23269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7984:
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#23270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7985:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#23271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7986:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#23272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7987:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#23273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7988:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#23274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7989:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#23275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7990:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#23276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7991:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#23277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7992:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#23278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7993:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#23279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7994:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#23280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7995:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#23281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7996:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#23282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7997:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#23283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7998:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#23284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:7999:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8000:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8001:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8002:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#23288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8003:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#23289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8004:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#23290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8005:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8006:
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#23292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8007:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#23293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8008:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#23294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8009:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#23295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8010:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#23296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8011:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#23297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8012:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#23298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8013:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8014:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8015:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#23301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8016:
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#23302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8017:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#23303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8018:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#23304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8019:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#23305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8020:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#23306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8021:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#23307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8022:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#23308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8023:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#23309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8024:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#23310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8025:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#23311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8026:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#23312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8027:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#23313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8028:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#23314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8029:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#23315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8030:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#23316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8031:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#23317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8032:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#23318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8033:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#23319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8034:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8035:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#23321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8036:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8037:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#23323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8038:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8039:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#23325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8040:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8041:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#23327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8042:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8043:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#23329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8044:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8045:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#23331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8046:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8047:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#23333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8048:
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#23334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8049:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#23335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8050:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#23336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8051:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#23337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8052:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#23338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8053:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#23339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8054:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8055:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#23341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8056:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#23342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8057:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8058:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8059:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8060:
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8061:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#23347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8062:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#23348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8063:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#23349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8064:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#23350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8065:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8066:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8067:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#23353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8068:
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#23354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8069:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#23355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8070:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#23356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8071:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#23357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8072:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#23358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8073:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#23359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8074:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#23360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8075:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#23361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8076:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#23362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8077:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#23363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8078:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#23364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8079:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#23365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8080:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#23366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8081:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#23367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8082:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#23368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8083:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#23369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8084:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#23370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8085:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#23371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8086:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8087:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8088:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8089:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8090:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8091:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8092:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8093:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8094:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8095:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8096:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8097:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#23383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8098:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8099:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8100:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8101:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8102:
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#23388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8103:
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#23389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8104:
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#23390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8105:
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#23391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8106:
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#23392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8107:
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#23393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8108:
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#23394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8109:
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#23395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8110:
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#23396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8111:
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#23397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8112:
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#23398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8113:
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#23399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8114:
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L

WARNING: line length of 113 exceeds 100 columns
#23400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8115:
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#23401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8116:
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#23402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8117:
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#23403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8118:
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x6

WARNING: line length of 113 exceeds 100 columns
#23404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8119:
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0x7

WARNING: line length of 121 exceeds 100 columns
#23405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8120:
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#23406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8121:
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8122:
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8123:
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8124:
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000080L

WARNING: line length of 113 exceeds 100 columns
#23410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8125:
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#23411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8126:
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4

WARNING: line length of 114 exceeds 100 columns
#23412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8127:
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#23413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8128:
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8129:
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8130:
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#23416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8131:
+#define ZSC_CNTL__FORCE_SOC_ACCESS__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#23417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8132:
+#define ZSC_CNTL__FORCE_SOC_ACCESS_MASK                                                                       0x00000003L

WARNING: line length of 113 exceeds 100 columns
#23418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8133:
+#define ZSC_CNTL2__ALLOW_Z10__SHIFT                                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#23419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8134:
+#define ZSC_CNTL2__ALLOW_Z10_MASK                                                                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#23420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8135:
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#23421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8136:
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#23422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8137:
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8138:
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#23424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8139:
+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#23425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8140:
+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#23426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8141:
+#define ZSC_STATUS__FENCE_REQ_STATUS__SHIFT                                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#23427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8142:
+#define ZSC_STATUS__FENCE_ACK_STATUS__SHIFT                                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#23428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8143:
+#define ZSC_STATUS__FENCE_STATUS__SHIFT                                                                       0xa

WARNING: line length of 121 exceeds 100 columns
#23429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8144:
+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS_MASK                                                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#23430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8145:
+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS_MASK                                                     0x00000070L

WARNING: line length of 121 exceeds 100 columns
#23431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8146:
+#define ZSC_STATUS__FENCE_REQ_STATUS_MASK                                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8147:
+#define ZSC_STATUS__FENCE_ACK_STATUS_MASK                                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8148:
+#define ZSC_STATUS__FENCE_STATUS_MASK                                                                         0x00000C00L

WARNING: line length of 113 exceeds 100 columns
#23434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8149:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#23435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8150:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4

WARNING: line length of 113 exceeds 100 columns
#23436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8151:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8

WARNING: line length of 113 exceeds 100 columns
#23437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8152:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#23438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8153:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10

WARNING: line length of 114 exceeds 100 columns
#23439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8154:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14

WARNING: line length of 121 exceeds 100 columns
#23440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8155:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#23441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8156:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L

WARNING: line length of 121 exceeds 100 columns
#23442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8157:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L

WARNING: line length of 121 exceeds 100 columns
#23443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8158:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#23444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8159:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L

WARNING: line length of 121 exceeds 100 columns
#23445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8160:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L

WARNING: line length of 113 exceeds 100 columns
#23446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8161:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0

WARNING: line length of 113 exceeds 100 columns
#23447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8162:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4

WARNING: line length of 113 exceeds 100 columns
#23448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8163:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8

WARNING: line length of 113 exceeds 100 columns
#23449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8164:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#23450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8165:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10

WARNING: line length of 114 exceeds 100 columns
#23451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8166:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14

WARNING: line length of 121 exceeds 100 columns
#23452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8167:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#23453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8168:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L

WARNING: line length of 121 exceeds 100 columns
#23454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8169:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L

WARNING: line length of 121 exceeds 100 columns
#23455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8170:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#23456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8171:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L

WARNING: line length of 121 exceeds 100 columns
#23457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8172:
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L

WARNING: line length of 113 exceeds 100 columns
#23458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8173:
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#23459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8174:
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#23460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8175:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#23461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8176:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#23462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8177:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb

WARNING: line length of 113 exceeds 100 columns
#23463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8178:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe

WARNING: line length of 114 exceeds 100 columns
#23464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8179:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11

WARNING: line length of 114 exceeds 100 columns
#23465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8180:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#23466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8181:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17

WARNING: line length of 121 exceeds 100 columns
#23467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8182:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#23468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8183:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L

WARNING: line length of 121 exceeds 100 columns
#23469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8184:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L

WARNING: line length of 121 exceeds 100 columns
#23470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8185:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L

WARNING: line length of 121 exceeds 100 columns
#23471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8186:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L

WARNING: line length of 121 exceeds 100 columns
#23472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8187:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L

WARNING: line length of 121 exceeds 100 columns
#23473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8188:
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L

WARNING: line length of 113 exceeds 100 columns
#23474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8189:
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#23475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8190:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#23476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8191:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#23477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8192:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#23478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8193:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7

WARNING: line length of 113 exceeds 100 columns
#23479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8194:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8

WARNING: line length of 113 exceeds 100 columns
#23480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8195:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#23481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8196:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa

WARNING: line length of 113 exceeds 100 columns
#23482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8197:
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf

WARNING: line length of 114 exceeds 100 columns
#23483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8198:
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#23484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8199:
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11

WARNING: line length of 114 exceeds 100 columns
#23485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8200:
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12

WARNING: line length of 114 exceeds 100 columns
#23486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8201:
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13

WARNING: line length of 114 exceeds 100 columns
#23487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8202:
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#23488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8203:
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT                                                      0x15

WARNING: line length of 114 exceeds 100 columns
#23489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8204:
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17

WARNING: line length of 114 exceeds 100 columns
#23490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8205:
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#23491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8206:
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#23492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8207:
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8208:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8209:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8210:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8211:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8212:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8213:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8214:
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8215:
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8216:
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8217:
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8218:
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8219:
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8220:
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8221:
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK                                                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#23507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8222:
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L

WARNING: line length of 121 exceeds 100 columns
#23508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8223:
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#23509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8224:
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8225:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1

WARNING: line length of 113 exceeds 100 columns
#23511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8226:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#23512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8227:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5

WARNING: line length of 113 exceeds 100 columns
#23513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8228:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6

WARNING: line length of 113 exceeds 100 columns
#23514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8229:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7

WARNING: line length of 113 exceeds 100 columns
#23515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8230:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8

WARNING: line length of 113 exceeds 100 columns
#23516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8231:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9

WARNING: line length of 113 exceeds 100 columns
#23517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8232:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa

WARNING: line length of 113 exceeds 100 columns
#23518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8233:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf

WARNING: line length of 114 exceeds 100 columns
#23519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8234:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#23520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8235:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#23521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8236:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12

WARNING: line length of 114 exceeds 100 columns
#23522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8237:
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13

WARNING: line length of 114 exceeds 100 columns
#23523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8238:
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#23524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8239:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#23525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8240:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#23526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8241:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#23527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8242:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f

WARNING: line length of 121 exceeds 100 columns
#23528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8243:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8244:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8245:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8246:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8247:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8248:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8249:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8250:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8251:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8252:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8253:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8254:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8255:
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8256:
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8257:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8258:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8259:
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8260:
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8261:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1

WARNING: line length of 113 exceeds 100 columns
#23547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8262:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#23548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8263:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#23549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8264:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6

WARNING: line length of 113 exceeds 100 columns
#23550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8265:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#23551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8266:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#23552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8267:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9

WARNING: line length of 113 exceeds 100 columns
#23553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8268:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa

WARNING: line length of 113 exceeds 100 columns
#23554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8269:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf

WARNING: line length of 114 exceeds 100 columns
#23555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8270:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#23556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8271:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#23557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8272:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#23558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8273:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13

WARNING: line length of 114 exceeds 100 columns
#23559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8274:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#23560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8275:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c

WARNING: line length of 114 exceeds 100 columns
#23561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8276:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d

WARNING: line length of 114 exceeds 100 columns
#23562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8277:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#23563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8278:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8279:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8280:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8281:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8282:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8283:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8284:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8285:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8286:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8287:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8288:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8289:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8290:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8291:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8292:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8293:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8294:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8295:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8296:
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8297:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1

WARNING: line length of 113 exceeds 100 columns
#23583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8298:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#23584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8299:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#23585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8300:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6

WARNING: line length of 113 exceeds 100 columns
#23586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8301:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#23587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8302:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#23588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8303:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9

WARNING: line length of 113 exceeds 100 columns
#23589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8304:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa

WARNING: line length of 113 exceeds 100 columns
#23590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8305:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf

WARNING: line length of 114 exceeds 100 columns
#23591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8306:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#23592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8307:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#23593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8308:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#23594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8309:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13

WARNING: line length of 114 exceeds 100 columns
#23595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8310:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#23596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8311:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18

WARNING: line length of 114 exceeds 100 columns
#23597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8312:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c

WARNING: line length of 114 exceeds 100 columns
#23598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8313:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d

WARNING: line length of 114 exceeds 100 columns
#23599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8314:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#23600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8315:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8316:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8317:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8318:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8319:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8320:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8321:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8322:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8323:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8324:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8325:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8326:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8327:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8328:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8329:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8330:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#23616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8331:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8332:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8333:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8334:
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8335:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#23621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8336:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1

WARNING: line length of 113 exceeds 100 columns
#23622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8337:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#23623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8338:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#23624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8339:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6

WARNING: line length of 113 exceeds 100 columns
#23625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8340:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#23626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8341:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#23627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8342:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9

WARNING: line length of 113 exceeds 100 columns
#23628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8343:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa

WARNING: line length of 113 exceeds 100 columns
#23629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8344:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf

WARNING: line length of 114 exceeds 100 columns
#23630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8345:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#23631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8346:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#23632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8347:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#23633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8348:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13

WARNING: line length of 114 exceeds 100 columns
#23634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8349:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#23635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8350:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c

WARNING: line length of 114 exceeds 100 columns
#23636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8351:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d

WARNING: line length of 114 exceeds 100 columns
#23637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8352:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#23638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8353:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8354:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8355:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8356:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8357:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8358:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8359:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8360:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8361:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8362:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8363:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8364:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8365:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8366:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8367:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8368:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8369:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8370:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8371:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8372:
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8373:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#23659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8374:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#23660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8375:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6

WARNING: line length of 113 exceeds 100 columns
#23661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8376:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#23662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8377:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#23663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8378:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9

WARNING: line length of 113 exceeds 100 columns
#23664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8379:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa

WARNING: line length of 113 exceeds 100 columns
#23665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8380:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf

WARNING: line length of 114 exceeds 100 columns
#23666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8381:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#23667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8382:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#23668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8383:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#23669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8384:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13

WARNING: line length of 114 exceeds 100 columns
#23670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8385:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#23671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8386:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19

WARNING: line length of 114 exceeds 100 columns
#23672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8387:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#23673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8388:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b

WARNING: line length of 114 exceeds 100 columns
#23674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8389:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c

WARNING: line length of 114 exceeds 100 columns
#23675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8390:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d

WARNING: line length of 114 exceeds 100 columns
#23676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8391:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#23677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8392:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8393:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8394:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8395:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8396:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8397:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8398:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8399:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8400:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8401:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8402:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8403:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8404:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8405:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8406:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#23692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8407:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8408:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8409:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8410:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8411:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8412:
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8413:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#23699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8414:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#23700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8415:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#23701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8416:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#23702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8417:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd

WARNING: line length of 114 exceeds 100 columns
#23703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8418:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11

WARNING: line length of 114 exceeds 100 columns
#23704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8419:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12

WARNING: line length of 114 exceeds 100 columns
#23705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8420:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13

WARNING: line length of 114 exceeds 100 columns
#23706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8421:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14

WARNING: line length of 114 exceeds 100 columns
#23707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8422:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15

WARNING: line length of 114 exceeds 100 columns
#23708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8423:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16

WARNING: line length of 114 exceeds 100 columns
#23709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8424:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17

WARNING: line length of 114 exceeds 100 columns
#23710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8425:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#23711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8426:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19

WARNING: line length of 114 exceeds 100 columns
#23712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8427:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#23713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8428:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#23714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8429:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c

WARNING: line length of 114 exceeds 100 columns
#23715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8430:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8431:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8432:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8433:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#23719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8434:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8435:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8436:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8437:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8438:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8439:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8440:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L

WARNING: line length of 121 exceeds 100 columns
#23726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8441:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8442:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#23728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8443:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#23729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8444:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#23730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8445:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8446:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8447:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8448:
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8449:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#23735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8450:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#23736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8451:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9

WARNING: line length of 113 exceeds 100 columns
#23737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8452:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa

WARNING: line length of 114 exceeds 100 columns
#23738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8453:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#23739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8454:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#23740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8455:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b

WARNING: line length of 114 exceeds 100 columns
#23741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8456:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c

WARNING: line length of 114 exceeds 100 columns
#23742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8457:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8458:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8459:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8460:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8461:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8462:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8463:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8464:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8465:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8466:
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8467:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#23753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8468:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#23754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8469:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9

WARNING: line length of 113 exceeds 100 columns
#23755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8470:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa

WARNING: line length of 114 exceeds 100 columns
#23756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8471:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#23757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8472:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13

WARNING: line length of 114 exceeds 100 columns
#23758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8473:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#23759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8474:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8475:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8476:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8477:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8478:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8479:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8480:
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8481:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#23767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8482:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#23768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8483:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9

WARNING: line length of 113 exceeds 100 columns
#23769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8484:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa

WARNING: line length of 114 exceeds 100 columns
#23770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8485:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#23771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8486:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13

WARNING: line length of 114 exceeds 100 columns
#23772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8487:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c

WARNING: line length of 114 exceeds 100 columns
#23773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8488:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e

WARNING: line length of 114 exceeds 100 columns
#23774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8489:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f

WARNING: line length of 121 exceeds 100 columns
#23775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8490:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8491:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8492:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8493:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8494:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8495:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8496:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8497:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8498:
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8499:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#23785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8500:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1

WARNING: line length of 113 exceeds 100 columns
#23786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8501:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#23787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8502:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3

WARNING: line length of 113 exceeds 100 columns
#23788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8503:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#23789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8504:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#23790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8505:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#23791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8506:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd

WARNING: line length of 114 exceeds 100 columns
#23792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8507:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16

WARNING: line length of 114 exceeds 100 columns
#23793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8508:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17

WARNING: line length of 114 exceeds 100 columns
#23794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8509:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18

WARNING: line length of 114 exceeds 100 columns
#23795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8510:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19

WARNING: line length of 114 exceeds 100 columns
#23796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8511:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#23797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8512:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#23798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8513:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#23799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8514:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8515:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8516:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8517:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8518:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8519:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#23805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8520:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8521:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8522:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8523:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L

WARNING: line length of 121 exceeds 100 columns
#23809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8524:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#23810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8525:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L

WARNING: line length of 121 exceeds 100 columns
#23811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8526:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8527:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8528:
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8529:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6

WARNING: line length of 113 exceeds 100 columns
#23815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8530:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7

WARNING: line length of 113 exceeds 100 columns
#23816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8531:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#23817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8532:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9

WARNING: line length of 113 exceeds 100 columns
#23818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8533:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf

WARNING: line length of 114 exceeds 100 columns
#23819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8534:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#23820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8535:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11

WARNING: line length of 114 exceeds 100 columns
#23821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8536:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#23822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8537:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13

WARNING: line length of 114 exceeds 100 columns
#23823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8538:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#23824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8539:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15

WARNING: line length of 114 exceeds 100 columns
#23825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8540:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16

WARNING: line length of 114 exceeds 100 columns
#23826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8541:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#23827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8542:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#23828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8543:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#23829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8544:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#23830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8545:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8546:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8547:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8548:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8549:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8550:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8551:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8552:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L

WARNING: line length of 121 exceeds 100 columns
#23838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8553:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8554:
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8555:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#23841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8556:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#23842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8557:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#23843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8558:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa

WARNING: line length of 114 exceeds 100 columns
#23844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8559:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#23845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8560:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#23846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8561:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#23847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8562:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8563:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8564:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8565:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8566:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8567:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8568:
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8569:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#23855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8570:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#23856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8571:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#23857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8572:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3

WARNING: line length of 113 exceeds 100 columns
#23858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8573:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4

WARNING: line length of 113 exceeds 100 columns
#23859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8574:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9

WARNING: line length of 113 exceeds 100 columns
#23860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8575:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa

WARNING: line length of 113 exceeds 100 columns
#23861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8576:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb

WARNING: line length of 113 exceeds 100 columns
#23862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8577:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc

WARNING: line length of 113 exceeds 100 columns
#23863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8578:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd

WARNING: line length of 113 exceeds 100 columns
#23864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8579:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe

WARNING: line length of 113 exceeds 100 columns
#23865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8580:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf

WARNING: line length of 114 exceeds 100 columns
#23866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8581:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#23867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8582:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12

WARNING: line length of 114 exceeds 100 columns
#23868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8583:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13

WARNING: line length of 114 exceeds 100 columns
#23869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8584:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#23870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8585:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#23871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8586:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#23872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8587:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#23873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8588:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#23874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8589:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8590:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8591:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#23877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8592:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L

WARNING: line length of 121 exceeds 100 columns
#23878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8593:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#23879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8594:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8595:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8596:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L

WARNING: line length of 121 exceeds 100 columns
#23882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8597:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8598:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8599:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8600:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8601:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8602:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8603:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8604:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8605:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8606:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8607:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8608:
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8609:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#23895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8610:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1

WARNING: line length of 113 exceeds 100 columns
#23896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8611:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9

WARNING: line length of 113 exceeds 100 columns
#23897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8612:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#23898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8613:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12

WARNING: line length of 114 exceeds 100 columns
#23899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8614:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13

WARNING: line length of 114 exceeds 100 columns
#23900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8615:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#23901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8616:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#23902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8617:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#23903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8618:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#23904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8619:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#23905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8620:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8621:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8622:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8623:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8624:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8625:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8626:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8627:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8628:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8629:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8630:
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8631:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#23917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8632:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1

WARNING: line length of 113 exceeds 100 columns
#23918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8633:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9

WARNING: line length of 113 exceeds 100 columns
#23919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8634:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#23920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8635:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12

WARNING: line length of 114 exceeds 100 columns
#23921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8636:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13

WARNING: line length of 114 exceeds 100 columns
#23922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8637:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#23923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8638:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#23924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8639:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#23925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8640:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#23926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8641:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#23927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8642:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8643:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8644:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8645:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8646:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8647:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8648:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8649:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8650:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#23936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8651:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#23937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8652:
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8653:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#23939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8654:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1

WARNING: line length of 113 exceeds 100 columns
#23940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8655:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9

WARNING: line length of 113 exceeds 100 columns
#23941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8656:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#23942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8657:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#23943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8658:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc

WARNING: line length of 113 exceeds 100 columns
#23944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8659:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd

WARNING: line length of 113 exceeds 100 columns
#23945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8660:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe

WARNING: line length of 113 exceeds 100 columns
#23946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8661:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf

WARNING: line length of 114 exceeds 100 columns
#23947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8662:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#23948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8663:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11

WARNING: line length of 114 exceeds 100 columns
#23949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8664:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12

WARNING: line length of 114 exceeds 100 columns
#23950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8665:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13

WARNING: line length of 114 exceeds 100 columns
#23951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8666:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14

WARNING: line length of 114 exceeds 100 columns
#23952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8667:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15

WARNING: line length of 114 exceeds 100 columns
#23953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8668:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#23954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8669:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17

WARNING: line length of 114 exceeds 100 columns
#23955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8670:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18

WARNING: line length of 114 exceeds 100 columns
#23956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8671:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19

WARNING: line length of 114 exceeds 100 columns
#23957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8672:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#23958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8673:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b

WARNING: line length of 114 exceeds 100 columns
#23959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8674:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c

WARNING: line length of 114 exceeds 100 columns
#23960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8675:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#23961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8676:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#23962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8677:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#23963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8678:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#23964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8679:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#23965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8680:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#23966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8681:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#23967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8682:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#23968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8683:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#23969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8684:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#23970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8685:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#23971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8686:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L

WARNING: line length of 121 exceeds 100 columns
#23972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8687:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#23973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8688:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#23974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8689:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#23975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8690:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L

WARNING: line length of 121 exceeds 100 columns
#23976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8691:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#23977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8692:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L

WARNING: line length of 121 exceeds 100 columns
#23978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8693:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#23979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8694:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#23980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8695:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#23981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8696:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L

WARNING: line length of 121 exceeds 100 columns
#23982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8697:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L

WARNING: line length of 121 exceeds 100 columns
#23983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8698:
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#23984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8699:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#23985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8700:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#23986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8701:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#23987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8702:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3

WARNING: line length of 113 exceeds 100 columns
#23988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8703:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#23989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8704:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5

WARNING: line length of 113 exceeds 100 columns
#23990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8705:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6

WARNING: line length of 113 exceeds 100 columns
#23991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8706:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7

WARNING: line length of 113 exceeds 100 columns
#23992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8707:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#23993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8708:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#23994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8709:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa

WARNING: line length of 113 exceeds 100 columns
#23995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8710:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb

WARNING: line length of 114 exceeds 100 columns
#23996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8711:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12

WARNING: line length of 114 exceeds 100 columns
#23997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8712:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#23998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8713:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14

WARNING: line length of 114 exceeds 100 columns
#23999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8714:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#24000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8715:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#24001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8716:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17

WARNING: line length of 114 exceeds 100 columns
#24002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8717:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18

WARNING: line length of 114 exceeds 100 columns
#24003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8718:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19

WARNING: line length of 114 exceeds 100 columns
#24004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8719:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a

WARNING: line length of 114 exceeds 100 columns
#24005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8720:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b

WARNING: line length of 114 exceeds 100 columns
#24006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8721:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8722:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8723:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8724:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8725:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8726:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8727:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8728:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8729:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8730:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8731:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8732:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8733:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8734:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8735:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8736:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8737:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8738:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8739:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8740:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8741:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8742:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8743:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L

WARNING: line length of 121 exceeds 100 columns
#24029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8744:
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8745:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#24031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8746:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1

WARNING: line length of 113 exceeds 100 columns
#24032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8747:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9

WARNING: line length of 113 exceeds 100 columns
#24033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8748:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa

WARNING: line length of 113 exceeds 100 columns
#24034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8749:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb

WARNING: line length of 113 exceeds 100 columns
#24035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8750:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc

WARNING: line length of 113 exceeds 100 columns
#24036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8751:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd

WARNING: line length of 113 exceeds 100 columns
#24037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8752:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe

WARNING: line length of 113 exceeds 100 columns
#24038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8753:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf

WARNING: line length of 114 exceeds 100 columns
#24039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8754:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#24040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8755:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#24041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8756:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12

WARNING: line length of 114 exceeds 100 columns
#24042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8757:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13

WARNING: line length of 114 exceeds 100 columns
#24043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8758:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14

WARNING: line length of 114 exceeds 100 columns
#24044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8759:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15

WARNING: line length of 114 exceeds 100 columns
#24045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8760:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16

WARNING: line length of 114 exceeds 100 columns
#24046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8761:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17

WARNING: line length of 114 exceeds 100 columns
#24047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8762:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18

WARNING: line length of 114 exceeds 100 columns
#24048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8763:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8764:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8765:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8766:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8767:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8768:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8769:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8770:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8771:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8772:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8773:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8774:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8775:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8776:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8777:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8778:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8779:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8780:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8781:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8782:
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8783:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#24069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8784:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1

WARNING: line length of 113 exceeds 100 columns
#24070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8785:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2

WARNING: line length of 113 exceeds 100 columns
#24071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8786:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#24072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8787:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4

WARNING: line length of 113 exceeds 100 columns
#24073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8788:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5

WARNING: line length of 113 exceeds 100 columns
#24074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8789:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6

WARNING: line length of 113 exceeds 100 columns
#24075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8790:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7

WARNING: line length of 113 exceeds 100 columns
#24076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8791:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8

WARNING: line length of 113 exceeds 100 columns
#24077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8792:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9

WARNING: line length of 113 exceeds 100 columns
#24078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8793:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa

WARNING: line length of 113 exceeds 100 columns
#24079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8794:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb

WARNING: line length of 113 exceeds 100 columns
#24080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8795:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc

WARNING: line length of 113 exceeds 100 columns
#24081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8796:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd

WARNING: line length of 113 exceeds 100 columns
#24082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8797:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe

WARNING: line length of 113 exceeds 100 columns
#24083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8798:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf

WARNING: line length of 114 exceeds 100 columns
#24084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8799:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#24085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8800:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11

WARNING: line length of 114 exceeds 100 columns
#24086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8801:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12

WARNING: line length of 114 exceeds 100 columns
#24087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8802:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#24088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8803:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14

WARNING: line length of 114 exceeds 100 columns
#24089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8804:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15

WARNING: line length of 114 exceeds 100 columns
#24090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8805:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16

WARNING: line length of 114 exceeds 100 columns
#24091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8806:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17

WARNING: line length of 114 exceeds 100 columns
#24092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8807:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#24093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8808:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d

WARNING: line length of 114 exceeds 100 columns
#24094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8809:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8810:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8811:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8812:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8813:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8814:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8815:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8816:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8817:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8818:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8819:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8820:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8821:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8822:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8823:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8824:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8825:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8826:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8827:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8828:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8829:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8830:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8831:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8832:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8833:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8834:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8835:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L

WARNING: line length of 121 exceeds 100 columns
#24121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8836:
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8837:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#24123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8838:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1

WARNING: line length of 113 exceeds 100 columns
#24124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8839:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2

WARNING: line length of 113 exceeds 100 columns
#24125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8840:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3

WARNING: line length of 113 exceeds 100 columns
#24126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8841:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#24127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8842:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5

WARNING: line length of 113 exceeds 100 columns
#24128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8843:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#24129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8844:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#24130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8845:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#24131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8846:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9

WARNING: line length of 113 exceeds 100 columns
#24132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8847:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa

WARNING: line length of 113 exceeds 100 columns
#24133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8848:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb

WARNING: line length of 113 exceeds 100 columns
#24134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8849:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#24135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8850:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#24136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8851:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe

WARNING: line length of 113 exceeds 100 columns
#24137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8852:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf

WARNING: line length of 114 exceeds 100 columns
#24138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8853:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10

WARNING: line length of 114 exceeds 100 columns
#24139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8854:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11

WARNING: line length of 114 exceeds 100 columns
#24140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8855:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12

WARNING: line length of 114 exceeds 100 columns
#24141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8856:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13

WARNING: line length of 114 exceeds 100 columns
#24142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8857:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#24143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8858:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15

WARNING: line length of 114 exceeds 100 columns
#24144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8859:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16

WARNING: line length of 114 exceeds 100 columns
#24145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8860:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17

WARNING: line length of 114 exceeds 100 columns
#24146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8861:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18

WARNING: line length of 114 exceeds 100 columns
#24147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8862:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19

WARNING: line length of 114 exceeds 100 columns
#24148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8863:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#24149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8864:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b

WARNING: line length of 114 exceeds 100 columns
#24150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8865:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#24151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8866:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d

WARNING: line length of 114 exceeds 100 columns
#24152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8867:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8868:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8869:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8870:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8871:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8872:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8873:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8874:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8875:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8876:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8877:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8878:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8879:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8880:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8881:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8882:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8883:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8884:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8885:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8886:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8887:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8888:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8889:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8890:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8891:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8892:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8893:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8894:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8895:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#24181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8896:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8897:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L

WARNING: line length of 121 exceeds 100 columns
#24183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8898:
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8899:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#24185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8900:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1

WARNING: line length of 113 exceeds 100 columns
#24186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8901:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2

WARNING: line length of 113 exceeds 100 columns
#24187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8902:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3

WARNING: line length of 113 exceeds 100 columns
#24188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8903:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#24189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8904:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5

WARNING: line length of 113 exceeds 100 columns
#24190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8905:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6

WARNING: line length of 113 exceeds 100 columns
#24191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8906:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#24192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8907:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8

WARNING: line length of 113 exceeds 100 columns
#24193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8908:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9

WARNING: line length of 113 exceeds 100 columns
#24194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8909:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa

WARNING: line length of 113 exceeds 100 columns
#24195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8910:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb

WARNING: line length of 113 exceeds 100 columns
#24196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8911:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc

WARNING: line length of 113 exceeds 100 columns
#24197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8912:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd

WARNING: line length of 114 exceeds 100 columns
#24198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8913:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#24199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8914:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d

WARNING: line length of 114 exceeds 100 columns
#24200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8915:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8916:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8917:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8918:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8919:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8920:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8921:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8922:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8923:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8924:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8925:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8926:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8927:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8928:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8929:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8930:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8931:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L

WARNING: line length of 121 exceeds 100 columns
#24217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8932:
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L

WARNING: line length of 114 exceeds 100 columns
#24218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8933:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#24219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8934:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14

WARNING: line length of 114 exceeds 100 columns
#24220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8935:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15

WARNING: line length of 114 exceeds 100 columns
#24221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8936:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16

WARNING: line length of 114 exceeds 100 columns
#24222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8937:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17

WARNING: line length of 114 exceeds 100 columns
#24223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8938:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18

WARNING: line length of 114 exceeds 100 columns
#24224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8939:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19

WARNING: line length of 114 exceeds 100 columns
#24225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8940:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#24226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8941:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#24227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8942:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#24228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8943:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#24229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8944:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e

WARNING: line length of 114 exceeds 100 columns
#24230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8945:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8946:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8947:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8948:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8949:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8950:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8951:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8952:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8953:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8954:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#24240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8955:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8956:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#24242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8957:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L

WARNING: line length of 121 exceeds 100 columns
#24243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8958:
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8959:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#24245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8960:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4

WARNING: line length of 113 exceeds 100 columns
#24246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8961:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8

WARNING: line length of 113 exceeds 100 columns
#24247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8962:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#24248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8963:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#24249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8964:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#24250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8965:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#24251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8966:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L

WARNING: line length of 121 exceeds 100 columns
#24252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8967:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L

WARNING: line length of 121 exceeds 100 columns
#24253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8968:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#24254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8969:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L

WARNING: line length of 121 exceeds 100 columns
#24255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8970:
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L

WARNING: line length of 113 exceeds 100 columns
#24256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8971:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#24257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8972:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#24258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8973:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8

WARNING: line length of 113 exceeds 100 columns
#24259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8974:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc

WARNING: line length of 114 exceeds 100 columns
#24260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8975:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#24261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8976:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14

WARNING: line length of 114 exceeds 100 columns
#24262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8977:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18

WARNING: line length of 114 exceeds 100 columns
#24263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8978:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c

WARNING: line length of 121 exceeds 100 columns
#24264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8979:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#24265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8980:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L

WARNING: line length of 121 exceeds 100 columns
#24266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8981:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#24267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8982:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L

WARNING: line length of 121 exceeds 100 columns
#24268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8983:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L

WARNING: line length of 121 exceeds 100 columns
#24269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8984:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L

WARNING: line length of 121 exceeds 100 columns
#24270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8985:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L

WARNING: line length of 121 exceeds 100 columns
#24271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8986:
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L

WARNING: line length of 113 exceeds 100 columns
#24272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8987:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0

WARNING: line length of 113 exceeds 100 columns
#24273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8988:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4

WARNING: line length of 113 exceeds 100 columns
#24274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8989:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8

WARNING: line length of 113 exceeds 100 columns
#24275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8990:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc

WARNING: line length of 114 exceeds 100 columns
#24276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8991:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#24277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8992:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14

WARNING: line length of 121 exceeds 100 columns
#24278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8993:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L

WARNING: line length of 121 exceeds 100 columns
#24279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8994:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L

WARNING: line length of 121 exceeds 100 columns
#24280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8995:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L

WARNING: line length of 121 exceeds 100 columns
#24281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8996:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#24282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8997:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L

WARNING: line length of 121 exceeds 100 columns
#24283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8998:
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L

WARNING: line length of 113 exceeds 100 columns
#24284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:8999:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0

WARNING: line length of 113 exceeds 100 columns
#24285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9000:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4

WARNING: line length of 113 exceeds 100 columns
#24286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9001:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8

WARNING: line length of 113 exceeds 100 columns
#24287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9002:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#24288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9003:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#24289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9004:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14

WARNING: line length of 114 exceeds 100 columns
#24290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9005:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18

WARNING: line length of 114 exceeds 100 columns
#24291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9006:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c

WARNING: line length of 121 exceeds 100 columns
#24292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9007:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#24293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9008:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#24294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9009:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L

WARNING: line length of 121 exceeds 100 columns
#24295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9010:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L

WARNING: line length of 121 exceeds 100 columns
#24296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9011:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L

WARNING: line length of 121 exceeds 100 columns
#24297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9012:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#24298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9013:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L

WARNING: line length of 121 exceeds 100 columns
#24299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9014:
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L

WARNING: line length of 113 exceeds 100 columns
#24300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9015:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#24301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9016:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1

WARNING: line length of 113 exceeds 100 columns
#24302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9017:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#24303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9018:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3

WARNING: line length of 113 exceeds 100 columns
#24304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9019:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#24305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9020:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5

WARNING: line length of 113 exceeds 100 columns
#24306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9021:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0xa

WARNING: line length of 113 exceeds 100 columns
#24307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9022:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0xb

WARNING: line length of 113 exceeds 100 columns
#24308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9023:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0xc

WARNING: line length of 113 exceeds 100 columns
#24309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9024:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0xd

WARNING: line length of 113 exceeds 100 columns
#24310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9025:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xe

WARNING: line length of 113 exceeds 100 columns
#24311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9026:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xf

WARNING: line length of 114 exceeds 100 columns
#24312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9027:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9028:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9029:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9030:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9031:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9032:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9033:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9034:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9035:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9036:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9037:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9038:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9039:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9040:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9041:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#24327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9042:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#24328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9043:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#24329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9044:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#24330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9045:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#24331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9046:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#24332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9047:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#24333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9048:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#24334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9049:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#24335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9050:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#24336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9051:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa

WARNING: line length of 113 exceeds 100 columns
#24337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9052:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb

WARNING: line length of 113 exceeds 100 columns
#24338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9053:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc

WARNING: line length of 113 exceeds 100 columns
#24339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9054:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd

WARNING: line length of 113 exceeds 100 columns
#24340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9055:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe

WARNING: line length of 113 exceeds 100 columns
#24341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9056:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf

WARNING: line length of 114 exceeds 100 columns
#24342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9057:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#24343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9058:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#24344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9059:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12

WARNING: line length of 114 exceeds 100 columns
#24345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9060:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13

WARNING: line length of 114 exceeds 100 columns
#24346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9061:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14

WARNING: line length of 114 exceeds 100 columns
#24347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9062:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15

WARNING: line length of 114 exceeds 100 columns
#24348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9063:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#24349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9064:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#24350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9065:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#24351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9066:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#24352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9067:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT                              0x1a

WARNING: line length of 114 exceeds 100 columns
#24353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9068:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT                              0x1b

WARNING: line length of 114 exceeds 100 columns
#24354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9069:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT                              0x1c

WARNING: line length of 114 exceeds 100 columns
#24355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9070:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x1d

WARNING: line length of 114 exceeds 100 columns
#24356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9071:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x1e

WARNING: line length of 114 exceeds 100 columns
#24357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9072:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f

WARNING: line length of 121 exceeds 100 columns
#24358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9073:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9074:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9075:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9076:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9077:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9078:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9079:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9080:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9081:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9082:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9083:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9084:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9085:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9086:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9087:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9088:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9089:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9090:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9091:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9092:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9093:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9094:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9095:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9096:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9097:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9098:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9099:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9100:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#24386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9101:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK                                0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9102:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x20000000L

WARNING: line length of 121 exceeds 100 columns
#24388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9103:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x40000000L

WARNING: line length of 121 exceeds 100 columns
#24389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9104:
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9105:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT                                               0xc

WARNING: line length of 113 exceeds 100 columns
#24391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9106:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT                     0xd

WARNING: line length of 114 exceeds 100 columns
#24392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9107:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#24393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9108:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1d

WARNING: line length of 114 exceeds 100 columns
#24394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9109:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#24395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9110:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9111:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9112:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9113:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#24399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9114:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#24400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9115:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#24401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9116:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#24402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9117:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#24403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9118:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#24404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9119:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#24405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9120:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#24406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9121:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc

WARNING: line length of 113 exceeds 100 columns
#24407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9122:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd

WARNING: line length of 113 exceeds 100 columns
#24408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9123:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe

WARNING: line length of 113 exceeds 100 columns
#24409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9124:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf

WARNING: line length of 121 exceeds 100 columns
#24410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9125:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9126:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9127:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9128:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9129:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9130:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9131:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9132:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9133:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9134:
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L

WARNING: line length of 113 exceeds 100 columns
#24420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9135:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#24421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9136:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#24422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9137:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#24423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9138:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#24424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9139:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#24425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9140:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#24426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9141:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#24427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9142:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT                                                  0x7

WARNING: line length of 113 exceeds 100 columns
#24428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9143:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#24429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9144:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#24430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9145:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#24431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9146:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0xb

WARNING: line length of 113 exceeds 100 columns
#24432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9147:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#24433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9148:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0xd

WARNING: line length of 113 exceeds 100 columns
#24434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9149:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0xe

WARNING: line length of 113 exceeds 100 columns
#24435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9150:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0xf

WARNING: line length of 114 exceeds 100 columns
#24436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9151:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#24437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9152:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#24438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9153:
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#24439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9154:
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0x13

WARNING: line length of 114 exceeds 100 columns
#24440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9155:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#24441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9156:
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1b

WARNING: line length of 121 exceeds 100 columns
#24442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9157:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9158:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9159:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9160:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9161:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9162:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9163:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9164:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK                                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9165:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9166:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9167:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9168:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9169:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9170:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9171:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9172:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9173:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9174:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9175:
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9176:
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9177:
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9178:
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x08000000L

WARNING: line length of 113 exceeds 100 columns
#24464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9179:
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#24465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9180:
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT                         0xd

WARNING: line length of 121 exceeds 100 columns
#24466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9181:
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9182:
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK                           0x00002000L

WARNING: line length of 113 exceeds 100 columns
#24468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9183:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#24469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9184:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#24470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9185:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#24471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9186:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#24472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9187:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#24473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9188:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#24474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9189:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#24475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9190:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7

WARNING: line length of 114 exceeds 100 columns
#24476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9191:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#24477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9192:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#24478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9193:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#24479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9194:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#24480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9195:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14

WARNING: line length of 114 exceeds 100 columns
#24481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9196:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#24482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9197:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#24483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9198:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17

WARNING: line length of 121 exceeds 100 columns
#24484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9199:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9200:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9201:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9202:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9203:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9204:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9205:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9206:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9207:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9208:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9209:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9210:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9211:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9212:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9213:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9214:
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L

WARNING: line length of 113 exceeds 100 columns
#24500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9215:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#24501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9216:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1

WARNING: line length of 113 exceeds 100 columns
#24502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9217:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#24503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9218:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3

WARNING: line length of 113 exceeds 100 columns
#24504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9219:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#24505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9220:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#24506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9221:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa

WARNING: line length of 113 exceeds 100 columns
#24507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9222:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb

WARNING: line length of 113 exceeds 100 columns
#24508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9223:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xc

WARNING: line length of 113 exceeds 100 columns
#24509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9224:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xd

WARNING: line length of 113 exceeds 100 columns
#24510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9225:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xe

WARNING: line length of 113 exceeds 100 columns
#24511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9226:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xf

WARNING: line length of 121 exceeds 100 columns
#24512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9227:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9228:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9229:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9230:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9231:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9232:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9233:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9234:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9235:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9236:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9237:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9238:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00008000L

WARNING: line length of 113 exceeds 100 columns
#24524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9239:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1

WARNING: line length of 113 exceeds 100 columns
#24525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9240:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#24526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9241:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#24527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9242:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#24528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9243:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5

WARNING: line length of 113 exceeds 100 columns
#24529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9244:
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8

WARNING: line length of 113 exceeds 100 columns
#24530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9245:
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc

WARNING: line length of 113 exceeds 100 columns
#24531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9246:
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd

WARNING: line length of 121 exceeds 100 columns
#24532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9247:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9248:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9249:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9250:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9251:
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9252:
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9253:
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9254:
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L

WARNING: line length of 113 exceeds 100 columns
#24540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9255:
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1

WARNING: line length of 113 exceeds 100 columns
#24541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9256:
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9

WARNING: line length of 113 exceeds 100 columns
#24542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9257:
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb

WARNING: line length of 113 exceeds 100 columns
#24543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9258:
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#24544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9259:
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#24545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9260:
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#24546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9261:
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#24547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9262:
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10

WARNING: line length of 114 exceeds 100 columns
#24548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9263:
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11

WARNING: line length of 121 exceeds 100 columns
#24549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9264:
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9265:
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9266:
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9267:
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9268:
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9269:
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9270:
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9271:
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9272:
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#24558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9273:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#24559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9274:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#24560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9275:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#24561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9276:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3

WARNING: line length of 113 exceeds 100 columns
#24562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9277:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#24563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9278:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#24564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9279:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#24565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9280:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#24566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9281:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#24567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9282:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#24568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9283:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#24569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9284:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#24570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9285:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#24571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9286:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd

WARNING: line length of 113 exceeds 100 columns
#24572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9287:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe

WARNING: line length of 113 exceeds 100 columns
#24573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9288:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#24574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9289:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#24575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9290:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11

WARNING: line length of 114 exceeds 100 columns
#24576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9291:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#24577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9292:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13

WARNING: line length of 114 exceeds 100 columns
#24578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9293:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#24579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9294:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15

WARNING: line length of 114 exceeds 100 columns
#24580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9295:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#24581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9296:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17

WARNING: line length of 114 exceeds 100 columns
#24582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9297:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#24583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9298:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19

WARNING: line length of 114 exceeds 100 columns
#24584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9299:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#24585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9300:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b

WARNING: line length of 114 exceeds 100 columns
#24586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9301:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#24587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9302:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#24588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9303:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#24589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9304:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#24590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9305:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9306:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9307:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9308:
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9309:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9310:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9311:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9312:
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9313:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9314:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9315:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9316:
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9317:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9318:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9319:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9320:
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9321:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9322:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9323:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9324:
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9325:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9326:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9327:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9328:
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9329:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9330:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9331:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9332:
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L

WARNING: line length of 121 exceeds 100 columns
#24618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9333:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9334:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#24620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9335:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#24621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9336:
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#24622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9337:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc

WARNING: line length of 113 exceeds 100 columns
#24623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9338:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd

WARNING: line length of 113 exceeds 100 columns
#24624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9339:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe

WARNING: line length of 113 exceeds 100 columns
#24625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9340:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf

WARNING: line length of 114 exceeds 100 columns
#24626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9341:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#24627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9342:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11

WARNING: line length of 114 exceeds 100 columns
#24628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9343:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12

WARNING: line length of 114 exceeds 100 columns
#24629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9344:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13

WARNING: line length of 114 exceeds 100 columns
#24630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9345:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14

WARNING: line length of 114 exceeds 100 columns
#24631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9346:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15

WARNING: line length of 114 exceeds 100 columns
#24632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9347:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16

WARNING: line length of 114 exceeds 100 columns
#24633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9348:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17

WARNING: line length of 114 exceeds 100 columns
#24634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9349:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18

WARNING: line length of 114 exceeds 100 columns
#24635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9350:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19

WARNING: line length of 114 exceeds 100 columns
#24636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9351:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a

WARNING: line length of 114 exceeds 100 columns
#24637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9352:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b

WARNING: line length of 114 exceeds 100 columns
#24638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9353:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c

WARNING: line length of 114 exceeds 100 columns
#24639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9354:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d

WARNING: line length of 121 exceeds 100 columns
#24640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9355:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9356:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9357:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9358:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9359:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9360:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9361:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9362:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9363:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9364:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9365:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9366:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9367:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9368:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9369:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9370:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#24656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9371:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9372:
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L

WARNING: line length of 113 exceeds 100 columns
#24658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9373:
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#24659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9374:
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#24660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9375:
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#24661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9376:
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#24662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9377:
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#24663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9378:
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#24664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9379:
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#24665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9380:
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#24666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9381:
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#24667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9382:
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#24668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9383:
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa

WARNING: line length of 113 exceeds 100 columns
#24669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9384:
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#24670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9385:
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#24671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9386:
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#24672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9387:
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe

WARNING: line length of 113 exceeds 100 columns
#24673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9388:
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#24674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9389:
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#24675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9390:
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19

WARNING: line length of 114 exceeds 100 columns
#24676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9391:
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a

WARNING: line length of 121 exceeds 100 columns
#24677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9392:
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9393:
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9394:
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9395:
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9396:
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9397:
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9398:
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9399:
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9400:
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9401:
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9402:
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9403:
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9404:
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9405:
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9406:
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9407:
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9408:
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9409:
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9410:
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L

WARNING: line length of 113 exceeds 100 columns
#24696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9411:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc

WARNING: line length of 113 exceeds 100 columns
#24697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9412:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd

WARNING: line length of 113 exceeds 100 columns
#24698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9413:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe

WARNING: line length of 113 exceeds 100 columns
#24699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9414:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf

WARNING: line length of 114 exceeds 100 columns
#24700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9415:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#24701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9416:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#24702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9417:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12

WARNING: line length of 114 exceeds 100 columns
#24703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9418:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13

WARNING: line length of 114 exceeds 100 columns
#24704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9419:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14

WARNING: line length of 114 exceeds 100 columns
#24705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9420:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15

WARNING: line length of 114 exceeds 100 columns
#24706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9421:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16

WARNING: line length of 114 exceeds 100 columns
#24707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9422:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17

WARNING: line length of 114 exceeds 100 columns
#24708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9423:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18

WARNING: line length of 114 exceeds 100 columns
#24709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9424:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19

WARNING: line length of 114 exceeds 100 columns
#24710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9425:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a

WARNING: line length of 114 exceeds 100 columns
#24711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9426:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b

WARNING: line length of 121 exceeds 100 columns
#24712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9427:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9428:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9429:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#24715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9430:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9431:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9432:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9433:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9434:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9435:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#24721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9436:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#24722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9437:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L

WARNING: line length of 121 exceeds 100 columns
#24723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9438:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L

WARNING: line length of 121 exceeds 100 columns
#24724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9439:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9440:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9441:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9442:
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L

WARNING: line length of 113 exceeds 100 columns
#24728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9443:
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#24729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9444:
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#24730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9445:
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#24731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9446:
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3

WARNING: line length of 113 exceeds 100 columns
#24732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9447:
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#24733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9448:
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#24734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9449:
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#24735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9450:
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7

WARNING: line length of 113 exceeds 100 columns
#24736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9451:
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#24737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9452:
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd

WARNING: line length of 121 exceeds 100 columns
#24738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9453:
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9454:
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9455:
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9456:
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9457:
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9458:
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9459:
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9460:
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9461:
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9462:
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L

WARNING: line length of 113 exceeds 100 columns
#24748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9463:
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#24749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9464:
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd

WARNING: line length of 121 exceeds 100 columns
#24750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9465:
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9466:
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L

WARNING: line length of 113 exceeds 100 columns
#24752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9467:
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc

WARNING: line length of 113 exceeds 100 columns
#24753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9468:
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd

WARNING: line length of 114 exceeds 100 columns
#24754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9469:
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18

WARNING: line length of 114 exceeds 100 columns
#24755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9470:
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19

WARNING: line length of 114 exceeds 100 columns
#24756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9471:
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#24757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9472:
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#24758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9473:
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#24759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9474:
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d

WARNING: line length of 121 exceeds 100 columns
#24760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9475:
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#24761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9476:
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L

WARNING: line length of 121 exceeds 100 columns
#24762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9477:
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#24763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9478:
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L

WARNING: line length of 121 exceeds 100 columns
#24764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9479:
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#24765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9480:
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#24766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9481:
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#24767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9482:
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L

WARNING: line length of 113 exceeds 100 columns
#24768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9483:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#24769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9484:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#24770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9485:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#24771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9486:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3

WARNING: line length of 113 exceeds 100 columns
#24772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9487:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#24773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9488:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5

WARNING: line length of 113 exceeds 100 columns
#24774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9489:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#24775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9490:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#24776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9491:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#24777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9492:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#24778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9493:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#24779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9494:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#24780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9495:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf

WARNING: line length of 114 exceeds 100 columns
#24781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9496:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#24782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9497:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#24783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9498:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#24784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9499:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13

WARNING: line length of 114 exceeds 100 columns
#24785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9500:
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14

WARNING: line length of 121 exceeds 100 columns
#24786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9501:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9502:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9503:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9504:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9505:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9506:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9507:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9508:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9509:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9510:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9511:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9512:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9513:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9514:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9515:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9516:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9517:
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9518:
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L

WARNING: line length of 113 exceeds 100 columns
#24804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9519:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#24805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9520:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#24806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9521:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#24807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9522:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3

WARNING: line length of 113 exceeds 100 columns
#24808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9523:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#24809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9524:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5

WARNING: line length of 113 exceeds 100 columns
#24810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9525:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#24811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9526:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#24812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9527:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#24813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9528:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#24814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9529:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#24815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9530:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#24816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9531:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf

WARNING: line length of 114 exceeds 100 columns
#24817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9532:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#24818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9533:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#24819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9534:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#24820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9535:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13

WARNING: line length of 114 exceeds 100 columns
#24821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9536:
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14

WARNING: line length of 121 exceeds 100 columns
#24822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9537:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9538:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9539:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9540:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9541:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9542:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9543:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9544:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9545:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9546:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9547:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9548:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9549:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9550:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9551:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9552:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9553:
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9554:
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L

WARNING: line length of 113 exceeds 100 columns
#24840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9555:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#24841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9556:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#24842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9557:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#24843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9558:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3

WARNING: line length of 113 exceeds 100 columns
#24844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9559:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#24845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9560:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5

WARNING: line length of 113 exceeds 100 columns
#24846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9561:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#24847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9562:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#24848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9563:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#24849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9564:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#24850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9565:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#24851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9566:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#24852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9567:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf

WARNING: line length of 114 exceeds 100 columns
#24853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9568:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#24854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9569:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#24855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9570:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#24856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9571:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13

WARNING: line length of 114 exceeds 100 columns
#24857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9572:
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14

WARNING: line length of 121 exceeds 100 columns
#24858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9573:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9574:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9575:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9576:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9577:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9578:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9579:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9580:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9581:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9582:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9583:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9584:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9585:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9586:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9587:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9588:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9589:
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9590:
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L

WARNING: line length of 113 exceeds 100 columns
#24876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9591:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#24877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9592:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#24878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9593:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#24879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9594:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3

WARNING: line length of 113 exceeds 100 columns
#24880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9595:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#24881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9596:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5

WARNING: line length of 113 exceeds 100 columns
#24882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9597:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#24883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9598:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#24884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9599:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#24885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9600:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#24886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9601:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#24887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9602:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#24888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9603:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf

WARNING: line length of 114 exceeds 100 columns
#24889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9604:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#24890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9605:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#24891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9606:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#24892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9607:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13

WARNING: line length of 114 exceeds 100 columns
#24893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9608:
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14

WARNING: line length of 121 exceeds 100 columns
#24894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9609:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9610:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9611:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9612:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9613:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9614:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9615:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9616:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9617:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9618:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9619:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9620:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9621:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9622:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9623:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9624:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9625:
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9626:
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L

WARNING: line length of 113 exceeds 100 columns
#24912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9627:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#24913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9628:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#24914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9629:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#24915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9630:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3

WARNING: line length of 113 exceeds 100 columns
#24916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9631:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#24917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9632:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5

WARNING: line length of 113 exceeds 100 columns
#24918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9633:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#24919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9634:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#24920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9635:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#24921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9636:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#24922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9637:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#24923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9638:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#24924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9639:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf

WARNING: line length of 114 exceeds 100 columns
#24925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9640:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#24926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9641:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#24927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9642:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#24928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9643:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13

WARNING: line length of 114 exceeds 100 columns
#24929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9644:
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14

WARNING: line length of 121 exceeds 100 columns
#24930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9645:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9646:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9647:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9648:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9649:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9650:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9651:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9652:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9653:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9654:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9655:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9656:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9657:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9658:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9659:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9660:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9661:
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9662:
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L

WARNING: line length of 113 exceeds 100 columns
#24948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9663:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#24949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9664:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#24950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9665:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#24951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9666:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3

WARNING: line length of 113 exceeds 100 columns
#24952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9667:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#24953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9668:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5

WARNING: line length of 113 exceeds 100 columns
#24954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9669:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#24955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9670:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#24956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9671:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#24957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9672:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#24958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9673:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#24959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9674:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#24960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9675:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf

WARNING: line length of 114 exceeds 100 columns
#24961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9676:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#24962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9677:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#24963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9678:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#24964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9679:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13

WARNING: line length of 114 exceeds 100 columns
#24965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9680:
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14

WARNING: line length of 121 exceeds 100 columns
#24966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9681:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#24967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9682:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#24968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9683:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#24969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9684:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#24970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9685:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#24971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9686:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#24972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9687:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#24973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9688:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#24974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9689:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#24975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9690:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#24976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9691:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#24977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9692:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#24978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9693:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#24979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9694:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#24980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9695:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#24981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9696:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#24982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9697:
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L

WARNING: line length of 121 exceeds 100 columns
#24983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9698:
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L

WARNING: line length of 113 exceeds 100 columns
#24984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9699:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#24985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9700:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#24986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9701:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2

WARNING: line length of 113 exceeds 100 columns
#24987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9702:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3

WARNING: line length of 113 exceeds 100 columns
#24988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9703:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#24989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9704:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5

WARNING: line length of 113 exceeds 100 columns
#24990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9705:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6

WARNING: line length of 113 exceeds 100 columns
#24991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9706:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7

WARNING: line length of 113 exceeds 100 columns
#24992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9707:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8

WARNING: line length of 113 exceeds 100 columns
#24993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9708:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9

WARNING: line length of 113 exceeds 100 columns
#24994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9709:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa

WARNING: line length of 113 exceeds 100 columns
#24995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9710:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb

WARNING: line length of 113 exceeds 100 columns
#24996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9711:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc

WARNING: line length of 113 exceeds 100 columns
#24997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9712:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd

WARNING: line length of 113 exceeds 100 columns
#24998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9713:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe

WARNING: line length of 113 exceeds 100 columns
#24999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9714:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf

WARNING: line length of 121 exceeds 100 columns
#25000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9715:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9716:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9717:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9718:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9719:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9720:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9721:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9722:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9723:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9724:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9725:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9726:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9727:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9728:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9729:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9730:
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L

WARNING: line length of 113 exceeds 100 columns
#25016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9731:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#25017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9732:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#25018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9733:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2

WARNING: line length of 113 exceeds 100 columns
#25019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9734:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#25020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9735:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#25021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9736:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5

WARNING: line length of 113 exceeds 100 columns
#25022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9737:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6

WARNING: line length of 113 exceeds 100 columns
#25023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9738:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7

WARNING: line length of 114 exceeds 100 columns
#25024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9739:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#25025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9740:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11

WARNING: line length of 114 exceeds 100 columns
#25026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9741:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12

WARNING: line length of 114 exceeds 100 columns
#25027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9742:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13

WARNING: line length of 114 exceeds 100 columns
#25028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9743:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#25029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9744:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15

WARNING: line length of 114 exceeds 100 columns
#25030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9745:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16

WARNING: line length of 121 exceeds 100 columns
#25031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9746:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9747:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9748:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9749:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9750:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9751:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9752:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9753:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9754:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9755:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9756:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9757:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L

WARNING: line length of 121 exceeds 100 columns
#25043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9758:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#25044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9759:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#25045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9760:
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L

WARNING: line length of 113 exceeds 100 columns
#25046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9761:
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#25047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9762:
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#25048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9763:
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd

WARNING: line length of 121 exceeds 100 columns
#25049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9764:
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9765:
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9766:
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L

WARNING: line length of 113 exceeds 100 columns
#25052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9767:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#25053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9768:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1

WARNING: line length of 113 exceeds 100 columns
#25054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9769:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2

WARNING: line length of 113 exceeds 100 columns
#25055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9770:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3

WARNING: line length of 113 exceeds 100 columns
#25056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9771:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#25057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9772:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5

WARNING: line length of 113 exceeds 100 columns
#25058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9773:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6

WARNING: line length of 114 exceeds 100 columns
#25059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9774:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10

WARNING: line length of 121 exceeds 100 columns
#25060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9775:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9776:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9777:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9778:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9779:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9780:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9781:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9782:
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L

WARNING: line length of 113 exceeds 100 columns
#25068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9783:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#25069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9784:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#25070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9785:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#25071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9786:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#25072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9787:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#25073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9788:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5

WARNING: line length of 113 exceeds 100 columns
#25074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9789:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#25075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9790:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#25076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9791:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#25077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9792:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb

WARNING: line length of 113 exceeds 100 columns
#25078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9793:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#25079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9794:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd

WARNING: line length of 121 exceeds 100 columns
#25080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9795:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9796:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9797:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9798:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9799:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9800:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9801:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9802:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9803:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9804:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9805:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9806:
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L

WARNING: line length of 113 exceeds 100 columns
#25092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9807:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#25093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9808:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#25094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9809:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#25095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9810:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#25096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9811:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#25097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9812:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#25098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9813:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#25099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9814:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#25100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9815:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#25101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9816:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#25102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9817:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#25103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9818:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#25104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9819:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#25105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9820:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#25106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9821:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#25107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9822:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#25108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9823:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#25109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9824:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#25110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9825:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#25111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9826:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13

WARNING: line length of 114 exceeds 100 columns
#25112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9827:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14

WARNING: line length of 114 exceeds 100 columns
#25113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9828:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15

WARNING: line length of 114 exceeds 100 columns
#25114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9829:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#25115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9830:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17

WARNING: line length of 114 exceeds 100 columns
#25116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9831:
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e

WARNING: line length of 114 exceeds 100 columns
#25117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9832:
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#25118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9833:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9834:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9835:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9836:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9837:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9838:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9839:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9840:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9841:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9842:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9843:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9844:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9845:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9846:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9847:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9848:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9849:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9850:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9851:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9852:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#25138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9853:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#25139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9854:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#25140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9855:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#25141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9856:
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#25142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9857:
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L

WARNING: line length of 121 exceeds 100 columns
#25143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9858:
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9859:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#25145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9860:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1

WARNING: line length of 113 exceeds 100 columns
#25146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9861:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#25147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9862:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#25148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9863:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#25149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9864:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5

WARNING: line length of 113 exceeds 100 columns
#25150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9865:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#25151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9866:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7

WARNING: line length of 113 exceeds 100 columns
#25152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9867:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8

WARNING: line length of 113 exceeds 100 columns
#25153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9868:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9

WARNING: line length of 113 exceeds 100 columns
#25154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9869:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa

WARNING: line length of 113 exceeds 100 columns
#25155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9870:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb

WARNING: line length of 114 exceeds 100 columns
#25156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9871:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10

WARNING: line length of 114 exceeds 100 columns
#25157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9872:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#25158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9873:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12

WARNING: line length of 114 exceeds 100 columns
#25159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9874:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#25160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9875:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#25161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9876:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#25162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9877:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16

WARNING: line length of 114 exceeds 100 columns
#25163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9878:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17

WARNING: line length of 114 exceeds 100 columns
#25164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9879:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18

WARNING: line length of 114 exceeds 100 columns
#25165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9880:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19

WARNING: line length of 114 exceeds 100 columns
#25166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9881:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a

WARNING: line length of 114 exceeds 100 columns
#25167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9882:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b

WARNING: line length of 121 exceeds 100 columns
#25168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9883:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9884:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9885:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9886:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9887:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9888:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9889:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9890:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9891:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9892:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9893:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9894:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9895:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9896:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9897:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9898:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#25184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9899:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#25185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9900:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#25186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9901:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L

WARNING: line length of 121 exceeds 100 columns
#25187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9902:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#25188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9903:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#25189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9904:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L

WARNING: line length of 121 exceeds 100 columns
#25190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9905:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L

WARNING: line length of 121 exceeds 100 columns
#25191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9906:
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L

WARNING: line length of 113 exceeds 100 columns
#25192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9907:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#25193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9908:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#25194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9909:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#25195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9910:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#25196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9911:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#25197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9912:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5

WARNING: line length of 113 exceeds 100 columns
#25198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9913:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#25199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9914:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#25200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9915:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8

WARNING: line length of 113 exceeds 100 columns
#25201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9916:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9

WARNING: line length of 113 exceeds 100 columns
#25202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9917:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa

WARNING: line length of 113 exceeds 100 columns
#25203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9918:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#25204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9919:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#25205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9920:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#25206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9921:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe

WARNING: line length of 113 exceeds 100 columns
#25207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9922:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf

WARNING: line length of 114 exceeds 100 columns
#25208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9923:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#25209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9924:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#25210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9925:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12

WARNING: line length of 114 exceeds 100 columns
#25211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9926:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13

WARNING: line length of 114 exceeds 100 columns
#25212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9927:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14

WARNING: line length of 114 exceeds 100 columns
#25213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9928:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#25214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9929:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16

WARNING: line length of 114 exceeds 100 columns
#25215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9930:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17

WARNING: line length of 121 exceeds 100 columns
#25216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9931:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9932:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9933:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9934:
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9935:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9936:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9937:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9938:
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9939:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9940:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9941:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9942:
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9943:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9944:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9945:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9946:
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9947:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9948:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9949:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9950:
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#25236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9951:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#25237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9952:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L

WARNING: line length of 121 exceeds 100 columns
#25238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9953:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#25239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9954:
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L

WARNING: line length of 113 exceeds 100 columns
#25240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9955:
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0x2

WARNING: line length of 113 exceeds 100 columns
#25241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9956:
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0x3

WARNING: line length of 121 exceeds 100 columns
#25242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9957:
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9958:
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00000008L

WARNING: line length of 113 exceeds 100 columns
#25244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9959:
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#25245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9960:
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT                                                  0x8

WARNING: line length of 121 exceeds 100 columns
#25246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9961:
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK                                                    0x00000070L

WARNING: line length of 121 exceeds 100 columns
#25247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9962:
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK                                                    0x01FFFF00L

WARNING: line length of 113 exceeds 100 columns
#25248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9963:
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9964:
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14

WARNING: line length of 121 exceeds 100 columns
#25250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9965:
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL

WARNING: line length of 121 exceeds 100 columns
#25251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9966:
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#25252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9967:
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#25253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9968:
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9969:
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#25255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9970:
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL

WARNING: line length of 113 exceeds 100 columns
#25256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9971:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2

WARNING: line length of 114 exceeds 100 columns
#25257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9972:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c

WARNING: line length of 114 exceeds 100 columns
#25258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9973:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d

WARNING: line length of 114 exceeds 100 columns
#25259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9974:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#25260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9975:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#25261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9976:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL

WARNING: line length of 121 exceeds 100 columns
#25262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9977:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L

WARNING: line length of 121 exceeds 100 columns
#25263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9978:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L

WARNING: line length of 121 exceeds 100 columns
#25264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9979:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#25265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9980:
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9981:
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#25267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9982:
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#25268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9983:
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2

WARNING: line length of 113 exceeds 100 columns
#25269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9984:
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3

WARNING: line length of 113 exceeds 100 columns
#25270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9985:
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#25271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9986:
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#25272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9987:
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#25273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9988:
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7

WARNING: line length of 113 exceeds 100 columns
#25274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9989:
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#25275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9990:
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#25276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9991:
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa

WARNING: line length of 113 exceeds 100 columns
#25277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9992:
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb

WARNING: line length of 113 exceeds 100 columns
#25278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9993:
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc

WARNING: line length of 113 exceeds 100 columns
#25279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9994:
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd

WARNING: line length of 113 exceeds 100 columns
#25280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9995:
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe

WARNING: line length of 113 exceeds 100 columns
#25281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9996:
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf

WARNING: line length of 114 exceeds 100 columns
#25282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9997:
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#25283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9998:
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11

WARNING: line length of 114 exceeds 100 columns
#25284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:9999:
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12

WARNING: line length of 114 exceeds 100 columns
#25285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10000:
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13

WARNING: line length of 114 exceeds 100 columns
#25286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10001:
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#25287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10002:
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15

WARNING: line length of 114 exceeds 100 columns
#25288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10003:
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16

WARNING: line length of 114 exceeds 100 columns
#25289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10004:
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17

WARNING: line length of 114 exceeds 100 columns
#25290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10005:
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18

WARNING: line length of 114 exceeds 100 columns
#25291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10006:
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19

WARNING: line length of 114 exceeds 100 columns
#25292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10007:
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a

WARNING: line length of 114 exceeds 100 columns
#25293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10008:
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b

WARNING: line length of 114 exceeds 100 columns
#25294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10009:
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c

WARNING: line length of 114 exceeds 100 columns
#25295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10010:
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#25296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10011:
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e

WARNING: line length of 114 exceeds 100 columns
#25297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10012:
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#25298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10013:
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10014:
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10015:
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10016:
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10017:
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10018:
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10019:
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10020:
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10021:
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10022:
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10023:
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10024:
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10025:
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10026:
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10027:
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10028:
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10029:
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10030:
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10031:
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10032:
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L

WARNING: line length of 121 exceeds 100 columns
#25318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10033:
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#25319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10034:
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#25320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10035:
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L

WARNING: line length of 121 exceeds 100 columns
#25321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10036:
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L

WARNING: line length of 121 exceeds 100 columns
#25322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10037:
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#25323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10038:
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#25324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10039:
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L

WARNING: line length of 121 exceeds 100 columns
#25325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10040:
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#25326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10041:
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L

WARNING: line length of 121 exceeds 100 columns
#25327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10042:
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#25328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10043:
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L

WARNING: line length of 121 exceeds 100 columns
#25329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10044:
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10045:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#25331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10046:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#25332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10047:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2

WARNING: line length of 113 exceeds 100 columns
#25333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10048:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3

WARNING: line length of 113 exceeds 100 columns
#25334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10049:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#25335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10050:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#25336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10051:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6

WARNING: line length of 121 exceeds 100 columns
#25337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10052:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10053:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10054:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10055:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10056:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10057:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10058:
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L

WARNING: line length of 113 exceeds 100 columns
#25344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10059:
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#25345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10060:
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#25346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10061:
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#25347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10062:
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6

WARNING: line length of 113 exceeds 100 columns
#25348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10063:
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#25349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10064:
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9

WARNING: line length of 114 exceeds 100 columns
#25350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10065:
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#25351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10066:
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#25352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10067:
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10068:
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10069:
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10070:
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10071:
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#25357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10072:
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#25358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10073:
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#25359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10074:
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10075:
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10076:
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10077:
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#25363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10078:
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10079:
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10080:
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10081:
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#25367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10082:
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10083:
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10084:
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10085:
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#25371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10086:
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10087:
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10088:
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10089:
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#25375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10090:
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10091:
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10092:
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10093:
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#25379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10094:
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10095:
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10096:
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10097:
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#25383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10098:
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10099:
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10100:
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10101:
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10102:
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#25388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10103:
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10104:
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10105:
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10106:
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#25392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10107:
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10108:
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10109:
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10110:
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#25396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10111:
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10112:
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10113:
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10114:
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#25400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10115:
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10116:
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10117:
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10118:
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#25404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10119:
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10120:
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10121:
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10122:
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#25408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10123:
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10124:
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10125:
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#25411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10126:
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#25412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10127:
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10128:
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10129:
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10130:
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10131:
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10132:
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10133:
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10134:
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10135:
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10136:
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10137:
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10138:
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10139:
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10140:
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10141:
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10142:
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10143:
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10144:
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10145:
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10146:
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10147:
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10148:
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10149:
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10150:
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10151:
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10152:
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10153:
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10154:
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10155:
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10156:
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10157:
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10158:
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10159:
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10160:
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10161:
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10162:
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10163:
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10164:
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10165:
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10166:
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10167:
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10168:
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10169:
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10170:
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10171:
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10172:
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10173:
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#25459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10174:
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#25460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10175:
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#25461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10176:
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#25462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10177:
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10178:
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10179:
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10180:
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10181:
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10182:
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10183:
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10184:
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10185:
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10186:
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10187:
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10188:
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10189:
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10190:
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10191:
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10192:
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10193:
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10194:
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10195:
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10196:
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10197:
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10198:
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10199:
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10200:
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10201:
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10202:
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10203:
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10204:
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10205:
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10206:
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#25492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10207:
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10208:
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10209:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#25495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10210:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#25496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10211:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#25497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10212:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#25498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10213:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#25499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10214:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5

WARNING: line length of 113 exceeds 100 columns
#25500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10215:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#25501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10216:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#25502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10217:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#25503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10218:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9

WARNING: line length of 113 exceeds 100 columns
#25504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10219:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#25505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10220:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#25506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10221:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#25507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10222:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#25508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10223:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT                                                    0xe

WARNING: line length of 113 exceeds 100 columns
#25509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10224:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT                                                    0xf

WARNING: line length of 114 exceeds 100 columns
#25510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10225:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#25511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10226:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT                                                  0x11

WARNING: line length of 114 exceeds 100 columns
#25512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10227:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0x12

WARNING: line length of 121 exceeds 100 columns
#25513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10228:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10229:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10230:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10231:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10232:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10233:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10234:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10235:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10236:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10237:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10238:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10239:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10240:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10241:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10242:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10243:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK                                                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10244:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10245:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK                                                    0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10246:
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00040000L

WARNING: line length of 113 exceeds 100 columns
#25532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10247:
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#25533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10248:
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#25534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10249:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#25535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10250:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3

WARNING: line length of 113 exceeds 100 columns
#25536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10251:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#25537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10252:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#25538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10253:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6

WARNING: line length of 113 exceeds 100 columns
#25539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10254:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7

WARNING: line length of 113 exceeds 100 columns
#25540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10255:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#25541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10256:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#25542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10257:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa

WARNING: line length of 113 exceeds 100 columns
#25543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10258:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb

WARNING: line length of 113 exceeds 100 columns
#25544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10259:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#25545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10260:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#25546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10261:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT                                                      0xe

WARNING: line length of 113 exceeds 100 columns
#25547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10262:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT                                                      0xf

WARNING: line length of 114 exceeds 100 columns
#25548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10263:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#25549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10264:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#25550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10265:
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0x12

WARNING: line length of 121 exceeds 100 columns
#25551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10266:
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10267:
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10268:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10269:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10270:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10271:
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10272:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10273:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10274:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10275:
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10276:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10277:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10278:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10279:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10280:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK                                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10281:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK                                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10282:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10283:
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10284:
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00040000L

WARNING: line length of 113 exceeds 100 columns
#25570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10285:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#25571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10286:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#25572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10287:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#25573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10288:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#25574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10289:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#25575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10290:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#25576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10291:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#25577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10292:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7

WARNING: line length of 113 exceeds 100 columns
#25578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10293:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#25579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10294:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#25580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10295:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#25581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10296:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb

WARNING: line length of 113 exceeds 100 columns
#25582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10297:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#25583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10298:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT                                                  0xd

WARNING: line length of 113 exceeds 100 columns
#25584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10299:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT                                                  0xe

WARNING: line length of 113 exceeds 100 columns
#25585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10300:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#25586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10301:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#25587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10302:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#25588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10303:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#25589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10304:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#25590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10305:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0x14

WARNING: line length of 121 exceeds 100 columns
#25591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10306:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10307:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10308:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10309:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10310:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10311:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10312:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10313:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10314:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10315:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10316:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10317:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10318:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10319:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK                                                    0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10320:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10321:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10322:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10323:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10324:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10325:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#25611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10326:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00100000L

WARNING: line length of 113 exceeds 100 columns
#25612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10327:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#25613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10328:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#25614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10329:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#25615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10330:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#25616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10331:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#25617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10332:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5

WARNING: line length of 113 exceeds 100 columns
#25618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10333:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#25619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10334:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#25620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10335:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#25621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10336:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9

WARNING: line length of 113 exceeds 100 columns
#25622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10337:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#25623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10338:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#25624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10339:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#25625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10340:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#25626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10341:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT                                                    0xe

WARNING: line length of 113 exceeds 100 columns
#25627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10342:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT                                                    0xf

WARNING: line length of 114 exceeds 100 columns
#25628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10343:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#25629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10344:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT                                                  0x11

WARNING: line length of 114 exceeds 100 columns
#25630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10345:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0x12

WARNING: line length of 121 exceeds 100 columns
#25631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10346:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10347:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10348:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10349:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10350:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10351:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10352:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10353:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10354:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10355:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#25641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10356:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#25642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10357:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#25643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10358:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#25644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10359:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10360:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10361:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK                                                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10362:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10363:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK                                                    0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10364:
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00040000L

WARNING: line length of 113 exceeds 100 columns
#25650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10365:
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#25651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10366:
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#25652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10367:
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#25653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10368:
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L

WARNING: line length of 113 exceeds 100 columns
#25654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10369:
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10370:
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10371:
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10372:
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#25658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10373:
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10374:
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10375:
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10376:
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10377:
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8

WARNING: line length of 114 exceeds 100 columns
#25663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10378:
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10

WARNING: line length of 114 exceeds 100 columns
#25664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10379:
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11

WARNING: line length of 114 exceeds 100 columns
#25665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10380:
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#25666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10381:
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#25667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10382:
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#25668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10383:
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19

WARNING: line length of 121 exceeds 100 columns
#25669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10384:
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#25670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10385:
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10386:
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10387:
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#25673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10388:
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L

WARNING: line length of 121 exceeds 100 columns
#25674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10389:
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#25675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10390:
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L

WARNING: line length of 113 exceeds 100 columns
#25676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10391:
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#25677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10392:
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4

WARNING: line length of 121 exceeds 100 columns
#25678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10393:
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#25679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10394:
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#25680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10395:
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10396:
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10397:
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10398:
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10399:
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10400:
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10401:
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10402:
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10403:
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10404:
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10405:
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10406:
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10407:
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10408:
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10409:
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10410:
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10411:
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10412:
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10413:
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10414:
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10415:
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10416:
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10417:
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10418:
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10419:
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10420:
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10421:
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10422:
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10423:
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10424:
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10425:
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10426:
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10427:
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10428:
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10429:
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10430:
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10431:
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#25717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10432:
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L

WARNING: line length of 113 exceeds 100 columns
#25718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10433:
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10434:
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10435:
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10436:
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10437:
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10438:
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10439:
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10440:
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10441:
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10442:
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10443:
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10444:
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10445:
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10446:
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10447:
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10448:
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10449:
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10450:
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10451:
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#25737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10452:
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10453:
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10454:
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10455:
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10456:
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10457:
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10458:
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10459:
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10460:
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10461:
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10462:
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10463:
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10464:
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10465:
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#25751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10466:
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#25752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10467:
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#25753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10468:
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12

WARNING: line length of 114 exceeds 100 columns
#25754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10469:
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#25755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10470:
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14

WARNING: line length of 121 exceeds 100 columns
#25756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10471:
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#25757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10472:
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#25758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10473:
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10474:
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10475:
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#25761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10476:
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L

WARNING: line length of 113 exceeds 100 columns
#25762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10477:
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10478:
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10479:
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10480:
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10481:
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10482:
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10483:
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#25769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10484:
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10485:
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#25771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10486:
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10487:
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#25773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10488:
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3

WARNING: line length of 113 exceeds 100 columns
#25774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10489:
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4

WARNING: line length of 121 exceeds 100 columns
#25775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10490:
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L

WARNING: line length of 121 exceeds 100 columns
#25776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10491:
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10492:
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L

WARNING: line length of 113 exceeds 100 columns
#25778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10493:
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10494:
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10495:
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10496:
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#25782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10497:
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#25783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10498:
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L

WARNING: line length of 113 exceeds 100 columns
#25784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10499:
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10500:
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10501:
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10502:
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10503:
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10504:
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10505:
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10506:
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10507:
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#25793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10508:
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10509:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#25795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10510:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#25796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10511:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#25797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10512:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#25798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10513:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7

WARNING: line length of 113 exceeds 100 columns
#25799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10514:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8

WARNING: line length of 114 exceeds 100 columns
#25800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10515:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#25801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10516:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10517:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10518:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#25804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10519:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#25805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10520:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10521:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#25807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10522:
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#25808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10523:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#25809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10524:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x1

WARNING: line length of 113 exceeds 100 columns
#25810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10525:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#25811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10526:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#25812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10527:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#25813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10528:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc

WARNING: line length of 114 exceeds 100 columns
#25814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10529:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#25815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10530:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10531:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10532:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L

WARNING: line length of 121 exceeds 100 columns
#25818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10533:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#25819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10534:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#25820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10535:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L

WARNING: line length of 121 exceeds 100 columns
#25821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10536:
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L

WARNING: line length of 113 exceeds 100 columns
#25822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10537:
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#25823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10538:
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#25824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10539:
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#25825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10540:
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#25826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10541:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#25827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10542:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#25828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10543:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#25829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10544:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#25830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10545:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#25831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10546:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#25832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10547:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#25833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10548:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#25834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10549:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#25835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10550:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10551:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10552:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10553:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10554:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10555:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#25841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10556:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#25842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10557:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#25843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10558:
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#25844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10559:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd

WARNING: line length of 113 exceeds 100 columns
#25845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10560:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe

WARNING: line length of 113 exceeds 100 columns
#25846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10561:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf

WARNING: line length of 114 exceeds 100 columns
#25847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10562:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#25848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10563:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#25849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10564:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12

WARNING: line length of 114 exceeds 100 columns
#25850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10565:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13

WARNING: line length of 121 exceeds 100 columns
#25851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10566:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10567:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10568:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10569:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10570:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10571:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10572:
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#25858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10573:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#25859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10574:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#25860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10575:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#25861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10576:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#25862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10577:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#25863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10578:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#25864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10579:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#25865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10580:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#25866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10581:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#25867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10582:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10583:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10584:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10585:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10586:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10587:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#25873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10588:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#25874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10589:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#25875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10590:
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#25876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10591:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd

WARNING: line length of 113 exceeds 100 columns
#25877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10592:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe

WARNING: line length of 113 exceeds 100 columns
#25878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10593:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf

WARNING: line length of 114 exceeds 100 columns
#25879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10594:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#25880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10595:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#25881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10596:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12

WARNING: line length of 114 exceeds 100 columns
#25882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10597:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13

WARNING: line length of 121 exceeds 100 columns
#25883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10598:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10599:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10600:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10601:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10602:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10603:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10604:
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#25890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10605:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#25891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10606:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#25892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10607:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#25893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10608:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#25894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10609:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#25895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10610:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#25896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10611:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#25897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10612:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#25898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10613:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#25899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10614:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10615:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10616:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10617:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10618:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10619:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#25905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10620:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#25906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10621:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#25907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10622:
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#25908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10623:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd

WARNING: line length of 113 exceeds 100 columns
#25909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10624:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe

WARNING: line length of 113 exceeds 100 columns
#25910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10625:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf

WARNING: line length of 114 exceeds 100 columns
#25911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10626:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#25912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10627:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#25913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10628:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12

WARNING: line length of 114 exceeds 100 columns
#25914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10629:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13

WARNING: line length of 121 exceeds 100 columns
#25915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10630:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10631:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10632:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10633:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10634:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10635:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10636:
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#25922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10637:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#25923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10638:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#25924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10639:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#25925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10640:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#25926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10641:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#25927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10642:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#25928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10643:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#25929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10644:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#25930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10645:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#25931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10646:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10647:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#25933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10648:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#25934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10649:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#25935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10650:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#25936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10651:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#25937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10652:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#25938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10653:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#25939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10654:
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#25940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10655:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd

WARNING: line length of 113 exceeds 100 columns
#25941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10656:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe

WARNING: line length of 113 exceeds 100 columns
#25942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10657:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf

WARNING: line length of 114 exceeds 100 columns
#25943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10658:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#25944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10659:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#25945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10660:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12

WARNING: line length of 114 exceeds 100 columns
#25946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10661:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13

WARNING: line length of 121 exceeds 100 columns
#25947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10662:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L

WARNING: line length of 121 exceeds 100 columns
#25948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10663:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#25949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10664:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#25950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10665:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#25951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10666:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#25952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10667:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L

WARNING: line length of 121 exceeds 100 columns
#25953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10668:
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#25954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10669:
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0

WARNING: line length of 114 exceeds 100 columns
#25955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10670:
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14

WARNING: line length of 121 exceeds 100 columns
#25956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10671:
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#25957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10672:
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#25958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10673:
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#25959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10674:
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#25960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10675:
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10676:
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10677:
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10678:
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10679:
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10680:
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10681:
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10682:
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10683:
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10684:
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10685:
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10686:
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10687:
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10688:
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10689:
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#25975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10690:
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#25976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10691:
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#25977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10692:
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#25978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10693:
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#25979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10694:
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#25980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10695:
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#25981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10696:
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#25982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10697:
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1

WARNING: line length of 121 exceeds 100 columns
#25983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10698:
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L

WARNING: line length of 113 exceeds 100 columns
#25984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10699:
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#25985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10700:
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L

WARNING: line length of 113 exceeds 100 columns
#25986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10701:
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1

WARNING: line length of 121 exceeds 100 columns
#25987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10702:
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L

WARNING: line length of 113 exceeds 100 columns
#25988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10703:
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#25989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10704:
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL

WARNING: line length of 113 exceeds 100 columns
#25990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10705:
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#25991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10706:
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#25992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10707:
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#25993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10708:
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK                                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#25994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10709:
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#25995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10710:
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#25996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10711:
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#25997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10712:
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#25998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10713:
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#25999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10714:
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10715:
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10716:
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10717:
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10718:
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10719:
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10720:
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10721:
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10722:
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10723:
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10724:
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10725:
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10726:
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10727:
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10728:
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10729:
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#26015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10730:
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#26016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10731:
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#26017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10732:
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#26018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10733:
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#26019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10734:
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#26020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10735:
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#26021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10736:
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#26022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10737:
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#26023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10738:
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#26024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10739:
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#26025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10740:
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#26026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10741:
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#26027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10742:
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#26028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10743:
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#26029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10744:
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#26030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10745:
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10746:
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#26032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10747:
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#26033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10748:
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#26034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10749:
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0

WARNING: line length of 114 exceeds 100 columns
#26035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10750:
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18

WARNING: line length of 121 exceeds 100 columns
#26036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10751:
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL

WARNING: line length of 121 exceeds 100 columns
#26037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10752:
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L

WARNING: line length of 113 exceeds 100 columns
#26038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10753:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#26039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10754:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#26040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10755:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#26041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10756:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L

WARNING: line length of 114 exceeds 100 columns
#26042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10757:
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#26043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10758:
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#26044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10759:
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#26045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10760:
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#26046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10761:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#26047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10762:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#26048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10763:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#26049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10764:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6

WARNING: line length of 113 exceeds 100 columns
#26050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10765:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#26051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10766:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10767:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10768:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#26054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10769:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#26055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10770:
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L

WARNING: line length of 113 exceeds 100 columns
#26056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10771:
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#26057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10772:
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10773:
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10774:
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL

WARNING: line length of 113 exceeds 100 columns
#26060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10775:
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#26061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10776:
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10777:
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#26063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10778:
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#26064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10779:
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#26065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10780:
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L

WARNING: line length of 114 exceeds 100 columns
#26066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10781:
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#26067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10782:
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16

WARNING: line length of 121 exceeds 100 columns
#26068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10783:
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L

WARNING: line length of 121 exceeds 100 columns
#26069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10784:
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L

WARNING: line length of 113 exceeds 100 columns
#26070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10785:
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#26071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10786:
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#26072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10787:
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#26073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10788:
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19

WARNING: line length of 121 exceeds 100 columns
#26074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10789:
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#26075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10790:
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#26076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10791:
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#26077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10792:
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L

WARNING: line length of 113 exceeds 100 columns
#26078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10793:
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10794:
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10795:
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10796:
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10797:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#26083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10798:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#26084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10799:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#26085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10800:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6

WARNING: line length of 121 exceeds 100 columns
#26086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10801:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10802:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#26088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10803:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10804:
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#26090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10805:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#26091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10806:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#26092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10807:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#26093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10808:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#26094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10809:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#26095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10810:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#26096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10811:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10812:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L

WARNING: line length of 121 exceeds 100 columns
#26098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10813:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#26099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10814:
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10815:
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#26101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10816:
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5

WARNING: line length of 113 exceeds 100 columns
#26102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10817:
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#26103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10818:
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa

WARNING: line length of 121 exceeds 100 columns
#26104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10819:
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#26105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10820:
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#26106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10821:
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#26107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10822:
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L

WARNING: line length of 113 exceeds 100 columns
#26108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10823:
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2

WARNING: line length of 113 exceeds 100 columns
#26109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10824:
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#26110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10825:
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10826:
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10827:
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10828:
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4

WARNING: line length of 121 exceeds 100 columns
#26114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10829:
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10830:
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#26116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10831:
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#26117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10832:
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#26118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10833:
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10834:
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#26120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10835:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#26121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10836:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#26122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10837:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#26123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10838:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#26124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10839:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#26125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10840:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#26126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10841:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#26127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10842:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#26128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10843:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#26129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10844:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#26130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10845:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#26131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10846:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#26132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10847:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#26133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10848:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#26134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10849:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#26135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10850:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#26136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10851:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#26137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10852:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#26138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10853:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#26139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10854:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#26140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10855:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#26141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10856:
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#26142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10857:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10858:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#26144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10859:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#26145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10860:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#26146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10861:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#26147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10862:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10863:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10864:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#26150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10865:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#26151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10866:
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#26152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10867:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#26153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10868:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#26154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10869:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#26155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10870:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#26156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10871:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#26157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10872:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#26158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10873:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#26159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10874:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#26160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10875:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#26161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10876:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#26162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10877:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#26163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10878:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#26164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10879:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#26165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10880:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#26166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10881:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#26167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10882:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#26168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10883:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10884:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10885:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10886:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#26172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10887:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#26173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10888:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#26174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10889:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#26175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10890:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#26176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10891:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#26177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10892:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#26178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10893:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#26179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10894:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#26180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10895:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#26181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10896:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#26182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10897:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#26183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10898:
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#26184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10899:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#26185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10900:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#26186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10901:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#26187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10902:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#26188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10903:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#26189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10904:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#26190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10905:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10906:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#26192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10907:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#26193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10908:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#26194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10909:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#26195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10910:
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#26196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10911:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#26197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10912:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#26198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10913:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#26199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10914:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#26200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10915:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10916:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10917:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#26203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10918:
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#26204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10919:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#26205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10920:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#26206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10921:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#26207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10922:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#26208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10923:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#26209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10924:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#26210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10925:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#26211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10926:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#26212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10927:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#26213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10928:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#26214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10929:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#26215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10930:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#26216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10931:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#26217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10932:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#26218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10933:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#26219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10934:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#26220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10935:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#26221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10936:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10937:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10938:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10939:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#26225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10940:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10941:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#26227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10942:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#26228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10943:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#26229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10944:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#26230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10945:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#26231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10946:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#26232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10947:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#26233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10948:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#26234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10949:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#26235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10950:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#26236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10951:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#26237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10952:
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10953:
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#26239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10954:
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10955:
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#26241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10956:
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#26242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10957:
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#26243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10958:
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#26244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10959:
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10960:
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10961:
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10962:
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10963:
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10964:
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10965:
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10966:
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10967:
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10968:
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10969:
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10970:
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10971:
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10972:
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10973:
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10974:
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10975:
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10976:
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10977:
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10978:
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10979:
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10980:
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10981:
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10982:
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10983:
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10984:
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10985:
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10986:
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10987:
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10988:
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10989:
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10990:
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10991:
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10992:
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10993:
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10994:
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10995:
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10996:
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10997:
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10998:
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:10999:
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11000:
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11001:
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11002:
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11003:
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11004:
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11005:
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11006:
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11007:
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11008:
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11009:
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11010:
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#26296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11011:
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#26297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11012:
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0xc

WARNING: line length of 121 exceeds 100 columns
#26298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11013:
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11014:
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11015:
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#26301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11016:
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x0000F000L

WARNING: line length of 113 exceeds 100 columns
#26302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11017:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#26303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11018:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#26304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11019:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#26305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11020:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#26306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11021:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#26307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11022:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#26308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11023:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#26309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11024:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#26310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11025:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#26311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11026:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#26312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11027:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#26313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11028:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#26314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11029:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#26315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11030:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#26316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11031:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#26317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11032:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#26318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11033:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#26319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11034:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#26320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11035:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#26321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11036:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#26322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11037:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#26323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11038:
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#26324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11039:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11040:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#26326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11041:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#26327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11042:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#26328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11043:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#26329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11044:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11045:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11046:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#26332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11047:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#26333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11048:
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#26334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11049:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#26335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11050:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#26336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11051:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#26337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11052:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#26338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11053:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#26339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11054:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#26340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11055:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#26341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11056:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#26342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11057:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#26343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11058:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#26344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11059:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#26345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11060:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#26346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11061:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#26347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11062:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#26348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11063:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#26349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11064:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#26350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11065:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11066:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11067:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11068:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#26354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11069:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#26355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11070:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#26356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11071:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#26357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11072:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#26358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11073:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#26359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11074:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#26360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11075:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#26361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11076:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#26362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11077:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#26363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11078:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#26364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11079:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#26365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11080:
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#26366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11081:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#26367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11082:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#26368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11083:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#26369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11084:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#26370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11085:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#26371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11086:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#26372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11087:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11088:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#26374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11089:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#26375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11090:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#26376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11091:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#26377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11092:
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#26378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11093:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#26379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11094:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#26380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11095:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#26381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11096:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#26382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11097:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11098:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11099:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#26385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11100:
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#26386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11101:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#26387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11102:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#26388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11103:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#26389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11104:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#26390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11105:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#26391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11106:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#26392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11107:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#26393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11108:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#26394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11109:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#26395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11110:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#26396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11111:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#26397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11112:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#26398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11113:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#26399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11114:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#26400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11115:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#26401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11116:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#26402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11117:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#26403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11118:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11119:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11120:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11121:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#26407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11122:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11123:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#26409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11124:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#26410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11125:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#26411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11126:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#26412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11127:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#26413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11128:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#26414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11129:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#26415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11130:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#26416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11131:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#26417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11132:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#26418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11133:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#26419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11134:
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11135:
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#26421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11136:
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11137:
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#26423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11138:
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#26424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11139:
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#26425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11140:
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#26426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11141:
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11142:
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11143:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11144:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11145:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11146:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11147:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11148:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11149:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11150:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11151:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11152:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11153:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11154:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11155:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11156:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11157:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11158:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11159:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11160:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11161:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11162:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11163:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11164:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11165:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11166:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11167:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11168:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11169:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11170:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11171:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11172:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11173:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#26459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11174:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11175:
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#26461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11176:
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4

WARNING: line length of 121 exceeds 100 columns
#26462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11177:
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11178:
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L

WARNING: line length of 113 exceeds 100 columns
#26464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11179:
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#26465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11180:
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#26466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11181:
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#26467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11182:
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11183:
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#26469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11184:
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L

WARNING: line length of 113 exceeds 100 columns
#26470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11185:
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1

WARNING: line length of 121 exceeds 100 columns
#26471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11186:
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L

WARNING: line length of 113 exceeds 100 columns
#26472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11187:
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11188:
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11189:
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#26475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11190:
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#26476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11191:
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#26477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11192:
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6

WARNING: line length of 114 exceeds 100 columns
#26478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11193:
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#26479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11194:
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11

WARNING: line length of 121 exceeds 100 columns
#26480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11195:
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11196:
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#26482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11197:
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11198:
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#26484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11199:
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#26485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11200:
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L

WARNING: line length of 113 exceeds 100 columns
#26486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11201:
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11202:
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#26488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11203:
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#26489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11204:
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6

WARNING: line length of 121 exceeds 100 columns
#26490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11205:
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11206:
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#26492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11207:
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11208:
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#26494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11209:
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#26495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11210:
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#26496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11211:
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5

WARNING: line length of 121 exceeds 100 columns
#26497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11212:
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11213:
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11214:
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L

WARNING: line length of 113 exceeds 100 columns
#26500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11215:
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#26501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11216:
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4

WARNING: line length of 121 exceeds 100 columns
#26502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11217:
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11218:
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#26504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11219:
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1

WARNING: line length of 121 exceeds 100 columns
#26505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11220:
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L

WARNING: line length of 113 exceeds 100 columns
#26506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11221:
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#26507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11222:
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#26508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11223:
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#26509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11224:
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11225:
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#26511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11226:
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#26512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11227:
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11228:
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#26514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11229:
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#26515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11230:
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11231:
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11232:
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L

WARNING: line length of 113 exceeds 100 columns
#26518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11233:
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#26519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11234:
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11235:
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#26521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11236:
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#26522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11237:
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#26523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11238:
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#26524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11239:
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#26525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11240:
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11241:
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11242:
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L

WARNING: line length of 113 exceeds 100 columns
#26528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11243:
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#26529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11244:
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11245:
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11246:
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#26532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11247:
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#26533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11248:
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11249:
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11250:
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L

WARNING: line length of 113 exceeds 100 columns
#26536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11251:
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#26537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11252:
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11253:
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#26539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11254:
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#26540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11255:
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#26541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11256:
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#26542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11257:
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#26543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11258:
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11259:
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11260:
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L

WARNING: line length of 113 exceeds 100 columns
#26546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11261:
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#26547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11262:
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11263:
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#26549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11264:
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#26550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11265:
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#26551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11266:
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc

WARNING: line length of 121 exceeds 100 columns
#26552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11267:
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11268:
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11269:
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L

WARNING: line length of 121 exceeds 100 columns
#26555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11270:
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L

WARNING: line length of 113 exceeds 100 columns
#26556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11271:
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11272:
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11273:
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#26559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11274:
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#26560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11275:
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#26561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11276:
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#26562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11277:
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11278:
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11279:
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11280:
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L

WARNING: line length of 113 exceeds 100 columns
#26566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11281:
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11282:
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11283:
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#26569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11284:
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#26570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11285:
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#26571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11286:
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc

WARNING: line length of 121 exceeds 100 columns
#26572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11287:
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11288:
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11289:
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L

WARNING: line length of 121 exceeds 100 columns
#26575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11290:
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L

WARNING: line length of 113 exceeds 100 columns
#26576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11291:
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#26577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11292:
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11293:
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#26579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11294:
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#26580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11295:
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#26581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11296:
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#26582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11297:
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11298:
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11299:
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#26585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11300:
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L

WARNING: line length of 113 exceeds 100 columns
#26586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11301:
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11302:
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11303:
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#26589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11304:
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#26590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11305:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#26591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11306:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#26592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11307:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6

WARNING: line length of 113 exceeds 100 columns
#26593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11308:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#26594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11309:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#26595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11310:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#26596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11311:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#26597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11312:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe

WARNING: line length of 113 exceeds 100 columns
#26598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11313:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf

WARNING: line length of 114 exceeds 100 columns
#26599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11314:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#26600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11315:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12

WARNING: line length of 114 exceeds 100 columns
#26601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11316:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14

WARNING: line length of 114 exceeds 100 columns
#26602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11317:
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#26603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11318:
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11319:
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11320:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L

WARNING: line length of 121 exceeds 100 columns
#26606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11321:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#26607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11322:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#26608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11323:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#26609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11324:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L

WARNING: line length of 121 exceeds 100 columns
#26610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11325:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#26611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11326:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L

WARNING: line length of 121 exceeds 100 columns
#26612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11327:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#26613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11328:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L

WARNING: line length of 121 exceeds 100 columns
#26614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11329:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#26615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11330:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#26616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11331:
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#26617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11332:
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L

WARNING: line length of 113 exceeds 100 columns
#26618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11333:
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#26619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11334:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#26620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11335:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#26621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11336:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#26622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11337:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#26623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11338:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#26624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11339:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc

WARNING: line length of 121 exceeds 100 columns
#26625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11340:
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11341:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#26627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11342:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11343:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#26629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11344:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#26630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11345:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#26631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11346:
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#26632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11347:
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0

WARNING: line length of 127 exceeds 100 columns
#26633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11348:
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11349:
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#26635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11350:
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11351:
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11352:
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4

WARNING: line length of 121 exceeds 100 columns
#26638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11353:
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L

WARNING: line length of 121 exceeds 100 columns
#26639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11354:
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L

WARNING: line length of 113 exceeds 100 columns
#26640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11355:
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#26641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11356:
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL

WARNING: line length of 113 exceeds 100 columns
#26642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11357:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0

WARNING: line length of 121 exceeds 100 columns
#26643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11358:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11359:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#26645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11360:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10

WARNING: line length of 121 exceeds 100 columns
#26646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11361:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#26647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11362:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L

WARNING: line length of 117 exceeds 100 columns
#26648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11363:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0

WARNING: line length of 123 exceeds 100 columns
#26649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11364:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11365:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0

WARNING: line length of 114 exceeds 100 columns
#26651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11366:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e

WARNING: line length of 114 exceeds 100 columns
#26652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11367:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#26653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11368:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#26654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11369:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L

WARNING: line length of 121 exceeds 100 columns
#26655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11370:
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#26656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11371:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11372:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#26658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11373:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#26659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11374:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa

WARNING: line length of 121 exceeds 100 columns
#26660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11375:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#26661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11376:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#26662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11377:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#26663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11378:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L

WARNING: line length of 113 exceeds 100 columns
#26664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11379:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#26665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11380:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#26666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11381:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#26667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11382:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8

WARNING: line length of 114 exceeds 100 columns
#26668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11383:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10

WARNING: line length of 114 exceeds 100 columns
#26669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11384:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18

WARNING: line length of 121 exceeds 100 columns
#26670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11385:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11386:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#26672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11387:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#26673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11388:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#26674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11389:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#26675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11390:
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11391:
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#26677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11392:
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4

WARNING: line length of 121 exceeds 100 columns
#26678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11393:
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L

WARNING: line length of 121 exceeds 100 columns
#26679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11394:
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L

WARNING: line length of 113 exceeds 100 columns
#26680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11395:
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#26681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11396:
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4

WARNING: line length of 121 exceeds 100 columns
#26682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11397:
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#26683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11398:
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L

WARNING: line length of 113 exceeds 100 columns
#26684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11399:
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11400:
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11401:
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11402:
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11403:
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11404:
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11405:
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11406:
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11407:
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11408:
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11409:
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11410:
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11411:
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11412:
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11413:
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#26699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11414:
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4

WARNING: line length of 121 exceeds 100 columns
#26700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11415:
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#26701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11416:
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L

WARNING: line length of 113 exceeds 100 columns
#26702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11417:
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#26703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11418:
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4

WARNING: line length of 121 exceeds 100 columns
#26704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11419:
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#26705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11420:
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#26706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11421:
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11422:
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11423:
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11424:
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11425:
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11426:
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11427:
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#26713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11428:
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#26714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11429:
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11430:
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11431:
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#26717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11432:
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11433:
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11434:
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11435:
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11436:
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11437:
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11438:
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11439:
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11440:
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11441:
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11442:
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11443:
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11444:
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11445:
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11446:
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11447:
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11448:
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11449:
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11450:
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11451:
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11452:
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11453:
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11454:
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11455:
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11456:
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11457:
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11458:
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11459:
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11460:
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11461:
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11462:
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11463:
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11464:
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#26750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11465:
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11466:
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11467:
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11468:
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11469:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11470:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11471:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11472:
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11473:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11474:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11475:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11476:
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11477:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11478:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11479:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11480:
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11481:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11482:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11483:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11484:
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11485:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11486:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11487:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11488:
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11489:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11490:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11491:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11492:
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11493:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11494:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11495:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11496:
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11497:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#26783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11498:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#26784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11499:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#26785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11500:
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11501:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11502:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#26788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11503:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3

WARNING: line length of 113 exceeds 100 columns
#26789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11504:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#26790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11505:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#26791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11506:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb

WARNING: line length of 113 exceeds 100 columns
#26792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11507:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc

WARNING: line length of 113 exceeds 100 columns
#26793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11508:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#26794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11509:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe

WARNING: line length of 113 exceeds 100 columns
#26795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11510:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf

WARNING: line length of 114 exceeds 100 columns
#26796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11511:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#26797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11512:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11513:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L

WARNING: line length of 121 exceeds 100 columns
#26799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11514:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L

WARNING: line length of 121 exceeds 100 columns
#26800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11515:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L

WARNING: line length of 121 exceeds 100 columns
#26801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11516:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#26802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11517:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L

WARNING: line length of 121 exceeds 100 columns
#26803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11518:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#26804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11519:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#26805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11520:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#26806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11521:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#26807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11522:
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L

WARNING: line length of 113 exceeds 100 columns
#26808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11523:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#26809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11524:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#26810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11525:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#26811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11526:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#26812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11527:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11528:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11529:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11530:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#26816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11531:
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#26817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11532:
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#26818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11533:
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11534:
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#26820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11535:
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11536:
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3

WARNING: line length of 121 exceeds 100 columns
#26822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11537:
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11538:
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L

WARNING: line length of 113 exceeds 100 columns
#26824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11539:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#26825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11540:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1

WARNING: line length of 113 exceeds 100 columns
#26826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11541:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#26827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11542:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#26828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11543:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#26829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11544:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa

WARNING: line length of 121 exceeds 100 columns
#26830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11545:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11546:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11547:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11548:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L

WARNING: line length of 121 exceeds 100 columns
#26834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11549:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L

WARNING: line length of 121 exceeds 100 columns
#26835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11550:
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L

WARNING: line length of 113 exceeds 100 columns
#26836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11551:
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#26837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11552:
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#26838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11553:
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#26839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11554:
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11555:
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#26841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11556:
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11557:
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#26843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11558:
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11559:
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11560:
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11561:
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0

WARNING: line length of 121 exceeds 100 columns
#26847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11562:
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11563:
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#26849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11564:
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11565:
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#26851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11566:
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#26852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11567:
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#26853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11568:
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#26854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11569:
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#26855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11570:
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#26856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11571:
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#26857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11572:
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2

WARNING: line length of 121 exceeds 100 columns
#26858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11573:
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11574:
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L

WARNING: line length of 113 exceeds 100 columns
#26860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11575:
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#26861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11576:
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#26862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11577:
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#26863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11578:
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2

WARNING: line length of 121 exceeds 100 columns
#26864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11579:
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11580:
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L

WARNING: line length of 113 exceeds 100 columns
#26866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11581:
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0

WARNING: line length of 121 exceeds 100 columns
#26867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11582:
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L

WARNING: line length of 113 exceeds 100 columns
#26868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11583:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#26869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11584:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#26870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11585:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#26871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11586:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3

WARNING: line length of 113 exceeds 100 columns
#26872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11587:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#26873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11588:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#26874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11589:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#26875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11590:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc

WARNING: line length of 114 exceeds 100 columns
#26876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11591:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#26877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11592:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11593:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11594:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11595:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#26881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11596:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11597:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#26883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11598:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#26884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11599:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#26885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11600:
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L

WARNING: line length of 113 exceeds 100 columns
#26886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11601:
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#26887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11602:
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#26888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11603:
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#26889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11604:
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11605:
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#26891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11606:
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#26892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11607:
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#26893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11608:
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11609:
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#26895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11610:
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#26896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11611:
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#26897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11612:
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11613:
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#26899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11614:
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#26900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11615:
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#26901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11616:
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11617:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#26903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11618:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#26904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11619:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#26905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11620:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4

WARNING: line length of 114 exceeds 100 columns
#26906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11621:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#26907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11622:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#26908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11623:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#26909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11624:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#26910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11625:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#26911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11626:
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#26912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11627:
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#26913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11628:
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11629:
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#26915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11630:
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11631:
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#26917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11632:
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#26918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11633:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#26919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11634:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#26920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11635:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10

WARNING: line length of 114 exceeds 100 columns
#26921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11636:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12

WARNING: line length of 114 exceeds 100 columns
#26922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11637:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13

WARNING: line length of 114 exceeds 100 columns
#26923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11638:
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#26924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11639:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#26925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11640:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#26926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11641:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#26927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11642:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#26928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11643:
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#26929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11644:
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#26930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11645:
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11646:
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#26932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11647:
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#26933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11648:
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00001F00L

WARNING: line length of 113 exceeds 100 columns
#26934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11649:
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11650:
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#26936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11651:
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#26937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11652:
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00001F00L

WARNING: line length of 113 exceeds 100 columns
#26938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11653:
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11654:
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#26940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11655:
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#26941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11656:
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00001F00L

WARNING: line length of 113 exceeds 100 columns
#26942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11657:
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#26943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11658:
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#26944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11659:
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#26945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11660:
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00001F00L

WARNING: line length of 113 exceeds 100 columns
#26946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11661:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#26947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11662:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#26948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11663:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#26949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11664:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#26950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11665:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#26951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11666:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa

WARNING: line length of 114 exceeds 100 columns
#26952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11667:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#26953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11668:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#26954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11669:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#26955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11670:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#26956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11671:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19

WARNING: line length of 114 exceeds 100 columns
#26957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11672:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT                                               0x1a

WARNING: line length of 121 exceeds 100 columns
#26958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11673:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11674:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#26960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11675:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11676:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#26962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11677:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#26963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11678:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#26964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11679:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#26965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11680:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#26966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11681:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#26967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11682:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#26968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11683:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L

WARNING: line length of 121 exceeds 100 columns
#26969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11684:
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK                                                 0x04000000L

WARNING: line length of 113 exceeds 100 columns
#26970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11685:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#26971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11686:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#26972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11687:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#26973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11688:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#26974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11689:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#26975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11690:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#26976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11691:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#26977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11692:
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#26978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11693:
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#26979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11694:
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#26980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11695:
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#26981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11696:
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#26982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11697:
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#26983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11698:
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#26984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11699:
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#26985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11700:
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#26986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11701:
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#26987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11702:
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe

WARNING: line length of 121 exceeds 100 columns
#26988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11703:
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#26989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11704:
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#26990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11705:
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L

WARNING: line length of 121 exceeds 100 columns
#26991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11706:
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK                                                  0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#26992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11707:
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L

WARNING: line length of 121 exceeds 100 columns
#26993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11708:
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#26994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11709:
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L

WARNING: line length of 121 exceeds 100 columns
#26995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11710:
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L

WARNING: line length of 113 exceeds 100 columns
#26996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11711:
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#26997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11712:
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#26998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11713:
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#26999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11714:
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11715:
+#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#27001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11716:
+#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#27002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11717:
+#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH__SHIFT                                                           0xc

WARNING: line length of 114 exceeds 100 columns
#27003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11718:
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#27004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11719:
+#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE__SHIFT                               0x1b

WARNING: line length of 114 exceeds 100 columns
#27005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11720:
+#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#27006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11721:
+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE__SHIFT                                     0x1d

WARNING: line length of 114 exceeds 100 columns
#27007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11722:
+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE__SHIFT                                         0x1e

WARNING: line length of 114 exceeds 100 columns
#27008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11723:
+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE__SHIFT                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#27009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11724:
+#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH_MASK                                                            0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#27010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11725:
+#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH_MASK                                                         0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#27011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11726:
+#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH_MASK                                                             0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#27012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11727:
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                                                 0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#27013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11728:
+#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE_MASK                                 0x08000000L

WARNING: line length of 121 exceeds 100 columns
#27014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11729:
+#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE_MASK                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#27015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11730:
+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE_MASK                                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#27016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11731:
+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE_MASK                                           0x40000000L

WARNING: line length of 121 exceeds 100 columns
#27017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11732:
+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE_MASK                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11733:
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#27019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11734:
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xa

WARNING: line length of 114 exceeds 100 columns
#27020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11735:
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT                   0x16

WARNING: line length of 121 exceeds 100 columns
#27021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11736:
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#27022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11737:
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x0007FC00L

WARNING: line length of 121 exceeds 100 columns
#27023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11738:
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK                     0x7FC00000L

WARNING: line length of 113 exceeds 100 columns
#27024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11739:
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#27025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11740:
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11741:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#27027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11742:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#27028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11743:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT                                          0xc

WARNING: line length of 121 exceeds 100 columns
#27029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11744:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#27030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11745:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11746:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK                                            0x0000F000L

WARNING: line length of 113 exceeds 100 columns
#27032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11747:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#27033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11748:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#27034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11749:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4

WARNING: line length of 113 exceeds 100 columns
#27035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11750:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5

WARNING: line length of 113 exceeds 100 columns
#27036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11751:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#27037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11752:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#27038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11753:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE__SHIFT                0x11

WARNING: line length of 114 exceeds 100 columns
#27039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11754:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY__SHIFT                0x12

WARNING: line length of 114 exceeds 100 columns
#27040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11755:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS__SHIFT                        0x18

WARNING: line length of 121 exceeds 100 columns
#27041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11756:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11757:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11758:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#27044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11759:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#27045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11760:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#27046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11761:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE_MASK                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#27047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11762:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE_MASK                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#27048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11763:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY_MASK                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#27049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11764:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS_MASK                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#27050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11765:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#27051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11766:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11767:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11768:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11769:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11770:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11771:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11772:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_MASK           0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11773:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11774:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11775:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11776:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_MASK             0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11777:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#27063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11778:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11779:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#27065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11780:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11781:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#27067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11782:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11783:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11784:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11785:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11786:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11787:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11788:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_MASK           0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11789:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11790:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11791:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11792:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_MASK             0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11793:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#27079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11794:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11795:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#27081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11796:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11797:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#27083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11798:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11799:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11800:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11801:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11802:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11803:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11804:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_MASK           0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11805:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11806:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11807:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11808:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_MASK             0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11809:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#27095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11810:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11811:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#27097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11812:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11813:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#27099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11814:
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11815:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11816:
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#27102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11817:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11818:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11819:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11820:
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_MASK           0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11821:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11822:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11823:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11824:
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_MASK             0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#27110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11825:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#27111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11826:
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11827:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#27113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11828:
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#27114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11829:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#27115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11830:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT                                    0x1

WARNING: line length of 113 exceeds 100 columns
#27116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11831:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT                                                       0x3

WARNING: line length of 113 exceeds 100 columns
#27117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11832:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#27118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11833:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#27119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11834:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#27120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11835:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT                                         0x7

WARNING: line length of 113 exceeds 100 columns
#27121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11836:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#27122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11837:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#27123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11838:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#27124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11839:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#27125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11840:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11841:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11842:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#27128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11843:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#27129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11844:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#27130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11845:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#27131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11846:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK                                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#27132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11847:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#27133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11848:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#27134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11849:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK                                                             0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#27135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11850:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#27136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11851:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#27137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11852:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4

WARNING: line length of 113 exceeds 100 columns
#27138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11853:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5

WARNING: line length of 113 exceeds 100 columns
#27139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11854:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8

WARNING: line length of 114 exceeds 100 columns
#27140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11855:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8__SHIFT                    0x10

WARNING: line length of 121 exceeds 100 columns
#27141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11856:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#27142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11857:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#27143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11858:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#27144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11859:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11860:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8_MASK                      0x00010000L

WARNING: line length of 113 exceeds 100 columns
#27146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11861:
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#27147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11862:
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#27148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11863:
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#27149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11864:
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#27150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11865:
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#27151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11866:
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#27152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11867:
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#27153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11868:
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#27154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11869:
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#27155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11870:
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11871:
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11872:
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#27158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11873:
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#27159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11874:
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11875:
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#27161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11876:
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11877:
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11878:
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#27164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11879:
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#27165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11880:
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11881:
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#27167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11882:
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11883:
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11884:
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#27170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11885:
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#27171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11886:
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11887:
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#27173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11888:
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11889:
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11890:
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#27176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11891:
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#27177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11892:
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11893:
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11894:
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#27180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11895:
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#27181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11896:
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#27182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11897:
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#27183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11898:
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11899:
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11900:
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#27186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11901:
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#27187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11902:
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#27188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11903:
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#27189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11904:
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11905:
+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11906:
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#27192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11907:
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#27193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11908:
+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#27194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11909:
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#27195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11910:
+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11911:
+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#27197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11912:
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#27198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11913:
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#27199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11914:
+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#27200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11915:
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#27201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11916:
+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11917:
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#27203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11918:
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#27204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11919:
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4

WARNING: line length of 121 exceeds 100 columns
#27205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11920:
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11921:
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11922:
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#27208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11923:
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#27209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11924:
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5

WARNING: line length of 113 exceeds 100 columns
#27210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11925:
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#27211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11926:
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x7

WARNING: line length of 121 exceeds 100 columns
#27212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11927:
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#27213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11928:
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#27214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11929:
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#27215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11930:
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK                                                       0x00000080L

WARNING: line length of 113 exceeds 100 columns
#27216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11931:
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#27217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11932:
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4

WARNING: line length of 114 exceeds 100 columns
#27218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11933:
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#27219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11934:
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#27220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11935:
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#27221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11936:
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11937:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#27223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11938:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1

WARNING: line length of 113 exceeds 100 columns
#27224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11939:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#27225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11940:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3

WARNING: line length of 113 exceeds 100 columns
#27226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11941:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#27227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11942:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa

WARNING: line length of 113 exceeds 100 columns
#27228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11943:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb

WARNING: line length of 121 exceeds 100 columns
#27229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11944:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11945:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11946:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11947:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L

WARNING: line length of 121 exceeds 100 columns
#27233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11948:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L

WARNING: line length of 121 exceeds 100 columns
#27234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11949:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#27235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11950:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x003FF800L

WARNING: line length of 113 exceeds 100 columns
#27236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11951:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#27237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11952:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1

WARNING: line length of 113 exceeds 100 columns
#27238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11953:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#27239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11954:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc

WARNING: line length of 114 exceeds 100 columns
#27240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11955:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x14

WARNING: line length of 114 exceeds 100 columns
#27241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11956:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#27242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11957:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11958:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#27244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11959:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#27245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11960:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L

WARNING: line length of 121 exceeds 100 columns
#27246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11961:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF00000L

WARNING: line length of 121 exceeds 100 columns
#27247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11962:
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11963:
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#27249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11964:
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#27250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11965:
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#27251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11966:
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#27252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11967:
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3

WARNING: line length of 114 exceeds 100 columns
#27253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11968:
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#27254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11969:
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11970:
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11971:
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#27257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11972:
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11973:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#27259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11974:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6

WARNING: line length of 121 exceeds 100 columns
#27260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11975:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#27261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11976:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L

WARNING: line length of 113 exceeds 100 columns
#27262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11977:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#27263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11978:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b

WARNING: line length of 114 exceeds 100 columns
#27264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11979:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#27265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11980:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#27266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11981:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L

WARNING: line length of 121 exceeds 100 columns
#27267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11982:
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#27268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11983:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#27269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11984:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1

WARNING: line length of 113 exceeds 100 columns
#27270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11985:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#27271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11986:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3

WARNING: line length of 121 exceeds 100 columns
#27272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11987:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11988:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11989:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11990:
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L

WARNING: line length of 113 exceeds 100 columns
#27276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11991:
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#27277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11992:
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#27278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11993:
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#27279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11994:
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#27280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11995:
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6

WARNING: line length of 113 exceeds 100 columns
#27281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11996:
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7

WARNING: line length of 113 exceeds 100 columns
#27282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11997:
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9

WARNING: line length of 113 exceeds 100 columns
#27283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11998:
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#27284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:11999:
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd

WARNING: line length of 114 exceeds 100 columns
#27285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12000:
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11

WARNING: line length of 114 exceeds 100 columns
#27286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12001:
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#27287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12002:
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b

WARNING: line length of 121 exceeds 100 columns
#27288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12003:
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12004:
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12005:
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#27291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12006:
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#27292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12007:
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#27293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12008:
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L

WARNING: line length of 121 exceeds 100 columns
#27294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12009:
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L

WARNING: line length of 121 exceeds 100 columns
#27295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12010:
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#27296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12011:
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L

WARNING: line length of 121 exceeds 100 columns
#27297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12012:
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L

WARNING: line length of 121 exceeds 100 columns
#27298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12013:
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L

WARNING: line length of 121 exceeds 100 columns
#27299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12014:
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L

WARNING: line length of 113 exceeds 100 columns
#27300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12015:
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#27301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12016:
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK                                             0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#27302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12017:
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#27303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12018:
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12019:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#27305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12020:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#27306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12021:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#27307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12022:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#27308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12023:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#27309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12024:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#27310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12025:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#27311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12026:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#27312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12027:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#27313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12028:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#27314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12029:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#27315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12030:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#27316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12031:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#27317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12032:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#27318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12033:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#27319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12034:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#27320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12035:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#27321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12036:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#27322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12037:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#27323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12038:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#27324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12039:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#27325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12040:
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#27326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12041:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#27327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12042:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#27328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12043:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#27329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12044:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#27330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12045:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#27331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12046:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#27332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12047:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12048:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#27334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12049:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#27335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12050:
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#27336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12051:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#27337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12052:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#27338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12053:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#27339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12054:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#27340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12055:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#27341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12056:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#27342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12057:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#27343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12058:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#27344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12059:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#27345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12060:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#27346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12061:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#27347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12062:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#27348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12063:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#27349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12064:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#27350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12065:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#27351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12066:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#27352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12067:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#27353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12068:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12069:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#27355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12070:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#27356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12071:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#27357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12072:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#27358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12073:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#27359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12074:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#27360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12075:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#27361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12076:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#27362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12077:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#27363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12078:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#27364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12079:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#27365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12080:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#27366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12081:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#27367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12082:
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#27368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12083:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#27369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12084:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#27370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12085:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#27371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12086:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#27372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12087:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#27373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12088:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#27374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12089:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#27375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12090:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#27376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12091:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#27377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12092:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#27378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12093:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#27379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12094:
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12095:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#27381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12096:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#27382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12097:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#27383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12098:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#27384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12099:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12100:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12101:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#27387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12102:
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#27388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12103:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#27389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12104:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#27390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12105:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#27391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12106:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#27392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12107:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#27393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12108:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#27394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12109:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#27395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12110:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#27396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12111:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#27397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12112:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#27398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12113:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#27399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12114:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#27400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12115:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#27401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12116:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#27402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12117:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#27403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12118:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#27404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12119:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#27405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12120:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12121:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12122:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12123:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#27409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12124:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#27410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12125:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#27411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12126:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#27412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12127:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#27413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12128:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12129:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#27415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12130:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#27416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12131:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#27417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12132:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#27418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12133:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#27419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12134:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#27420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12135:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#27421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12136:
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#27422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12137:
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#27423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12138:
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12139:
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#27425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12140:
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#27426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12141:
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#27427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12142:
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#27428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12143:
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#27429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12144:
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12145:
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12146:
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12147:
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12148:
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12149:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12150:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12151:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12152:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12153:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12154:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12155:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12156:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12157:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12158:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12159:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12160:
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12161:
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12162:
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12163:
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12164:
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12165:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12166:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12167:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12168:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12169:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12170:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12171:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12172:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12173:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12174:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12175:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12176:
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12177:
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12178:
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12179:
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12180:
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12181:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12182:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12183:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12184:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12185:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12186:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12187:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12188:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12189:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12190:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12191:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12192:
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12193:
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12194:
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12195:
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12196:
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12197:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12198:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12199:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12200:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12201:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12202:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12203:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12204:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12205:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12206:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12207:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12208:
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12209:
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12210:
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12211:
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12212:
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12213:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12214:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12215:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12216:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12217:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12218:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12219:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12220:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12221:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12222:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12223:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12224:
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12225:
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12226:
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12227:
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12228:
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12229:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12230:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12231:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12232:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12233:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12234:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12235:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12236:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12237:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12238:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12239:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12240:
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12241:
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12242:
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12243:
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12244:
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12245:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12246:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12247:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12248:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12249:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12250:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12251:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12252:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12253:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12254:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12255:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12256:
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12257:
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12258:
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12259:
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12260:
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12261:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12262:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12263:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12264:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12265:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12266:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12267:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12268:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12269:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12270:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12271:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12272:
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12273:
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12274:
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12275:
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12276:
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12277:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12278:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12279:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12280:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12281:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12282:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12283:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12284:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12285:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12286:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12287:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12288:
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12289:
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#27575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12290:
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3

WARNING: line length of 121 exceeds 100 columns
#27576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12291:
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12292:
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12293:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12294:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12295:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#27581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12296:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12297:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#27583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12298:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12299:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0

WARNING: line length of 121 exceeds 100 columns
#27585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12300:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12301:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0

WARNING: line length of 121 exceeds 100 columns
#27587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12302:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12303:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12304:
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12305:
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#27591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12306:
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3

WARNING: line length of 121 exceeds 100 columns
#27592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12307:
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12308:
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12309:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12310:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12311:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12312:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12313:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#27599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12314:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12315:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12316:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12317:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#27603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12318:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12319:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12320:
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12321:
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#27607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12322:
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3

WARNING: line length of 121 exceeds 100 columns
#27608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12323:
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12324:
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12325:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12326:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12327:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12328:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12329:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#27615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12330:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12331:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12332:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12333:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#27619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12334:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12335:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12336:
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12337:
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#27623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12338:
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3

WARNING: line length of 121 exceeds 100 columns
#27624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12339:
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12340:
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12341:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12342:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12343:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12344:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12345:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#27631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12346:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12347:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12348:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12349:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#27635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12350:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12351:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12352:
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12353:
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#27639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12354:
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3

WARNING: line length of 121 exceeds 100 columns
#27640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12355:
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12356:
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12357:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12358:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12359:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12360:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12361:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#27647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12362:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12363:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12364:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12365:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#27651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12366:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12367:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12368:
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12369:
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#27655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12370:
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3

WARNING: line length of 121 exceeds 100 columns
#27656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12371:
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12372:
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12373:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12374:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12375:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12376:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12377:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#27663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12378:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12379:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12380:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12381:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#27667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12382:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12383:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12384:
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12385:
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#27671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12386:
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3

WARNING: line length of 121 exceeds 100 columns
#27672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12387:
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L

WARNING: line length of 121 exceeds 100 columns
#27673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12388:
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L

WARNING: line length of 113 exceeds 100 columns
#27674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12389:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12390:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12391:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12392:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12393:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#27679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12394:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12395:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12396:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12397:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#27683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12398:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12399:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12400:
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12401:
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#27687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12402:
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#27688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12403:
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d

WARNING: line length of 121 exceeds 100 columns
#27689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12404:
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#27690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12405:
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#27691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12406:
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L

WARNING: line length of 113 exceeds 100 columns
#27692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12407:
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#27693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12408:
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12409:
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#27695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12410:
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#27696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12411:
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#27697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12412:
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#27698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12413:
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9

WARNING: line length of 121 exceeds 100 columns
#27699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12414:
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12415:
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12416:
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12417:
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12418:
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L

WARNING: line length of 113 exceeds 100 columns
#27704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12419:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#27705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12420:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#27706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12421:
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14

WARNING: line length of 114 exceeds 100 columns
#27707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12422:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#27708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12423:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#27709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12424:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#27710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12425:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#27711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12426:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#27712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12427:
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#27713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12428:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#27714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12429:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L

WARNING: line length of 121 exceeds 100 columns
#27715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12430:
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12431:
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#27717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12432:
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12433:
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#27719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12434:
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12435:
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#27721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12436:
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#27722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12437:
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa

WARNING: line length of 113 exceeds 100 columns
#27723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12438:
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb

WARNING: line length of 121 exceeds 100 columns
#27724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12439:
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#27725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12440:
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L

WARNING: line length of 121 exceeds 100 columns
#27726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12441:
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L

WARNING: line length of 121 exceeds 100 columns
#27727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12442:
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L

WARNING: line length of 113 exceeds 100 columns
#27728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12443:
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#27729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12444:
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6

WARNING: line length of 113 exceeds 100 columns
#27730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12445:
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc

WARNING: line length of 114 exceeds 100 columns
#27731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12446:
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#27732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12447:
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#27733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12448:
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#27734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12449:
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#27735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12450:
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L

WARNING: line length of 113 exceeds 100 columns
#27736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12451:
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#27737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12452:
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#27738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12453:
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#27739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12454:
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#27740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12455:
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#27741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12456:
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#27742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12457:
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#27743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12458:
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L

WARNING: line length of 113 exceeds 100 columns
#27744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12459:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#27745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12460:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#27746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12461:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12462:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12463:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#27749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12464:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#27750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12465:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12466:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12467:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#27753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12468:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#27754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12469:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12470:
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12471:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#27757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12472:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#27758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12473:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12474:
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12475:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#27761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12476:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#27762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12477:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12478:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12479:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#27765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12480:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#27766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12481:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12482:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12483:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#27769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12484:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#27770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12485:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12486:
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12487:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#27773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12488:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#27774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12489:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12490:
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12491:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#27777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12492:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#27778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12493:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#27779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12494:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb

WARNING: line length of 114 exceeds 100 columns
#27780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12495:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#27781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12496:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#27782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12497:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#27783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12498:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#27784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12499:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#27785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12500:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L

WARNING: line length of 121 exceeds 100 columns
#27786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12501:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L

WARNING: line length of 121 exceeds 100 columns
#27787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12502:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L

WARNING: line length of 121 exceeds 100 columns
#27788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12503:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#27789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12504:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#27790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12505:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L

WARNING: line length of 121 exceeds 100 columns
#27791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12506:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L

WARNING: line length of 113 exceeds 100 columns
#27792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12507:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#27793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12508:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#27794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12509:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#27795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12510:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb

WARNING: line length of 114 exceeds 100 columns
#27796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12511:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#27797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12512:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#27798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12513:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14

WARNING: line length of 121 exceeds 100 columns
#27799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12514:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#27800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12515:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#27801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12516:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L

WARNING: line length of 121 exceeds 100 columns
#27802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12517:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L

WARNING: line length of 121 exceeds 100 columns
#27803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12518:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#27804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12519:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#27805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12520:
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L

WARNING: line length of 113 exceeds 100 columns
#27806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12521:
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#27807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12522:
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#27808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12523:
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#27809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12524:
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3

WARNING: line length of 113 exceeds 100 columns
#27810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12525:
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4

WARNING: line length of 113 exceeds 100 columns
#27811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12526:
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#27812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12527:
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#27813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12528:
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#27814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12529:
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#27815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12530:
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#27816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12531:
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd

WARNING: line length of 114 exceeds 100 columns
#27817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12532:
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#27818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12533:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#27819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12534:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#27820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12535:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#27821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12536:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#27822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12537:
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c

WARNING: line length of 114 exceeds 100 columns
#27823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12538:
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#27824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12539:
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12540:
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12541:
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12542:
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#27828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12543:
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#27829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12544:
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12545:
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#27831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12546:
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#27832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12547:
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#27833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12548:
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#27834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12549:
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#27835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12550:
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#27836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12551:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#27837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12552:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#27838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12553:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#27839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12554:
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#27840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12555:
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L

WARNING: line length of 121 exceeds 100 columns
#27841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12556:
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#27842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12557:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#27843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12558:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#27844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12559:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#27845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12560:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#27846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12561:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#27847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12562:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#27848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12563:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#27849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12564:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#27850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12565:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#27851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12566:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#27852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12567:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12568:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#27854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12569:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12570:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#27856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12571:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#27857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12572:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#27858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12573:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#27859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12574:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#27860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12575:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#27861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12576:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#27862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12577:
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#27863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12578:
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#27864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12579:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#27865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12580:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#27866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12581:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#27867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12582:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#27868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12583:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#27869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12584:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12585:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#27871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12586:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#27872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12587:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L

WARNING: line length of 121 exceeds 100 columns
#27873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12588:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#27874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12589:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#27875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12590:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#27876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12591:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#27877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12592:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#27878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12593:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14

WARNING: line length of 121 exceeds 100 columns
#27879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12594:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12595:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12596:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#27882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12597:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#27883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12598:
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L

WARNING: line length of 113 exceeds 100 columns
#27884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12599:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#27885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12600:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#27886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12601:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12602:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12603:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#27889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12604:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#27890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12605:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#27891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12606:
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#27892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12607:
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#27893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12608:
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#27894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12609:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#27895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12610:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12611:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#27897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12612:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12613:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#27899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12614:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12615:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12616:
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12617:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#27903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12618:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12619:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12620:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12621:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#27907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12622:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12623:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12624:
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12625:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#27911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12626:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12627:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#27913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12628:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12629:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12630:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12631:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12632:
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12633:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#27919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12634:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12635:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#27921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12636:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12637:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#27923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12638:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#27924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12639:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#27925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12640:
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#27926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12641:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#27927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12642:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#27928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12643:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#27929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12644:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#27930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12645:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#27931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12646:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#27932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12647:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#27933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12648:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#27934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12649:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc

WARNING: line length of 113 exceeds 100 columns
#27935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12650:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd

WARNING: line length of 114 exceeds 100 columns
#27936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12651:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#27937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12652:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#27938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12653:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#27939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12654:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13

WARNING: line length of 121 exceeds 100 columns
#27940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12655:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12656:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12657:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#27943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12658:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#27944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12659:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#27945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12660:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12661:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#27947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12662:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#27948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12663:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#27949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12664:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L

WARNING: line length of 121 exceeds 100 columns
#27950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12665:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#27951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12666:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#27952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12667:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#27953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12668:
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#27954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12669:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#27955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12670:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1

WARNING: line length of 113 exceeds 100 columns
#27956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12671:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#27957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12672:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#27958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12673:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9

WARNING: line length of 113 exceeds 100 columns
#27959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12674:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#27960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12675:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#27961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12676:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11

WARNING: line length of 114 exceeds 100 columns
#27962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12677:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#27963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12678:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14

WARNING: line length of 121 exceeds 100 columns
#27964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12679:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12680:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12681:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#27967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12682:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12683:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#27969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12684:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#27970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12685:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#27971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12686:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L

WARNING: line length of 121 exceeds 100 columns
#27972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12687:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#27973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12688:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#27974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12689:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#27975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12690:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#27976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12691:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#27977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12692:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#27978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12693:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc

WARNING: line length of 121 exceeds 100 columns
#27979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12694:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#27980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12695:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12696:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#27982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12697:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#27983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12698:
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L

WARNING: line length of 113 exceeds 100 columns
#27984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12699:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#27985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12700:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#27986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12701:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2

WARNING: line length of 113 exceeds 100 columns
#27987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12702:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3

WARNING: line length of 113 exceeds 100 columns
#27988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12703:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#27989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12704:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9

WARNING: line length of 114 exceeds 100 columns
#27990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12705:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#27991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12706:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#27992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12707:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12

WARNING: line length of 114 exceeds 100 columns
#27993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12708:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13

WARNING: line length of 121 exceeds 100 columns
#27994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12709:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#27995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12710:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#27996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12711:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#27997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12712:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#27998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12713:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#27999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12714:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12715:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#28001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12716:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#28002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12717:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#28003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12718:
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L

WARNING: line length of 113 exceeds 100 columns
#28004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12719:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#28005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12720:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12721:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#28007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12722:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#28008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12723:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12724:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12725:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12726:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12727:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#28013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12728:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#28014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12729:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12730:
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12731:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#28017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12732:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12733:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#28019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12734:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c

WARNING: line length of 121 exceeds 100 columns
#28020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12735:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12736:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12737:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#28023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12738:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12739:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#28025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12740:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c

WARNING: line length of 121 exceeds 100 columns
#28026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12741:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12742:
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12743:
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#28029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12744:
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#28030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12745:
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#28031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12746:
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#28032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12747:
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12748:
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#28034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12749:
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L

WARNING: line length of 121 exceeds 100 columns
#28035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12750:
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#28036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12751:
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#28037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12752:
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#28038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12753:
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12754:
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12755:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#28041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12756:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18

WARNING: line length of 114 exceeds 100 columns
#28042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12757:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#28043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12758:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b

WARNING: line length of 114 exceeds 100 columns
#28044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12759:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c

WARNING: line length of 121 exceeds 100 columns
#28045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12760:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#28046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12761:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#28047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12762:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#28048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12763:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#28049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12764:
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12765:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#28051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12766:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#28052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12767:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#28053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12768:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12769:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12770:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12771:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#28057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12772:
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12773:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#28059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12774:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#28060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12775:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#28061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12776:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12777:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12778:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12779:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#28065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12780:
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12781:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#28067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12782:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#28068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12783:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#28069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12784:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12785:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12786:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12787:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12788:
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12789:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#28075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12790:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#28076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12791:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#28077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12792:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12793:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12794:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12795:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12796:
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12797:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#28083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12798:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#28084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12799:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#28085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12800:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18

WARNING: line length of 114 exceeds 100 columns
#28086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12801:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#28087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12802:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#28088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12803:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#28089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12804:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12805:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#28091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12806:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#28092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12807:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#28093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12808:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#28094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12809:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#28095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12810:
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#28096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12811:
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#28097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12812:
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12813:
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#28099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12814:
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12815:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#28101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12816:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#28102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12817:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#28103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12818:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6

WARNING: line length of 121 exceeds 100 columns
#28104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12819:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12820:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L

WARNING: line length of 121 exceeds 100 columns
#28106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12821:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#28107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12822:
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L

WARNING: line length of 113 exceeds 100 columns
#28108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12823:
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#28109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12824:
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#28110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12825:
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12826:
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12827:
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#28113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12828:
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#28114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12829:
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#28115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12830:
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12831:
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#28117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12832:
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#28118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12833:
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12834:
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L

WARNING: line length of 113 exceeds 100 columns
#28120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12835:
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#28121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12836:
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#28122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12837:
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12838:
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#28124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12839:
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#28125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12840:
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12841:
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#28127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12842:
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#28128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12843:
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#28129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12844:
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#28130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12845:
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#28131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12846:
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12847:
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#28133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12848:
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12849:
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#28135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12850:
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12851:
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#28137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12852:
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12853:
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#28139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12854:
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#28140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12855:
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#28141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12856:
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#28142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12857:
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#28143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12858:
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12859:
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12860:
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12861:
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#28147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12862:
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12863:
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#28149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12864:
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12865:
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#28151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12866:
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12867:
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#28153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12868:
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12869:
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12870:
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12871:
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#28157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12872:
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12873:
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12874:
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12875:
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#28161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12876:
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12877:
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#28163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12878:
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10

WARNING: line length of 121 exceeds 100 columns
#28164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12879:
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12880:
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12881:
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#28167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12882:
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#28168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12883:
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12884:
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12885:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#28171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12886:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#28172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12887:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#28173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12888:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#28174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12889:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#28175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12890:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#28176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12891:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#28177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12892:
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L

WARNING: line length of 113 exceeds 100 columns
#28178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12893:
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12894:
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12895:
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#28181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12896:
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#28182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12897:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#28183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12898:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#28184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12899:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#28185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12900:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6

WARNING: line length of 113 exceeds 100 columns
#28186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12901:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#28187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12902:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#28188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12903:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#28189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12904:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe

WARNING: line length of 121 exceeds 100 columns
#28190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12905:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12906:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12907:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#28193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12908:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#28194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12909:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#28195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12910:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12911:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L

WARNING: line length of 121 exceeds 100 columns
#28197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12912:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L

WARNING: line length of 113 exceeds 100 columns
#28198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12913:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#28199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12914:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#28200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12915:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#28201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12916:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6

WARNING: line length of 121 exceeds 100 columns
#28202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12917:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12918:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#28204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12919:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#28205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12920:
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#28206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12921:
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12922:
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12923:
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#28209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12924:
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12925:
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#28211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12926:
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12927:
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#28213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12928:
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12929:
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#28215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12930:
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12931:
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12932:
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12933:
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#28219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12934:
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf

WARNING: line length of 114 exceeds 100 columns
#28220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12935:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#28221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12936:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#28222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12937:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#28223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12938:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#28224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12939:
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#28225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12940:
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L

WARNING: line length of 121 exceeds 100 columns
#28226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12941:
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L

WARNING: line length of 121 exceeds 100 columns
#28227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12942:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#28228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12943:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#28229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12944:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#28230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12945:
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#28231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12946:
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#28232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12947:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#28233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12948:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa

WARNING: line length of 114 exceeds 100 columns
#28234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12949:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#28235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12950:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#28236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12951:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#28237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12952:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#28238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12953:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12954:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L

WARNING: line length of 121 exceeds 100 columns
#28240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12955:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#28241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12956:
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L

WARNING: line length of 113 exceeds 100 columns
#28242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12957:
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#28243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12958:
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#28244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12959:
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#28245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12960:
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L

WARNING: line length of 113 exceeds 100 columns
#28246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12961:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#28247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12962:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12963:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#28249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12964:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#28250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12965:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12966:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#28252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12967:
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#28253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12968:
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#28254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12969:
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12970:
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12971:
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#28257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12972:
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#28258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12973:
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12974:
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12975:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#28261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12976:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#28262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12977:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#28263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12978:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#28264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12979:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#28265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12980:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#28266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12981:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#28267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12982:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#28268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12983:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#28269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12984:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc

WARNING: line length of 113 exceeds 100 columns
#28270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12985:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd

WARNING: line length of 113 exceeds 100 columns
#28271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12986:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#28272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12987:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#28273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12988:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#28274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12989:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12

WARNING: line length of 121 exceeds 100 columns
#28275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12990:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12991:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12992:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12993:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#28279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12994:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#28280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12995:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#28281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12996:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12997:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12998:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:12999:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#28285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13000:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#28286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13001:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#28287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13002:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#28288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13003:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#28289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13004:
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L

WARNING: line length of 113 exceeds 100 columns
#28290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13005:
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#28291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13006:
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#28292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13007:
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13008:
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13009:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#28295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13010:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#28296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13011:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5

WARNING: line length of 113 exceeds 100 columns
#28297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13012:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#28298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13013:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa

WARNING: line length of 121 exceeds 100 columns
#28299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13014:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13015:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#28301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13016:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#28302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13017:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13018:
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L

WARNING: line length of 113 exceeds 100 columns
#28304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13019:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#28305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13020:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#28306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13021:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#28307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13022:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#28308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13023:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc

WARNING: line length of 114 exceeds 100 columns
#28309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13024:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#28310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13025:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#28311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13026:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#28312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13027:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#28313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13028:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#28314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13029:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13030:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13031:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#28317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13032:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#28318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13033:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#28319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13034:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#28320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13035:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#28321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13036:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#28322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13037:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#28323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13038:
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#28324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13039:
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13040:
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13041:
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#28327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13042:
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13043:
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#28329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13044:
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#28330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13045:
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#28331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13046:
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#28332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13047:
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#28333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13048:
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#28334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13049:
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13050:
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13051:
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#28337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13052:
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#28338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13053:
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#28339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13054:
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#28340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13055:
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#28341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13056:
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4

WARNING: line length of 114 exceeds 100 columns
#28342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13057:
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12

WARNING: line length of 121 exceeds 100 columns
#28343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13058:
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13059:
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L

WARNING: line length of 121 exceeds 100 columns
#28345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13060:
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L

WARNING: line length of 113 exceeds 100 columns
#28346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13061:
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#28347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13062:
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#28348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13063:
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#28349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13064:
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#28350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13065:
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#28351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13066:
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13067:
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13068:
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#28354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13069:
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13070:
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L

WARNING: line length of 113 exceeds 100 columns
#28356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13071:
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#28357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13072:
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#28358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13073:
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13074:
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L

WARNING: line length of 113 exceeds 100 columns
#28360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13075:
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#28361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13076:
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13077:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#28363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13078:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#28364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13079:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2

WARNING: line length of 114 exceeds 100 columns
#28365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13080:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#28366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13081:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13082:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13083:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13084:
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13085:
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#28371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13086:
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4

WARNING: line length of 114 exceeds 100 columns
#28372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13087:
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#28373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13088:
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13089:
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#28375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13090:
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#28376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13091:
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#28377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13092:
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#28378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13093:
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#28379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13094:
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13095:
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13096:
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#28382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13097:
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#28383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13098:
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1

WARNING: line length of 114 exceeds 100 columns
#28384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13099:
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#28385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13100:
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13101:
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13102:
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13103:
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13104:
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13105:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#28391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13106:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#28392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13107:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#28393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13108:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#28394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13109:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#28395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13110:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#28396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13111:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#28397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13112:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#28398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13113:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#28399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13114:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#28400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13115:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#28401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13116:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#28402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13117:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#28403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13118:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#28404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13119:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#28405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13120:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#28406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13121:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#28407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13122:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#28408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13123:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#28409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13124:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#28410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13125:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#28411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13126:
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#28412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13127:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#28413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13128:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#28414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13129:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#28415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13130:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#28416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13131:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#28417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13132:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13133:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13134:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#28420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13135:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#28421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13136:
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#28422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13137:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#28423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13138:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#28424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13139:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#28425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13140:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#28426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13141:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#28427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13142:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#28428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13143:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#28429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13144:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#28430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13145:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#28431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13146:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#28432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13147:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#28433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13148:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#28434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13149:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#28435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13150:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#28436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13151:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#28437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13152:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#28438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13153:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13154:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13155:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#28441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13156:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#28442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13157:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#28443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13158:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13159:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#28445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13160:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#28446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13161:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#28447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13162:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#28448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13163:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#28449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13164:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#28450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13165:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#28451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13166:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#28452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13167:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#28453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13168:
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#28454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13169:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#28455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13170:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#28456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13171:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#28457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13172:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#28458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13173:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#28459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13174:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#28460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13175:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13176:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#28462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13177:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#28463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13178:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#28464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13179:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#28465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13180:
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#28466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13181:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#28467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13182:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#28468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13183:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#28469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13184:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#28470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13185:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13186:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13187:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#28473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13188:
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#28474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13189:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#28475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13190:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#28476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13191:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#28477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13192:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#28478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13193:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#28479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13194:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#28480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13195:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#28481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13196:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#28482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13197:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#28483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13198:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#28484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13199:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#28485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13200:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#28486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13201:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#28487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13202:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#28488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13203:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#28489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13204:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#28490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13205:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#28491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13206:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13207:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13208:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13209:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#28495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13210:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#28496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13211:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#28497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13212:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#28498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13213:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#28499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13214:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13215:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13216:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13217:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#28503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13218:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#28504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13219:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#28505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13220:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#28506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13221:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#28507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13222:
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#28508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13223:
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#28509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13224:
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13225:
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#28511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13226:
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#28512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13227:
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13228:
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#28514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13229:
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#28515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13230:
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13231:
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#28517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13232:
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#28518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13233:
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa

WARNING: line length of 113 exceeds 100 columns
#28519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13234:
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb

WARNING: line length of 121 exceeds 100 columns
#28520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13235:
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#28521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13236:
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L

WARNING: line length of 121 exceeds 100 columns
#28522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13237:
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13238:
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L

WARNING: line length of 113 exceeds 100 columns
#28524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13239:
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#28525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13240:
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6

WARNING: line length of 113 exceeds 100 columns
#28526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13241:
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc

WARNING: line length of 114 exceeds 100 columns
#28527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13242:
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#28528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13243:
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#28529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13244:
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#28530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13245:
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#28531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13246:
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L

WARNING: line length of 113 exceeds 100 columns
#28532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13247:
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#28533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13248:
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#28534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13249:
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#28535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13250:
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#28536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13251:
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#28537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13252:
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#28538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13253:
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13254:
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L

WARNING: line length of 113 exceeds 100 columns
#28540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13255:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#28541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13256:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#28542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13257:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13258:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13259:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#28545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13260:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#28546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13261:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13262:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13263:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#28549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13264:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#28550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13265:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13266:
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13267:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#28553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13268:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#28554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13269:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13270:
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13271:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#28557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13272:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#28558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13273:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13274:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13275:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#28561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13276:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#28562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13277:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13278:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13279:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#28565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13280:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#28566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13281:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13282:
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13283:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#28569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13284:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#28570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13285:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13286:
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13287:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#28573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13288:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#28574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13289:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#28575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13290:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb

WARNING: line length of 114 exceeds 100 columns
#28576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13291:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#28577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13292:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#28578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13293:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#28579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13294:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#28580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13295:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#28581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13296:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L

WARNING: line length of 121 exceeds 100 columns
#28582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13297:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L

WARNING: line length of 121 exceeds 100 columns
#28583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13298:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L

WARNING: line length of 121 exceeds 100 columns
#28584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13299:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#28585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13300:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#28586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13301:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L

WARNING: line length of 121 exceeds 100 columns
#28587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13302:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L

WARNING: line length of 113 exceeds 100 columns
#28588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13303:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#28589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13304:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#28590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13305:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#28591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13306:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb

WARNING: line length of 114 exceeds 100 columns
#28592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13307:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#28593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13308:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#28594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13309:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14

WARNING: line length of 121 exceeds 100 columns
#28595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13310:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#28596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13311:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#28597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13312:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L

WARNING: line length of 121 exceeds 100 columns
#28598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13313:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L

WARNING: line length of 121 exceeds 100 columns
#28599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13314:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#28600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13315:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#28601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13316:
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L

WARNING: line length of 113 exceeds 100 columns
#28602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13317:
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#28603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13318:
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#28604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13319:
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#28605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13320:
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3

WARNING: line length of 113 exceeds 100 columns
#28606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13321:
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4

WARNING: line length of 113 exceeds 100 columns
#28607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13322:
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#28608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13323:
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#28609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13324:
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#28610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13325:
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#28611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13326:
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#28612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13327:
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd

WARNING: line length of 114 exceeds 100 columns
#28613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13328:
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#28614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13329:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#28615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13330:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#28616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13331:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#28617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13332:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#28618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13333:
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c

WARNING: line length of 114 exceeds 100 columns
#28619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13334:
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#28620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13335:
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13336:
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13337:
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13338:
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#28624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13339:
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#28625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13340:
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13341:
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13342:
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13343:
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#28629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13344:
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#28630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13345:
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#28631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13346:
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#28632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13347:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#28633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13348:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#28634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13349:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#28635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13350:
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#28636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13351:
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L

WARNING: line length of 121 exceeds 100 columns
#28637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13352:
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#28638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13353:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#28639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13354:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#28640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13355:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#28641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13356:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#28642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13357:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#28643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13358:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#28644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13359:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#28645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13360:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#28646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13361:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#28647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13362:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#28648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13363:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13364:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#28650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13365:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13366:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#28652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13367:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#28653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13368:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#28654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13369:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#28655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13370:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#28656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13371:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#28657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13372:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13373:
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13374:
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#28660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13375:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#28661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13376:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#28662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13377:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#28663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13378:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#28664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13379:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#28665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13380:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13381:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#28667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13382:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#28668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13383:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L

WARNING: line length of 121 exceeds 100 columns
#28669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13384:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#28670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13385:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#28671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13386:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#28672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13387:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#28673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13388:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#28674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13389:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14

WARNING: line length of 121 exceeds 100 columns
#28675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13390:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13391:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13392:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#28678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13393:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#28679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13394:
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L

WARNING: line length of 113 exceeds 100 columns
#28680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13395:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#28681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13396:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#28682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13397:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13398:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13399:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#28685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13400:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#28686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13401:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13402:
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13403:
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#28689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13404:
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#28690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13405:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#28691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13406:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13407:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#28693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13408:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13409:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#28695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13410:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13411:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#28697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13412:
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13413:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#28699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13414:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13415:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#28701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13416:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13417:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#28703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13418:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13419:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#28705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13420:
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13421:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#28707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13422:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13423:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#28709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13424:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13425:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#28711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13426:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13427:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#28713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13428:
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13429:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#28715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13430:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13431:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#28717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13432:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13433:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#28719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13434:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13435:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#28721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13436:
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#28722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13437:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#28723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13438:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#28724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13439:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#28725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13440:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#28726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13441:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#28727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13442:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#28728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13443:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#28729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13444:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#28730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13445:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc

WARNING: line length of 113 exceeds 100 columns
#28731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13446:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd

WARNING: line length of 114 exceeds 100 columns
#28732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13447:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#28733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13448:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#28734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13449:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#28735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13450:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13

WARNING: line length of 121 exceeds 100 columns
#28736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13451:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13452:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13453:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#28739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13454:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#28740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13455:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#28741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13456:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13457:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13458:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#28744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13459:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#28745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13460:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L

WARNING: line length of 121 exceeds 100 columns
#28746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13461:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#28747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13462:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#28748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13463:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#28749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13464:
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#28750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13465:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#28751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13466:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1

WARNING: line length of 113 exceeds 100 columns
#28752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13467:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#28753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13468:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#28754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13469:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9

WARNING: line length of 113 exceeds 100 columns
#28755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13470:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#28756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13471:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#28757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13472:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11

WARNING: line length of 114 exceeds 100 columns
#28758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13473:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#28759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13474:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14

WARNING: line length of 121 exceeds 100 columns
#28760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13475:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13476:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13477:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#28763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13478:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13479:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13480:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#28766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13481:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#28767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13482:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L

WARNING: line length of 121 exceeds 100 columns
#28768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13483:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#28769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13484:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#28770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13485:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#28771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13486:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#28772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13487:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#28773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13488:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#28774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13489:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc

WARNING: line length of 121 exceeds 100 columns
#28775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13490:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#28776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13491:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13492:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13493:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13494:
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L

WARNING: line length of 113 exceeds 100 columns
#28780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13495:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#28781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13496:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#28782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13497:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2

WARNING: line length of 113 exceeds 100 columns
#28783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13498:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3

WARNING: line length of 113 exceeds 100 columns
#28784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13499:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#28785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13500:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9

WARNING: line length of 114 exceeds 100 columns
#28786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13501:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#28787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13502:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#28788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13503:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12

WARNING: line length of 114 exceeds 100 columns
#28789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13504:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13

WARNING: line length of 121 exceeds 100 columns
#28790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13505:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13506:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#28792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13507:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13508:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#28794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13509:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#28795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13510:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#28796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13511:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#28797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13512:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#28798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13513:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#28799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13514:
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L

WARNING: line length of 113 exceeds 100 columns
#28800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13515:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#28801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13516:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13517:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#28803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13518:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#28804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13519:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13520:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13521:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13522:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13523:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#28809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13524:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#28810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13525:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13526:
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13527:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#28813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13528:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13529:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#28815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13530:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c

WARNING: line length of 121 exceeds 100 columns
#28816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13531:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13532:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13533:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#28819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13534:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13535:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#28821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13536:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c

WARNING: line length of 121 exceeds 100 columns
#28822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13537:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13538:
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13539:
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#28825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13540:
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#28826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13541:
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#28827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13542:
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#28828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13543:
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13544:
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#28830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13545:
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L

WARNING: line length of 121 exceeds 100 columns
#28831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13546:
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#28832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13547:
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#28833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13548:
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#28834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13549:
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#28835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13550:
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13551:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#28837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13552:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18

WARNING: line length of 114 exceeds 100 columns
#28838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13553:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#28839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13554:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b

WARNING: line length of 114 exceeds 100 columns
#28840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13555:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c

WARNING: line length of 121 exceeds 100 columns
#28841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13556:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#28842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13557:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#28843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13558:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#28844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13559:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#28845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13560:
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#28846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13561:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#28847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13562:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#28848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13563:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#28849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13564:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13565:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13566:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13567:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#28853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13568:
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13569:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#28855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13570:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#28856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13571:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#28857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13572:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13573:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13574:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13575:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#28861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13576:
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13577:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#28863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13578:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#28864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13579:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#28865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13580:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13581:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13582:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13583:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13584:
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13585:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#28871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13586:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#28872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13587:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#28873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13588:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13589:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#28875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13590:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#28876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13591:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13592:
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13593:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#28879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13594:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#28880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13595:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#28881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13596:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18

WARNING: line length of 114 exceeds 100 columns
#28882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13597:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#28883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13598:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#28884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13599:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#28885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13600:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#28886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13601:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#28887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13602:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#28888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13603:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#28889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13604:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#28890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13605:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#28891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13606:
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#28892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13607:
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#28893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13608:
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13609:
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#28895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13610:
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#28896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13611:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#28897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13612:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#28898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13613:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#28899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13614:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6

WARNING: line length of 121 exceeds 100 columns
#28900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13615:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#28901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13616:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L

WARNING: line length of 121 exceeds 100 columns
#28902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13617:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#28903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13618:
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L

WARNING: line length of 113 exceeds 100 columns
#28904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13619:
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#28905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13620:
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#28906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13621:
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13622:
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13623:
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#28909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13624:
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#28910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13625:
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#28911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13626:
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13627:
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#28913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13628:
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#28914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13629:
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13630:
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L

WARNING: line length of 113 exceeds 100 columns
#28916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13631:
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#28917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13632:
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#28918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13633:
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL

WARNING: line length of 121 exceeds 100 columns
#28919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13634:
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#28920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13635:
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#28921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13636:
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13637:
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#28923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13638:
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#28924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13639:
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#28925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13640:
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#28926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13641:
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#28927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13642:
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13643:
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#28929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13644:
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13645:
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#28931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13646:
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13647:
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#28933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13648:
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13649:
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#28935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13650:
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#28936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13651:
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#28937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13652:
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#28938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13653:
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#28939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13654:
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13655:
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#28941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13656:
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13657:
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#28943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13658:
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13659:
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#28945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13660:
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13661:
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#28947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13662:
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13663:
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#28949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13664:
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13665:
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13666:
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13667:
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#28953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13668:
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13669:
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13670:
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#28956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13671:
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#28957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13672:
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13673:
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#28959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13674:
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10

WARNING: line length of 121 exceeds 100 columns
#28960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13675:
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13676:
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13677:
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#28963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13678:
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#28964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13679:
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#28965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13680:
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#28966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13681:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#28967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13682:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#28968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13683:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#28969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13684:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#28970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13685:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#28971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13686:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#28972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13687:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#28973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13688:
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L

WARNING: line length of 113 exceeds 100 columns
#28974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13689:
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#28975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13690:
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#28976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13691:
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#28977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13692:
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#28978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13693:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#28979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13694:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#28980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13695:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#28981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13696:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6

WARNING: line length of 113 exceeds 100 columns
#28982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13697:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#28983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13698:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#28984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13699:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#28985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13700:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe

WARNING: line length of 121 exceeds 100 columns
#28986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13701:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13702:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#28988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13703:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#28989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13704:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#28990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13705:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#28991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13706:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#28992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13707:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L

WARNING: line length of 121 exceeds 100 columns
#28993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13708:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L

WARNING: line length of 113 exceeds 100 columns
#28994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13709:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#28995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13710:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#28996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13711:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#28997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13712:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6

WARNING: line length of 121 exceeds 100 columns
#28998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13713:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#28999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13714:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#29000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13715:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#29001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13716:
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#29002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13717:
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13718:
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13719:
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#29005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13720:
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13721:
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#29007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13722:
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13723:
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#29009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13724:
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13725:
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#29011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13726:
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13727:
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13728:
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13729:
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#29015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13730:
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf

WARNING: line length of 114 exceeds 100 columns
#29016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13731:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#29017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13732:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#29018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13733:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#29019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13734:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#29020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13735:
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#29021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13736:
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L

WARNING: line length of 121 exceeds 100 columns
#29022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13737:
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L

WARNING: line length of 121 exceeds 100 columns
#29023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13738:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13739:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#29025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13740:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#29026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13741:
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#29027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13742:
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#29028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13743:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#29029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13744:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa

WARNING: line length of 114 exceeds 100 columns
#29030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13745:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#29031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13746:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#29032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13747:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#29033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13748:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#29034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13749:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13750:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13751:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#29037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13752:
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L

WARNING: line length of 113 exceeds 100 columns
#29038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13753:
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#29039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13754:
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#29040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13755:
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#29041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13756:
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L

WARNING: line length of 113 exceeds 100 columns
#29042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13757:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#29043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13758:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13759:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#29045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13760:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#29046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13761:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13762:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#29048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13763:
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#29049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13764:
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#29050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13765:
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13766:
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13767:
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#29053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13768:
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#29054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13769:
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13770:
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13771:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#29057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13772:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#29058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13773:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#29059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13774:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#29060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13775:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#29061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13776:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#29062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13777:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#29063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13778:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#29064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13779:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#29065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13780:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc

WARNING: line length of 113 exceeds 100 columns
#29066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13781:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd

WARNING: line length of 113 exceeds 100 columns
#29067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13782:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#29068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13783:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#29069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13784:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#29070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13785:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12

WARNING: line length of 121 exceeds 100 columns
#29071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13786:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13787:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13788:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13789:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13790:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#29076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13791:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#29077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13792:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13793:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13794:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13795:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13796:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#29082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13797:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#29083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13798:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13799:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#29085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13800:
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L

WARNING: line length of 113 exceeds 100 columns
#29086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13801:
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#29087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13802:
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#29088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13803:
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13804:
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13805:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#29091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13806:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#29092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13807:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5

WARNING: line length of 113 exceeds 100 columns
#29093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13808:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#29094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13809:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa

WARNING: line length of 121 exceeds 100 columns
#29095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13810:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13811:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13812:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#29098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13813:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13814:
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L

WARNING: line length of 113 exceeds 100 columns
#29100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13815:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#29101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13816:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#29102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13817:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#29103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13818:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#29104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13819:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc

WARNING: line length of 114 exceeds 100 columns
#29105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13820:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#29106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13821:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#29107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13822:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#29108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13823:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#29109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13824:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#29110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13825:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13826:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13827:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13828:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#29114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13829:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13830:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13831:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#29117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13832:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#29118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13833:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#29119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13834:
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#29120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13835:
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13836:
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13837:
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#29123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13838:
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13839:
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#29125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13840:
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#29126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13841:
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#29127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13842:
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#29128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13843:
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#29129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13844:
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#29130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13845:
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13846:
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13847:
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#29133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13848:
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#29134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13849:
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#29135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13850:
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#29136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13851:
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#29137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13852:
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4

WARNING: line length of 114 exceeds 100 columns
#29138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13853:
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12

WARNING: line length of 121 exceeds 100 columns
#29139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13854:
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13855:
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L

WARNING: line length of 121 exceeds 100 columns
#29141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13856:
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L

WARNING: line length of 113 exceeds 100 columns
#29142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13857:
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#29143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13858:
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#29144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13859:
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#29145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13860:
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#29146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13861:
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#29147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13862:
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13863:
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13864:
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#29150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13865:
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#29151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13866:
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L

WARNING: line length of 113 exceeds 100 columns
#29152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13867:
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#29153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13868:
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#29154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13869:
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13870:
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L

WARNING: line length of 113 exceeds 100 columns
#29156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13871:
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#29157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13872:
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13873:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#29159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13874:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#29160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13875:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2

WARNING: line length of 114 exceeds 100 columns
#29161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13876:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#29162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13877:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13878:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13879:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13880:
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13881:
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#29167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13882:
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4

WARNING: line length of 114 exceeds 100 columns
#29168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13883:
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#29169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13884:
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13885:
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#29171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13886:
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#29172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13887:
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#29173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13888:
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#29174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13889:
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#29175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13890:
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13891:
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13892:
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#29178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13893:
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#29179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13894:
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1

WARNING: line length of 114 exceeds 100 columns
#29180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13895:
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#29181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13896:
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13897:
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13898:
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13899:
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13900:
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13901:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#29187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13902:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#29188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13903:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#29189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13904:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#29190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13905:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#29191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13906:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#29192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13907:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#29193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13908:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#29194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13909:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#29195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13910:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#29196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13911:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#29197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13912:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#29198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13913:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#29199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13914:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#29200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13915:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#29201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13916:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13917:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#29203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13918:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#29204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13919:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#29205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13920:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#29206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13921:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#29207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13922:
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#29208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13923:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#29209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13924:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#29210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13925:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#29211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13926:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#29212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13927:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#29213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13928:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13929:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13930:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#29216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13931:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#29217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13932:
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#29218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13933:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#29219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13934:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#29220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13935:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#29221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13936:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#29222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13937:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#29223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13938:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#29224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13939:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#29225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13940:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#29226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13941:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#29227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13942:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#29228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13943:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#29229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13944:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#29230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13945:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#29231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13946:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#29232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13947:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#29233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13948:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#29234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13949:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13950:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13951:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#29237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13952:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#29238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13953:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#29239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13954:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13955:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#29241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13956:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#29242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13957:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13958:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#29244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13959:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#29245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13960:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#29246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13961:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#29247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13962:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#29248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13963:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#29249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13964:
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#29250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13965:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#29251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13966:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#29252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13967:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#29253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13968:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#29254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13969:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#29255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13970:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#29256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13971:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13972:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#29258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13973:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#29259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13974:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#29260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13975:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#29261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13976:
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#29262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13977:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#29263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13978:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#29264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13979:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#29265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13980:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#29266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13981:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13982:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13983:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#29269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13984:
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#29270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13985:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#29271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13986:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#29272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13987:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#29273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13988:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#29274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13989:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#29275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13990:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#29276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13991:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#29277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13992:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#29278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13993:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#29279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13994:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#29280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13995:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#29281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13996:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#29282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13997:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#29283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13998:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#29284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:13999:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#29285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14000:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#29286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14001:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#29287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14002:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14003:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14004:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14005:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#29291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14006:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14007:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#29293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14008:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#29294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14009:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#29295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14010:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14011:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14012:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14013:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#29299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14014:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14015:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#29301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14016:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#29302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14017:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#29303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14018:
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#29304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14019:
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#29305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14020:
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14021:
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#29307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14022:
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#29308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14023:
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14024:
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#29310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14025:
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#29311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14026:
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14027:
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#29313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14028:
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#29314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14029:
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa

WARNING: line length of 113 exceeds 100 columns
#29315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14030:
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb

WARNING: line length of 121 exceeds 100 columns
#29316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14031:
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#29317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14032:
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L

WARNING: line length of 121 exceeds 100 columns
#29318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14033:
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14034:
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L

WARNING: line length of 113 exceeds 100 columns
#29320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14035:
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#29321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14036:
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6

WARNING: line length of 113 exceeds 100 columns
#29322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14037:
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc

WARNING: line length of 114 exceeds 100 columns
#29323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14038:
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#29324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14039:
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#29325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14040:
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#29326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14041:
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#29327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14042:
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L

WARNING: line length of 113 exceeds 100 columns
#29328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14043:
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#29329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14044:
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#29330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14045:
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#29331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14046:
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#29332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14047:
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#29333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14048:
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#29334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14049:
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14050:
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L

WARNING: line length of 113 exceeds 100 columns
#29336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14051:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#29337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14052:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#29338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14053:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14054:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14055:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#29341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14056:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#29342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14057:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14058:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14059:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#29345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14060:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#29346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14061:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14062:
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14063:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#29349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14064:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#29350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14065:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14066:
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14067:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#29353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14068:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#29354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14069:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14070:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14071:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#29357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14072:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#29358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14073:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14074:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14075:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#29361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14076:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#29362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14077:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14078:
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14079:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#29365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14080:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#29366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14081:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14082:
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14083:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#29369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14084:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#29370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14085:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#29371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14086:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb

WARNING: line length of 114 exceeds 100 columns
#29372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14087:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#29373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14088:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#29374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14089:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#29375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14090:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#29376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14091:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#29377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14092:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L

WARNING: line length of 121 exceeds 100 columns
#29378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14093:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L

WARNING: line length of 121 exceeds 100 columns
#29379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14094:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L

WARNING: line length of 121 exceeds 100 columns
#29380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14095:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14096:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#29382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14097:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L

WARNING: line length of 121 exceeds 100 columns
#29383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14098:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L

WARNING: line length of 113 exceeds 100 columns
#29384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14099:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#29385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14100:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#29386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14101:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#29387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14102:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb

WARNING: line length of 114 exceeds 100 columns
#29388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14103:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#29389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14104:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#29390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14105:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14

WARNING: line length of 121 exceeds 100 columns
#29391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14106:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#29392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14107:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#29393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14108:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L

WARNING: line length of 121 exceeds 100 columns
#29394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14109:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L

WARNING: line length of 121 exceeds 100 columns
#29395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14110:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14111:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#29397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14112:
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L

WARNING: line length of 113 exceeds 100 columns
#29398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14113:
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#29399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14114:
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#29400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14115:
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#29401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14116:
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3

WARNING: line length of 113 exceeds 100 columns
#29402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14117:
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4

WARNING: line length of 113 exceeds 100 columns
#29403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14118:
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#29404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14119:
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#29405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14120:
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#29406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14121:
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#29407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14122:
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#29408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14123:
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd

WARNING: line length of 114 exceeds 100 columns
#29409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14124:
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#29410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14125:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#29411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14126:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#29412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14127:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#29413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14128:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#29414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14129:
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c

WARNING: line length of 114 exceeds 100 columns
#29415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14130:
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#29416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14131:
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14132:
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14133:
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14134:
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#29420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14135:
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#29421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14136:
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14137:
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14138:
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14139:
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#29425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14140:
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14141:
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#29427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14142:
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#29428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14143:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#29429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14144:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#29430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14145:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#29431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14146:
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#29432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14147:
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L

WARNING: line length of 121 exceeds 100 columns
#29433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14148:
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#29434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14149:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#29435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14150:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#29436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14151:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#29437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14152:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#29438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14153:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#29439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14154:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#29440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14155:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#29441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14156:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#29442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14157:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#29443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14158:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#29444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14159:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14160:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14161:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14162:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14163:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14164:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#29450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14165:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#29451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14166:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#29452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14167:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#29453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14168:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#29454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14169:
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#29455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14170:
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#29456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14171:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#29457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14172:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#29458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14173:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#29459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14174:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#29460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14175:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#29461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14176:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14177:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#29463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14178:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#29464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14179:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L

WARNING: line length of 121 exceeds 100 columns
#29465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14180:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#29466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14181:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#29467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14182:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#29468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14183:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#29469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14184:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#29470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14185:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14

WARNING: line length of 121 exceeds 100 columns
#29471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14186:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14187:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14188:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#29474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14189:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#29475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14190:
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L

WARNING: line length of 113 exceeds 100 columns
#29476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14191:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#29477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14192:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#29478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14193:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14194:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14195:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#29481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14196:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#29482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14197:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14198:
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14199:
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#29485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14200:
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#29486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14201:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#29487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14202:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14203:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#29489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14204:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14205:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#29491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14206:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14207:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#29493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14208:
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14209:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#29495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14210:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14211:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#29497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14212:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14213:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#29499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14214:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14215:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#29501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14216:
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14217:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#29503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14218:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14219:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#29505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14220:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14221:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#29507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14222:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14223:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#29509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14224:
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14225:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#29511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14226:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14227:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#29513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14228:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14229:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#29515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14230:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14231:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#29517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14232:
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14233:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#29519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14234:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#29520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14235:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#29521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14236:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#29522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14237:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#29523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14238:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#29524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14239:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#29525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14240:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#29526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14241:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc

WARNING: line length of 113 exceeds 100 columns
#29527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14242:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd

WARNING: line length of 114 exceeds 100 columns
#29528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14243:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#29529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14244:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#29530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14245:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#29531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14246:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13

WARNING: line length of 121 exceeds 100 columns
#29532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14247:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14248:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14249:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#29535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14250:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14251:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#29537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14252:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14253:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14254:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#29540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14255:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14256:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L

WARNING: line length of 121 exceeds 100 columns
#29542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14257:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14258:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#29544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14259:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#29545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14260:
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#29546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14261:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#29547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14262:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1

WARNING: line length of 113 exceeds 100 columns
#29548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14263:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#29549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14264:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#29550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14265:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9

WARNING: line length of 113 exceeds 100 columns
#29551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14266:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#29552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14267:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#29553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14268:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11

WARNING: line length of 114 exceeds 100 columns
#29554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14269:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#29555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14270:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14

WARNING: line length of 121 exceeds 100 columns
#29556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14271:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14272:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14273:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#29559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14274:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14275:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14276:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#29562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14277:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14278:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L

WARNING: line length of 121 exceeds 100 columns
#29564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14279:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#29565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14280:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#29566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14281:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#29567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14282:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#29568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14283:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#29569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14284:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#29570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14285:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc

WARNING: line length of 121 exceeds 100 columns
#29571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14286:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#29572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14287:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14288:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14289:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14290:
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L

WARNING: line length of 113 exceeds 100 columns
#29576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14291:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#29577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14292:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#29578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14293:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2

WARNING: line length of 113 exceeds 100 columns
#29579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14294:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3

WARNING: line length of 113 exceeds 100 columns
#29580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14295:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#29581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14296:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9

WARNING: line length of 114 exceeds 100 columns
#29582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14297:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#29583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14298:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#29584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14299:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12

WARNING: line length of 114 exceeds 100 columns
#29585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14300:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13

WARNING: line length of 121 exceeds 100 columns
#29586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14301:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14302:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14303:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14304:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#29590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14305:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14306:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14307:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14308:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#29594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14309:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#29595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14310:
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L

WARNING: line length of 113 exceeds 100 columns
#29596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14311:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#29597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14312:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14313:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#29599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14314:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#29600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14315:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14316:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#29602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14317:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14318:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14319:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#29605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14320:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#29606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14321:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14322:
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#29608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14323:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#29609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14324:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14325:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#29611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14326:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c

WARNING: line length of 121 exceeds 100 columns
#29612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14327:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14328:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#29614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14329:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#29615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14330:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14331:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#29617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14332:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c

WARNING: line length of 121 exceeds 100 columns
#29618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14333:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14334:
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#29620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14335:
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#29621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14336:
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#29622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14337:
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#29623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14338:
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#29624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14339:
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14340:
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#29626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14341:
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L

WARNING: line length of 121 exceeds 100 columns
#29627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14342:
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#29628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14343:
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#29629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14344:
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#29630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14345:
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14346:
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14347:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#29633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14348:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18

WARNING: line length of 114 exceeds 100 columns
#29634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14349:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#29635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14350:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b

WARNING: line length of 114 exceeds 100 columns
#29636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14351:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c

WARNING: line length of 121 exceeds 100 columns
#29637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14352:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#29638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14353:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#29639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14354:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#29640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14355:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#29641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14356:
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#29642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14357:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#29643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14358:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#29644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14359:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#29645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14360:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#29646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14361:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#29647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14362:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#29648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14363:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#29649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14364:
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14365:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#29651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14366:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#29652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14367:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#29653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14368:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#29654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14369:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#29655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14370:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#29656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14371:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#29657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14372:
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14373:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#29659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14374:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#29660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14375:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#29661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14376:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#29662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14377:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#29663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14378:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#29664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14379:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14380:
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14381:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#29667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14382:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#29668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14383:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#29669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14384:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#29670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14385:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#29671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14386:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#29672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14387:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14388:
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14389:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#29675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14390:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#29676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14391:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#29677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14392:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18

WARNING: line length of 114 exceeds 100 columns
#29678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14393:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#29679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14394:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#29680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14395:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#29681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14396:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14397:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#29683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14398:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#29684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14399:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#29685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14400:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#29686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14401:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#29687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14402:
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#29688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14403:
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#29689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14404:
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14405:
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#29691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14406:
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14407:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#29693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14408:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#29694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14409:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#29695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14410:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6

WARNING: line length of 121 exceeds 100 columns
#29696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14411:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14412:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L

WARNING: line length of 121 exceeds 100 columns
#29698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14413:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#29699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14414:
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L

WARNING: line length of 113 exceeds 100 columns
#29700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14415:
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#29701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14416:
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#29702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14417:
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#29703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14418:
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14419:
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#29705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14420:
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#29706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14421:
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#29707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14422:
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14423:
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#29709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14424:
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#29710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14425:
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#29711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14426:
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L

WARNING: line length of 113 exceeds 100 columns
#29712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14427:
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#29713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14428:
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#29714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14429:
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL

WARNING: line length of 121 exceeds 100 columns
#29715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14430:
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#29716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14431:
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#29717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14432:
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14433:
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#29719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14434:
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#29720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14435:
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#29721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14436:
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#29722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14437:
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#29723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14438:
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14439:
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#29725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14440:
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14441:
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#29727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14442:
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14443:
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#29729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14444:
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14445:
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#29731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14446:
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#29732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14447:
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#29733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14448:
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#29734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14449:
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#29735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14450:
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14451:
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14452:
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14453:
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#29739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14454:
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#29740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14455:
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#29741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14456:
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14457:
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#29743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14458:
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#29744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14459:
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#29745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14460:
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14461:
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#29747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14462:
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#29748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14463:
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#29749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14464:
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14465:
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#29751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14466:
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#29752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14467:
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#29753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14468:
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14469:
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#29755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14470:
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10

WARNING: line length of 121 exceeds 100 columns
#29756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14471:
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#29757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14472:
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14473:
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#29759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14474:
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#29760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14475:
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#29761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14476:
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14477:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#29763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14478:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#29764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14479:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#29765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14480:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#29766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14481:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#29767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14482:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#29768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14483:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#29769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14484:
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L

WARNING: line length of 113 exceeds 100 columns
#29770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14485:
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#29771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14486:
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14487:
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#29773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14488:
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#29774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14489:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#29775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14490:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#29776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14491:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#29777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14492:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6

WARNING: line length of 113 exceeds 100 columns
#29778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14493:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#29779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14494:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#29780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14495:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#29781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14496:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe

WARNING: line length of 121 exceeds 100 columns
#29782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14497:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14498:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14499:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#29785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14500:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#29786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14501:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#29787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14502:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14503:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L

WARNING: line length of 121 exceeds 100 columns
#29789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14504:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L

WARNING: line length of 113 exceeds 100 columns
#29790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14505:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#29791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14506:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#29792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14507:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#29793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14508:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6

WARNING: line length of 121 exceeds 100 columns
#29794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14509:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14510:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#29796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14511:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#29797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14512:
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#29798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14513:
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14514:
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14515:
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#29801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14516:
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14517:
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#29803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14518:
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14519:
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#29805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14520:
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14521:
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#29807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14522:
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14523:
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14524:
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#29810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14525:
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#29811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14526:
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf

WARNING: line length of 114 exceeds 100 columns
#29812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14527:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#29813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14528:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#29814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14529:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#29815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14530:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#29816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14531:
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#29817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14532:
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L

WARNING: line length of 121 exceeds 100 columns
#29818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14533:
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L

WARNING: line length of 121 exceeds 100 columns
#29819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14534:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14535:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#29821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14536:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#29822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14537:
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#29823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14538:
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#29824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14539:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#29825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14540:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa

WARNING: line length of 114 exceeds 100 columns
#29826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14541:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#29827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14542:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#29828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14543:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#29829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14544:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#29830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14545:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14546:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14547:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#29833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14548:
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L

WARNING: line length of 113 exceeds 100 columns
#29834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14549:
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#29835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14550:
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#29836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14551:
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#29837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14552:
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L

WARNING: line length of 113 exceeds 100 columns
#29838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14553:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#29839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14554:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14555:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#29841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14556:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#29842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14557:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14558:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#29844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14559:
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#29845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14560:
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#29846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14561:
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14562:
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14563:
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#29849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14564:
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#29850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14565:
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14566:
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14567:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#29853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14568:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#29854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14569:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#29855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14570:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#29856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14571:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#29857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14572:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#29858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14573:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#29859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14574:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#29860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14575:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#29861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14576:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc

WARNING: line length of 113 exceeds 100 columns
#29862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14577:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd

WARNING: line length of 113 exceeds 100 columns
#29863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14578:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#29864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14579:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#29865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14580:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#29866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14581:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12

WARNING: line length of 121 exceeds 100 columns
#29867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14582:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14583:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14584:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14585:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14586:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#29872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14587:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#29873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14588:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14589:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#29875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14590:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#29876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14591:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14592:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#29878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14593:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#29879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14594:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14595:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#29881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14596:
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L

WARNING: line length of 113 exceeds 100 columns
#29882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14597:
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#29883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14598:
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#29884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14599:
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14600:
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14601:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#29887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14602:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#29888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14603:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5

WARNING: line length of 113 exceeds 100 columns
#29889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14604:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#29890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14605:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa

WARNING: line length of 121 exceeds 100 columns
#29891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14606:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14607:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14608:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#29894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14609:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#29895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14610:
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L

WARNING: line length of 113 exceeds 100 columns
#29896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14611:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#29897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14612:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#29898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14613:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#29899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14614:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#29900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14615:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc

WARNING: line length of 114 exceeds 100 columns
#29901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14616:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#29902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14617:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#29903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14618:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#29904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14619:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#29905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14620:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#29906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14621:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14622:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14623:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#29909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14624:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#29910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14625:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#29911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14626:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#29912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14627:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#29913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14628:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#29914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14629:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#29915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14630:
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#29916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14631:
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14632:
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14633:
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#29919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14634:
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#29920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14635:
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#29921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14636:
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#29922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14637:
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#29923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14638:
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#29924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14639:
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#29925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14640:
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#29926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14641:
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#29927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14642:
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14643:
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#29929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14644:
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#29930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14645:
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#29931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14646:
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#29932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14647:
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#29933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14648:
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4

WARNING: line length of 114 exceeds 100 columns
#29934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14649:
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12

WARNING: line length of 121 exceeds 100 columns
#29935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14650:
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14651:
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L

WARNING: line length of 121 exceeds 100 columns
#29937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14652:
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L

WARNING: line length of 113 exceeds 100 columns
#29938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14653:
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#29939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14654:
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#29940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14655:
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#29941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14656:
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#29942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14657:
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#29943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14658:
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L

WARNING: line length of 121 exceeds 100 columns
#29944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14659:
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14660:
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#29946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14661:
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#29947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14662:
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L

WARNING: line length of 113 exceeds 100 columns
#29948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14663:
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#29949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14664:
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#29950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14665:
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#29951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14666:
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L

WARNING: line length of 113 exceeds 100 columns
#29952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14667:
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#29953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14668:
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14669:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#29955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14670:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#29956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14671:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2

WARNING: line length of 114 exceeds 100 columns
#29957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14672:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#29958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14673:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14674:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14675:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14676:
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14677:
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#29963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14678:
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4

WARNING: line length of 114 exceeds 100 columns
#29964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14679:
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#29965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14680:
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14681:
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#29967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14682:
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#29968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14683:
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#29969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14684:
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#29970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14685:
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#29971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14686:
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14687:
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#29973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14688:
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#29974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14689:
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#29975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14690:
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1

WARNING: line length of 114 exceeds 100 columns
#29976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14691:
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#29977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14692:
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#29978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14693:
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#29979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14694:
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#29980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14695:
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#29981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14696:
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#29982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14697:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#29983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14698:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#29984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14699:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#29985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14700:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#29986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14701:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#29987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14702:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#29988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14703:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#29989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14704:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#29990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14705:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#29991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14706:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#29992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14707:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#29993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14708:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#29994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14709:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#29995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14710:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#29996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14711:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#29997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14712:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#29998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14713:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#29999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14714:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#30000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14715:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#30001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14716:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#30002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14717:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#30003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14718:
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#30004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14719:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#30005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14720:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#30006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14721:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#30007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14722:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#30008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14723:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#30009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14724:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14725:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14726:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#30012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14727:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#30013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14728:
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#30014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14729:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#30015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14730:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#30016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14731:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#30017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14732:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#30018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14733:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#30019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14734:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#30020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14735:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#30021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14736:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#30022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14737:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#30023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14738:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#30024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14739:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#30025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14740:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#30026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14741:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#30027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14742:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#30028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14743:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#30029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14744:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#30030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14745:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14746:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14747:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#30033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14748:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#30034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14749:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#30035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14750:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14751:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#30037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14752:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#30038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14753:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#30039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14754:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#30040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14755:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#30041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14756:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#30042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14757:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#30043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14758:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#30044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14759:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#30045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14760:
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#30046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14761:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#30047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14762:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#30048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14763:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#30049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14764:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#30050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14765:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#30051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14766:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#30052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14767:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14768:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#30054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14769:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#30055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14770:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#30056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14771:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#30057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14772:
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#30058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14773:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#30059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14774:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#30060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14775:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#30061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14776:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#30062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14777:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14778:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14779:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#30065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14780:
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#30066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14781:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#30067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14782:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#30068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14783:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#30069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14784:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#30070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14785:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#30071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14786:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#30072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14787:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#30073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14788:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#30074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14789:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#30075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14790:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#30076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14791:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#30077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14792:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#30078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14793:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#30079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14794:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#30080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14795:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#30081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14796:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#30082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14797:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#30083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14798:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14799:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14800:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14801:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#30087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14802:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14803:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#30089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14804:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#30090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14805:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#30091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14806:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14807:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14808:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14809:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#30095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14810:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14811:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#30097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14812:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#30098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14813:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#30099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14814:
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#30100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14815:
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#30101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14816:
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14817:
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#30103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14818:
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#30104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14819:
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14820:
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#30106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14821:
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#30107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14822:
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14823:
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#30109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14824:
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#30110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14825:
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa

WARNING: line length of 113 exceeds 100 columns
#30111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14826:
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb

WARNING: line length of 121 exceeds 100 columns
#30112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14827:
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#30113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14828:
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L

WARNING: line length of 121 exceeds 100 columns
#30114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14829:
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14830:
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L

WARNING: line length of 113 exceeds 100 columns
#30116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14831:
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#30117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14832:
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6

WARNING: line length of 113 exceeds 100 columns
#30118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14833:
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc

WARNING: line length of 114 exceeds 100 columns
#30119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14834:
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#30120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14835:
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#30121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14836:
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#30122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14837:
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#30123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14838:
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L

WARNING: line length of 113 exceeds 100 columns
#30124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14839:
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#30125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14840:
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#30126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14841:
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#30127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14842:
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#30128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14843:
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#30129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14844:
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#30130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14845:
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14846:
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L

WARNING: line length of 113 exceeds 100 columns
#30132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14847:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#30133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14848:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#30134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14849:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14850:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14851:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#30137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14852:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#30138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14853:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14854:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14855:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#30141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14856:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#30142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14857:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14858:
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14859:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#30145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14860:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#30146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14861:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14862:
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14863:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#30149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14864:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#30150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14865:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14866:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14867:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#30153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14868:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#30154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14869:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14870:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14871:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#30157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14872:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#30158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14873:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14874:
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14875:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#30161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14876:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#30162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14877:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14878:
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14879:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#30165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14880:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#30166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14881:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#30167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14882:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb

WARNING: line length of 114 exceeds 100 columns
#30168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14883:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#30169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14884:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#30170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14885:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#30171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14886:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#30172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14887:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#30173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14888:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L

WARNING: line length of 121 exceeds 100 columns
#30174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14889:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L

WARNING: line length of 121 exceeds 100 columns
#30175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14890:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L

WARNING: line length of 121 exceeds 100 columns
#30176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14891:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#30177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14892:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#30178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14893:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L

WARNING: line length of 121 exceeds 100 columns
#30179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14894:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L

WARNING: line length of 113 exceeds 100 columns
#30180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14895:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#30181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14896:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#30182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14897:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#30183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14898:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb

WARNING: line length of 114 exceeds 100 columns
#30184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14899:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#30185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14900:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#30186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14901:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14

WARNING: line length of 121 exceeds 100 columns
#30187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14902:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#30188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14903:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#30189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14904:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L

WARNING: line length of 121 exceeds 100 columns
#30190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14905:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L

WARNING: line length of 121 exceeds 100 columns
#30191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14906:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#30192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14907:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#30193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14908:
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L

WARNING: line length of 113 exceeds 100 columns
#30194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14909:
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#30195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14910:
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#30196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14911:
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#30197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14912:
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3

WARNING: line length of 113 exceeds 100 columns
#30198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14913:
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4

WARNING: line length of 113 exceeds 100 columns
#30199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14914:
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#30200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14915:
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#30201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14916:
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#30202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14917:
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#30203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14918:
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#30204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14919:
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd

WARNING: line length of 114 exceeds 100 columns
#30205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14920:
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#30206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14921:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#30207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14922:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#30208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14923:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#30209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14924:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#30210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14925:
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c

WARNING: line length of 114 exceeds 100 columns
#30211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14926:
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#30212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14927:
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14928:
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14929:
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14930:
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#30216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14931:
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#30217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14932:
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14933:
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14934:
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14935:
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#30221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14936:
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14937:
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#30223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14938:
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#30224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14939:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#30225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14940:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#30226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14941:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#30227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14942:
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#30228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14943:
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L

WARNING: line length of 121 exceeds 100 columns
#30229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14944:
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#30230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14945:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#30231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14946:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#30232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14947:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#30233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14948:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#30234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14949:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#30235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14950:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#30236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14951:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#30237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14952:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#30238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14953:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#30239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14954:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#30240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14955:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14956:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14957:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14958:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14959:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14960:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#30246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14961:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#30247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14962:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#30248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14963:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#30249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14964:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#30250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14965:
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#30251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14966:
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#30252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14967:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#30253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14968:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#30254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14969:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#30255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14970:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#30256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14971:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#30257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14972:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14973:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#30259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14974:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#30260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14975:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L

WARNING: line length of 121 exceeds 100 columns
#30261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14976:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#30262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14977:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#30263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14978:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#30264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14979:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#30265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14980:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc

WARNING: line length of 114 exceeds 100 columns
#30266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14981:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14

WARNING: line length of 121 exceeds 100 columns
#30267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14982:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14983:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14984:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L

WARNING: line length of 121 exceeds 100 columns
#30270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14985:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L

WARNING: line length of 121 exceeds 100 columns
#30271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14986:
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L

WARNING: line length of 113 exceeds 100 columns
#30272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14987:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#30273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14988:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#30274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14989:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14990:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14991:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#30277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14992:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#30278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14993:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14994:
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14995:
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#30281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14996:
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#30282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14997:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#30283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14998:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:14999:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#30285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15000:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15001:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#30287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15002:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15003:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#30289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15004:
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15005:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#30291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15006:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15007:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#30293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15008:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15009:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#30295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15010:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15011:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#30297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15012:
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15013:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#30299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15014:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15015:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#30301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15016:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15017:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#30303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15018:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15019:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#30305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15020:
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15021:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#30307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15022:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15023:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#30309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15024:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15025:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0

WARNING: line length of 121 exceeds 100 columns
#30311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15026:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15027:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#30313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15028:
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15029:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#30315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15030:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#30316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15031:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#30317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15032:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#30318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15033:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#30319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15034:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#30320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15035:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#30321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15036:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#30322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15037:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc

WARNING: line length of 113 exceeds 100 columns
#30323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15038:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd

WARNING: line length of 114 exceeds 100 columns
#30324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15039:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#30325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15040:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#30326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15041:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#30327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15042:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13

WARNING: line length of 121 exceeds 100 columns
#30328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15043:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15044:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15045:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#30331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15046:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15047:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#30333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15048:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15049:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15050:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#30336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15051:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15052:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L

WARNING: line length of 121 exceeds 100 columns
#30338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15053:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15054:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#30340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15055:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#30341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15056:
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L

WARNING: line length of 113 exceeds 100 columns
#30342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15057:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#30343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15058:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1

WARNING: line length of 113 exceeds 100 columns
#30344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15059:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#30345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15060:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#30346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15061:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9

WARNING: line length of 113 exceeds 100 columns
#30347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15062:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#30348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15063:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#30349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15064:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11

WARNING: line length of 114 exceeds 100 columns
#30350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15065:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#30351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15066:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14

WARNING: line length of 121 exceeds 100 columns
#30352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15067:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15068:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15069:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#30355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15070:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15071:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15072:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#30358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15073:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15074:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L

WARNING: line length of 121 exceeds 100 columns
#30360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15075:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#30361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15076:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#30362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15077:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#30363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15078:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#30364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15079:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#30365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15080:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#30366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15081:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc

WARNING: line length of 121 exceeds 100 columns
#30367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15082:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#30368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15083:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15084:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15085:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15086:
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L

WARNING: line length of 113 exceeds 100 columns
#30372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15087:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#30373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15088:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#30374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15089:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2

WARNING: line length of 113 exceeds 100 columns
#30375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15090:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3

WARNING: line length of 113 exceeds 100 columns
#30376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15091:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#30377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15092:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9

WARNING: line length of 114 exceeds 100 columns
#30378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15093:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#30379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15094:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#30380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15095:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12

WARNING: line length of 114 exceeds 100 columns
#30381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15096:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13

WARNING: line length of 121 exceeds 100 columns
#30382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15097:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15098:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15099:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15100:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#30386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15101:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15102:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15103:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15104:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#30390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15105:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#30391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15106:
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L

WARNING: line length of 113 exceeds 100 columns
#30392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15107:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#30393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15108:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15109:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#30395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15110:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#30396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15111:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15112:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#30398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15113:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15114:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15115:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#30401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15116:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#30402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15117:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15118:
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#30404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15119:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#30405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15120:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15121:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#30407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15122:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c

WARNING: line length of 121 exceeds 100 columns
#30408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15123:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15124:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#30410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15125:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#30411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15126:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15127:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#30413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15128:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c

WARNING: line length of 121 exceeds 100 columns
#30414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15129:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15130:
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#30416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15131:
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#30417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15132:
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#30418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15133:
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#30419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15134:
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#30420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15135:
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15136:
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#30422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15137:
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L

WARNING: line length of 121 exceeds 100 columns
#30423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15138:
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#30424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15139:
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#30425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15140:
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#30426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15141:
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15142:
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15143:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#30429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15144:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18

WARNING: line length of 114 exceeds 100 columns
#30430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15145:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#30431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15146:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b

WARNING: line length of 114 exceeds 100 columns
#30432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15147:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c

WARNING: line length of 121 exceeds 100 columns
#30433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15148:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#30434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15149:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#30435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15150:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#30436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15151:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#30437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15152:
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#30438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15153:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#30439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15154:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#30440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15155:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#30441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15156:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#30442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15157:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#30443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15158:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#30444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15159:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#30445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15160:
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15161:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#30447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15162:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#30448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15163:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#30449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15164:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#30450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15165:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#30451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15166:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#30452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15167:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#30453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15168:
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15169:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#30455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15170:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#30456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15171:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#30457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15172:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#30458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15173:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#30459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15174:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#30460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15175:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15176:
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15177:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0

WARNING: line length of 114 exceeds 100 columns
#30463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15178:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#30464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15179:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#30465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15180:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL

WARNING: line length of 121 exceeds 100 columns
#30466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15181:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#30467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15182:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#30468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15183:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15184:
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15185:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#30471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15186:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#30472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15187:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#30473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15188:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18

WARNING: line length of 114 exceeds 100 columns
#30474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15189:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#30475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15190:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#30476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15191:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#30477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15192:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15193:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#30479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15194:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#30480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15195:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#30481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15196:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#30482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15197:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#30483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15198:
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#30484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15199:
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#30485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15200:
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15201:
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#30487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15202:
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15203:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#30489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15204:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#30490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15205:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5

WARNING: line length of 113 exceeds 100 columns
#30491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15206:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6

WARNING: line length of 121 exceeds 100 columns
#30492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15207:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15208:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L

WARNING: line length of 121 exceeds 100 columns
#30494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15209:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#30495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15210:
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L

WARNING: line length of 113 exceeds 100 columns
#30496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15211:
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#30497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15212:
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#30498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15213:
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#30499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15214:
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15215:
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#30501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15216:
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#30502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15217:
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#30503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15218:
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15219:
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#30505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15220:
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#30506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15221:
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#30507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15222:
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L

WARNING: line length of 113 exceeds 100 columns
#30508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15223:
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#30509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15224:
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#30510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15225:
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL

WARNING: line length of 121 exceeds 100 columns
#30511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15226:
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#30512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15227:
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#30513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15228:
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15229:
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#30515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15230:
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#30516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15231:
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#30517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15232:
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#30518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15233:
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#30519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15234:
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15235:
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#30521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15236:
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15237:
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#30523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15238:
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15239:
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#30525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15240:
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15241:
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#30527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15242:
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#30528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15243:
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#30529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15244:
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#30530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15245:
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#30531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15246:
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15247:
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15248:
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15249:
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#30535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15250:
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#30536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15251:
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#30537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15252:
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15253:
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#30539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15254:
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#30540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15255:
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#30541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15256:
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15257:
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#30543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15258:
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#30544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15259:
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#30545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15260:
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15261:
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#30547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15262:
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#30548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15263:
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#30549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15264:
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15265:
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0

WARNING: line length of 114 exceeds 100 columns
#30551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15266:
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10

WARNING: line length of 121 exceeds 100 columns
#30552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15267:
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#30553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15268:
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15269:
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#30555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15270:
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#30556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15271:
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#30557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15272:
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15273:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#30559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15274:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#30560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15275:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#30561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15276:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#30562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15277:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#30563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15278:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#30564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15279:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#30565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15280:
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L

WARNING: line length of 113 exceeds 100 columns
#30566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15281:
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#30567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15282:
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15283:
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#30569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15284:
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#30570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15285:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#30571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15286:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#30572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15287:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#30573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15288:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6

WARNING: line length of 113 exceeds 100 columns
#30574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15289:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#30575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15290:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#30576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15291:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#30577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15292:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe

WARNING: line length of 121 exceeds 100 columns
#30578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15293:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15294:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15295:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#30581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15296:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#30582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15297:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#30583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15298:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15299:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L

WARNING: line length of 121 exceeds 100 columns
#30585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15300:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L

WARNING: line length of 113 exceeds 100 columns
#30586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15301:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#30587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15302:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#30588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15303:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#30589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15304:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6

WARNING: line length of 121 exceeds 100 columns
#30590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15305:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15306:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#30592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15307:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#30593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15308:
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L

WARNING: line length of 113 exceeds 100 columns
#30594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15309:
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15310:
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15311:
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#30597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15312:
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15313:
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#30599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15314:
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15315:
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#30601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15316:
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15317:
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#30603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15318:
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15319:
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15320:
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL

WARNING: line length of 113 exceeds 100 columns
#30606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15321:
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#30607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15322:
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf

WARNING: line length of 114 exceeds 100 columns
#30608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15323:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#30609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15324:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#30610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15325:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#30611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15326:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#30612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15327:
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#30613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15328:
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L

WARNING: line length of 121 exceeds 100 columns
#30614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15329:
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L

WARNING: line length of 121 exceeds 100 columns
#30615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15330:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#30616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15331:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#30617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15332:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#30618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15333:
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#30619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15334:
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#30620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15335:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#30621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15336:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa

WARNING: line length of 114 exceeds 100 columns
#30622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15337:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#30623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15338:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#30624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15339:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#30625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15340:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L

WARNING: line length of 121 exceeds 100 columns
#30626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15341:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15342:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L

WARNING: line length of 121 exceeds 100 columns
#30628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15343:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#30629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15344:
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L

WARNING: line length of 113 exceeds 100 columns
#30630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15345:
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#30631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15346:
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#30632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15347:
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#30633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15348:
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L

WARNING: line length of 113 exceeds 100 columns
#30634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15349:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#30635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15350:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15351:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#30637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15352:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#30638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15353:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15354:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#30640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15355:
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#30641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15356:
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#30642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15357:
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15358:
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15359:
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#30645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15360:
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#30646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15361:
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15362:
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15363:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#30649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15364:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#30650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15365:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#30651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15366:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#30652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15367:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#30653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15368:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6

WARNING: line length of 113 exceeds 100 columns
#30654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15369:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#30655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15370:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#30656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15371:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#30657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15372:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc

WARNING: line length of 113 exceeds 100 columns
#30658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15373:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd

WARNING: line length of 113 exceeds 100 columns
#30659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15374:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#30660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15375:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#30661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15376:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#30662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15377:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12

WARNING: line length of 121 exceeds 100 columns
#30663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15378:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15379:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15380:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15381:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15382:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#30668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15383:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L

WARNING: line length of 121 exceeds 100 columns
#30669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15384:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15385:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15386:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15387:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15388:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#30674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15389:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#30675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15390:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15391:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#30677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15392:
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L

WARNING: line length of 113 exceeds 100 columns
#30678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15393:
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#30679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15394:
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#30680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15395:
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15396:
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15397:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#30683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15398:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#30684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15399:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5

WARNING: line length of 113 exceeds 100 columns
#30685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15400:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#30686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15401:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa

WARNING: line length of 121 exceeds 100 columns
#30687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15402:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15403:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15404:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#30690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15405:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15406:
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L

WARNING: line length of 113 exceeds 100 columns
#30692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15407:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#30693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15408:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#30694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15409:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#30695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15410:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#30696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15411:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc

WARNING: line length of 114 exceeds 100 columns
#30697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15412:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#30698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15413:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#30699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15414:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#30700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15415:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#30701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15416:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#30702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15417:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15418:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15419:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15420:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L

WARNING: line length of 121 exceeds 100 columns
#30706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15421:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15422:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#30708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15423:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#30709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15424:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#30710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15425:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#30711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15426:
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#30712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15427:
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15428:
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15429:
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#30715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15430:
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#30716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15431:
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#30717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15432:
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#30718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15433:
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#30719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15434:
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#30720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15435:
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#30721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15436:
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#30722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15437:
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#30723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15438:
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15439:
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#30725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15440:
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#30726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15441:
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#30727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15442:
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#30728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15443:
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#30729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15444:
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4

WARNING: line length of 114 exceeds 100 columns
#30730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15445:
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12

WARNING: line length of 121 exceeds 100 columns
#30731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15446:
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15447:
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L

WARNING: line length of 121 exceeds 100 columns
#30733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15448:
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L

WARNING: line length of 113 exceeds 100 columns
#30734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15449:
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#30735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15450:
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#30736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15451:
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#30737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15452:
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#30738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15453:
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#30739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15454:
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15455:
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15456:
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#30742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15457:
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#30743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15458:
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L

WARNING: line length of 113 exceeds 100 columns
#30744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15459:
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#30745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15460:
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#30746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15461:
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15462:
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L

WARNING: line length of 113 exceeds 100 columns
#30748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15463:
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#30749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15464:
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15465:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#30751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15466:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#30752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15467:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2

WARNING: line length of 114 exceeds 100 columns
#30753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15468:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#30754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15469:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15470:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15471:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15472:
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15473:
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#30759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15474:
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4

WARNING: line length of 114 exceeds 100 columns
#30760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15475:
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#30761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15476:
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15477:
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#30763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15478:
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#30764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15479:
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#30765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15480:
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#30766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15481:
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#30767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15482:
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15483:
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15484:
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#30770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15485:
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#30771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15486:
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1

WARNING: line length of 114 exceeds 100 columns
#30772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15487:
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#30773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15488:
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15489:
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15490:
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#30776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15491:
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15492:
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15493:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#30779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15494:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#30780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15495:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#30781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15496:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#30782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15497:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#30783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15498:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#30784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15499:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17

WARNING: line length of 114 exceeds 100 columns
#30785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15500:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18

WARNING: line length of 114 exceeds 100 columns
#30786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15501:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19

WARNING: line length of 114 exceeds 100 columns
#30787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15502:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a

WARNING: line length of 114 exceeds 100 columns
#30788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15503:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d

WARNING: line length of 121 exceeds 100 columns
#30789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15504:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#30790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15505:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#30791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15506:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L

WARNING: line length of 121 exceeds 100 columns
#30792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15507:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#30793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15508:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15509:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#30795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15510:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#30796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15511:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#30797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15512:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L

WARNING: line length of 121 exceeds 100 columns
#30798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15513:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#30799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15514:
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#30800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15515:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#30801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15516:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#30802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15517:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#30803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15518:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#30804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15519:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#30805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15520:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15521:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15522:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#30808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15523:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#30809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15524:
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#30810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15525:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#30811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15526:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#30812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15527:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#30813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15528:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#30814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15529:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#30815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15530:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#30816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15531:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#30817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15532:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#30818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15533:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#30819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15534:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12

WARNING: line length of 114 exceeds 100 columns
#30820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15535:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#30821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15536:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16

WARNING: line length of 114 exceeds 100 columns
#30822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15537:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#30823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15538:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#30824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15539:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#30825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15540:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#30826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15541:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15542:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15543:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#30829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15544:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#30830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15545:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#30831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15546:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15547:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L

WARNING: line length of 121 exceeds 100 columns
#30833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15548:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#30834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15549:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#30835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15550:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L

WARNING: line length of 121 exceeds 100 columns
#30836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15551:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#30837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15552:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#30838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15553:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#30839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15554:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#30840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15555:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L

WARNING: line length of 121 exceeds 100 columns
#30841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15556:
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#30842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15557:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#30843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15558:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#30844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15559:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#30845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15560:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#30846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15561:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#30847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15562:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#30848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15563:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#30849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15564:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#30850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15565:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#30851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15566:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#30852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15567:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#30853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15568:
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#30854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15569:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#30855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15570:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#30856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15571:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#30857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15572:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa

WARNING: line length of 121 exceeds 100 columns
#30858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15573:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15574:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15575:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#30861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15576:
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#30862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15577:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#30863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15578:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#30864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15579:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#30865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15580:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#30866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15581:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#30867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15582:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#30868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15583:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6

WARNING: line length of 113 exceeds 100 columns
#30869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15584:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#30870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15585:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#30871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15586:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#30872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15587:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#30873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15588:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#30874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15589:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc

WARNING: line length of 113 exceeds 100 columns
#30875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15590:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd

WARNING: line length of 113 exceeds 100 columns
#30876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15591:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe

WARNING: line length of 113 exceeds 100 columns
#30877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15592:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf

WARNING: line length of 114 exceeds 100 columns
#30878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15593:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#30879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15594:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15595:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15596:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15597:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#30883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15598:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15599:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#30885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15600:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#30886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15601:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#30887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15602:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15603:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#30889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15604:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15605:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#30891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15606:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15607:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#30893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15608:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#30894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15609:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#30895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15610:
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#30896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15611:
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#30897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15612:
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15613:
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#30899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15614:
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d

WARNING: line length of 121 exceeds 100 columns
#30900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15615:
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15616:
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#30902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15617:
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#30903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15618:
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#30904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15619:
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#30905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15620:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#30906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15621:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#30907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15622:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc

WARNING: line length of 113 exceeds 100 columns
#30908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15623:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#30909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15624:
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#30910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15625:
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#30911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15626:
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#30912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15627:
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15628:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15629:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#30915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15630:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15631:
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#30917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15632:
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15633:
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#30919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15634:
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#30920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15635:
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#30921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15636:
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#30922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15637:
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#30923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15638:
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc

WARNING: line length of 121 exceeds 100 columns
#30924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15639:
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15640:
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15641:
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15642:
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#30928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15643:
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#30929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15644:
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#30930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15645:
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15646:
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#30932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15647:
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#30933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15648:
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#30934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15649:
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#30935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15650:
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#30936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15651:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#30937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15652:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#30938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15653:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#30939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15654:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#30940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15655:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#30941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15656:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#30942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15657:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#30943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15658:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#30944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15659:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb

WARNING: line length of 113 exceeds 100 columns
#30945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15660:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe

WARNING: line length of 114 exceeds 100 columns
#30946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15661:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#30947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15662:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15663:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#30949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15664:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#30950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15665:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#30951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15666:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#30952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15667:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#30953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15668:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L

WARNING: line length of 121 exceeds 100 columns
#30954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15669:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L

WARNING: line length of 121 exceeds 100 columns
#30955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15670:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L

WARNING: line length of 121 exceeds 100 columns
#30956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15671:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#30957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15672:
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#30958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15673:
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#30959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15674:
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#30960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15675:
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#30961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15676:
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#30962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15677:
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#30963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15678:
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#30964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15679:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#30965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15680:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#30966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15681:
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#30967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15682:
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#30968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15683:
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd

WARNING: line length of 114 exceeds 100 columns
#30969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15684:
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#30970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15685:
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#30971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15686:
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#30972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15687:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#30973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15688:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#30974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15689:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#30975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15690:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#30976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15691:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#30977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15692:
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#30978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15693:
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#30979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15694:
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#30980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15695:
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#30981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15696:
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#30982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15697:
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#30983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15698:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L

WARNING: line length of 121 exceeds 100 columns
#30984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15699:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#30985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15700:
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#30986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15701:
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15702:
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#30988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15703:
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15704:
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#30990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15705:
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#30991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15706:
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#30992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15707:
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#30993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15708:
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#30994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15709:
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#30995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15710:
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#30996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15711:
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#30997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15712:
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#30998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15713:
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#30999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15714:
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#31000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15715:
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15716:
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L

WARNING: line length of 113 exceeds 100 columns
#31002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15717:
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15718:
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#31004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15719:
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15720:
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15721:
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15722:
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#31008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15723:
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15724:
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15725:
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15726:
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#31012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15727:
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15728:
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15729:
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#31015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15730:
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#31016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15731:
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15732:
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15733:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#31019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15734:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#31020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15735:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#31021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15736:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#31022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15737:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#31023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15738:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#31024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15739:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#31025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15740:
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#31026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15741:
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#31027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15742:
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#31028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15743:
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15744:
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#31030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15745:
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#31031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15746:
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2

WARNING: line length of 121 exceeds 100 columns
#31032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15747:
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15748:
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#31034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15749:
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15750:
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#31036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15751:
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15752:
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15753:
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15754:
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#31040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15755:
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15756:
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15757:
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15758:
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#31044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15759:
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15760:
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15761:
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15762:
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#31048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15763:
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15764:
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15765:
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15766:
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#31052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15767:
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15768:
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15769:
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15770:
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#31056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15771:
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15772:
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15773:
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#31059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15774:
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#31060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15775:
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15776:
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15777:
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#31063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15778:
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#31064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15779:
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15780:
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15781:
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#31067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15782:
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#31068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15783:
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15784:
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15785:
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#31071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15786:
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#31072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15787:
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15788:
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15789:
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#31075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15790:
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#31076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15791:
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15792:
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15793:
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#31079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15794:
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#31080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15795:
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15796:
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15797:
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#31083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15798:
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#31084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15799:
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#31085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15800:
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#31086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15801:
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15802:
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#31088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15803:
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#31089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15804:
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#31090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15805:
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15806:
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#31092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15807:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#31093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15808:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#31094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15809:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#31095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15810:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#31096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15811:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#31097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15812:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7

WARNING: line length of 114 exceeds 100 columns
#31098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15813:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#31099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15814:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15815:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#31101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15816:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15817:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#31103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15818:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L

WARNING: line length of 121 exceeds 100 columns
#31104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15819:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#31105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15820:
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L

WARNING: line length of 113 exceeds 100 columns
#31106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15821:
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#31107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15822:
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15823:
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#31109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15824:
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15825:
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15826:
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#31112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15827:
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15828:
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15829:
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#31115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15830:
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8

WARNING: line length of 114 exceeds 100 columns
#31116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15831:
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#31117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15832:
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15833:
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#31119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15834:
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L

WARNING: line length of 113 exceeds 100 columns
#31120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15835:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#31121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15836:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#31122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15837:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#31123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15838:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#31124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15839:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#31125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15840:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#31126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15841:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L

WARNING: line length of 121 exceeds 100 columns
#31127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15842:
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#31128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15843:
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#31129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15844:
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#31130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15845:
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#31131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15846:
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#31132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15847:
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#31133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15848:
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#31134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15849:
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#31135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15850:
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#31136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15851:
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#31137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15852:
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#31138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15853:
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#31139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15854:
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#31140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15855:
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#31141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15856:
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#31142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15857:
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#31143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15858:
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc

WARNING: line length of 121 exceeds 100 columns
#31144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15859:
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#31145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15860:
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L

WARNING: line length of 121 exceeds 100 columns
#31146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15861:
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L

WARNING: line length of 121 exceeds 100 columns
#31147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15862:
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L

WARNING: line length of 113 exceeds 100 columns
#31148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15863:
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#31149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15864:
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#31150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15865:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#31151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15866:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#31152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15867:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#31153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15868:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#31154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15869:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#31155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15870:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#31156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15871:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15872:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#31158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15873:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L

WARNING: line length of 121 exceeds 100 columns
#31159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15874:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#31160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15875:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#31161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15876:
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L

WARNING: line length of 113 exceeds 100 columns
#31162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15877:
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#31163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15878:
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8

WARNING: line length of 121 exceeds 100 columns
#31164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15879:
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#31165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15880:
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#31166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15881:
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15882:
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15883:
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#31169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15884:
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#31170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15885:
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#31171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15886:
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#31172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15887:
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#31173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15888:
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15889:
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#31175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15890:
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#31176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15891:
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#31177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15892:
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#31178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15893:
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15894:
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15895:
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#31181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15896:
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#31182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15897:
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#31183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15898:
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#31184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15899:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#31185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15900:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#31186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15901:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#31187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15902:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#31188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15903:
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#31189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15904:
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15905:
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#31191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15906:
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#31192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15907:
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#31193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15908:
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#31194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15909:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#31195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15910:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#31196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15911:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#31197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15912:
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#31198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15913:
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#31199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15914:
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#31200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15915:
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15916:
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15917:
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#31203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15918:
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#31204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15919:
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#31205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15920:
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#31206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15921:
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#31207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15922:
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15923:
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#31209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15924:
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L

WARNING: line length of 113 exceeds 100 columns
#31210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15925:
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15926:
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#31212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15927:
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#31213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15928:
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15929:
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#31215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15930:
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10

WARNING: line length of 121 exceeds 100 columns
#31216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15931:
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#31217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15932:
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15933:
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#31219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15934:
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15935:
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#31221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15936:
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15937:
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#31223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15938:
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15939:
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#31225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15940:
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15941:
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15942:
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15943:
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#31229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15944:
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15945:
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#31231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15946:
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#31232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15947:
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#31233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15948:
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15949:
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#31235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15950:
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#31236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15951:
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#31237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15952:
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15953:
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#31239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15954:
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4

WARNING: line length of 121 exceeds 100 columns
#31240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15955:
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15956:
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L

WARNING: line length of 113 exceeds 100 columns
#31242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15957:
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#31243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15958:
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#31244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15959:
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#31245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15960:
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#31246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15961:
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15962:
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#31248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15963:
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L

WARNING: line length of 121 exceeds 100 columns
#31249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15964:
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L

WARNING: line length of 113 exceeds 100 columns
#31250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15965:
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#31251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15966:
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#31252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15967:
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#31253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15968:
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#31254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15969:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#31255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15970:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#31256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15971:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#31257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15972:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#31258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15973:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#31259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15974:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#31260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15975:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#31261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15976:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe

WARNING: line length of 114 exceeds 100 columns
#31262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15977:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#31263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15978:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#31264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15979:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#31265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15980:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16

WARNING: line length of 114 exceeds 100 columns
#31266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15981:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#31267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15982:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a

WARNING: line length of 114 exceeds 100 columns
#31268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15983:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#31269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15984:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15985:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15986:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#31272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15987:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#31273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15988:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#31274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15989:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#31275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15990:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L

WARNING: line length of 121 exceeds 100 columns
#31276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15991:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#31277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15992:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#31278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15993:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#31279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15994:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L

WARNING: line length of 121 exceeds 100 columns
#31280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15995:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#31281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15996:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L

WARNING: line length of 121 exceeds 100 columns
#31282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15997:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#31283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15998:
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L

WARNING: line length of 113 exceeds 100 columns
#31284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:15999:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#31285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16000:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#31286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16001:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#31287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16002:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#31288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16003:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#31289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16004:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa

WARNING: line length of 113 exceeds 100 columns
#31290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16005:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc

WARNING: line length of 121 exceeds 100 columns
#31291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16006:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16007:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#31293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16008:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#31294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16009:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#31295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16010:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L

WARNING: line length of 121 exceeds 100 columns
#31296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16011:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#31297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16012:
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L

WARNING: line length of 113 exceeds 100 columns
#31298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16013:
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#31299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16014:
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#31300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16015:
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#31301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16016:
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#31302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16017:
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16018:
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#31304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16019:
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16020:
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#31306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16021:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#31307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16022:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#31308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16023:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#31309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16024:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#31310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16025:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16026:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16027:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#31313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16028:
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L

WARNING: line length of 113 exceeds 100 columns
#31314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16029:
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#31315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16030:
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8

WARNING: line length of 121 exceeds 100 columns
#31316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16031:
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16032:
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#31318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16033:
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#31319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16034:
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2

WARNING: line length of 121 exceeds 100 columns
#31320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16035:
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16036:
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#31322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16037:
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#31323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16038:
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#31324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16039:
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16040:
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16041:
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#31327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16042:
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#31328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16043:
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16044:
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16045:
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#31331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16046:
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#31332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16047:
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16048:
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16049:
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#31335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16050:
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#31336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16051:
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16052:
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16053:
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#31339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16054:
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#31340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16055:
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16056:
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16057:
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#31343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16058:
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#31344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16059:
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16060:
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16061:
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#31347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16062:
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#31348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16063:
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16064:
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16065:
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#31351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16066:
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#31352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16067:
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16068:
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16069:
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#31355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16070:
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#31356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16071:
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16072:
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16073:
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#31359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16074:
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#31360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16075:
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16076:
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16077:
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#31363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16078:
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#31364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16079:
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16080:
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16081:
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#31367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16082:
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#31368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16083:
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16084:
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16085:
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#31371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16086:
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2

WARNING: line length of 121 exceeds 100 columns
#31372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16087:
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16088:
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#31374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16089:
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16090:
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#31376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16091:
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16092:
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16093:
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16094:
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#31380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16095:
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16096:
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16097:
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16098:
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#31384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16099:
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16100:
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16101:
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16102:
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#31388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16103:
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16104:
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16105:
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16106:
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#31392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16107:
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16108:
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16109:
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#31395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16110:
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#31396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16111:
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16112:
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16113:
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16114:
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16115:
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16116:
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16117:
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16118:
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16119:
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16120:
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16121:
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16122:
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16123:
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16124:
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16125:
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16126:
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16127:
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16128:
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16129:
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16130:
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16131:
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16132:
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16133:
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#31419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16134:
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16135:
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16136:
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16137:
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#31423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16138:
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#31424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16139:
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#31425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16140:
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#31426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16141:
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16142:
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16143:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#31429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16144:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2

WARNING: line length of 113 exceeds 100 columns
#31430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16145:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#31431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16146:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#31432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16147:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#31433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16148:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16149:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16150:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#31436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16151:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#31437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16152:
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#31438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16153:
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#31439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16154:
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#31440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16155:
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#31441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16156:
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16157:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#31443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16158:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#31444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16159:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6

WARNING: line length of 113 exceeds 100 columns
#31445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16160:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7

WARNING: line length of 121 exceeds 100 columns
#31446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16161:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#31447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16162:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#31448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16163:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#31449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16164:
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#31450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16165:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#31451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16166:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#31452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16167:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#31453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16168:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#31454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16169:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#31455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16170:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#31456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16171:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#31457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16172:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#31458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16173:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#31459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16174:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#31460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16175:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#31461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16176:
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#31462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16177:
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#31463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16178:
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16179:
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#31465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16180:
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16181:
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#31467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16182:
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16183:
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#31469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16184:
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16185:
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#31471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16186:
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16187:
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#31473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16188:
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16189:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#31475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16190:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16191:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#31477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16192:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#31478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16193:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16194:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16195:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#31481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16196:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16197:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#31483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16198:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#31484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16199:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16200:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16201:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#31487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16202:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16203:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#31489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16204:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#31490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16205:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16206:
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16207:
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16208:
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#31494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16209:
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16210:
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#31496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16211:
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16212:
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#31498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16213:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16214:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16215:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16216:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16217:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16218:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16219:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16220:
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16221:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16222:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16223:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16224:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16225:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16226:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16227:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16228:
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16229:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16230:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16231:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16232:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16233:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16234:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16235:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16236:
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16237:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16238:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16239:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16240:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16241:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16242:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16243:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16244:
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16245:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16246:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16247:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16248:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16249:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16250:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16251:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16252:
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16253:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16254:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16255:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16256:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16257:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16258:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16259:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16260:
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16261:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16262:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16263:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16264:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16265:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16266:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16267:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16268:
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16269:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16270:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16271:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16272:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16273:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16274:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16275:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16276:
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16277:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16278:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16279:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16280:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16281:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16282:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16283:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16284:
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16285:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16286:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16287:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16288:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16289:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16290:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16291:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16292:
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16293:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16294:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16295:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16296:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16297:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16298:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16299:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16300:
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16301:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16302:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16303:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16304:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16305:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16306:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16307:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16308:
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16309:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16310:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16311:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16312:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16313:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16314:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16315:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16316:
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16317:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16318:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16319:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16320:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16321:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16322:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16323:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16324:
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16325:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16326:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16327:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16328:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16329:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16330:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16331:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16332:
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16333:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16334:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16335:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16336:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16337:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16338:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16339:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16340:
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16341:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16342:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16343:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16344:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16345:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16346:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16347:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16348:
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16349:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#31635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16350:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#31636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16351:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#31637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16352:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#31638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16353:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#31639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16354:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#31640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16355:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#31641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16356:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#31642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16357:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#31643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16358:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#31644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16359:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#31645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16360:
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#31646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16361:
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#31647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16362:
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16363:
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#31649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16364:
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16365:
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#31651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16366:
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16367:
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#31653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16368:
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16369:
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#31655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16370:
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16371:
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#31657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16372:
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16373:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#31659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16374:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16375:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#31661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16376:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#31662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16377:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16378:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16379:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#31665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16380:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16381:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#31667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16382:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#31668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16383:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16384:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16385:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#31671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16386:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#31672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16387:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#31673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16388:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#31674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16389:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16390:
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16391:
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16392:
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#31678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16393:
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16394:
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#31680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16395:
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#31681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16396:
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#31682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16397:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16398:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16399:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16400:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16401:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16402:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16403:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16404:
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16405:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16406:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16407:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16408:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16409:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16410:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16411:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16412:
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16413:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16414:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16415:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16416:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16417:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16418:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16419:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16420:
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16421:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16422:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16423:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16424:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16425:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16426:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16427:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16428:
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16429:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#31715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16430:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#31716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16431:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#31717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16432:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16433:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16434:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16435:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16436:
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16437:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16438:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16439:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16440:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16441:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16442:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16443:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16444:
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16445:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16446:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16447:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16448:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16449:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16450:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16451:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16452:
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16453:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16454:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16455:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16456:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16457:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16458:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16459:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16460:
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16461:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16462:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16463:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16464:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16465:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16466:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16467:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16468:
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16469:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16470:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16471:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16472:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16473:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16474:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16475:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16476:
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16477:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16478:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16479:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16480:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16481:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16482:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16483:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16484:
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16485:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16486:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16487:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16488:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16489:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16490:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16491:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16492:
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16493:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16494:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16495:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16496:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16497:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16498:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16499:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16500:
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16501:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16502:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16503:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16504:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16505:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16506:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16507:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16508:
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16509:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16510:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16511:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16512:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16513:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16514:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16515:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16516:
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16517:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16518:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16519:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16520:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16521:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16522:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16523:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16524:
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16525:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#31811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16526:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#31812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16527:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#31813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16528:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#31814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16529:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16530:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16531:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#31817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16532:
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16533:
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#31819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16534:
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#31820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16535:
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#31821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16536:
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2

WARNING: line length of 121 exceeds 100 columns
#31822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16537:
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16538:
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L

WARNING: line length of 113 exceeds 100 columns
#31824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16539:
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#31825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16540:
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#31826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16541:
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#31827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16542:
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1

WARNING: line length of 121 exceeds 100 columns
#31828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16543:
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16544:
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L

WARNING: line length of 113 exceeds 100 columns
#31830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16545:
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#31831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16546:
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#31832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16547:
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#31833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16548:
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16549:
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#31835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16550:
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#31836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16551:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#31837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16552:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#31838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16553:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#31839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16554:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#31840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16555:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#31841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16556:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#31842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16557:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#31843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16558:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#31844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16559:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#31845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16560:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#31846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16561:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#31847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16562:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#31848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16563:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#31849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16564:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#31850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16565:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#31851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16566:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#31852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16567:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#31853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16568:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#31854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16569:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#31855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16570:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#31856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16571:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#31857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16572:
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#31858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16573:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#31859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16574:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#31860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16575:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#31861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16576:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#31862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16577:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#31863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16578:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16579:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16580:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#31866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16581:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#31867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16582:
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#31868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16583:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#31869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16584:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#31870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16585:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#31871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16586:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#31872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16587:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#31873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16588:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#31874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16589:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#31875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16590:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#31876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16591:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#31877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16592:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#31878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16593:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#31879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16594:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#31880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16595:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#31881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16596:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#31882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16597:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#31883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16598:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#31884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16599:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16600:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16601:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#31887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16602:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#31888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16603:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#31889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16604:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#31890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16605:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#31891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16606:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#31892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16607:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#31893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16608:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#31894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16609:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#31895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16610:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#31896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16611:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#31897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16612:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#31898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16613:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#31899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16614:
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#31900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16615:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#31901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16616:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#31902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16617:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#31903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16618:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#31904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16619:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#31905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16620:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#31906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16621:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#31907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16622:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#31908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16623:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#31909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16624:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#31910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16625:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#31911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16626:
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#31912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16627:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#31913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16628:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#31914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16629:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#31915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16630:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#31916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16631:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16632:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#31918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16633:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#31919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16634:
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#31920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16635:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#31921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16636:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#31922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16637:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#31923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16638:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#31924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16639:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#31925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16640:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#31926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16641:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#31927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16642:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#31928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16643:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#31929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16644:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#31930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16645:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#31931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16646:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#31932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16647:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#31933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16648:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#31934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16649:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#31935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16650:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#31936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16651:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#31937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16652:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16653:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#31939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16654:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#31940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16655:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#31941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16656:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#31942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16657:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#31943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16658:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#31944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16659:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#31945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16660:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#31946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16661:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#31947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16662:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#31948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16663:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#31949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16664:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#31950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16665:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#31951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16666:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#31952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16667:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#31953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16668:
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16669:
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#31955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16670:
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16671:
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#31957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16672:
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#31958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16673:
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16674:
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#31960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16675:
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#31961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16676:
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#31962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16677:
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#31963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16678:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#31964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16679:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#31965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16680:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc

WARNING: line length of 113 exceeds 100 columns
#31966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16681:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#31967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16682:
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#31968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16683:
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#31969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16684:
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#31970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16685:
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#31971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16686:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#31972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16687:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#31973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16688:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#31974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16689:
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#31975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16690:
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#31976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16691:
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#31977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16692:
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#31978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16693:
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#31979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16694:
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#31980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16695:
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#31981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16696:
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc

WARNING: line length of 121 exceeds 100 columns
#31982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16697:
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#31983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16698:
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#31984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16699:
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#31985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16700:
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#31986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16701:
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16702:
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#31988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16703:
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16704:
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16705:
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#31991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16706:
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#31992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16707:
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#31993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16708:
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#31994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16709:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#31995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16710:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#31996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16711:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#31997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16712:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#31998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16713:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#31999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16714:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#32000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16715:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#32001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16716:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#32002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16717:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb

WARNING: line length of 113 exceeds 100 columns
#32003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16718:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe

WARNING: line length of 114 exceeds 100 columns
#32004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16719:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#32005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16720:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16721:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#32007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16722:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16723:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#32009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16724:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#32010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16725:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#32011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16726:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L

WARNING: line length of 121 exceeds 100 columns
#32012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16727:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L

WARNING: line length of 121 exceeds 100 columns
#32013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16728:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L

WARNING: line length of 121 exceeds 100 columns
#32014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16729:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#32015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16730:
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16731:
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#32017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16732:
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#32018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16733:
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#32019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16734:
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#32020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16735:
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#32021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16736:
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#32022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16737:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#32023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16738:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#32024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16739:
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#32025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16740:
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#32026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16741:
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd

WARNING: line length of 114 exceeds 100 columns
#32027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16742:
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#32028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16743:
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#32029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16744:
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#32030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16745:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#32031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16746:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#32032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16747:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#32033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16748:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16749:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#32035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16750:
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#32036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16751:
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#32037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16752:
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#32038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16753:
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#32039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16754:
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#32040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16755:
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#32041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16756:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L

WARNING: line length of 121 exceeds 100 columns
#32042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16757:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#32043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16758:
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#32044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16759:
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#32045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16760:
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16761:
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#32047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16762:
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16763:
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#32049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16764:
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16765:
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#32051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16766:
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16767:
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#32053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16768:
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16769:
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#32055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16770:
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16771:
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#32057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16772:
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#32058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16773:
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16774:
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L

WARNING: line length of 113 exceeds 100 columns
#32060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16775:
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16776:
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#32062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16777:
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16778:
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16779:
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16780:
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#32066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16781:
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16782:
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16783:
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16784:
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#32070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16785:
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16786:
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16787:
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#32073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16788:
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#32074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16789:
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16790:
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16791:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#32077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16792:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#32078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16793:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#32079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16794:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#32080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16795:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#32081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16796:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#32082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16797:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#32083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16798:
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#32084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16799:
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#32085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16800:
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#32086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16801:
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16802:
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#32088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16803:
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#32089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16804:
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2

WARNING: line length of 121 exceeds 100 columns
#32090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16805:
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16806:
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#32092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16807:
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#32093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16808:
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#32094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16809:
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16810:
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16811:
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#32097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16812:
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#32098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16813:
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16814:
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16815:
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#32101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16816:
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#32102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16817:
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16818:
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16819:
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#32105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16820:
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#32106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16821:
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16822:
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16823:
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#32109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16824:
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#32110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16825:
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16826:
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16827:
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#32113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16828:
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#32114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16829:
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16830:
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16831:
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#32117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16832:
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#32118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16833:
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16834:
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16835:
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#32121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16836:
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#32122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16837:
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16838:
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16839:
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#32125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16840:
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#32126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16841:
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16842:
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16843:
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#32129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16844:
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#32130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16845:
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16846:
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16847:
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#32133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16848:
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#32134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16849:
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16850:
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16851:
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#32137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16852:
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#32138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16853:
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16854:
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16855:
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#32141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16856:
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#32142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16857:
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#32143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16858:
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#32144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16859:
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16860:
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#32146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16861:
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#32147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16862:
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#32148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16863:
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16864:
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#32150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16865:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#32151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16866:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#32152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16867:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#32153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16868:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#32154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16869:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#32155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16870:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7

WARNING: line length of 114 exceeds 100 columns
#32156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16871:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#32157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16872:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16873:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#32159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16874:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16875:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#32161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16876:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L

WARNING: line length of 121 exceeds 100 columns
#32162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16877:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#32163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16878:
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L

WARNING: line length of 113 exceeds 100 columns
#32164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16879:
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#32165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16880:
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#32166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16881:
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#32167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16882:
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#32168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16883:
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16884:
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#32170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16885:
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16886:
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16887:
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#32173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16888:
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8

WARNING: line length of 114 exceeds 100 columns
#32174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16889:
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#32175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16890:
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16891:
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#32177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16892:
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L

WARNING: line length of 113 exceeds 100 columns
#32178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16893:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#32179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16894:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#32180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16895:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#32181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16896:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#32182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16897:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#32183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16898:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#32184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16899:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L

WARNING: line length of 121 exceeds 100 columns
#32185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16900:
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#32186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16901:
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#32187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16902:
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#32188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16903:
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#32189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16904:
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#32190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16905:
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#32191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16906:
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#32192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16907:
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#32193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16908:
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#32194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16909:
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#32195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16910:
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#32196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16911:
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#32197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16912:
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#32198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16913:
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#32199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16914:
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#32200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16915:
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#32201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16916:
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc

WARNING: line length of 121 exceeds 100 columns
#32202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16917:
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#32203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16918:
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L

WARNING: line length of 121 exceeds 100 columns
#32204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16919:
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L

WARNING: line length of 121 exceeds 100 columns
#32205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16920:
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L

WARNING: line length of 113 exceeds 100 columns
#32206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16921:
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#32207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16922:
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#32208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16923:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#32209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16924:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#32210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16925:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#32211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16926:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#32212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16927:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#32213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16928:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#32214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16929:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16930:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#32216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16931:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L

WARNING: line length of 121 exceeds 100 columns
#32217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16932:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#32218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16933:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#32219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16934:
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L

WARNING: line length of 113 exceeds 100 columns
#32220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16935:
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#32221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16936:
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8

WARNING: line length of 121 exceeds 100 columns
#32222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16937:
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#32223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16938:
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#32224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16939:
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16940:
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#32226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16941:
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#32227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16942:
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#32228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16943:
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#32229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16944:
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#32230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16945:
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#32231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16946:
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#32232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16947:
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#32233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16948:
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#32234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16949:
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#32235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16950:
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#32236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16951:
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16952:
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#32238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16953:
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#32239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16954:
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#32240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16955:
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#32241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16956:
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#32242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16957:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#32243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16958:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#32244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16959:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#32245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16960:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#32246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16961:
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#32247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16962:
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#32248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16963:
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#32249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16964:
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#32250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16965:
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#32251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16966:
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#32252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16967:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#32253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16968:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#32254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16969:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#32255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16970:
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#32256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16971:
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#32257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16972:
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#32258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16973:
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16974:
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16975:
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#32261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16976:
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#32262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16977:
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#32263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16978:
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#32264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16979:
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#32265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16980:
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16981:
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#32267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16982:
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L

WARNING: line length of 113 exceeds 100 columns
#32268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16983:
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#32269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16984:
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#32270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16985:
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#32271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16986:
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16987:
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#32273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16988:
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10

WARNING: line length of 121 exceeds 100 columns
#32274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16989:
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#32275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16990:
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16991:
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#32277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16992:
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16993:
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#32279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16994:
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16995:
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#32281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16996:
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16997:
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#32283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16998:
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:16999:
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17000:
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17001:
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#32287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17002:
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17003:
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#32289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17004:
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#32290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17005:
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#32291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17006:
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17007:
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#32293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17008:
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#32294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17009:
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#32295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17010:
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17011:
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#32297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17012:
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4

WARNING: line length of 121 exceeds 100 columns
#32298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17013:
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17014:
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L

WARNING: line length of 113 exceeds 100 columns
#32300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17015:
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#32301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17016:
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#32302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17017:
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#32303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17018:
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#32304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17019:
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17020:
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#32306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17021:
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L

WARNING: line length of 121 exceeds 100 columns
#32307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17022:
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L

WARNING: line length of 113 exceeds 100 columns
#32308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17023:
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#32309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17024:
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#32310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17025:
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#32311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17026:
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#32312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17027:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#32313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17028:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#32314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17029:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#32315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17030:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#32316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17031:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#32317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17032:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#32318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17033:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#32319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17034:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe

WARNING: line length of 114 exceeds 100 columns
#32320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17035:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#32321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17036:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#32322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17037:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#32323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17038:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16

WARNING: line length of 114 exceeds 100 columns
#32324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17039:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#32325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17040:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a

WARNING: line length of 114 exceeds 100 columns
#32326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17041:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#32327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17042:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17043:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17044:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#32330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17045:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#32331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17046:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#32332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17047:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#32333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17048:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L

WARNING: line length of 121 exceeds 100 columns
#32334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17049:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#32335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17050:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#32336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17051:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#32337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17052:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L

WARNING: line length of 121 exceeds 100 columns
#32338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17053:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#32339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17054:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L

WARNING: line length of 121 exceeds 100 columns
#32340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17055:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#32341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17056:
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L

WARNING: line length of 113 exceeds 100 columns
#32342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17057:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#32343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17058:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#32344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17059:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#32345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17060:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#32346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17061:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#32347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17062:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa

WARNING: line length of 113 exceeds 100 columns
#32348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17063:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc

WARNING: line length of 121 exceeds 100 columns
#32349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17064:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17065:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#32351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17066:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#32352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17067:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#32353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17068:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L

WARNING: line length of 121 exceeds 100 columns
#32354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17069:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#32355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17070:
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L

WARNING: line length of 113 exceeds 100 columns
#32356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17071:
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#32357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17072:
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#32358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17073:
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#32359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17074:
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#32360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17075:
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17076:
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#32362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17077:
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17078:
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#32364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17079:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#32365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17080:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#32366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17081:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#32367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17082:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#32368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17083:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17084:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17085:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#32371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17086:
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L

WARNING: line length of 113 exceeds 100 columns
#32372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17087:
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#32373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17088:
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8

WARNING: line length of 121 exceeds 100 columns
#32374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17089:
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17090:
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#32376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17091:
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#32377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17092:
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2

WARNING: line length of 121 exceeds 100 columns
#32378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17093:
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17094:
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#32380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17095:
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#32381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17096:
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#32382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17097:
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17098:
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17099:
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#32385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17100:
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#32386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17101:
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17102:
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17103:
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#32389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17104:
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#32390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17105:
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17106:
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17107:
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#32393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17108:
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#32394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17109:
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17110:
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17111:
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#32397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17112:
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#32398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17113:
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17114:
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17115:
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#32401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17116:
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#32402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17117:
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17118:
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17119:
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#32405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17120:
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#32406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17121:
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17122:
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17123:
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#32409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17124:
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#32410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17125:
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17126:
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17127:
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#32413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17128:
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#32414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17129:
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17130:
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17131:
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#32417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17132:
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#32418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17133:
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17134:
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17135:
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#32421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17136:
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#32422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17137:
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17138:
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17139:
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#32425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17140:
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#32426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17141:
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17142:
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17143:
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#32429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17144:
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2

WARNING: line length of 121 exceeds 100 columns
#32430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17145:
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17146:
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#32432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17147:
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17148:
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#32434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17149:
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17150:
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17151:
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17152:
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#32438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17153:
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17154:
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17155:
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17156:
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#32442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17157:
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17158:
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17159:
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17160:
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#32446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17161:
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17162:
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17163:
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17164:
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#32450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17165:
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17166:
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17167:
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#32453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17168:
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#32454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17169:
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17170:
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17171:
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17172:
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17173:
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17174:
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17175:
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17176:
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17177:
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17178:
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17179:
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17180:
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17181:
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17182:
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17183:
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17184:
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17185:
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17186:
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17187:
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17188:
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17189:
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17190:
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17191:
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#32477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17192:
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17193:
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17194:
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17195:
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#32481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17196:
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#32482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17197:
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#32483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17198:
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#32484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17199:
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17200:
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17201:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#32487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17202:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2

WARNING: line length of 113 exceeds 100 columns
#32488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17203:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#32489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17204:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#32490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17205:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#32491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17206:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17207:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17208:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#32494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17209:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#32495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17210:
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#32496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17211:
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#32497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17212:
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#32498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17213:
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#32499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17214:
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17215:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#32501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17216:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#32502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17217:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6

WARNING: line length of 113 exceeds 100 columns
#32503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17218:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7

WARNING: line length of 121 exceeds 100 columns
#32504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17219:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#32505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17220:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#32506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17221:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#32507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17222:
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#32508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17223:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#32509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17224:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#32510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17225:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#32511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17226:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#32512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17227:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#32513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17228:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#32514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17229:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#32515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17230:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#32516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17231:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#32517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17232:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#32518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17233:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#32519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17234:
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#32520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17235:
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#32521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17236:
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17237:
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#32523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17238:
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17239:
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#32525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17240:
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17241:
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#32527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17242:
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17243:
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#32529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17244:
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17245:
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#32531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17246:
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17247:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#32533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17248:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17249:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#32535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17250:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#32536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17251:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17252:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17253:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#32539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17254:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17255:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#32541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17256:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#32542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17257:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17258:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17259:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#32545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17260:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17261:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#32547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17262:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#32548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17263:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17264:
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17265:
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17266:
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17267:
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17268:
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17269:
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17270:
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17271:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17272:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17273:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17274:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17275:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17276:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17277:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17278:
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17279:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17280:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17281:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17282:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17283:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17284:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17285:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17286:
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17287:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17288:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17289:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17290:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17291:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17292:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17293:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17294:
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17295:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17296:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17297:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17298:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17299:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17300:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17301:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17302:
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17303:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17304:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17305:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17306:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17307:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17308:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17309:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17310:
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17311:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17312:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17313:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17314:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17315:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17316:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17317:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17318:
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17319:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17320:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17321:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17322:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17323:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17324:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17325:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17326:
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17327:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17328:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17329:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17330:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17331:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17332:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17333:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17334:
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17335:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17336:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17337:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17338:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17339:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17340:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17341:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17342:
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17343:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17344:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17345:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17346:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17347:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17348:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17349:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17350:
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17351:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17352:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17353:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17354:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17355:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17356:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17357:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17358:
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17359:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17360:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17361:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17362:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17363:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17364:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17365:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17366:
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17367:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17368:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17369:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17370:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17371:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17372:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17373:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17374:
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17375:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17376:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17377:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17378:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17379:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17380:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17381:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17382:
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17383:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17384:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17385:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17386:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17387:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17388:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17389:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17390:
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17391:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17392:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17393:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17394:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17395:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17396:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17397:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17398:
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17399:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17400:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17401:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17402:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17403:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17404:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17405:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17406:
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17407:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#32693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17408:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#32694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17409:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#32695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17410:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#32696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17411:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#32697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17412:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#32698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17413:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#32699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17414:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#32700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17415:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#32701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17416:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#32702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17417:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#32703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17418:
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#32704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17419:
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#32705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17420:
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17421:
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#32707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17422:
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17423:
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#32709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17424:
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17425:
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#32711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17426:
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17427:
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#32713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17428:
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17429:
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#32715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17430:
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17431:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#32717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17432:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17433:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#32719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17434:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#32720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17435:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17436:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17437:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#32723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17438:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17439:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#32725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17440:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#32726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17441:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17442:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17443:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#32729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17444:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#32730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17445:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#32731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17446:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#32732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17447:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#32733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17448:
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#32734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17449:
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17450:
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17451:
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17452:
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17453:
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#32739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17454:
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17455:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17456:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17457:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17458:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17459:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17460:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17461:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17462:
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17463:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17464:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17465:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17466:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17467:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17468:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17469:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17470:
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17471:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17472:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17473:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17474:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17475:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17476:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17477:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17478:
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17479:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17480:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17481:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17482:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17483:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17484:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17485:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17486:
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17487:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#32773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17488:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#32774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17489:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#32775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17490:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#32776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17491:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17492:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17493:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17494:
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17495:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17496:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17497:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17498:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17499:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17500:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17501:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17502:
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17503:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17504:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17505:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17506:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17507:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17508:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17509:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17510:
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17511:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17512:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17513:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17514:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17515:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17516:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17517:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17518:
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17519:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17520:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17521:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17522:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17523:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17524:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17525:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17526:
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17527:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17528:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17529:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17530:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17531:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17532:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17533:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17534:
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17535:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17536:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17537:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17538:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17539:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17540:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17541:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17542:
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17543:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17544:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17545:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17546:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17547:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17548:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17549:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17550:
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17551:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17552:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17553:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17554:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17555:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17556:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17557:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17558:
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17559:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17560:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17561:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17562:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17563:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17564:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17565:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17566:
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17567:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17568:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17569:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17570:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17571:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17572:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17573:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17574:
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17575:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17576:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17577:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17578:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17579:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17580:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17581:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17582:
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17583:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#32869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17584:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#32870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17585:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#32871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17586:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#32872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17587:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17588:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17589:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#32875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17590:
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#32876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17591:
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#32877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17592:
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#32878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17593:
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#32879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17594:
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2

WARNING: line length of 121 exceeds 100 columns
#32880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17595:
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17596:
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L

WARNING: line length of 113 exceeds 100 columns
#32882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17597:
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#32883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17598:
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#32884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17599:
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#32885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17600:
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1

WARNING: line length of 121 exceeds 100 columns
#32886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17601:
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17602:
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L

WARNING: line length of 113 exceeds 100 columns
#32888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17603:
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#32889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17604:
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#32890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17605:
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#32891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17606:
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17607:
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#32893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17608:
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#32894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17609:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#32895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17610:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#32896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17611:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#32897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17612:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#32898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17613:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#32899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17614:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#32900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17615:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#32901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17616:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#32902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17617:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#32903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17618:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#32904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17619:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#32905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17620:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#32906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17621:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#32907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17622:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#32908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17623:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#32909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17624:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#32910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17625:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#32911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17626:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#32912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17627:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#32913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17628:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#32914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17629:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#32915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17630:
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#32916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17631:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#32917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17632:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#32918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17633:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#32919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17634:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#32920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17635:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#32921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17636:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17637:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17638:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#32924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17639:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#32925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17640:
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#32926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17641:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#32927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17642:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#32928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17643:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#32929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17644:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#32930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17645:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#32931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17646:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#32932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17647:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#32933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17648:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#32934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17649:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#32935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17650:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#32936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17651:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#32937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17652:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#32938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17653:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#32939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17654:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#32940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17655:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#32941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17656:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#32942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17657:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17658:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17659:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#32945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17660:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#32946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17661:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#32947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17662:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#32948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17663:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#32949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17664:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#32950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17665:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#32951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17666:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#32952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17667:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#32953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17668:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#32954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17669:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#32955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17670:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#32956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17671:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#32957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17672:
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#32958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17673:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#32959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17674:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#32960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17675:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#32961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17676:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#32962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17677:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#32963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17678:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#32964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17679:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#32965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17680:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#32966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17681:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#32967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17682:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#32968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17683:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#32969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17684:
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#32970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17685:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#32971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17686:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#32972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17687:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#32973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17688:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#32974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17689:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17690:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#32976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17691:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#32977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17692:
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#32978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17693:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#32979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17694:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#32980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17695:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#32981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17696:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#32982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17697:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#32983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17698:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#32984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17699:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#32985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17700:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#32986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17701:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#32987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17702:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#32988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17703:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#32989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17704:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#32990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17705:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#32991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17706:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#32992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17707:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#32993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17708:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#32994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17709:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#32995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17710:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#32996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17711:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#32997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17712:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#32998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17713:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#32999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17714:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#33000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17715:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#33001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17716:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#33002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17717:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#33003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17718:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#33004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17719:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#33005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17720:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#33006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17721:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#33007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17722:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#33008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17723:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#33009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17724:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#33010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17725:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#33011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17726:
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17727:
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#33013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17728:
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17729:
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#33015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17730:
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#33016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17731:
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17732:
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#33018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17733:
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#33019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17734:
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17735:
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#33021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17736:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#33022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17737:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#33023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17738:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc

WARNING: line length of 113 exceeds 100 columns
#33024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17739:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#33025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17740:
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#33026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17741:
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#33027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17742:
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17743:
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#33029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17744:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#33030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17745:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#33031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17746:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#33032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17747:
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#33033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17748:
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#33034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17749:
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#33035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17750:
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17751:
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#33037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17752:
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#33038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17753:
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#33039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17754:
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc

WARNING: line length of 121 exceeds 100 columns
#33040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17755:
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17756:
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#33042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17757:
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#33043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17758:
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#33044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17759:
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17760:
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#33046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17761:
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17762:
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17763:
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17764:
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#33050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17765:
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17766:
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17767:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#33053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17768:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#33054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17769:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#33055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17770:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#33056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17771:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#33057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17772:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#33058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17773:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#33059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17774:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#33060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17775:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb

WARNING: line length of 113 exceeds 100 columns
#33061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17776:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe

WARNING: line length of 114 exceeds 100 columns
#33062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17777:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#33063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17778:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17779:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#33065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17780:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#33066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17781:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#33067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17782:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#33068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17783:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#33069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17784:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L

WARNING: line length of 121 exceeds 100 columns
#33070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17785:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L

WARNING: line length of 121 exceeds 100 columns
#33071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17786:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L

WARNING: line length of 121 exceeds 100 columns
#33072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17787:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#33073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17788:
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17789:
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#33075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17790:
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#33076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17791:
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#33077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17792:
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#33078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17793:
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#33079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17794:
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#33080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17795:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#33081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17796:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#33082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17797:
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#33083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17798:
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#33084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17799:
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd

WARNING: line length of 114 exceeds 100 columns
#33085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17800:
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#33086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17801:
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#33087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17802:
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#33088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17803:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#33089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17804:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#33090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17805:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#33091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17806:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17807:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#33093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17808:
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#33094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17809:
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#33095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17810:
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#33096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17811:
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#33097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17812:
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#33098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17813:
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#33099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17814:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L

WARNING: line length of 121 exceeds 100 columns
#33100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17815:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#33101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17816:
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#33102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17817:
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#33103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17818:
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17819:
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#33105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17820:
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17821:
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#33107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17822:
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17823:
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#33109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17824:
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17825:
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#33111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17826:
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17827:
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#33113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17828:
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17829:
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#33115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17830:
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#33116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17831:
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17832:
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L

WARNING: line length of 113 exceeds 100 columns
#33118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17833:
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17834:
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#33120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17835:
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17836:
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17837:
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17838:
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#33124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17839:
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17840:
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17841:
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17842:
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#33128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17843:
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17844:
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17845:
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#33131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17846:
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#33132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17847:
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17848:
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17849:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#33135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17850:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#33136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17851:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#33137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17852:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#33138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17853:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#33139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17854:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#33140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17855:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#33141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17856:
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#33142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17857:
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#33143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17858:
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#33144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17859:
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17860:
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#33146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17861:
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#33147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17862:
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2

WARNING: line length of 121 exceeds 100 columns
#33148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17863:
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17864:
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#33150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17865:
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17866:
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#33152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17867:
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17868:
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17869:
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17870:
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#33156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17871:
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17872:
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17873:
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17874:
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#33160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17875:
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17876:
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17877:
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17878:
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#33164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17879:
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17880:
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17881:
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17882:
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#33168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17883:
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17884:
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17885:
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17886:
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#33172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17887:
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17888:
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17889:
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#33175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17890:
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#33176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17891:
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17892:
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17893:
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#33179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17894:
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#33180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17895:
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17896:
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17897:
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#33183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17898:
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#33184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17899:
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17900:
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17901:
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#33187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17902:
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#33188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17903:
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17904:
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17905:
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#33191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17906:
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#33192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17907:
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17908:
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17909:
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#33195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17910:
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#33196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17911:
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17912:
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17913:
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#33199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17914:
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#33200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17915:
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#33201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17916:
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#33202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17917:
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17918:
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#33204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17919:
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#33205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17920:
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#33206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17921:
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17922:
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#33208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17923:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#33209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17924:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#33210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17925:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#33211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17926:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#33212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17927:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#33213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17928:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7

WARNING: line length of 114 exceeds 100 columns
#33214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17929:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#33215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17930:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17931:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#33217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17932:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#33218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17933:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#33219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17934:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L

WARNING: line length of 121 exceeds 100 columns
#33220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17935:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#33221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17936:
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L

WARNING: line length of 113 exceeds 100 columns
#33222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17937:
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#33223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17938:
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17939:
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#33225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17940:
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17941:
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17942:
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#33228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17943:
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17944:
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17945:
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#33231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17946:
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8

WARNING: line length of 114 exceeds 100 columns
#33232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17947:
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#33233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17948:
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17949:
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#33235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17950:
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L

WARNING: line length of 113 exceeds 100 columns
#33236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17951:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#33237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17952:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#33238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17953:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#33239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17954:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#33240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17955:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#33241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17956:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#33242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17957:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L

WARNING: line length of 121 exceeds 100 columns
#33243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17958:
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#33244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17959:
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#33245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17960:
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#33246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17961:
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#33247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17962:
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#33248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17963:
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#33249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17964:
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#33250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17965:
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#33251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17966:
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#33252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17967:
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#33253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17968:
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#33254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17969:
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#33255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17970:
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#33256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17971:
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#33257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17972:
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#33258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17973:
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#33259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17974:
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc

WARNING: line length of 121 exceeds 100 columns
#33260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17975:
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#33261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17976:
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L

WARNING: line length of 121 exceeds 100 columns
#33262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17977:
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L

WARNING: line length of 121 exceeds 100 columns
#33263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17978:
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L

WARNING: line length of 113 exceeds 100 columns
#33264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17979:
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#33265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17980:
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#33266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17981:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#33267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17982:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#33268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17983:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#33269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17984:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#33270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17985:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#33271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17986:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#33272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17987:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17988:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#33274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17989:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L

WARNING: line length of 121 exceeds 100 columns
#33275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17990:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#33276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17991:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#33277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17992:
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L

WARNING: line length of 113 exceeds 100 columns
#33278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17993:
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#33279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17994:
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8

WARNING: line length of 121 exceeds 100 columns
#33280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17995:
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#33281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17996:
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#33282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17997:
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17998:
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:17999:
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#33285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18000:
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#33286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18001:
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#33287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18002:
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#33288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18003:
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#33289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18004:
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18005:
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#33291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18006:
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#33292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18007:
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#33293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18008:
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#33294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18009:
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18010:
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18011:
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#33297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18012:
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#33298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18013:
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#33299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18014:
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#33300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18015:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#33301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18016:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#33302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18017:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#33303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18018:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#33304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18019:
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#33305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18020:
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#33306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18021:
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#33307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18022:
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#33308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18023:
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#33309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18024:
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#33310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18025:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#33311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18026:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#33312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18027:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#33313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18028:
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#33314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18029:
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#33315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18030:
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#33316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18031:
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18032:
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18033:
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#33319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18034:
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#33320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18035:
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#33321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18036:
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#33322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18037:
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#33323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18038:
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18039:
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#33325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18040:
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L

WARNING: line length of 113 exceeds 100 columns
#33326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18041:
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#33327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18042:
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#33328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18043:
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#33329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18044:
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18045:
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#33331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18046:
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10

WARNING: line length of 121 exceeds 100 columns
#33332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18047:
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#33333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18048:
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18049:
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#33335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18050:
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18051:
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#33337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18052:
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18053:
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#33339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18054:
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18055:
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#33341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18056:
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18057:
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18058:
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18059:
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#33345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18060:
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18061:
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#33347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18062:
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#33348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18063:
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#33349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18064:
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18065:
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#33351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18066:
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#33352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18067:
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#33353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18068:
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18069:
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#33355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18070:
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4

WARNING: line length of 121 exceeds 100 columns
#33356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18071:
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18072:
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L

WARNING: line length of 113 exceeds 100 columns
#33358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18073:
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#33359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18074:
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#33360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18075:
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#33361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18076:
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#33362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18077:
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18078:
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#33364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18079:
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L

WARNING: line length of 121 exceeds 100 columns
#33365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18080:
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L

WARNING: line length of 113 exceeds 100 columns
#33366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18081:
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#33367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18082:
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#33368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18083:
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#33369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18084:
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#33370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18085:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#33371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18086:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#33372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18087:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#33373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18088:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#33374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18089:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#33375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18090:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#33376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18091:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#33377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18092:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe

WARNING: line length of 114 exceeds 100 columns
#33378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18093:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#33379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18094:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#33380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18095:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#33381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18096:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16

WARNING: line length of 114 exceeds 100 columns
#33382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18097:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#33383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18098:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a

WARNING: line length of 114 exceeds 100 columns
#33384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18099:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#33385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18100:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18101:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#33387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18102:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#33388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18103:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#33389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18104:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#33390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18105:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#33391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18106:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L

WARNING: line length of 121 exceeds 100 columns
#33392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18107:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#33393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18108:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#33394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18109:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#33395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18110:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L

WARNING: line length of 121 exceeds 100 columns
#33396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18111:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#33397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18112:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L

WARNING: line length of 121 exceeds 100 columns
#33398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18113:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#33399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18114:
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L

WARNING: line length of 113 exceeds 100 columns
#33400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18115:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#33401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18116:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#33402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18117:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#33403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18118:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#33404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18119:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#33405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18120:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa

WARNING: line length of 113 exceeds 100 columns
#33406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18121:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc

WARNING: line length of 121 exceeds 100 columns
#33407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18122:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18123:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#33409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18124:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#33410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18125:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#33411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18126:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L

WARNING: line length of 121 exceeds 100 columns
#33412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18127:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#33413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18128:
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L

WARNING: line length of 113 exceeds 100 columns
#33414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18129:
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#33415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18130:
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#33416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18131:
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#33417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18132:
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#33418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18133:
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18134:
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#33420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18135:
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#33421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18136:
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#33422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18137:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#33423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18138:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#33424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18139:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#33425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18140:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#33426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18141:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18142:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#33428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18143:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#33429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18144:
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L

WARNING: line length of 113 exceeds 100 columns
#33430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18145:
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#33431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18146:
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8

WARNING: line length of 121 exceeds 100 columns
#33432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18147:
+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18148:
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#33434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18149:
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#33435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18150:
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2

WARNING: line length of 121 exceeds 100 columns
#33436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18151:
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18152:
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#33438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18153:
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#33439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18154:
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#33440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18155:
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18156:
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18157:
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#33443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18158:
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#33444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18159:
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18160:
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18161:
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#33447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18162:
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#33448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18163:
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18164:
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18165:
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#33451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18166:
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#33452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18167:
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18168:
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18169:
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#33455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18170:
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#33456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18171:
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18172:
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18173:
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#33459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18174:
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#33460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18175:
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18176:
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18177:
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#33463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18178:
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#33464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18179:
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18180:
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18181:
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#33467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18182:
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#33468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18183:
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18184:
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18185:
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#33471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18186:
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#33472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18187:
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18188:
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18189:
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#33475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18190:
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#33476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18191:
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18192:
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18193:
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#33479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18194:
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#33480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18195:
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18196:
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18197:
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#33483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18198:
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#33484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18199:
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18200:
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18201:
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#33487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18202:
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2

WARNING: line length of 121 exceeds 100 columns
#33488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18203:
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18204:
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#33490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18205:
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18206:
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#33492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18207:
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18208:
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18209:
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18210:
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#33496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18211:
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18212:
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18213:
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18214:
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#33500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18215:
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18216:
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18217:
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18218:
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#33504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18219:
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18220:
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18221:
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18222:
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#33508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18223:
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18224:
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18225:
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#33511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18226:
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#33512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18227:
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18228:
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18229:
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18230:
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18231:
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18232:
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18233:
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18234:
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18235:
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18236:
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18237:
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18238:
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18239:
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18240:
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18241:
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18242:
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18243:
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18244:
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18245:
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18246:
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18247:
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18248:
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18249:
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#33535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18250:
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18251:
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18252:
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18253:
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#33539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18254:
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#33540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18255:
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#33541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18256:
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#33542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18257:
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18258:
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18259:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#33545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18260:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2

WARNING: line length of 113 exceeds 100 columns
#33546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18261:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#33547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18262:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#33548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18263:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#33549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18264:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18265:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#33551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18266:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#33552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18267:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#33553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18268:
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#33554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18269:
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#33555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18270:
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#33556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18271:
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#33557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18272:
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18273:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#33559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18274:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#33560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18275:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6

WARNING: line length of 113 exceeds 100 columns
#33561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18276:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7

WARNING: line length of 121 exceeds 100 columns
#33562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18277:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#33563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18278:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#33564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18279:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#33565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18280:
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#33566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18281:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#33567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18282:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#33568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18283:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#33569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18284:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#33570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18285:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#33571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18286:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#33572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18287:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#33573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18288:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#33574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18289:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#33575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18290:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#33576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18291:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#33577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18292:
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#33578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18293:
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#33579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18294:
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18295:
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#33581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18296:
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18297:
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#33583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18298:
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18299:
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#33585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18300:
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18301:
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#33587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18302:
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18303:
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#33589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18304:
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18305:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#33591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18306:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18307:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#33593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18308:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#33594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18309:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18310:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18311:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#33597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18312:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18313:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#33599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18314:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#33600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18315:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18316:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18317:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#33603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18318:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18319:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#33605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18320:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#33606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18321:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18322:
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18323:
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18324:
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18325:
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18326:
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18327:
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18328:
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18329:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18330:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18331:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18332:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18333:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18334:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18335:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18336:
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18337:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18338:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18339:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18340:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18341:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18342:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18343:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18344:
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18345:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18346:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18347:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18348:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18349:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18350:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18351:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18352:
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18353:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18354:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18355:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18356:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18357:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18358:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18359:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18360:
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18361:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18362:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18363:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18364:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18365:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18366:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18367:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18368:
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18369:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18370:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18371:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18372:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18373:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18374:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18375:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18376:
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18377:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18378:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18379:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18380:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18381:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18382:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18383:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18384:
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18385:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18386:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18387:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18388:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18389:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18390:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18391:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18392:
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18393:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18394:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18395:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18396:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18397:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18398:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18399:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18400:
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18401:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18402:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18403:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18404:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18405:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18406:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18407:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18408:
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18409:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18410:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18411:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18412:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18413:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18414:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18415:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18416:
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18417:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18418:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18419:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18420:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18421:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18422:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18423:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18424:
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18425:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18426:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18427:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18428:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18429:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18430:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18431:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18432:
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18433:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18434:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18435:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18436:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18437:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18438:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18439:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18440:
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18441:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18442:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18443:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18444:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18445:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18446:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18447:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18448:
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18449:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18450:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18451:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18452:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18453:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18454:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18455:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18456:
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18457:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18458:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18459:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18460:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18461:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18462:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18463:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18464:
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18465:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#33751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18466:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#33752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18467:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#33753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18468:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#33754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18469:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#33755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18470:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#33756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18471:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#33757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18472:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#33758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18473:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#33759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18474:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#33760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18475:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#33761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18476:
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#33762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18477:
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#33763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18478:
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18479:
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#33765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18480:
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18481:
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#33767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18482:
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18483:
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#33769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18484:
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18485:
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#33771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18486:
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18487:
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#33773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18488:
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18489:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#33775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18490:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18491:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#33777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18492:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#33778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18493:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18494:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18495:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#33781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18496:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18497:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#33783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18498:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#33784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18499:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18500:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18501:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#33787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18502:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#33788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18503:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#33789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18504:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#33790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18505:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#33791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18506:
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#33792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18507:
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18508:
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18509:
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18510:
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18511:
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#33797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18512:
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18513:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18514:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18515:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18516:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18517:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18518:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18519:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18520:
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18521:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18522:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18523:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18524:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18525:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18526:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18527:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18528:
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18529:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18530:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18531:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18532:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18533:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18534:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18535:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18536:
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18537:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18538:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18539:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18540:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18541:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18542:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18543:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18544:
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18545:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#33831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18546:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#33832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18547:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#33833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18548:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#33834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18549:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18550:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18551:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18552:
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18553:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18554:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18555:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18556:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18557:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18558:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18559:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18560:
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18561:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18562:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18563:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18564:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18565:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18566:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18567:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18568:
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18569:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18570:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18571:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18572:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18573:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18574:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18575:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18576:
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18577:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18578:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18579:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18580:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18581:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18582:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18583:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18584:
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18585:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18586:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18587:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18588:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18589:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18590:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18591:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18592:
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18593:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18594:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18595:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18596:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18597:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18598:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18599:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18600:
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18601:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18602:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18603:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18604:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18605:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18606:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18607:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18608:
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18609:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18610:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18611:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18612:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18613:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18614:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18615:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18616:
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18617:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18618:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18619:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18620:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18621:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18622:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18623:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18624:
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18625:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18626:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18627:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18628:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18629:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18630:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18631:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18632:
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18633:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18634:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18635:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18636:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18637:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18638:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18639:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18640:
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18641:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#33927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18642:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#33928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18643:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#33929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18644:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#33930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18645:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18646:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18647:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#33933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18648:
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#33934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18649:
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#33935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18650:
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#33936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18651:
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#33937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18652:
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2

WARNING: line length of 121 exceeds 100 columns
#33938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18653:
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18654:
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L

WARNING: line length of 113 exceeds 100 columns
#33940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18655:
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#33941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18656:
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#33942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18657:
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#33943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18658:
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1

WARNING: line length of 121 exceeds 100 columns
#33944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18659:
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18660:
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L

WARNING: line length of 113 exceeds 100 columns
#33946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18661:
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#33947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18662:
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#33948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18663:
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#33949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18664:
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#33950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18665:
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#33951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18666:
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#33952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18667:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#33953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18668:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#33954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18669:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#33955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18670:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#33956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18671:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#33957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18672:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#33958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18673:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#33959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18674:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#33960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18675:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#33961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18676:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#33962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18677:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#33963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18678:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#33964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18679:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#33965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18680:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#33966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18681:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#33967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18682:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#33968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18683:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#33969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18684:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#33970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18685:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#33971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18686:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#33972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18687:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#33973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18688:
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#33974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18689:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#33975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18690:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#33976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18691:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#33977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18692:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#33978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18693:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#33979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18694:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#33980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18695:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#33981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18696:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#33982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18697:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#33983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18698:
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#33984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18699:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#33985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18700:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#33986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18701:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#33987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18702:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#33988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18703:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#33989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18704:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#33990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18705:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#33991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18706:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#33992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18707:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#33993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18708:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#33994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18709:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#33995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18710:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#33996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18711:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#33997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18712:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#33998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18713:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#33999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18714:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#34000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18715:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18716:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18717:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#34003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18718:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#34004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18719:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#34005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18720:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#34006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18721:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#34007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18722:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#34008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18723:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#34009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18724:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#34010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18725:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#34011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18726:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#34012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18727:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#34013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18728:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#34014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18729:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#34015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18730:
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#34016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18731:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#34017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18732:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#34018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18733:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#34019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18734:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#34020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18735:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#34021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18736:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#34022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18737:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18738:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#34024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18739:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#34025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18740:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#34026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18741:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#34027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18742:
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#34028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18743:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#34029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18744:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#34030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18745:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#34031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18746:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#34032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18747:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18748:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#34034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18749:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#34035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18750:
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#34036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18751:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#34037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18752:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#34038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18753:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#34039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18754:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#34040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18755:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#34041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18756:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#34042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18757:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#34043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18758:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#34044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18759:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#34045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18760:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#34046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18761:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#34047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18762:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#34048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18763:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#34049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18764:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#34050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18765:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#34051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18766:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#34052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18767:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#34053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18768:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18769:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#34055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18770:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18771:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#34057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18772:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#34058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18773:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#34059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18774:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#34060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18775:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#34061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18776:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#34062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18777:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#34063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18778:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#34064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18779:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#34065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18780:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#34066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18781:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#34067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18782:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#34068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18783:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#34069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18784:
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18785:
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#34071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18786:
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18787:
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#34073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18788:
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#34074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18789:
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18790:
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#34076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18791:
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#34077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18792:
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18793:
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#34079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18794:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#34080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18795:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#34081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18796:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc

WARNING: line length of 113 exceeds 100 columns
#34082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18797:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#34083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18798:
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#34084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18799:
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#34085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18800:
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18801:
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#34087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18802:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#34088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18803:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#34089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18804:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#34090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18805:
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#34091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18806:
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#34092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18807:
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#34093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18808:
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18809:
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#34095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18810:
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#34096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18811:
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#34097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18812:
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc

WARNING: line length of 121 exceeds 100 columns
#34098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18813:
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18814:
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#34100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18815:
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#34101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18816:
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#34102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18817:
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18818:
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#34104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18819:
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18820:
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18821:
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18822:
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#34108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18823:
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18824:
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18825:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#34111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18826:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#34112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18827:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#34113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18828:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#34114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18829:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#34115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18830:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#34116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18831:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7

WARNING: line length of 113 exceeds 100 columns
#34117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18832:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#34118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18833:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb

WARNING: line length of 113 exceeds 100 columns
#34119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18834:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe

WARNING: line length of 114 exceeds 100 columns
#34120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18835:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#34121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18836:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18837:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#34123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18838:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18839:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#34125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18840:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#34126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18841:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#34127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18842:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L

WARNING: line length of 121 exceeds 100 columns
#34128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18843:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L

WARNING: line length of 121 exceeds 100 columns
#34129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18844:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L

WARNING: line length of 121 exceeds 100 columns
#34130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18845:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#34131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18846:
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18847:
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#34133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18848:
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#34134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18849:
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#34135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18850:
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8

WARNING: line length of 121 exceeds 100 columns
#34136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18851:
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#34137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18852:
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#34138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18853:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#34139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18854:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#34140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18855:
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#34141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18856:
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#34142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18857:
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd

WARNING: line length of 114 exceeds 100 columns
#34143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18858:
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#34144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18859:
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#34145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18860:
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#34146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18861:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#34147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18862:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#34148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18863:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#34149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18864:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18865:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#34151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18866:
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#34152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18867:
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#34153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18868:
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#34154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18869:
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#34155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18870:
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#34156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18871:
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#34157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18872:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L

WARNING: line length of 121 exceeds 100 columns
#34158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18873:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#34159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18874:
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#34160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18875:
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#34161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18876:
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18877:
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#34163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18878:
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18879:
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#34165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18880:
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18881:
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#34167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18882:
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18883:
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#34169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18884:
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18885:
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#34171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18886:
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18887:
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#34173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18888:
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#34174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18889:
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18890:
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L

WARNING: line length of 113 exceeds 100 columns
#34176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18891:
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18892:
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#34178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18893:
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18894:
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18895:
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18896:
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#34182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18897:
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18898:
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18899:
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18900:
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#34186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18901:
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18902:
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18903:
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#34189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18904:
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#34190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18905:
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18906:
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18907:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#34193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18908:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#34194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18909:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#34195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18910:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#34196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18911:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#34197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18912:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#34198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18913:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#34199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18914:
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#34200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18915:
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#34201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18916:
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#34202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18917:
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18918:
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#34204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18919:
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#34205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18920:
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2

WARNING: line length of 121 exceeds 100 columns
#34206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18921:
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18922:
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#34208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18923:
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18924:
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#34210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18925:
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18926:
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18927:
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18928:
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#34214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18929:
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18930:
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18931:
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18932:
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#34218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18933:
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18934:
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18935:
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18936:
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#34222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18937:
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18938:
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18939:
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18940:
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#34226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18941:
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18942:
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18943:
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18944:
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#34230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18945:
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18946:
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18947:
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#34233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18948:
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#34234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18949:
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18950:
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18951:
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#34237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18952:
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#34238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18953:
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18954:
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18955:
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#34241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18956:
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#34242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18957:
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18958:
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18959:
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#34245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18960:
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#34246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18961:
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18962:
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18963:
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#34249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18964:
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#34250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18965:
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18966:
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18967:
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#34253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18968:
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#34254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18969:
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18970:
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18971:
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#34257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18972:
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#34258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18973:
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#34259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18974:
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#34260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18975:
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18976:
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#34262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18977:
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#34263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18978:
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4

WARNING: line length of 121 exceeds 100 columns
#34264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18979:
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18980:
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L

WARNING: line length of 113 exceeds 100 columns
#34266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18981:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#34267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18982:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#34268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18983:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#34269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18984:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#34270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18985:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#34271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18986:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7

WARNING: line length of 114 exceeds 100 columns
#34272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18987:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#34273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18988:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18989:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#34275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18990:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18991:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#34277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18992:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L

WARNING: line length of 121 exceeds 100 columns
#34278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18993:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#34279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18994:
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L

WARNING: line length of 113 exceeds 100 columns
#34280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18995:
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#34281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18996:
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18997:
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#34283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18998:
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:18999:
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19000:
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#34286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19001:
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19002:
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19003:
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#34289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19004:
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8

WARNING: line length of 114 exceeds 100 columns
#34290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19005:
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#34291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19006:
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19007:
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#34293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19008:
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L

WARNING: line length of 113 exceeds 100 columns
#34294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19009:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#34295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19010:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#34296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19011:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#34297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19012:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#34298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19013:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#34299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19014:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#34300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19015:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L

WARNING: line length of 121 exceeds 100 columns
#34301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19016:
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#34302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19017:
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#34303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19018:
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#34304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19019:
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#34305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19020:
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#34306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19021:
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#34307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19022:
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#34308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19023:
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#34309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19024:
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#34310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19025:
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#34311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19026:
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#34312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19027:
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#34313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19028:
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#34314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19029:
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#34315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19030:
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#34316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19031:
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#34317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19032:
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc

WARNING: line length of 121 exceeds 100 columns
#34318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19033:
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#34319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19034:
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L

WARNING: line length of 121 exceeds 100 columns
#34320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19035:
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L

WARNING: line length of 121 exceeds 100 columns
#34321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19036:
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L

WARNING: line length of 113 exceeds 100 columns
#34322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19037:
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#34323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19038:
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#34324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19039:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#34325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19040:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#34326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19041:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#34327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19042:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#34328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19043:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#34329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19044:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#34330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19045:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19046:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#34332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19047:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L

WARNING: line length of 121 exceeds 100 columns
#34333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19048:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#34334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19049:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#34335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19050:
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L

WARNING: line length of 113 exceeds 100 columns
#34336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19051:
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#34337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19052:
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8

WARNING: line length of 121 exceeds 100 columns
#34338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19053:
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#34339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19054:
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#34340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19055:
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19056:
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19057:
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#34343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19058:
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#34344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19059:
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#34345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19060:
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#34346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19061:
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#34347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19062:
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19063:
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#34349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19064:
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#34350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19065:
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#34351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19066:
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#34352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19067:
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19068:
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19069:
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#34355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19070:
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#34356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19071:
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#34357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19072:
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#34358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19073:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#34359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19074:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#34360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19075:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#34361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19076:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#34362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19077:
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#34363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19078:
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#34364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19079:
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#34365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19080:
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#34366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19081:
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#34367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19082:
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#34368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19083:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#34369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19084:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#34370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19085:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#34371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19086:
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L

WARNING: line length of 113 exceeds 100 columns
#34372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19087:
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#34373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19088:
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#34374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19089:
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19090:
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19091:
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#34377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19092:
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#34378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19093:
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#34379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19094:
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#34380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19095:
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#34381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19096:
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19097:
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#34383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19098:
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L

WARNING: line length of 113 exceeds 100 columns
#34384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19099:
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#34385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19100:
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#34386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19101:
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#34387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19102:
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19103:
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#34389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19104:
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10

WARNING: line length of 121 exceeds 100 columns
#34390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19105:
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#34391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19106:
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19107:
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#34393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19108:
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19109:
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#34395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19110:
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19111:
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#34397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19112:
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19113:
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#34399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19114:
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19115:
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19116:
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19117:
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#34403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19118:
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19119:
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#34405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19120:
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#34406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19121:
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#34407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19122:
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19123:
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#34409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19124:
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#34410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19125:
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#34411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19126:
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19127:
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#34413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19128:
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4

WARNING: line length of 121 exceeds 100 columns
#34414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19129:
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19130:
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L

WARNING: line length of 113 exceeds 100 columns
#34416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19131:
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#34417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19132:
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#34418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19133:
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#34419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19134:
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#34420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19135:
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19136:
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#34422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19137:
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L

WARNING: line length of 121 exceeds 100 columns
#34423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19138:
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L

WARNING: line length of 113 exceeds 100 columns
#34424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19139:
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#34425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19140:
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#34426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19141:
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#34427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19142:
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#34428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19143:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#34429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19144:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#34430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19145:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#34431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19146:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#34432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19147:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#34433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19148:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#34434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19149:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#34435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19150:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe

WARNING: line length of 114 exceeds 100 columns
#34436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19151:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#34437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19152:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#34438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19153:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#34439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19154:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16

WARNING: line length of 114 exceeds 100 columns
#34440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19155:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#34441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19156:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a

WARNING: line length of 114 exceeds 100 columns
#34442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19157:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#34443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19158:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19159:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19160:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#34446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19161:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#34447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19162:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#34448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19163:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#34449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19164:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L

WARNING: line length of 121 exceeds 100 columns
#34450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19165:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#34451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19166:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#34452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19167:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#34453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19168:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L

WARNING: line length of 121 exceeds 100 columns
#34454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19169:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#34455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19170:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L

WARNING: line length of 121 exceeds 100 columns
#34456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19171:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#34457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19172:
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L

WARNING: line length of 113 exceeds 100 columns
#34458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19173:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#34459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19174:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#34460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19175:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#34461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19176:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#34462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19177:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#34463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19178:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa

WARNING: line length of 113 exceeds 100 columns
#34464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19179:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc

WARNING: line length of 121 exceeds 100 columns
#34465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19180:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19181:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#34467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19182:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#34468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19183:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#34469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19184:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L

WARNING: line length of 121 exceeds 100 columns
#34470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19185:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#34471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19186:
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L

WARNING: line length of 113 exceeds 100 columns
#34472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19187:
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#34473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19188:
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#34474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19189:
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#34475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19190:
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4

WARNING: line length of 121 exceeds 100 columns
#34476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19191:
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19192:
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#34478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19193:
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19194:
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#34480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19195:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#34481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19196:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#34482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19197:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#34483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19198:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#34484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19199:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19200:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19201:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#34487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19202:
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L

WARNING: line length of 113 exceeds 100 columns
#34488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19203:
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#34489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19204:
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8

WARNING: line length of 121 exceeds 100 columns
#34490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19205:
+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#34491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19206:
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L

WARNING: line length of 113 exceeds 100 columns
#34492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19207:
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#34493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19208:
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2

WARNING: line length of 121 exceeds 100 columns
#34494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19209:
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19210:
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#34496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19211:
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#34497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19212:
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#34498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19213:
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19214:
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19215:
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#34501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19216:
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#34502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19217:
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19218:
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19219:
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#34505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19220:
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#34506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19221:
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19222:
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19223:
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#34509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19224:
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#34510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19225:
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19226:
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19227:
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#34513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19228:
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#34514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19229:
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19230:
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19231:
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#34517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19232:
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#34518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19233:
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19234:
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19235:
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#34521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19236:
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#34522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19237:
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19238:
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19239:
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#34525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19240:
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#34526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19241:
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19242:
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19243:
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#34529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19244:
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#34530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19245:
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19246:
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19247:
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#34533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19248:
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#34534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19249:
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19250:
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19251:
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#34537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19252:
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#34538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19253:
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19254:
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19255:
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#34541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19256:
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#34542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19257:
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19258:
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19259:
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#34545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19260:
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2

WARNING: line length of 121 exceeds 100 columns
#34546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19261:
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19262:
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#34548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19263:
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19264:
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#34550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19265:
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19266:
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19267:
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19268:
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#34554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19269:
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19270:
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19271:
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19272:
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#34558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19273:
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19274:
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19275:
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19276:
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#34562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19277:
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19278:
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19279:
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19280:
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#34566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19281:
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19282:
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19283:
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#34569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19284:
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#34570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19285:
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19286:
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19287:
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19288:
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19289:
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19290:
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19291:
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19292:
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19293:
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19294:
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19295:
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19296:
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19297:
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19298:
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19299:
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19300:
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19301:
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19302:
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19303:
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19304:
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19305:
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19306:
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19307:
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#34593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19308:
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19309:
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19310:
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19311:
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#34597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19312:
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#34598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19313:
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#34599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19314:
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#34600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19315:
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19316:
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19317:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#34603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19318:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2

WARNING: line length of 113 exceeds 100 columns
#34604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19319:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#34605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19320:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#34606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19321:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6

WARNING: line length of 121 exceeds 100 columns
#34607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19322:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19323:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#34609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19324:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#34610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19325:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#34611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19326:
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#34612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19327:
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#34613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19328:
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#34614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19329:
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#34615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19330:
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19331:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#34617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19332:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#34618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19333:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6

WARNING: line length of 113 exceeds 100 columns
#34619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19334:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7

WARNING: line length of 121 exceeds 100 columns
#34620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19335:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#34621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19336:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#34622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19337:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#34623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19338:
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#34624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19339:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#34625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19340:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#34626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19341:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#34627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19342:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#34628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19343:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#34629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19344:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#34630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19345:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#34631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19346:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#34632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19347:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#34633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19348:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#34634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19349:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#34635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19350:
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#34636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19351:
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#34637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19352:
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19353:
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#34639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19354:
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19355:
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#34641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19356:
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19357:
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#34643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19358:
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19359:
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#34645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19360:
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19361:
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#34647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19362:
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19363:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#34649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19364:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19365:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#34651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19366:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#34652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19367:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19368:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19369:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#34655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19370:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19371:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#34657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19372:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#34658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19373:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19374:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19375:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#34661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19376:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19377:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#34663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19378:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#34664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19379:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19380:
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19381:
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19382:
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19383:
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19384:
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19385:
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19386:
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19387:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19388:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19389:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19390:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19391:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19392:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19393:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19394:
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19395:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19396:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19397:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19398:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19399:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19400:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19401:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19402:
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19403:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19404:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19405:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19406:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19407:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19408:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19409:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19410:
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19411:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19412:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19413:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19414:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19415:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19416:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19417:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19418:
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19419:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19420:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19421:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19422:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19423:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19424:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19425:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19426:
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19427:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19428:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19429:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19430:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19431:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19432:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19433:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19434:
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19435:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19436:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19437:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19438:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19439:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19440:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19441:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19442:
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19443:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19444:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19445:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19446:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19447:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19448:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19449:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19450:
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19451:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19452:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19453:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19454:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19455:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19456:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19457:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19458:
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19459:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19460:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19461:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19462:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19463:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19464:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19465:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19466:
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19467:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19468:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19469:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19470:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19471:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19472:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19473:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19474:
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19475:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19476:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19477:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19478:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19479:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19480:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19481:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19482:
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19483:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19484:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19485:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19486:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19487:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19488:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19489:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19490:
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19491:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19492:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19493:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19494:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19495:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19496:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19497:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19498:
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19499:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19500:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19501:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19502:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19503:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19504:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19505:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19506:
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19507:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19508:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19509:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19510:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19511:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19512:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19513:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19514:
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19515:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19516:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19517:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19518:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19519:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19520:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19521:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19522:
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19523:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#34809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19524:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#34810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19525:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#34811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19526:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#34812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19527:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#34813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19528:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#34814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19529:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#34815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19530:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#34816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19531:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#34817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19532:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14

WARNING: line length of 121 exceeds 100 columns
#34818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19533:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#34819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19534:
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#34820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19535:
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#34821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19536:
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19537:
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#34823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19538:
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19539:
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#34825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19540:
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19541:
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#34827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19542:
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19543:
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#34829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19544:
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19545:
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0

WARNING: line length of 121 exceeds 100 columns
#34831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19546:
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19547:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#34833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19548:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19549:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#34835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19550:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#34836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19551:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19552:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19553:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#34839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19554:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19555:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#34841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19556:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#34842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19557:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19558:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19559:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#34845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19560:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#34846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19561:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0

WARNING: line length of 114 exceeds 100 columns
#34847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19562:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10

WARNING: line length of 121 exceeds 100 columns
#34848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19563:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#34849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19564:
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#34850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19565:
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19566:
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19567:
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19568:
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19569:
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#34855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19570:
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19571:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19572:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19573:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19574:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19575:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19576:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19577:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19578:
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19579:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19580:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19581:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19582:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19583:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19584:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19585:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19586:
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19587:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19588:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19589:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19590:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19591:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19592:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19593:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19594:
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19595:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19596:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19597:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19598:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19599:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19600:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19601:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19602:
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19603:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#34889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19604:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc

WARNING: line length of 114 exceeds 100 columns
#34890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19605:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10

WARNING: line length of 114 exceeds 100 columns
#34891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19606:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c

WARNING: line length of 121 exceeds 100 columns
#34892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19607:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19608:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19609:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19610:
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19611:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19612:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19613:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19614:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19615:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19616:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19617:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19618:
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19619:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19620:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19621:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19622:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19623:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19624:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19625:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19626:
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19627:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19628:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19629:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19630:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19631:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19632:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19633:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19634:
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19635:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19636:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19637:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19638:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19639:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19640:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19641:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19642:
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19643:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19644:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19645:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19646:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19647:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19648:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19649:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19650:
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19651:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19652:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19653:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19654:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19655:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19656:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19657:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19658:
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19659:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19660:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19661:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19662:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19663:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19664:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19665:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19666:
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19667:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19668:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19669:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19670:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19671:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19672:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19673:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19674:
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19675:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19676:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19677:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19678:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19679:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19680:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19681:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19682:
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19683:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19684:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19685:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19686:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19687:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19688:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19689:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19690:
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19691:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19692:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19693:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19694:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19695:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19696:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19697:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19698:
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19699:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0

WARNING: line length of 113 exceeds 100 columns
#34985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19700:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc

WARNING: line length of 114 exceeds 100 columns
#34986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19701:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#34987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19702:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c

WARNING: line length of 121 exceeds 100 columns
#34988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19703:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#34989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19704:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#34990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19705:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#34991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19706:
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#34992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19707:
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#34993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19708:
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#34994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19709:
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#34995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19710:
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2

WARNING: line length of 121 exceeds 100 columns
#34996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19711:
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#34997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19712:
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L

WARNING: line length of 113 exceeds 100 columns
#34998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19713:
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#34999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19714:
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#35000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19715:
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19716:
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1

WARNING: line length of 121 exceeds 100 columns
#35002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19717:
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19718:
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L

WARNING: line length of 113 exceeds 100 columns
#35004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19719:
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#35005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19720:
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#35006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19721:
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#35007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19722:
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19723:
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19724:
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#35010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19725:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#35011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19726:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#35012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19727:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#35013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19728:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#35014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19729:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#35015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19730:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#35016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19731:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#35017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19732:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#35018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19733:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#35019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19734:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#35020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19735:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#35021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19736:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#35022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19737:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#35023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19738:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#35024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19739:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#35025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19740:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#35026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19741:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#35027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19742:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#35028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19743:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19744:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#35030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19745:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#35031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19746:
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#35032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19747:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#35033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19748:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#35034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19749:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#35035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19750:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#35036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19751:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#35037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19752:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19753:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#35039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19754:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#35040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19755:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#35041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19756:
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#35042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19757:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#35043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19758:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#35044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19759:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#35045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19760:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#35046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19761:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#35047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19762:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#35048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19763:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#35049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19764:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#35050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19765:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#35051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19766:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#35052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19767:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#35053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19768:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#35054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19769:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#35055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19770:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#35056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19771:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#35057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19772:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#35058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19773:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19774:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#35060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19775:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#35061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19776:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#35062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19777:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19778:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#35064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19779:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19780:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19781:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#35067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19782:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#35068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19783:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#35069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19784:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#35070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19785:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#35071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19786:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#35072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19787:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#35073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19788:
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#35074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19789:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#35075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19790:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#35076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19791:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#35077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19792:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#35078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19793:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#35079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19794:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#35080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19795:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19796:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#35082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19797:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#35083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19798:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#35084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19799:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#35085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19800:
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#35086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19801:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#35087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19802:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#35088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19803:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#35089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19804:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#35090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19805:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19806:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19807:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#35093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19808:
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#35094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19809:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19810:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19811:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#35097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19812:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#35098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19813:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#35099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19814:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#35100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19815:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#35101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19816:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#35102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19817:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#35103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19818:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#35104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19819:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#35105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19820:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#35106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19821:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#35107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19822:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#35108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19823:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#35109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19824:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#35110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19825:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#35111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19826:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19827:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19828:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#35114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19829:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#35115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19830:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19831:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#35117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19832:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#35118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19833:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#35119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19834:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19835:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#35121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19836:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#35122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19837:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#35123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19838:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#35124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19839:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#35125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19840:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19841:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#35127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19842:
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19843:
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#35129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19844:
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#35130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19845:
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#35131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19846:
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#35132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19847:
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19848:
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#35134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19849:
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#35135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19850:
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#35136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19851:
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19852:
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19853:
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19854:
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19855:
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19856:
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19857:
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19858:
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19859:
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19860:
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19861:
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19862:
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19863:
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19864:
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#35150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19865:
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19866:
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19867:
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#35153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19868:
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#35154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19869:
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc

WARNING: line length of 114 exceeds 100 columns
#35155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19870:
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#35156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19871:
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#35157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19872:
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#35158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19873:
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15

WARNING: line length of 114 exceeds 100 columns
#35159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19874:
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#35160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19875:
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19876:
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#35162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19877:
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19878:
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L

WARNING: line length of 121 exceeds 100 columns
#35164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19879:
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#35165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19880:
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#35166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19881:
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#35167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19882:
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19883:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#35169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19884:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19885:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#35171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19886:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#35172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19887:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#35173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19888:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb

WARNING: line length of 113 exceeds 100 columns
#35174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19889:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd

WARNING: line length of 113 exceeds 100 columns
#35175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19890:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe

WARNING: line length of 113 exceeds 100 columns
#35176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19891:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#35177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19892:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#35178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19893:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#35179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19894:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#35180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19895:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19896:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#35182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19897:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a

WARNING: line length of 114 exceeds 100 columns
#35183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19898:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#35184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19899:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#35185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19900:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19901:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19902:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#35188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19903:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19904:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L

WARNING: line length of 121 exceeds 100 columns
#35190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19905:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L

WARNING: line length of 121 exceeds 100 columns
#35191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19906:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#35192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19907:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19908:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#35194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19909:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#35195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19910:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L

WARNING: line length of 121 exceeds 100 columns
#35196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19911:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L

WARNING: line length of 121 exceeds 100 columns
#35197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19912:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19913:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#35199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19914:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#35200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19915:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L

WARNING: line length of 121 exceeds 100 columns
#35201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19916:
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#35202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19917:
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19918:
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19919:
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19920:
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19921:
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19922:
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19923:
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19924:
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19925:
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19926:
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19927:
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19928:
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19929:
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19930:
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19931:
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19932:
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L

WARNING: line length of 113 exceeds 100 columns
#35218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19933:
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#35219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19934:
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#35220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19935:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#35221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19936:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#35222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19937:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#35223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19938:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc

WARNING: line length of 121 exceeds 100 columns
#35224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19939:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19940:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19941:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19942:
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L

WARNING: line length of 113 exceeds 100 columns
#35228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19943:
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#35229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19944:
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19945:
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#35231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19946:
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19947:
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#35233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19948:
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#35234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19949:
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#35235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19950:
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#35236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19951:
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#35237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19952:
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19953:
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19954:
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19955:
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19956:
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#35242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19957:
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19958:
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19959:
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#35245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19960:
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19961:
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#35247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19962:
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19963:
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19964:
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#35250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19965:
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19966:
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#35252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19967:
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19968:
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19969:
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19970:
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19971:
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19972:
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19973:
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#35259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19974:
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#35260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19975:
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19976:
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19977:
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19978:
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19979:
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19980:
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19981:
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#35267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19982:
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#35268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19983:
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19984:
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19985:
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#35271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19986:
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19987:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#35273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19988:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#35274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19989:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#35275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19990:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19991:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#35277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19992:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19993:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L

WARNING: line length of 121 exceeds 100 columns
#35279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19994:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19995:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19996:
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19997:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#35283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19998:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa

WARNING: line length of 114 exceeds 100 columns
#35284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:19999:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14

WARNING: line length of 121 exceeds 100 columns
#35285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20000:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#35286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20001:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#35287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20002:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#35288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20003:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#35289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20004:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#35290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20005:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#35291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20006:
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20007:
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20008:
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L

WARNING: line length of 113 exceeds 100 columns
#35294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20009:
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20010:
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20011:
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#35297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20012:
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20013:
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20014:
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20015:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#35301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20016:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#35302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20017:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#35303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20018:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#35304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20019:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#35305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20020:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe

WARNING: line length of 114 exceeds 100 columns
#35306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20021:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#35307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20022:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20023:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c

WARNING: line length of 121 exceeds 100 columns
#35309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20024:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20025:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20026:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20027:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#35313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20028:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20029:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20030:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L

WARNING: line length of 121 exceeds 100 columns
#35316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20031:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20032:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20033:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#35319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20034:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20035:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20036:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20037:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20038:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20039:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20040:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20041:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20042:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20043:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20044:
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20045:
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20046:
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20047:
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20048:
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20049:
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20050:
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20051:
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20052:
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20053:
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20054:
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20055:
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20056:
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20057:
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20058:
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#35344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20059:
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20060:
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20061:
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#35347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20062:
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#35348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20063:
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc

WARNING: line length of 114 exceeds 100 columns
#35349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20064:
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#35350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20065:
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#35351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20066:
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#35352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20067:
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15

WARNING: line length of 114 exceeds 100 columns
#35353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20068:
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#35354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20069:
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20070:
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#35356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20071:
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20072:
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L

WARNING: line length of 121 exceeds 100 columns
#35358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20073:
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#35359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20074:
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#35360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20075:
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#35361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20076:
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20077:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#35363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20078:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20079:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#35365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20080:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#35366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20081:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#35367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20082:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb

WARNING: line length of 113 exceeds 100 columns
#35368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20083:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd

WARNING: line length of 113 exceeds 100 columns
#35369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20084:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe

WARNING: line length of 113 exceeds 100 columns
#35370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20085:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#35371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20086:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#35372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20087:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#35373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20088:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#35374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20089:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20090:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#35376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20091:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a

WARNING: line length of 114 exceeds 100 columns
#35377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20092:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#35378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20093:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#35379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20094:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20095:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20096:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#35382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20097:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20098:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L

WARNING: line length of 121 exceeds 100 columns
#35384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20099:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L

WARNING: line length of 121 exceeds 100 columns
#35385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20100:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#35386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20101:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20102:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#35388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20103:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#35389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20104:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L

WARNING: line length of 121 exceeds 100 columns
#35390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20105:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L

WARNING: line length of 121 exceeds 100 columns
#35391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20106:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20107:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#35393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20108:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#35394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20109:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L

WARNING: line length of 121 exceeds 100 columns
#35395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20110:
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#35396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20111:
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20112:
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20113:
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20114:
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20115:
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20116:
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20117:
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20118:
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20119:
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20120:
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20121:
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20122:
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20123:
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20124:
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20125:
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20126:
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L

WARNING: line length of 113 exceeds 100 columns
#35412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20127:
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#35413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20128:
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#35414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20129:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#35415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20130:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#35416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20131:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#35417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20132:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc

WARNING: line length of 121 exceeds 100 columns
#35418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20133:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20134:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20135:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20136:
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L

WARNING: line length of 113 exceeds 100 columns
#35422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20137:
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#35423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20138:
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20139:
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#35425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20140:
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20141:
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#35427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20142:
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#35428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20143:
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#35429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20144:
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#35430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20145:
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#35431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20146:
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20147:
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20148:
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20149:
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20150:
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#35436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20151:
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20152:
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20153:
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#35439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20154:
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20155:
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#35441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20156:
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20157:
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20158:
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#35444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20159:
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20160:
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#35446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20161:
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20162:
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20163:
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20164:
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20165:
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20166:
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20167:
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#35453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20168:
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#35454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20169:
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20170:
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20171:
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20172:
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20173:
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20174:
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20175:
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#35461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20176:
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#35462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20177:
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20178:
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20179:
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#35465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20180:
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20181:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#35467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20182:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#35468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20183:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#35469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20184:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20185:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#35471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20186:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20187:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L

WARNING: line length of 121 exceeds 100 columns
#35473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20188:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20189:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20190:
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20191:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#35477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20192:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa

WARNING: line length of 114 exceeds 100 columns
#35478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20193:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14

WARNING: line length of 121 exceeds 100 columns
#35479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20194:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#35480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20195:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#35481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20196:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#35482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20197:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#35483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20198:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#35484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20199:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#35485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20200:
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20201:
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20202:
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L

WARNING: line length of 113 exceeds 100 columns
#35488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20203:
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20204:
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20205:
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#35491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20206:
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20207:
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20208:
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20209:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#35495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20210:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#35496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20211:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#35497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20212:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#35498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20213:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#35499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20214:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe

WARNING: line length of 114 exceeds 100 columns
#35500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20215:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#35501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20216:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20217:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c

WARNING: line length of 121 exceeds 100 columns
#35503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20218:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20219:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20220:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20221:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#35507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20222:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20223:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20224:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L

WARNING: line length of 121 exceeds 100 columns
#35510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20225:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20226:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20227:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#35513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20228:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20229:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20230:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20231:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20232:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20233:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20234:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20235:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20236:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20237:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20238:
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20239:
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20240:
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20241:
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20242:
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20243:
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20244:
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20245:
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20246:
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20247:
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20248:
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20249:
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20250:
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20251:
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20252:
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#35538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20253:
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20254:
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20255:
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#35541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20256:
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#35542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20257:
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc

WARNING: line length of 114 exceeds 100 columns
#35543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20258:
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#35544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20259:
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#35545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20260:
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#35546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20261:
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15

WARNING: line length of 114 exceeds 100 columns
#35547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20262:
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#35548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20263:
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20264:
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#35550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20265:
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20266:
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L

WARNING: line length of 121 exceeds 100 columns
#35552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20267:
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#35553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20268:
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#35554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20269:
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#35555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20270:
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20271:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#35557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20272:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20273:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#35559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20274:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#35560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20275:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#35561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20276:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb

WARNING: line length of 113 exceeds 100 columns
#35562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20277:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd

WARNING: line length of 113 exceeds 100 columns
#35563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20278:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe

WARNING: line length of 113 exceeds 100 columns
#35564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20279:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#35565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20280:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#35566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20281:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#35567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20282:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#35568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20283:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20284:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#35570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20285:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a

WARNING: line length of 114 exceeds 100 columns
#35571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20286:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#35572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20287:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#35573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20288:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20289:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20290:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#35576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20291:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20292:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L

WARNING: line length of 121 exceeds 100 columns
#35578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20293:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L

WARNING: line length of 121 exceeds 100 columns
#35579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20294:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#35580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20295:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20296:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#35582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20297:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#35583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20298:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L

WARNING: line length of 121 exceeds 100 columns
#35584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20299:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L

WARNING: line length of 121 exceeds 100 columns
#35585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20300:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20301:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#35587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20302:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#35588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20303:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L

WARNING: line length of 121 exceeds 100 columns
#35589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20304:
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#35590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20305:
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20306:
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20307:
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20308:
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20309:
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20310:
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20311:
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20312:
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20313:
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20314:
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20315:
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20316:
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20317:
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20318:
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20319:
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20320:
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L

WARNING: line length of 113 exceeds 100 columns
#35606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20321:
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#35607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20322:
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#35608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20323:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#35609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20324:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#35610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20325:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#35611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20326:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc

WARNING: line length of 121 exceeds 100 columns
#35612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20327:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20328:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20329:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20330:
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L

WARNING: line length of 113 exceeds 100 columns
#35616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20331:
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#35617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20332:
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20333:
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#35619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20334:
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20335:
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#35621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20336:
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#35622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20337:
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#35623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20338:
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#35624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20339:
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#35625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20340:
+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20341:
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20342:
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20343:
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20344:
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#35630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20345:
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20346:
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20347:
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#35633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20348:
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20349:
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#35635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20350:
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20351:
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20352:
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#35638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20353:
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20354:
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#35640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20355:
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20356:
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20357:
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20358:
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20359:
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20360:
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20361:
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#35647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20362:
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#35648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20363:
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20364:
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20365:
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20366:
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20367:
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20368:
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20369:
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#35655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20370:
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#35656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20371:
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20372:
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20373:
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#35659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20374:
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20375:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#35661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20376:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#35662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20377:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#35663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20378:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20379:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#35665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20380:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20381:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L

WARNING: line length of 121 exceeds 100 columns
#35667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20382:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20383:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20384:
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20385:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#35671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20386:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa

WARNING: line length of 114 exceeds 100 columns
#35672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20387:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14

WARNING: line length of 121 exceeds 100 columns
#35673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20388:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#35674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20389:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#35675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20390:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#35676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20391:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#35677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20392:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#35678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20393:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#35679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20394:
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20395:
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20396:
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L

WARNING: line length of 113 exceeds 100 columns
#35682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20397:
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20398:
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20399:
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#35685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20400:
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20401:
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20402:
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20403:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#35689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20404:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#35690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20405:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#35691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20406:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#35692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20407:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#35693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20408:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe

WARNING: line length of 114 exceeds 100 columns
#35694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20409:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#35695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20410:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20411:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c

WARNING: line length of 121 exceeds 100 columns
#35697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20412:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20413:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20414:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20415:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#35701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20416:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20417:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20418:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L

WARNING: line length of 121 exceeds 100 columns
#35704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20419:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20420:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20421:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#35707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20422:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20423:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20424:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20425:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20426:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20427:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20428:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20429:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20430:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20431:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20432:
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20433:
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20434:
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20435:
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20436:
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20437:
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20438:
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20439:
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20440:
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20441:
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#35727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20442:
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#35728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20443:
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20444:
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20445:
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20446:
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#35732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20447:
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20448:
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20449:
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#35735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20450:
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#35736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20451:
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc

WARNING: line length of 114 exceeds 100 columns
#35737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20452:
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#35738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20453:
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#35739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20454:
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#35740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20455:
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15

WARNING: line length of 114 exceeds 100 columns
#35741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20456:
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#35742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20457:
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20458:
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#35744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20459:
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20460:
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L

WARNING: line length of 121 exceeds 100 columns
#35746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20461:
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#35747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20462:
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#35748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20463:
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#35749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20464:
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20465:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#35751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20466:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20467:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#35753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20468:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#35754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20469:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#35755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20470:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb

WARNING: line length of 113 exceeds 100 columns
#35756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20471:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd

WARNING: line length of 113 exceeds 100 columns
#35757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20472:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe

WARNING: line length of 113 exceeds 100 columns
#35758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20473:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#35759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20474:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#35760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20475:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#35761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20476:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#35762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20477:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20478:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#35764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20479:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a

WARNING: line length of 114 exceeds 100 columns
#35765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20480:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#35766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20481:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#35767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20482:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20483:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20484:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#35770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20485:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20486:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L

WARNING: line length of 121 exceeds 100 columns
#35772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20487:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L

WARNING: line length of 121 exceeds 100 columns
#35773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20488:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#35774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20489:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20490:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#35776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20491:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#35777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20492:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L

WARNING: line length of 121 exceeds 100 columns
#35778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20493:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L

WARNING: line length of 121 exceeds 100 columns
#35779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20494:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20495:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#35781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20496:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#35782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20497:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L

WARNING: line length of 121 exceeds 100 columns
#35783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20498:
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#35784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20499:
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20500:
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20501:
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20502:
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20503:
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20504:
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20505:
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20506:
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20507:
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#35793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20508:
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#35794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20509:
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#35795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20510:
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20511:
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20512:
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#35798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20513:
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20514:
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L

WARNING: line length of 113 exceeds 100 columns
#35800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20515:
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0

WARNING: line length of 121 exceeds 100 columns
#35801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20516:
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL

WARNING: line length of 113 exceeds 100 columns
#35802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20517:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#35803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20518:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#35804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20519:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#35805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20520:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc

WARNING: line length of 121 exceeds 100 columns
#35806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20521:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20522:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20523:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20524:
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L

WARNING: line length of 113 exceeds 100 columns
#35810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20525:
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#35811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20526:
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20527:
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#35813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20528:
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20529:
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#35815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20530:
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#35816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20531:
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#35817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20532:
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#35818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20533:
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#35819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20534:
+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20535:
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20536:
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20537:
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20538:
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#35824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20539:
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20540:
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#35826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20541:
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#35827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20542:
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20543:
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#35829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20544:
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20545:
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20546:
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#35832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20547:
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20548:
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#35834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20549:
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20550:
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20551:
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20552:
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20553:
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20554:
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20555:
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#35841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20556:
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#35842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20557:
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20558:
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20559:
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#35845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20560:
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#35846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20561:
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20562:
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20563:
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#35849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20564:
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#35850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20565:
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20566:
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20567:
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#35853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20568:
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#35854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20569:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#35855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20570:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#35856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20571:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#35857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20572:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#35858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20573:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#35859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20574:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#35860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20575:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L

WARNING: line length of 121 exceeds 100 columns
#35861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20576:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#35862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20577:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#35863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20578:
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20579:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#35865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20580:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa

WARNING: line length of 114 exceeds 100 columns
#35866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20581:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14

WARNING: line length of 121 exceeds 100 columns
#35867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20582:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#35868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20583:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#35869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20584:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#35870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20585:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#35871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20586:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#35872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20587:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#35873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20588:
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#35874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20589:
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20590:
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L

WARNING: line length of 113 exceeds 100 columns
#35876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20591:
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#35877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20592:
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#35878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20593:
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#35879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20594:
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20595:
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#35881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20596:
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#35882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20597:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#35883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20598:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#35884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20599:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#35885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20600:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#35886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20601:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#35887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20602:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe

WARNING: line length of 114 exceeds 100 columns
#35888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20603:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#35889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20604:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#35890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20605:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c

WARNING: line length of 121 exceeds 100 columns
#35891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20606:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20607:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20608:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#35894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20609:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#35895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20610:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#35896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20611:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20612:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L

WARNING: line length of 121 exceeds 100 columns
#35898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20613:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20614:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L

WARNING: line length of 113 exceeds 100 columns
#35900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20615:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#35901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20616:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20617:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20618:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20619:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20620:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20621:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#35907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20622:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#35908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20623:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#35909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20624:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#35910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20625:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#35911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20626:
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#35912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20627:
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#35913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20628:
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#35914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20629:
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#35915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20630:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#35916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20631:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd

WARNING: line length of 113 exceeds 100 columns
#35917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20632:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe

WARNING: line length of 113 exceeds 100 columns
#35918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20633:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf

WARNING: line length of 121 exceeds 100 columns
#35919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20634:
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20635:
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#35921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20636:
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#35922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20637:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#35923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20638:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#35924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20639:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#35925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20640:
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L

WARNING: line length of 113 exceeds 100 columns
#35926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20641:
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#35927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20642:
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L

WARNING: line length of 113 exceeds 100 columns
#35928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20643:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#35929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20644:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20645:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8

WARNING: line length of 113 exceeds 100 columns
#35931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20646:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#35932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20647:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20648:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20649:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20650:
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L

WARNING: line length of 113 exceeds 100 columns
#35936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20651:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#35937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20652:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20653:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8

WARNING: line length of 113 exceeds 100 columns
#35939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20654:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#35940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20655:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20656:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20657:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20658:
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L

WARNING: line length of 113 exceeds 100 columns
#35944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20659:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#35945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20660:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20661:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8

WARNING: line length of 113 exceeds 100 columns
#35947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20662:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#35948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20663:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20664:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20665:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20666:
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L

WARNING: line length of 113 exceeds 100 columns
#35952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20667:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#35953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20668:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#35954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20669:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8

WARNING: line length of 113 exceeds 100 columns
#35955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20670:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#35956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20671:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#35957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20672:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#35958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20673:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#35959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20674:
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L

WARNING: line length of 113 exceeds 100 columns
#35960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20675:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#35961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20676:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#35962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20677:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#35963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20678:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#35964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20679:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#35965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20680:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#35966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20681:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#35967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20682:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#35968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20683:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#35969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20684:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#35970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20685:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#35971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20686:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#35972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20687:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#35973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20688:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#35974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20689:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#35975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20690:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#35976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20691:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#35977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20692:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#35978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20693:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#35979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20694:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#35980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20695:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#35981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20696:
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#35982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20697:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#35983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20698:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#35984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20699:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#35985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20700:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#35986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20701:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#35987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20702:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#35988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20703:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#35989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20704:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#35990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20705:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#35991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20706:
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#35992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20707:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#35993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20708:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#35994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20709:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#35995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20710:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#35996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20711:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#35997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20712:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#35998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20713:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#35999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20714:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#36000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20715:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#36001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20716:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#36002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20717:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#36003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20718:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#36004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20719:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#36005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20720:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#36006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20721:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#36007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20722:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#36008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20723:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20724:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#36010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20725:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#36011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20726:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#36012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20727:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20728:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20729:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#36015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20730:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#36016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20731:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#36017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20732:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#36018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20733:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#36019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20734:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#36020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20735:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#36021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20736:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#36022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20737:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#36023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20738:
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#36024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20739:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#36025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20740:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#36026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20741:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#36027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20742:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#36028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20743:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#36029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20744:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#36030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20745:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20746:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#36032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20747:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#36033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20748:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#36034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20749:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#36035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20750:
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20751:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#36037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20752:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#36038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20753:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#36039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20754:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#36040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20755:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20756:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20757:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#36043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20758:
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#36044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20759:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#36045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20760:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#36046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20761:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#36047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20762:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#36048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20763:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#36049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20764:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#36050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20765:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#36051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20766:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#36052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20767:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#36053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20768:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#36054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20769:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#36055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20770:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#36056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20771:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#36057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20772:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#36058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20773:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#36059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20774:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#36060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20775:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20776:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20777:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20778:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#36064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20779:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#36065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20780:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20781:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#36067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20782:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#36068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20783:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#36069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20784:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20785:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20786:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20787:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20788:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20789:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20790:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#36076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20791:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#36077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20792:
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20793:
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#36079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20794:
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20795:
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#36081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20796:
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#36082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20797:
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20798:
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#36084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20799:
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20800:
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20801:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#36087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20802:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#36088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20803:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#36089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20804:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#36090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20805:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#36091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20806:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#36092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20807:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd

WARNING: line length of 114 exceeds 100 columns
#36093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20808:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#36094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20809:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20810:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20811:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20812:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20813:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20814:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20815:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20816:
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20817:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#36103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20818:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8

WARNING: line length of 114 exceeds 100 columns
#36104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20819:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#36105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20820:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#36106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20821:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#36107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20822:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#36108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20823:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20824:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20825:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#36111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20826:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#36112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20827:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#36113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20828:
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#36114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20829:
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#36115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20830:
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4

WARNING: line length of 121 exceeds 100 columns
#36116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20831:
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20832:
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L

WARNING: line length of 113 exceeds 100 columns
#36118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20833:
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#36119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20834:
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20835:
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#36121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20836:
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#36122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20837:
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#36123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20838:
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20839:
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#36125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20840:
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#36126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20841:
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2

WARNING: line length of 121 exceeds 100 columns
#36127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20842:
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20843:
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20844:
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#36130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20845:
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20846:
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20847:
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20848:
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20849:
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#36135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20850:
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20851:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#36137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20852:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#36138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20853:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#36139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20854:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#36140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20855:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#36141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20856:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#36142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20857:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd

WARNING: line length of 114 exceeds 100 columns
#36143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20858:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#36144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20859:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20860:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20861:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20862:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20863:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20864:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20865:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20866:
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20867:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#36153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20868:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8

WARNING: line length of 114 exceeds 100 columns
#36154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20869:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#36155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20870:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#36156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20871:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#36157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20872:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#36158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20873:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20874:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20875:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#36161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20876:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#36162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20877:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#36163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20878:
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#36164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20879:
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#36165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20880:
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4

WARNING: line length of 121 exceeds 100 columns
#36166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20881:
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20882:
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L

WARNING: line length of 113 exceeds 100 columns
#36168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20883:
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#36169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20884:
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20885:
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#36171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20886:
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#36172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20887:
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#36173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20888:
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20889:
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#36175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20890:
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#36176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20891:
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2

WARNING: line length of 121 exceeds 100 columns
#36177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20892:
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20893:
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20894:
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#36180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20895:
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20896:
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20897:
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20898:
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20899:
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#36185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20900:
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20901:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#36187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20902:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#36188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20903:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#36189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20904:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#36190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20905:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#36191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20906:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#36192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20907:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd

WARNING: line length of 114 exceeds 100 columns
#36193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20908:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#36194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20909:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20910:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20911:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20912:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20913:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20914:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20915:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20916:
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20917:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#36203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20918:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8

WARNING: line length of 114 exceeds 100 columns
#36204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20919:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#36205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20920:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#36206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20921:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#36207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20922:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#36208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20923:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20924:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20925:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#36211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20926:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#36212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20927:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#36213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20928:
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#36214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20929:
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#36215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20930:
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4

WARNING: line length of 121 exceeds 100 columns
#36216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20931:
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20932:
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L

WARNING: line length of 113 exceeds 100 columns
#36218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20933:
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#36219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20934:
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20935:
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#36221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20936:
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#36222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20937:
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#36223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20938:
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20939:
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#36225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20940:
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#36226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20941:
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2

WARNING: line length of 121 exceeds 100 columns
#36227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20942:
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20943:
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20944:
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#36230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20945:
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20946:
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20947:
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20948:
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20949:
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#36235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20950:
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20951:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#36237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20952:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#36238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20953:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#36239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20954:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#36240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20955:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb

WARNING: line length of 113 exceeds 100 columns
#36241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20956:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#36242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20957:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd

WARNING: line length of 114 exceeds 100 columns
#36243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20958:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#36244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20959:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20960:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20961:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20962:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20963:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20964:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20965:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20966:
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20967:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#36253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20968:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8

WARNING: line length of 114 exceeds 100 columns
#36254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20969:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#36255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20970:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#36256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20971:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#36257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20972:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c

WARNING: line length of 121 exceeds 100 columns
#36258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20973:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20974:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20975:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#36261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20976:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#36262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20977:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#36263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20978:
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#36264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20979:
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#36265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20980:
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4

WARNING: line length of 121 exceeds 100 columns
#36266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20981:
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20982:
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L

WARNING: line length of 113 exceeds 100 columns
#36268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20983:
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#36269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20984:
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20985:
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#36271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20986:
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#36272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20987:
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#36273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20988:
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20989:
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#36275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20990:
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#36276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20991:
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2

WARNING: line length of 121 exceeds 100 columns
#36277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20992:
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20993:
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20994:
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#36280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20995:
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20996:
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20997:
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20998:
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:20999:
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#36285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21000:
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21001:
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#36287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21002:
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21003:
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#36289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21004:
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#36290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21005:
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21006:
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21007:
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21008:
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#36294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21009:
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21010:
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21011:
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#36297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21012:
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#36298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21013:
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11

WARNING: line length of 121 exceeds 100 columns
#36299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21014:
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21015:
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21016:
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L

WARNING: line length of 113 exceeds 100 columns
#36302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21017:
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#36303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21018:
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#36304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21019:
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#36305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21020:
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21021:
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21022:
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L

WARNING: line length of 113 exceeds 100 columns
#36308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21023:
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#36309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21024:
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21025:
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21026:
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21027:
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21028:
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21029:
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21030:
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21031:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#36317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21032:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#36318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21033:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#36319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21034:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#36320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21035:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#36321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21036:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#36322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21037:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#36323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21038:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#36324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21039:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21040:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21041:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#36327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21042:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#36328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21043:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21044:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#36330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21045:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#36331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21046:
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21047:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#36333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21048:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#36334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21049:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8

WARNING: line length of 113 exceeds 100 columns
#36335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21050:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc

WARNING: line length of 121 exceeds 100 columns
#36336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21051:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21052:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21053:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21054:
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#36340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21055:
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#36341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21056:
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#36342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21057:
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21058:
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#36344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21059:
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#36345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21060:
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#36346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21061:
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21062:
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21063:
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21064:
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#36350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21065:
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21066:
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21067:
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#36353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21068:
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#36354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21069:
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21070:
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#36356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21071:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#36357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21072:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#36358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21073:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#36359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21074:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#36360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21075:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#36361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21076:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#36362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21077:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#36363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21078:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#36364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21079:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#36365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21080:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#36366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21081:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#36367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21082:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#36368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21083:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#36369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21084:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#36370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21085:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#36371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21086:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21087:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21088:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21089:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#36375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21090:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#36376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21091:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#36377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21092:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#36378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21093:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#36379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21094:
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21095:
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#36381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21096:
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21097:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#36383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21098:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#36384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21099:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#36385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21100:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#36386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21101:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#36387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21102:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#36388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21103:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#36389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21104:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#36390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21105:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#36391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21106:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#36392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21107:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#36393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21108:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#36394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21109:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#36395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21110:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#36396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21111:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#36397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21112:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21113:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21114:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21115:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#36401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21116:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#36402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21117:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#36403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21118:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#36404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21119:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#36405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21120:
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21121:
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#36407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21122:
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21123:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#36409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21124:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#36410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21125:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#36411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21126:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#36412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21127:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#36413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21128:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21129:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21130:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21131:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21132:
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#36418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21133:
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#36419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21134:
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L

WARNING: line length of 113 exceeds 100 columns
#36420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21135:
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#36421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21136:
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#36422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21137:
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#36423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21138:
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd

WARNING: line length of 113 exceeds 100 columns
#36424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21139:
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#36425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21140:
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#36426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21141:
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14

WARNING: line length of 121 exceeds 100 columns
#36427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21142:
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21143:
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21144:
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21145:
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21146:
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#36432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21147:
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21148:
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L

WARNING: line length of 113 exceeds 100 columns
#36434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21149:
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#36435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21150:
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#36436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21151:
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21152:
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L

WARNING: line length of 113 exceeds 100 columns
#36438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21153:
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#36439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21154:
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1

WARNING: line length of 121 exceeds 100 columns
#36440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21155:
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21156:
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L

WARNING: line length of 113 exceeds 100 columns
#36442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21157:
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21158:
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#36444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21159:
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21160:
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21161:
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#36447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21162:
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#36448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21163:
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#36449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21164:
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1

WARNING: line length of 113 exceeds 100 columns
#36450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21165:
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#36451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21166:
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#36452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21167:
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5

WARNING: line length of 114 exceeds 100 columns
#36453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21168:
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#36454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21169:
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11

WARNING: line length of 114 exceeds 100 columns
#36455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21170:
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12

WARNING: line length of 121 exceeds 100 columns
#36456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21171:
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21172:
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21173:
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#36459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21174:
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#36460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21175:
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#36461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21176:
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21177:
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#36463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21178:
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L

WARNING: line length of 113 exceeds 100 columns
#36464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21179:
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#36465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21180:
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#36466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21181:
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21182:
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21183:
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#36469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21184:
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21185:
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#36471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21186:
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21187:
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#36473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21188:
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21189:
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#36475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21190:
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21191:
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#36477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21192:
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1

WARNING: line length of 121 exceeds 100 columns
#36478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21193:
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21194:
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL

WARNING: line length of 113 exceeds 100 columns
#36480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21195:
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#36481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21196:
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21197:
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#36483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21198:
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21199:
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#36485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21200:
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#36486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21201:
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#36487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21202:
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21203:
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21204:
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L

WARNING: line length of 113 exceeds 100 columns
#36490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21205:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#36491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21206:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#36492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21207:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#36493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21208:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#36494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21209:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#36495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21210:
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e

WARNING: line length of 114 exceeds 100 columns
#36496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21211:
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#36497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21212:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21213:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21214:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21215:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21216:
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#36502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21217:
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L

WARNING: line length of 121 exceeds 100 columns
#36503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21218:
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21219:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#36505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21220:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf

WARNING: line length of 114 exceeds 100 columns
#36506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21221:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#36507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21222:
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12

WARNING: line length of 114 exceeds 100 columns
#36508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21223:
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#36509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21224:
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#36510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21225:
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#36511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21226:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#36512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21227:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21228:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#36514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21229:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#36515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21230:
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#36516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21231:
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#36517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21232:
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21233:
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#36519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21234:
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#36520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21235:
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#36521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21236:
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#36522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21237:
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#36523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21238:
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21239:
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21240:
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#36526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21241:
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21242:
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#36528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21243:
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#36529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21244:
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#36530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21245:
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21246:
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21247:
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#36533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21248:
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21249:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#36535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21250:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#36536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21251:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#36537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21252:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9

WARNING: line length of 114 exceeds 100 columns
#36538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21253:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#36539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21254:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11

WARNING: line length of 114 exceeds 100 columns
#36540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21255:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#36541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21256:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#36542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21257:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#36543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21258:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b

WARNING: line length of 114 exceeds 100 columns
#36544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21259:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c

WARNING: line length of 114 exceeds 100 columns
#36545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21260:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#36546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21261:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#36547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21262:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#36548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21263:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21264:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21265:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21266:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21267:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21268:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#36554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21269:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#36555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21270:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#36556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21271:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#36557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21272:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L

WARNING: line length of 121 exceeds 100 columns
#36558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21273:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L

WARNING: line length of 121 exceeds 100 columns
#36559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21274:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#36560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21275:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#36561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21276:
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21277:
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21278:
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21279:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#36565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21280:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#36566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21281:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#36567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21282:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#36568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21283:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#36569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21284:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#36570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21285:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9

WARNING: line length of 113 exceeds 100 columns
#36571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21286:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#36572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21287:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#36573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21288:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21289:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21290:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#36576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21291:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#36577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21292:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#36578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21293:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21294:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21295:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21296:
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L

WARNING: line length of 113 exceeds 100 columns
#36582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21297:
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#36583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21298:
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21299:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#36585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21300:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10

WARNING: line length of 121 exceeds 100 columns
#36586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21301:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21302:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21303:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4

WARNING: line length of 113 exceeds 100 columns
#36589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21304:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#36590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21305:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#36591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21306:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#36592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21307:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#36593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21308:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18

WARNING: line length of 114 exceeds 100 columns
#36594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21309:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#36595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21310:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21311:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21312:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21313:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21314:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21315:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#36601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21316:
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L

WARNING: line length of 113 exceeds 100 columns
#36602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21317:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#36603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21318:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21319:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#36605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21320:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#36606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21321:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#36607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21322:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#36608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21323:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#36609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21324:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21325:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21326:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21327:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21328:
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#36614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21329:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#36615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21330:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21331:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#36617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21332:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#36618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21333:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#36619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21334:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#36620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21335:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#36621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21336:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21337:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21338:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21339:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21340:
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#36626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21341:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#36627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21342:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3

WARNING: line length of 113 exceeds 100 columns
#36628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21343:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#36629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21344:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#36630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21345:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7

WARNING: line length of 113 exceeds 100 columns
#36631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21346:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#36632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21347:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa

WARNING: line length of 113 exceeds 100 columns
#36633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21348:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc

WARNING: line length of 114 exceeds 100 columns
#36634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21349:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13

WARNING: line length of 114 exceeds 100 columns
#36635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21350:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#36636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21351:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#36637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21352:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#36638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21353:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#36639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21354:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#36640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21355:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#36641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21356:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21357:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#36643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21358:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21359:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#36645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21360:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#36646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21361:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21362:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21363:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L

WARNING: line length of 121 exceeds 100 columns
#36649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21364:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#36650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21365:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L

WARNING: line length of 121 exceeds 100 columns
#36651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21366:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#36652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21367:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#36653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21368:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#36654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21369:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#36655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21370:
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21371:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21372:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21373:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21374:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21375:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21376:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21377:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21378:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21379:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21380:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21381:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21382:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21383:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21384:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21385:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21386:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21387:
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#36673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21388:
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#36674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21389:
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21390:
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21391:
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#36677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21392:
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21393:
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21394:
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21395:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21396:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21397:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21398:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21399:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21400:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21401:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21402:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21403:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21404:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21405:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21406:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21407:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21408:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21409:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21410:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21411:
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#36697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21412:
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#36698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21413:
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21414:
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21415:
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#36701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21416:
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21417:
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21418:
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21419:
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#36705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21420:
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#36706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21421:
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21422:
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21423:
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#36709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21424:
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21425:
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21426:
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21427:
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#36713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21428:
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#36714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21429:
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21430:
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21431:
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#36717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21432:
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21433:
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21434:
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21435:
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21436:
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21437:
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21438:
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21439:
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#36725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21440:
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21441:
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21442:
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#36728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21443:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#36729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21444:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#36730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21445:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#36731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21446:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#36732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21447:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#36733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21448:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b

WARNING: line length of 114 exceeds 100 columns
#36734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21449:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#36735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21450:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e

WARNING: line length of 114 exceeds 100 columns
#36736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21451:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#36737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21452:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21453:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#36739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21454:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#36740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21455:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#36741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21456:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#36742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21457:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#36743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21458:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#36744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21459:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L

WARNING: line length of 121 exceeds 100 columns
#36745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21460:
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21461:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#36747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21462:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#36748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21463:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#36749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21464:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#36750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21465:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11

WARNING: line length of 114 exceeds 100 columns
#36751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21466:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12

WARNING: line length of 121 exceeds 100 columns
#36752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21467:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21468:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#36754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21469:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21470:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21471:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#36757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21472:
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L

WARNING: line length of 113 exceeds 100 columns
#36758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21473:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#36759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21474:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#36760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21475:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#36761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21476:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#36762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21477:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13

WARNING: line length of 114 exceeds 100 columns
#36763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21478:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#36764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21479:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17

WARNING: line length of 114 exceeds 100 columns
#36765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21480:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#36766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21481:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#36767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21482:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#36768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21483:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21484:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L

WARNING: line length of 121 exceeds 100 columns
#36770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21485:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#36771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21486:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21487:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L

WARNING: line length of 121 exceeds 100 columns
#36773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21488:
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#36774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21489:
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#36775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21490:
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L

WARNING: line length of 113 exceeds 100 columns
#36776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21491:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#36777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21492:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#36778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21493:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#36779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21494:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#36780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21495:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#36781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21496:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21497:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21498:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21499:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21500:
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L

WARNING: line length of 113 exceeds 100 columns
#36786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21501:
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0

WARNING: line length of 121 exceeds 100 columns
#36787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21502:
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#36788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21503:
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#36789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21504:
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#36790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21505:
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21506:
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#36792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21507:
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#36793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21508:
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#36794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21509:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#36795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21510:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#36796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21511:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#36797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21512:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#36798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21513:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#36799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21514:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5

WARNING: line length of 113 exceeds 100 columns
#36800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21515:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#36801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21516:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7

WARNING: line length of 113 exceeds 100 columns
#36802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21517:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#36803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21518:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#36804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21519:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa

WARNING: line length of 113 exceeds 100 columns
#36805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21520:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#36806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21521:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#36807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21522:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#36808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21523:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe

WARNING: line length of 113 exceeds 100 columns
#36809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21524:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf

WARNING: line length of 114 exceeds 100 columns
#36810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21525:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#36811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21526:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#36812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21527:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#36813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21528:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13

WARNING: line length of 114 exceeds 100 columns
#36814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21529:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#36815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21530:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15

WARNING: line length of 114 exceeds 100 columns
#36816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21531:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#36817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21532:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#36818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21533:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19

WARNING: line length of 121 exceeds 100 columns
#36819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21534:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21535:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21536:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#36822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21537:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#36823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21538:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21539:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#36825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21540:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#36826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21541:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#36827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21542:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21543:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#36829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21544:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21545:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#36831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21546:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21547:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21548:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#36834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21549:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#36835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21550:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21551:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#36837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21552:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#36838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21553:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#36839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21554:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21555:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#36841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21556:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#36842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21557:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#36843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21558:
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L

WARNING: line length of 113 exceeds 100 columns
#36844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21559:
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#36845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21560:
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#36846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21561:
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21562:
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#36848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21563:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#36849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21564:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#36850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21565:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#36851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21566:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3

WARNING: line length of 113 exceeds 100 columns
#36852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21567:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#36853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21568:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#36854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21569:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#36855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21570:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c

WARNING: line length of 114 exceeds 100 columns
#36856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21571:
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#36857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21572:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21573:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#36859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21574:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#36860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21575:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#36861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21576:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L

WARNING: line length of 121 exceeds 100 columns
#36862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21577:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#36863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21578:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#36864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21579:
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L

WARNING: line length of 121 exceeds 100 columns
#36865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21580:
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21581:
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#36867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21582:
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#36868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21583:
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21584:
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21585:
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#36871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21586:
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#36872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21587:
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21588:
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21589:
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#36875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21590:
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#36876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21591:
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f

WARNING: line length of 121 exceeds 100 columns
#36877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21592:
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#36878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21593:
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#36879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21594:
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21595:
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#36881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21596:
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#36882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21597:
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#36883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21598:
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21599:
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#36885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21600:
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21601:
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#36887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21602:
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#36888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21603:
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#36889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21604:
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21605:
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#36891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21606:
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21607:
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#36893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21608:
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#36894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21609:
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19

WARNING: line length of 114 exceeds 100 columns
#36895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21610:
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#36896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21611:
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#36897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21612:
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#36898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21613:
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#36899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21614:
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L

WARNING: line length of 121 exceeds 100 columns
#36900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21615:
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#36901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21616:
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21617:
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#36903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21618:
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4

WARNING: line length of 114 exceeds 100 columns
#36904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21619:
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#36905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21620:
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#36906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21621:
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21622:
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#36908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21623:
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L

WARNING: line length of 121 exceeds 100 columns
#36909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21624:
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L

WARNING: line length of 113 exceeds 100 columns
#36910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21625:
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#36911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21626:
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#36912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21627:
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#36913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21628:
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21629:
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#36915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21630:
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#36916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21631:
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#36917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21632:
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21633:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#36919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21634:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#36920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21635:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8

WARNING: line length of 113 exceeds 100 columns
#36921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21636:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc

WARNING: line length of 113 exceeds 100 columns
#36922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21637:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd

WARNING: line length of 114 exceeds 100 columns
#36923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21638:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#36924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21639:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14

WARNING: line length of 114 exceeds 100 columns
#36925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21640:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18

WARNING: line length of 114 exceeds 100 columns
#36926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21641:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c

WARNING: line length of 114 exceeds 100 columns
#36927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21642:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d

WARNING: line length of 121 exceeds 100 columns
#36928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21643:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21644:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21645:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21646:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#36932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21647:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#36933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21648:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21649:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#36935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21650:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#36936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21651:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#36937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21652:
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L

WARNING: line length of 113 exceeds 100 columns
#36938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21653:
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0

WARNING: line length of 114 exceeds 100 columns
#36939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21654:
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10

WARNING: line length of 121 exceeds 100 columns
#36940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21655:
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21656:
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21657:
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#36943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21658:
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21659:
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#36945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21660:
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#36946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21661:
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21662:
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21663:
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#36949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21664:
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#36950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21665:
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21666:
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21667:
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#36953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21668:
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21669:
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#36955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21670:
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21671:
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#36957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21672:
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#36958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21673:
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21674:
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#36960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21675:
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21676:
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#36962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21677:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#36963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21678:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#36964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21679:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#36965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21680:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#36966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21681:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21682:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#36968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21683:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21684:
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L

WARNING: line length of 113 exceeds 100 columns
#36970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21685:
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#36971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21686:
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#36972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21687:
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#36973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21688:
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21689:
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#36975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21690:
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#36976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21691:
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21692:
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21693:
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#36979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21694:
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#36980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21695:
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#36981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21696:
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#36982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21697:
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#36983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21698:
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#36984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21699:
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11

WARNING: line length of 121 exceeds 100 columns
#36985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21700:
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#36986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21701:
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#36987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21702:
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L

WARNING: line length of 113 exceeds 100 columns
#36988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21703:
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#36989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21704:
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#36990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21705:
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#36991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21706:
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#36992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21707:
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#36993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21708:
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L

WARNING: line length of 113 exceeds 100 columns
#36994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21709:
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#36995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21710:
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21711:
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21712:
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#36998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21713:
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#36999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21714:
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21715:
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21716:
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21717:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21718:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#37004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21719:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#37005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21720:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#37006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21721:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#37007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21722:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#37008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21723:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#37009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21724:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#37010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21725:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21726:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21727:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#37013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21728:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#37014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21729:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21730:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#37016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21731:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#37017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21732:
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21733:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#37019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21734:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#37020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21735:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8

WARNING: line length of 113 exceeds 100 columns
#37021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21736:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc

WARNING: line length of 121 exceeds 100 columns
#37022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21737:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21738:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21739:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21740:
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#37026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21741:
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21742:
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#37028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21743:
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21744:
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#37030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21745:
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#37031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21746:
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#37032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21747:
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21748:
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21749:
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#37035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21750:
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#37036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21751:
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21752:
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21753:
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#37039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21754:
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#37040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21755:
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21756:
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#37042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21757:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21758:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#37044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21759:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#37045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21760:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#37046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21761:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#37047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21762:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#37048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21763:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#37049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21764:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#37050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21765:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#37051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21766:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#37052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21767:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#37053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21768:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#37054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21769:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#37055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21770:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#37056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21771:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#37057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21772:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#37058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21773:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21774:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21775:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#37061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21776:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#37062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21777:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#37063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21778:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#37064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21779:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#37065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21780:
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21781:
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21782:
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21783:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21784:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#37070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21785:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#37071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21786:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#37072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21787:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#37073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21788:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#37074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21789:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#37075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21790:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#37076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21791:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#37077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21792:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#37078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21793:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#37079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21794:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#37080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21795:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#37081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21796:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#37082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21797:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#37083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21798:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#37084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21799:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21800:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21801:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#37087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21802:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#37088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21803:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#37089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21804:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#37090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21805:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#37091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21806:
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21807:
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21808:
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21809:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#37095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21810:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#37096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21811:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#37097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21812:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#37098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21813:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#37099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21814:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#37100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21815:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21816:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21817:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21818:
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21819:
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#37105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21820:
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L

WARNING: line length of 113 exceeds 100 columns
#37106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21821:
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#37107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21822:
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#37108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21823:
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#37109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21824:
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd

WARNING: line length of 113 exceeds 100 columns
#37110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21825:
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#37111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21826:
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#37112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21827:
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14

WARNING: line length of 121 exceeds 100 columns
#37113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21828:
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21829:
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#37115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21830:
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21831:
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21832:
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#37118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21833:
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21834:
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L

WARNING: line length of 113 exceeds 100 columns
#37120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21835:
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#37121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21836:
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#37122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21837:
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21838:
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L

WARNING: line length of 113 exceeds 100 columns
#37124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21839:
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#37125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21840:
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1

WARNING: line length of 121 exceeds 100 columns
#37126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21841:
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21842:
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L

WARNING: line length of 113 exceeds 100 columns
#37128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21843:
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#37129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21844:
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#37130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21845:
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21846:
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21847:
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#37133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21848:
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#37134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21849:
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21850:
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1

WARNING: line length of 113 exceeds 100 columns
#37136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21851:
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#37137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21852:
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#37138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21853:
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5

WARNING: line length of 114 exceeds 100 columns
#37139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21854:
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#37140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21855:
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11

WARNING: line length of 114 exceeds 100 columns
#37141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21856:
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12

WARNING: line length of 121 exceeds 100 columns
#37142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21857:
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21858:
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21859:
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#37145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21860:
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#37146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21861:
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#37147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21862:
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21863:
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21864:
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L

WARNING: line length of 113 exceeds 100 columns
#37150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21865:
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#37151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21866:
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#37152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21867:
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21868:
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21869:
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#37155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21870:
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21871:
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#37157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21872:
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21873:
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#37159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21874:
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21875:
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#37161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21876:
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21877:
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21878:
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1

WARNING: line length of 121 exceeds 100 columns
#37164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21879:
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21880:
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL

WARNING: line length of 113 exceeds 100 columns
#37166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21881:
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#37167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21882:
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21883:
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#37169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21884:
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21885:
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#37171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21886:
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#37172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21887:
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#37173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21888:
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21889:
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21890:
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L

WARNING: line length of 113 exceeds 100 columns
#37176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21891:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#37177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21892:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#37178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21893:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#37179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21894:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#37180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21895:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#37181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21896:
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e

WARNING: line length of 114 exceeds 100 columns
#37182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21897:
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#37183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21898:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21899:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21900:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21901:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21902:
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#37188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21903:
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L

WARNING: line length of 121 exceeds 100 columns
#37189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21904:
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21905:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#37191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21906:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf

WARNING: line length of 114 exceeds 100 columns
#37192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21907:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#37193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21908:
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12

WARNING: line length of 114 exceeds 100 columns
#37194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21909:
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#37195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21910:
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#37196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21911:
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#37197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21912:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#37198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21913:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21914:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#37200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21915:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21916:
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#37202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21917:
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#37203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21918:
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21919:
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#37205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21920:
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21921:
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#37207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21922:
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#37208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21923:
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#37209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21924:
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21925:
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21926:
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#37212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21927:
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21928:
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#37214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21929:
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#37215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21930:
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#37216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21931:
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21932:
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21933:
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21934:
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21935:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#37221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21936:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#37222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21937:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#37223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21938:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9

WARNING: line length of 114 exceeds 100 columns
#37224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21939:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#37225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21940:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11

WARNING: line length of 114 exceeds 100 columns
#37226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21941:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#37227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21942:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#37228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21943:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#37229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21944:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b

WARNING: line length of 114 exceeds 100 columns
#37230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21945:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c

WARNING: line length of 114 exceeds 100 columns
#37231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21946:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#37232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21947:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#37233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21948:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#37234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21949:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21950:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21951:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21952:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#37238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21953:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21954:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21955:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#37241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21956:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#37242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21957:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#37243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21958:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L

WARNING: line length of 121 exceeds 100 columns
#37244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21959:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L

WARNING: line length of 121 exceeds 100 columns
#37245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21960:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#37246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21961:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#37247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21962:
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21963:
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21964:
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21965:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#37251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21966:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#37252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21967:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#37253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21968:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#37254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21969:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#37255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21970:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#37256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21971:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9

WARNING: line length of 113 exceeds 100 columns
#37257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21972:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#37258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21973:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#37259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21974:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21975:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21976:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#37262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21977:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#37263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21978:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#37264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21979:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21980:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#37266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21981:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#37267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21982:
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L

WARNING: line length of 113 exceeds 100 columns
#37268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21983:
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21984:
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21985:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#37271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21986:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10

WARNING: line length of 121 exceeds 100 columns
#37272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21987:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21988:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21989:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4

WARNING: line length of 113 exceeds 100 columns
#37275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21990:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#37276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21991:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#37277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21992:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#37278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21993:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#37279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21994:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18

WARNING: line length of 114 exceeds 100 columns
#37280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21995:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#37281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21996:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21997:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21998:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:21999:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22000:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22001:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#37287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22002:
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L

WARNING: line length of 113 exceeds 100 columns
#37288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22003:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#37289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22004:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22005:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#37291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22006:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#37292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22007:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#37293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22008:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#37294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22009:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#37295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22010:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22011:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22012:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22013:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22014:
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22015:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#37301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22016:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22017:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#37303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22018:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#37304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22019:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#37305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22020:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#37306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22021:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#37307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22022:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22023:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22024:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22025:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22026:
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22027:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22028:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3

WARNING: line length of 113 exceeds 100 columns
#37314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22029:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#37315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22030:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#37316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22031:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7

WARNING: line length of 113 exceeds 100 columns
#37317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22032:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#37318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22033:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa

WARNING: line length of 113 exceeds 100 columns
#37319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22034:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc

WARNING: line length of 114 exceeds 100 columns
#37320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22035:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13

WARNING: line length of 114 exceeds 100 columns
#37321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22036:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#37322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22037:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#37323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22038:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#37324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22039:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#37325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22040:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#37326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22041:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#37327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22042:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22043:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#37329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22044:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22045:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#37331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22046:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#37332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22047:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#37333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22048:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#37334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22049:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L

WARNING: line length of 121 exceeds 100 columns
#37335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22050:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#37336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22051:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L

WARNING: line length of 121 exceeds 100 columns
#37337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22052:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#37338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22053:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#37339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22054:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#37340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22055:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#37341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22056:
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22057:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22058:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22059:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22060:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22061:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22062:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22063:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22064:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22065:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22066:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22067:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22068:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22069:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22070:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22071:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22072:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22073:
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#37359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22074:
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#37360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22075:
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22076:
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22077:
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#37363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22078:
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#37364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22079:
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22080:
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22081:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22082:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22083:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22084:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22085:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22086:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22087:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22088:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22089:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22090:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22091:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22092:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22093:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22094:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22095:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22096:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22097:
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#37383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22098:
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#37384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22099:
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22100:
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22101:
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#37387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22102:
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#37388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22103:
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22104:
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22105:
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#37391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22106:
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#37392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22107:
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22108:
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22109:
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#37395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22110:
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#37396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22111:
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22112:
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22113:
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#37399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22114:
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#37400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22115:
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22116:
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22117:
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#37403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22118:
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#37404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22119:
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22120:
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22121:
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#37407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22122:
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22123:
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22124:
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22125:
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#37411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22126:
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#37412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22127:
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22128:
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22129:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#37415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22130:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#37416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22131:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#37417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22132:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#37418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22133:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#37419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22134:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b

WARNING: line length of 114 exceeds 100 columns
#37420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22135:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#37421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22136:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e

WARNING: line length of 114 exceeds 100 columns
#37422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22137:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#37423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22138:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22139:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#37425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22140:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#37426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22141:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#37427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22142:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#37428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22143:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#37429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22144:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#37430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22145:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L

WARNING: line length of 121 exceeds 100 columns
#37431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22146:
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22147:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#37433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22148:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#37434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22149:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#37435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22150:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#37436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22151:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11

WARNING: line length of 114 exceeds 100 columns
#37437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22152:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12

WARNING: line length of 121 exceeds 100 columns
#37438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22153:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22154:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#37440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22155:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22156:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22157:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22158:
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L

WARNING: line length of 113 exceeds 100 columns
#37444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22159:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#37445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22160:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#37446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22161:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#37447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22162:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#37448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22163:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13

WARNING: line length of 114 exceeds 100 columns
#37449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22164:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#37450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22165:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17

WARNING: line length of 114 exceeds 100 columns
#37451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22166:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#37452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22167:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#37453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22168:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#37454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22169:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22170:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L

WARNING: line length of 121 exceeds 100 columns
#37456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22171:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#37457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22172:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22173:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L

WARNING: line length of 121 exceeds 100 columns
#37459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22174:
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#37460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22175:
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#37461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22176:
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L

WARNING: line length of 113 exceeds 100 columns
#37462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22177:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#37463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22178:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#37464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22179:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#37465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22180:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#37466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22181:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#37467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22182:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22183:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22184:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22185:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22186:
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L

WARNING: line length of 113 exceeds 100 columns
#37472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22187:
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0

WARNING: line length of 121 exceeds 100 columns
#37473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22188:
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#37474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22189:
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#37475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22190:
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#37476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22191:
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22192:
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#37478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22193:
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#37479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22194:
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#37480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22195:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22196:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#37482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22197:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#37483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22198:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#37484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22199:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#37485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22200:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5

WARNING: line length of 113 exceeds 100 columns
#37486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22201:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#37487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22202:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7

WARNING: line length of 113 exceeds 100 columns
#37488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22203:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#37489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22204:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#37490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22205:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa

WARNING: line length of 113 exceeds 100 columns
#37491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22206:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#37492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22207:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#37493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22208:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#37494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22209:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe

WARNING: line length of 113 exceeds 100 columns
#37495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22210:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf

WARNING: line length of 114 exceeds 100 columns
#37496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22211:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#37497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22212:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#37498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22213:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#37499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22214:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13

WARNING: line length of 114 exceeds 100 columns
#37500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22215:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#37501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22216:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15

WARNING: line length of 114 exceeds 100 columns
#37502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22217:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#37503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22218:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#37504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22219:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19

WARNING: line length of 121 exceeds 100 columns
#37505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22220:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22221:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22222:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#37508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22223:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#37509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22224:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22225:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#37511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22226:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#37512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22227:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#37513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22228:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22229:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#37515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22230:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#37516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22231:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#37517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22232:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22233:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22234:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#37520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22235:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#37521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22236:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22237:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22238:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#37524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22239:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#37525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22240:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22241:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#37527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22242:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#37528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22243:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#37529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22244:
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L

WARNING: line length of 113 exceeds 100 columns
#37530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22245:
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#37531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22246:
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#37532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22247:
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22248:
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#37534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22249:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#37535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22250:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#37536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22251:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#37537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22252:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3

WARNING: line length of 113 exceeds 100 columns
#37538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22253:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#37539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22254:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#37540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22255:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#37541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22256:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c

WARNING: line length of 114 exceeds 100 columns
#37542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22257:
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#37543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22258:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22259:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22260:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#37546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22261:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#37547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22262:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L

WARNING: line length of 121 exceeds 100 columns
#37548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22263:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#37549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22264:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#37550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22265:
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L

WARNING: line length of 121 exceeds 100 columns
#37551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22266:
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22267:
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#37553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22268:
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#37554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22269:
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22270:
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22271:
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#37557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22272:
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#37558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22273:
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22274:
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22275:
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#37561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22276:
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#37562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22277:
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f

WARNING: line length of 121 exceeds 100 columns
#37563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22278:
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22279:
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#37565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22280:
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22281:
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#37567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22282:
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#37568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22283:
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#37569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22284:
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22285:
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#37571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22286:
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22287:
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#37573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22288:
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#37574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22289:
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#37575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22290:
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22291:
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#37577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22292:
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22293:
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#37579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22294:
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#37580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22295:
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19

WARNING: line length of 114 exceeds 100 columns
#37581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22296:
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#37582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22297:
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#37583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22298:
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#37584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22299:
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#37585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22300:
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L

WARNING: line length of 121 exceeds 100 columns
#37586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22301:
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#37587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22302:
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22303:
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#37589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22304:
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4

WARNING: line length of 114 exceeds 100 columns
#37590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22305:
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#37591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22306:
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#37592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22307:
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#37593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22308:
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#37594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22309:
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L

WARNING: line length of 121 exceeds 100 columns
#37595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22310:
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L

WARNING: line length of 113 exceeds 100 columns
#37596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22311:
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#37597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22312:
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#37598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22313:
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#37599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22314:
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22315:
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#37601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22316:
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22317:
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22318:
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22319:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#37605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22320:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#37606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22321:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8

WARNING: line length of 113 exceeds 100 columns
#37607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22322:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc

WARNING: line length of 113 exceeds 100 columns
#37608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22323:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd

WARNING: line length of 114 exceeds 100 columns
#37609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22324:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#37610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22325:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14

WARNING: line length of 114 exceeds 100 columns
#37611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22326:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18

WARNING: line length of 114 exceeds 100 columns
#37612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22327:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c

WARNING: line length of 114 exceeds 100 columns
#37613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22328:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d

WARNING: line length of 121 exceeds 100 columns
#37614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22329:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22330:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22331:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22332:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22333:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22334:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22335:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22336:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#37622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22337:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#37623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22338:
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L

WARNING: line length of 113 exceeds 100 columns
#37624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22339:
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0

WARNING: line length of 114 exceeds 100 columns
#37625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22340:
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10

WARNING: line length of 121 exceeds 100 columns
#37626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22341:
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22342:
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22343:
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#37629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22344:
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22345:
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#37631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22346:
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#37632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22347:
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22348:
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22349:
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#37635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22350:
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#37636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22351:
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#37637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22352:
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22353:
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#37639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22354:
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22355:
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#37641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22356:
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22357:
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#37643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22358:
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22359:
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#37645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22360:
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#37646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22361:
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22362:
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#37648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22363:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22364:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#37650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22365:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#37651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22366:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#37652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22367:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22368:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22369:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22370:
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L

WARNING: line length of 113 exceeds 100 columns
#37656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22371:
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#37657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22372:
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22373:
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#37659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22374:
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22375:
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#37661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22376:
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#37662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22377:
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22378:
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22379:
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#37665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22380:
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#37666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22381:
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22382:
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22383:
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#37669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22384:
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#37670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22385:
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11

WARNING: line length of 121 exceeds 100 columns
#37671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22386:
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22387:
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22388:
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L

WARNING: line length of 113 exceeds 100 columns
#37674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22389:
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22390:
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#37676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22391:
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#37677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22392:
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#37678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22393:
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22394:
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L

WARNING: line length of 113 exceeds 100 columns
#37680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22395:
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#37681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22396:
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22397:
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22398:
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22399:
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22400:
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22401:
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22402:
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22403:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22404:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#37690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22405:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#37691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22406:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#37692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22407:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#37693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22408:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#37694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22409:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#37695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22410:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#37696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22411:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22412:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22413:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#37699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22414:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#37700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22415:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22416:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#37702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22417:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#37703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22418:
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22419:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#37705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22420:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#37706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22421:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8

WARNING: line length of 113 exceeds 100 columns
#37707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22422:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc

WARNING: line length of 121 exceeds 100 columns
#37708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22423:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22424:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22425:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22426:
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#37712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22427:
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22428:
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#37714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22429:
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22430:
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#37716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22431:
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#37717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22432:
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#37718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22433:
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22434:
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22435:
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#37721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22436:
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#37722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22437:
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22438:
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22439:
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#37725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22440:
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#37726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22441:
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22442:
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#37728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22443:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22444:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#37730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22445:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#37731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22446:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#37732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22447:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#37733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22448:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#37734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22449:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#37735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22450:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#37736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22451:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#37737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22452:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#37738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22453:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#37739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22454:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#37740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22455:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#37741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22456:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#37742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22457:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#37743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22458:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#37744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22459:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22460:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22461:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#37747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22462:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#37748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22463:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#37749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22464:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#37750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22465:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#37751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22466:
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22467:
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22468:
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22469:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22470:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#37756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22471:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#37757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22472:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#37758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22473:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#37759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22474:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#37760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22475:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#37761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22476:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#37762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22477:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#37763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22478:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#37764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22479:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#37765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22480:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#37766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22481:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#37767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22482:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#37768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22483:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#37769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22484:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#37770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22485:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22486:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22487:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#37773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22488:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#37774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22489:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#37775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22490:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#37776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22491:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#37777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22492:
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22493:
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22494:
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22495:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#37781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22496:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#37782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22497:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#37783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22498:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#37784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22499:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#37785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22500:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#37786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22501:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22502:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22503:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22504:
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22505:
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#37791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22506:
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L

WARNING: line length of 113 exceeds 100 columns
#37792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22507:
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#37793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22508:
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#37794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22509:
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#37795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22510:
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd

WARNING: line length of 113 exceeds 100 columns
#37796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22511:
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#37797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22512:
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#37798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22513:
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14

WARNING: line length of 121 exceeds 100 columns
#37799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22514:
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22515:
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#37801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22516:
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22517:
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#37803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22518:
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#37804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22519:
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22520:
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L

WARNING: line length of 113 exceeds 100 columns
#37806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22521:
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#37807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22522:
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#37808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22523:
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22524:
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L

WARNING: line length of 113 exceeds 100 columns
#37810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22525:
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#37811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22526:
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1

WARNING: line length of 121 exceeds 100 columns
#37812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22527:
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22528:
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L

WARNING: line length of 113 exceeds 100 columns
#37814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22529:
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#37815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22530:
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#37816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22531:
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#37817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22532:
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#37818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22533:
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#37819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22534:
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#37820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22535:
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#37821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22536:
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1

WARNING: line length of 113 exceeds 100 columns
#37822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22537:
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#37823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22538:
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#37824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22539:
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5

WARNING: line length of 114 exceeds 100 columns
#37825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22540:
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#37826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22541:
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11

WARNING: line length of 114 exceeds 100 columns
#37827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22542:
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12

WARNING: line length of 121 exceeds 100 columns
#37828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22543:
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22544:
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22545:
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#37831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22546:
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#37832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22547:
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#37833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22548:
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22549:
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22550:
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L

WARNING: line length of 113 exceeds 100 columns
#37836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22551:
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#37837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22552:
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#37838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22553:
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22554:
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22555:
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#37841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22556:
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22557:
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#37843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22558:
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22559:
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#37845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22560:
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22561:
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#37847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22562:
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22563:
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22564:
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1

WARNING: line length of 121 exceeds 100 columns
#37850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22565:
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22566:
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL

WARNING: line length of 113 exceeds 100 columns
#37852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22567:
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#37853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22568:
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22569:
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#37855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22570:
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22571:
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#37857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22572:
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#37858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22573:
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#37859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22574:
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22575:
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22576:
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L

WARNING: line length of 113 exceeds 100 columns
#37862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22577:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#37863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22578:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#37864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22579:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#37865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22580:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#37866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22581:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#37867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22582:
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e

WARNING: line length of 114 exceeds 100 columns
#37868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22583:
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#37869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22584:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22585:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22586:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22587:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22588:
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#37874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22589:
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L

WARNING: line length of 121 exceeds 100 columns
#37875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22590:
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22591:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#37877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22592:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf

WARNING: line length of 114 exceeds 100 columns
#37878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22593:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#37879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22594:
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12

WARNING: line length of 114 exceeds 100 columns
#37880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22595:
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#37881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22596:
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#37882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22597:
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#37883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22598:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#37884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22599:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22600:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#37886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22601:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22602:
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#37888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22603:
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#37889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22604:
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22605:
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#37891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22606:
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22607:
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#37893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22608:
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#37894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22609:
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#37895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22610:
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22611:
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22612:
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#37898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22613:
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22614:
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#37900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22615:
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#37901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22616:
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#37902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22617:
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22618:
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22619:
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22620:
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#37906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22621:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#37907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22622:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#37908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22623:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#37909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22624:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9

WARNING: line length of 114 exceeds 100 columns
#37910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22625:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#37911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22626:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11

WARNING: line length of 114 exceeds 100 columns
#37912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22627:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#37913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22628:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#37914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22629:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#37915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22630:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b

WARNING: line length of 114 exceeds 100 columns
#37916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22631:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c

WARNING: line length of 114 exceeds 100 columns
#37917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22632:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#37918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22633:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#37919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22634:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#37920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22635:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22636:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#37922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22637:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22638:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#37924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22639:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22640:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#37926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22641:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#37927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22642:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#37928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22643:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#37929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22644:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L

WARNING: line length of 121 exceeds 100 columns
#37930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22645:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L

WARNING: line length of 121 exceeds 100 columns
#37931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22646:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#37932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22647:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#37933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22648:
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#37934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22649:
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#37935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22650:
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22651:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#37937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22652:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#37938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22653:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#37939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22654:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#37940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22655:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#37941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22656:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#37942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22657:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9

WARNING: line length of 113 exceeds 100 columns
#37943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22658:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#37944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22659:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#37945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22660:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#37946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22661:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22662:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#37948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22663:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#37949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22664:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#37950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22665:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22666:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#37952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22667:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#37953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22668:
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L

WARNING: line length of 113 exceeds 100 columns
#37954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22669:
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#37955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22670:
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#37956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22671:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#37957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22672:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10

WARNING: line length of 121 exceeds 100 columns
#37958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22673:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#37959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22674:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#37960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22675:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4

WARNING: line length of 113 exceeds 100 columns
#37961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22676:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#37962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22677:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#37963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22678:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#37964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22679:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#37965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22680:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18

WARNING: line length of 114 exceeds 100 columns
#37966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22681:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#37967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22682:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#37968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22683:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22684:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22685:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22686:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22687:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#37973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22688:
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L

WARNING: line length of 113 exceeds 100 columns
#37974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22689:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#37975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22690:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22691:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#37977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22692:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#37978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22693:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#37979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22694:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#37980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22695:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#37981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22696:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22697:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22698:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22699:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22700:
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22701:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#37987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22702:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#37988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22703:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#37989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22704:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#37990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22705:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#37991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22706:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#37992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22707:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#37993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22708:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#37994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22709:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#37995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22710:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#37996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22711:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#37997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22712:
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#37998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22713:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#37999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22714:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3

WARNING: line length of 113 exceeds 100 columns
#38000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22715:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#38001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22716:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#38002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22717:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7

WARNING: line length of 113 exceeds 100 columns
#38003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22718:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#38004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22719:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa

WARNING: line length of 113 exceeds 100 columns
#38005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22720:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc

WARNING: line length of 114 exceeds 100 columns
#38006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22721:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13

WARNING: line length of 114 exceeds 100 columns
#38007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22722:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#38008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22723:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#38009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22724:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#38010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22725:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#38011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22726:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#38012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22727:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#38013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22728:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22729:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22730:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22731:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#38017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22732:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#38018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22733:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#38019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22734:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#38020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22735:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L

WARNING: line length of 121 exceeds 100 columns
#38021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22736:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#38022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22737:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L

WARNING: line length of 121 exceeds 100 columns
#38023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22738:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#38024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22739:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22740:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#38026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22741:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22742:
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22743:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22744:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22745:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22746:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22747:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22748:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22749:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22750:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22751:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22752:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22753:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22754:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22755:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22756:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22757:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22758:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22759:
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22760:
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22761:
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22762:
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22763:
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22764:
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22765:
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22766:
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22767:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22768:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22769:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22770:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22771:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22772:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22773:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22774:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22775:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22776:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22777:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22778:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22779:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22780:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22781:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22782:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22783:
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22784:
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22785:
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22786:
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22787:
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22788:
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22789:
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22790:
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22791:
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22792:
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22793:
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22794:
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22795:
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22796:
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22797:
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22798:
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22799:
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22800:
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22801:
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22802:
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22803:
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22804:
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22805:
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22806:
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22807:
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#38093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22808:
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22809:
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22810:
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22811:
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22812:
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22813:
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22814:
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22815:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#38101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22816:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#38102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22817:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#38103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22818:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#38104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22819:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#38105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22820:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b

WARNING: line length of 114 exceeds 100 columns
#38106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22821:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#38107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22822:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e

WARNING: line length of 114 exceeds 100 columns
#38108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22823:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#38109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22824:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22825:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#38111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22826:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22827:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#38113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22828:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#38114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22829:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#38115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22830:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22831:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22832:
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22833:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#38119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22834:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#38120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22835:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#38121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22836:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#38122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22837:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11

WARNING: line length of 114 exceeds 100 columns
#38123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22838:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12

WARNING: line length of 121 exceeds 100 columns
#38124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22839:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22840:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#38126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22841:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22842:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22843:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#38129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22844:
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L

WARNING: line length of 113 exceeds 100 columns
#38130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22845:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#38131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22846:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#38132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22847:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#38133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22848:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#38134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22849:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13

WARNING: line length of 114 exceeds 100 columns
#38135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22850:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#38136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22851:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17

WARNING: line length of 114 exceeds 100 columns
#38137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22852:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#38138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22853:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#38139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22854:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#38140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22855:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22856:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L

WARNING: line length of 121 exceeds 100 columns
#38142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22857:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#38143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22858:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22859:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L

WARNING: line length of 121 exceeds 100 columns
#38145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22860:
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#38146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22861:
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#38147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22862:
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L

WARNING: line length of 113 exceeds 100 columns
#38148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22863:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#38149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22864:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#38150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22865:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#38151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22866:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#38152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22867:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#38153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22868:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22869:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22870:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22871:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22872:
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L

WARNING: line length of 113 exceeds 100 columns
#38158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22873:
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0

WARNING: line length of 121 exceeds 100 columns
#38159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22874:
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#38160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22875:
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#38161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22876:
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#38162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22877:
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22878:
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#38164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22879:
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#38165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22880:
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#38166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22881:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#38167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22882:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#38168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22883:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#38169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22884:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#38170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22885:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#38171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22886:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5

WARNING: line length of 113 exceeds 100 columns
#38172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22887:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#38173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22888:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7

WARNING: line length of 113 exceeds 100 columns
#38174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22889:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#38175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22890:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#38176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22891:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa

WARNING: line length of 113 exceeds 100 columns
#38177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22892:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#38178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22893:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#38179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22894:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#38180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22895:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe

WARNING: line length of 113 exceeds 100 columns
#38181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22896:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf

WARNING: line length of 114 exceeds 100 columns
#38182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22897:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#38183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22898:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#38184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22899:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#38185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22900:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13

WARNING: line length of 114 exceeds 100 columns
#38186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22901:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#38187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22902:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15

WARNING: line length of 114 exceeds 100 columns
#38188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22903:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#38189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22904:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#38190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22905:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19

WARNING: line length of 121 exceeds 100 columns
#38191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22906:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22907:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22908:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#38194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22909:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22910:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22911:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#38197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22912:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#38198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22913:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#38199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22914:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22915:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#38201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22916:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#38202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22917:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#38203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22918:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22919:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#38205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22920:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#38206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22921:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#38207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22922:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22923:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#38209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22924:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#38210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22925:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#38211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22926:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22927:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#38213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22928:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#38214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22929:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22930:
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L

WARNING: line length of 113 exceeds 100 columns
#38216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22931:
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#38217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22932:
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#38218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22933:
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22934:
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#38220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22935:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#38221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22936:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#38222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22937:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#38223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22938:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3

WARNING: line length of 113 exceeds 100 columns
#38224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22939:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#38225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22940:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#38226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22941:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#38227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22942:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c

WARNING: line length of 114 exceeds 100 columns
#38228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22943:
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#38229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22944:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22945:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22946:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#38232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22947:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22948:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L

WARNING: line length of 121 exceeds 100 columns
#38234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22949:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#38235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22950:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#38236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22951:
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22952:
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22953:
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#38239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22954:
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#38240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22955:
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22956:
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22957:
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#38243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22958:
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#38244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22959:
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22960:
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22961:
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#38247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22962:
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#38248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22963:
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f

WARNING: line length of 121 exceeds 100 columns
#38249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22964:
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22965:
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#38251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22966:
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22967:
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#38253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22968:
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#38254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22969:
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#38255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22970:
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22971:
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#38257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22972:
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22973:
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#38259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22974:
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#38260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22975:
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#38261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22976:
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22977:
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#38263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22978:
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22979:
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#38265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22980:
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#38266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22981:
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19

WARNING: line length of 114 exceeds 100 columns
#38267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22982:
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#38268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22983:
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#38269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22984:
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#38270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22985:
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#38271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22986:
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L

WARNING: line length of 121 exceeds 100 columns
#38272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22987:
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22988:
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22989:
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#38275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22990:
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4

WARNING: line length of 114 exceeds 100 columns
#38276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22991:
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#38277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22992:
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#38278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22993:
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#38279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22994:
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#38280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22995:
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L

WARNING: line length of 121 exceeds 100 columns
#38281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22996:
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L

WARNING: line length of 113 exceeds 100 columns
#38282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22997:
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22998:
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#38284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:22999:
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#38285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23000:
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23001:
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#38287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23002:
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23003:
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#38289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23004:
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23005:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#38291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23006:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#38292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23007:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8

WARNING: line length of 113 exceeds 100 columns
#38293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23008:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc

WARNING: line length of 113 exceeds 100 columns
#38294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23009:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd

WARNING: line length of 114 exceeds 100 columns
#38295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23010:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#38296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23011:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14

WARNING: line length of 114 exceeds 100 columns
#38297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23012:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18

WARNING: line length of 114 exceeds 100 columns
#38298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23013:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c

WARNING: line length of 114 exceeds 100 columns
#38299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23014:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d

WARNING: line length of 121 exceeds 100 columns
#38300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23015:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23016:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23017:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23018:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23019:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#38305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23020:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23021:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23022:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23023:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23024:
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L

WARNING: line length of 113 exceeds 100 columns
#38310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23025:
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0

WARNING: line length of 114 exceeds 100 columns
#38311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23026:
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10

WARNING: line length of 121 exceeds 100 columns
#38312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23027:
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23028:
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23029:
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#38315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23030:
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23031:
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#38317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23032:
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#38318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23033:
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23034:
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23035:
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#38321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23036:
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#38322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23037:
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#38323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23038:
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23039:
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#38325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23040:
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#38326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23041:
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#38327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23042:
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#38328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23043:
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#38329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23044:
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23045:
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#38331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23046:
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23047:
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23048:
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#38334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23049:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#38335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23050:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#38336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23051:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#38337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23052:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23053:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23054:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23055:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23056:
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L

WARNING: line length of 113 exceeds 100 columns
#38342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23057:
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#38343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23058:
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#38344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23059:
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#38345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23060:
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23061:
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#38347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23062:
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#38348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23063:
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23064:
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23065:
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#38351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23066:
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#38352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23067:
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23068:
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23069:
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#38355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23070:
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#38356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23071:
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11

WARNING: line length of 121 exceeds 100 columns
#38357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23072:
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23073:
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23074:
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L

WARNING: line length of 113 exceeds 100 columns
#38360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23075:
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#38361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23076:
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#38362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23077:
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#38363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23078:
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#38364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23079:
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23080:
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L

WARNING: line length of 113 exceeds 100 columns
#38366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23081:
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#38367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23082:
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23083:
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#38369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23084:
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23085:
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#38371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23086:
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23087:
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#38373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23088:
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23089:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#38375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23090:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#38376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23091:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#38377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23092:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#38378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23093:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#38379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23094:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#38380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23095:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#38381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23096:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#38382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23097:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23098:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23099:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#38385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23100:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23101:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23102:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#38388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23103:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#38389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23104:
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23105:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#38391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23106:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#38392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23107:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8

WARNING: line length of 113 exceeds 100 columns
#38393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23108:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc

WARNING: line length of 121 exceeds 100 columns
#38394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23109:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23110:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23111:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23112:
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#38398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23113:
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#38399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23114:
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4

WARNING: line length of 121 exceeds 100 columns
#38400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23115:
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23116:
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L

WARNING: line length of 113 exceeds 100 columns
#38402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23117:
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#38403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23118:
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#38404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23119:
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23120:
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23121:
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#38407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23122:
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#38408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23123:
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23124:
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23125:
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#38411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23126:
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#38412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23127:
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23128:
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#38414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23129:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#38415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23130:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#38416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23131:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#38417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23132:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#38418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23133:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#38419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23134:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#38420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23135:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#38421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23136:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#38422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23137:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#38423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23138:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#38424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23139:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#38425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23140:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#38426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23141:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#38427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23142:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#38428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23143:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#38429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23144:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#38430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23145:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23146:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#38432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23147:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#38433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23148:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#38434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23149:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#38435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23150:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#38436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23151:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#38437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23152:
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23153:
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#38439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23154:
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23155:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#38441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23156:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#38442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23157:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#38443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23158:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#38444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23159:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#38445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23160:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd

WARNING: line length of 113 exceeds 100 columns
#38446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23161:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe

WARNING: line length of 114 exceeds 100 columns
#38447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23162:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#38448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23163:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12

WARNING: line length of 114 exceeds 100 columns
#38449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23164:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#38450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23165:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#38451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23166:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f

WARNING: line length of 121 exceeds 100 columns
#38452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23167:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#38453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23168:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#38454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23169:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L

WARNING: line length of 121 exceeds 100 columns
#38455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23170:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#38456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23171:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23172:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#38458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23173:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L

WARNING: line length of 121 exceeds 100 columns
#38459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23174:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#38460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23175:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#38461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23176:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L

WARNING: line length of 121 exceeds 100 columns
#38462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23177:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#38463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23178:
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23179:
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#38465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23180:
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23181:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#38467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23182:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#38468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23183:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#38469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23184:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10

WARNING: line length of 114 exceeds 100 columns
#38470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23185:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#38471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23186:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#38472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23187:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23188:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23189:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23190:
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#38476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23191:
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#38477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23192:
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L

WARNING: line length of 113 exceeds 100 columns
#38478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23193:
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#38479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23194:
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#38480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23195:
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#38481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23196:
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd

WARNING: line length of 113 exceeds 100 columns
#38482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23197:
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#38483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23198:
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#38484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23199:
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14

WARNING: line length of 121 exceeds 100 columns
#38485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23200:
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23201:
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L

WARNING: line length of 121 exceeds 100 columns
#38487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23202:
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23203:
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#38489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23204:
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#38490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23205:
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23206:
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L

WARNING: line length of 113 exceeds 100 columns
#38492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23207:
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23208:
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#38494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23209:
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23210:
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L

WARNING: line length of 113 exceeds 100 columns
#38496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23211:
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#38497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23212:
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1

WARNING: line length of 121 exceeds 100 columns
#38498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23213:
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23214:
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L

WARNING: line length of 113 exceeds 100 columns
#38500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23215:
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#38501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23216:
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#38502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23217:
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23218:
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23219:
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#38505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23220:
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#38506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23221:
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#38507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23222:
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1

WARNING: line length of 113 exceeds 100 columns
#38508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23223:
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#38509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23224:
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#38510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23225:
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5

WARNING: line length of 114 exceeds 100 columns
#38511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23226:
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#38512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23227:
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11

WARNING: line length of 114 exceeds 100 columns
#38513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23228:
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12

WARNING: line length of 121 exceeds 100 columns
#38514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23229:
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23230:
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23231:
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#38517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23232:
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23233:
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#38519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23234:
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23235:
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#38521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23236:
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L

WARNING: line length of 113 exceeds 100 columns
#38522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23237:
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#38523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23238:
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#38524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23239:
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23240:
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23241:
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#38527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23242:
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23243:
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#38529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23244:
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#38530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23245:
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#38531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23246:
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#38532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23247:
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#38533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23248:
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#38534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23249:
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#38535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23250:
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1

WARNING: line length of 121 exceeds 100 columns
#38536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23251:
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23252:
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL

WARNING: line length of 113 exceeds 100 columns
#38538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23253:
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#38539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23254:
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23255:
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#38541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23256:
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23257:
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#38543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23258:
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#38544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23259:
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#38545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23260:
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23261:
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23262:
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L

WARNING: line length of 113 exceeds 100 columns
#38548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23263:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#38549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23264:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#38550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23265:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#38551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23266:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#38552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23267:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#38553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23268:
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e

WARNING: line length of 114 exceeds 100 columns
#38554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23269:
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#38555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23270:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23271:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23272:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23273:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23274:
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L

WARNING: line length of 121 exceeds 100 columns
#38560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23275:
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23276:
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23277:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#38563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23278:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf

WARNING: line length of 114 exceeds 100 columns
#38564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23279:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#38565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23280:
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12

WARNING: line length of 114 exceeds 100 columns
#38566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23281:
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#38567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23282:
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#38568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23283:
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#38569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23284:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#38570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23285:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23286:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#38572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23287:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#38573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23288:
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L

WARNING: line length of 121 exceeds 100 columns
#38574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23289:
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#38575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23290:
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23291:
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#38577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23292:
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#38578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23293:
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#38579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23294:
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#38580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23295:
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#38581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23296:
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23297:
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23298:
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#38584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23299:
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#38585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23300:
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#38586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23301:
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#38587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23302:
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#38588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23303:
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23304:
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23305:
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#38591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23306:
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#38592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23307:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#38593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23308:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#38594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23309:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#38595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23310:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9

WARNING: line length of 114 exceeds 100 columns
#38596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23311:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#38597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23312:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11

WARNING: line length of 114 exceeds 100 columns
#38598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23313:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#38599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23314:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#38600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23315:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#38601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23316:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b

WARNING: line length of 114 exceeds 100 columns
#38602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23317:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c

WARNING: line length of 114 exceeds 100 columns
#38603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23318:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#38604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23319:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#38605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23320:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#38606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23321:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23322:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23323:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23324:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#38610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23325:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23326:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#38612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23327:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23328:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#38614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23329:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#38615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23330:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L

WARNING: line length of 121 exceeds 100 columns
#38616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23331:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23332:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#38618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23333:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23334:
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23335:
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#38621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23336:
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23337:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#38623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23338:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#38624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23339:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5

WARNING: line length of 113 exceeds 100 columns
#38625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23340:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#38626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23341:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#38627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23342:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#38628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23343:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9

WARNING: line length of 113 exceeds 100 columns
#38629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23344:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#38630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23345:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#38631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23346:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23347:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23348:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#38634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23349:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#38635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23350:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#38636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23351:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23352:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#38638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23353:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#38639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23354:
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L

WARNING: line length of 113 exceeds 100 columns
#38640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23355:
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#38641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23356:
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23357:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#38643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23358:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10

WARNING: line length of 121 exceeds 100 columns
#38644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23359:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23360:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23361:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4

WARNING: line length of 113 exceeds 100 columns
#38647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23362:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#38648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23363:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#38649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23364:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#38650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23365:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#38651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23366:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18

WARNING: line length of 114 exceeds 100 columns
#38652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23367:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#38653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23368:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23369:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23370:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23371:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23372:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23373:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23374:
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L

WARNING: line length of 113 exceeds 100 columns
#38660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23375:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#38661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23376:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23377:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#38663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23378:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#38664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23379:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#38665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23380:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#38666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23381:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#38667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23382:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23383:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23384:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23385:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23386:
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#38672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23387:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#38673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23388:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#38674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23389:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8

WARNING: line length of 113 exceeds 100 columns
#38675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23390:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc

WARNING: line length of 114 exceeds 100 columns
#38676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23391:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#38677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23392:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14

WARNING: line length of 114 exceeds 100 columns
#38678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23393:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18

WARNING: line length of 121 exceeds 100 columns
#38679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23394:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23395:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23396:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23397:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23398:
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#38684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23399:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#38685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23400:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3

WARNING: line length of 113 exceeds 100 columns
#38686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23401:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#38687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23402:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#38688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23403:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7

WARNING: line length of 113 exceeds 100 columns
#38689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23404:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#38690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23405:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa

WARNING: line length of 113 exceeds 100 columns
#38691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23406:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc

WARNING: line length of 114 exceeds 100 columns
#38692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23407:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13

WARNING: line length of 114 exceeds 100 columns
#38693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23408:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#38694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23409:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#38695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23410:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#38696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23411:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#38697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23412:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#38698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23413:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#38699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23414:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23415:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23416:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23417:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L

WARNING: line length of 121 exceeds 100 columns
#38703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23418:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#38704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23419:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#38705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23420:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#38706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23421:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L

WARNING: line length of 121 exceeds 100 columns
#38707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23422:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#38708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23423:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L

WARNING: line length of 121 exceeds 100 columns
#38709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23424:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#38710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23425:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23426:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#38712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23427:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23428:
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23429:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23430:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23431:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23432:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23433:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23434:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23435:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23436:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23437:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23438:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23439:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23440:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23441:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23442:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23443:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23444:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23445:
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23446:
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23447:
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23448:
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23449:
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23450:
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23451:
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23452:
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23453:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23454:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23455:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23456:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23457:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23458:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23459:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23460:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23461:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23462:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23463:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23464:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23465:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23466:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23467:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23468:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23469:
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23470:
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23471:
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23472:
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23473:
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23474:
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23475:
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23476:
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23477:
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23478:
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23479:
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23480:
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23481:
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23482:
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23483:
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23484:
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23485:
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#38771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23486:
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10

WARNING: line length of 121 exceeds 100 columns
#38772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23487:
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23488:
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23489:
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23490:
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23491:
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23492:
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23493:
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#38779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23494:
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#38780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23495:
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23496:
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23497:
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#38783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23498:
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#38784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23499:
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23500:
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#38786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23501:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#38787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23502:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#38788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23503:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#38789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23504:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#38790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23505:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#38791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23506:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b

WARNING: line length of 114 exceeds 100 columns
#38792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23507:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#38793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23508:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e

WARNING: line length of 114 exceeds 100 columns
#38794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23509:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#38795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23510:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23511:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#38797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23512:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23513:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#38799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23514:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#38800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23515:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#38801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23516:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23517:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23518:
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23519:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#38805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23520:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#38806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23521:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc

WARNING: line length of 114 exceeds 100 columns
#38807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23522:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#38808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23523:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11

WARNING: line length of 114 exceeds 100 columns
#38809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23524:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12

WARNING: line length of 121 exceeds 100 columns
#38810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23525:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23526:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#38812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23527:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23528:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23529:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#38815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23530:
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L

WARNING: line length of 113 exceeds 100 columns
#38816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23531:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#38817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23532:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#38818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23533:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#38819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23534:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#38820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23535:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13

WARNING: line length of 114 exceeds 100 columns
#38821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23536:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#38822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23537:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17

WARNING: line length of 114 exceeds 100 columns
#38823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23538:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#38824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23539:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#38825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23540:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#38826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23541:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23542:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L

WARNING: line length of 121 exceeds 100 columns
#38828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23543:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#38829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23544:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23545:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L

WARNING: line length of 121 exceeds 100 columns
#38831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23546:
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#38832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23547:
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#38833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23548:
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L

WARNING: line length of 113 exceeds 100 columns
#38834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23549:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#38835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23550:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#38836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23551:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#38837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23552:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#38838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23553:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#38839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23554:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23555:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23556:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23557:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23558:
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L

WARNING: line length of 113 exceeds 100 columns
#38844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23559:
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0

WARNING: line length of 121 exceeds 100 columns
#38845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23560:
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#38846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23561:
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#38847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23562:
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10

WARNING: line length of 121 exceeds 100 columns
#38848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23563:
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23564:
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#38850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23565:
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#38851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23566:
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#38852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23567:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#38853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23568:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#38854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23569:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2

WARNING: line length of 113 exceeds 100 columns
#38855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23570:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#38856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23571:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#38857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23572:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5

WARNING: line length of 113 exceeds 100 columns
#38858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23573:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#38859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23574:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7

WARNING: line length of 113 exceeds 100 columns
#38860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23575:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#38861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23576:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9

WARNING: line length of 113 exceeds 100 columns
#38862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23577:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa

WARNING: line length of 113 exceeds 100 columns
#38863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23578:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#38864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23579:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#38865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23580:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#38866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23581:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe

WARNING: line length of 113 exceeds 100 columns
#38867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23582:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf

WARNING: line length of 114 exceeds 100 columns
#38868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23583:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#38869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23584:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#38870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23585:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#38871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23586:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13

WARNING: line length of 114 exceeds 100 columns
#38872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23587:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#38873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23588:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15

WARNING: line length of 114 exceeds 100 columns
#38874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23589:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#38875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23590:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#38876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23591:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19

WARNING: line length of 121 exceeds 100 columns
#38877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23592:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23593:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23594:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#38880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23595:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23596:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23597:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#38883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23598:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#38884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23599:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#38885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23600:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23601:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#38887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23602:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#38888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23603:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#38889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23604:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23605:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#38891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23606:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#38892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23607:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#38893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23608:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23609:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#38895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23610:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#38896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23611:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#38897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23612:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23613:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#38899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23614:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#38900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23615:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23616:
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L

WARNING: line length of 113 exceeds 100 columns
#38902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23617:
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#38903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23618:
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#38904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23619:
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23620:
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#38906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23621:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#38907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23622:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#38908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23623:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#38909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23624:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3

WARNING: line length of 113 exceeds 100 columns
#38910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23625:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#38911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23626:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#38912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23627:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#38913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23628:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c

WARNING: line length of 114 exceeds 100 columns
#38914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23629:
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#38915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23630:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23631:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#38917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23632:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#38918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23633:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#38919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23634:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L

WARNING: line length of 121 exceeds 100 columns
#38920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23635:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#38921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23636:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#38922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23637:
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23638:
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23639:
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#38925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23640:
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#38926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23641:
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23642:
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23643:
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#38929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23644:
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#38930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23645:
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23646:
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#38932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23647:
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#38933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23648:
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#38934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23649:
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f

WARNING: line length of 121 exceeds 100 columns
#38935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23650:
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#38936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23651:
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#38937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23652:
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23653:
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#38939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23654:
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#38940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23655:
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#38941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23656:
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23657:
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#38943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23658:
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23659:
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#38945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23660:
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#38946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23661:
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#38947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23662:
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23663:
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#38949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23664:
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23665:
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#38951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23666:
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#38952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23667:
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19

WARNING: line length of 114 exceeds 100 columns
#38953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23668:
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#38954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23669:
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f

WARNING: line length of 121 exceeds 100 columns
#38955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23670:
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#38956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23671:
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#38957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23672:
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L

WARNING: line length of 121 exceeds 100 columns
#38958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23673:
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#38959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23674:
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23675:
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#38961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23676:
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4

WARNING: line length of 114 exceeds 100 columns
#38962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23677:
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#38963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23678:
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#38964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23679:
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#38965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23680:
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#38966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23681:
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L

WARNING: line length of 121 exceeds 100 columns
#38967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23682:
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L

WARNING: line length of 113 exceeds 100 columns
#38968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23683:
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#38969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23684:
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#38970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23685:
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#38971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23686:
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23687:
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#38973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23688:
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#38974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23689:
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#38975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23690:
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L

WARNING: line length of 113 exceeds 100 columns
#38976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23691:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#38977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23692:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#38978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23693:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8

WARNING: line length of 113 exceeds 100 columns
#38979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23694:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc

WARNING: line length of 113 exceeds 100 columns
#38980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23695:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd

WARNING: line length of 114 exceeds 100 columns
#38981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23696:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#38982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23697:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14

WARNING: line length of 114 exceeds 100 columns
#38983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23698:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18

WARNING: line length of 114 exceeds 100 columns
#38984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23699:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c

WARNING: line length of 114 exceeds 100 columns
#38985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23700:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d

WARNING: line length of 121 exceeds 100 columns
#38986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23701:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#38987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23702:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#38988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23703:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#38989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23704:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#38990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23705:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#38991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23706:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#38992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23707:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#38993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23708:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L

WARNING: line length of 121 exceeds 100 columns
#38994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23709:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#38995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23710:
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L

WARNING: line length of 113 exceeds 100 columns
#38996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23711:
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0

WARNING: line length of 114 exceeds 100 columns
#38997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23712:
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10

WARNING: line length of 121 exceeds 100 columns
#38998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23713:
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#38999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23714:
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#39000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23715:
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#39001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23716:
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#39002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23717:
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#39003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23718:
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#39004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23719:
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#39005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23720:
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#39006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23721:
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#39007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23722:
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#39008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23723:
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23724:
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#39010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23725:
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#39011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23726:
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23727:
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#39013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23728:
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23729:
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23730:
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#39016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23731:
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#39017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23732:
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#39018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23733:
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#39019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23734:
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#39020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23735:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#39021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23736:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#39022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23737:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#39023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23738:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#39024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23739:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23740:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23741:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23742:
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L

WARNING: line length of 113 exceeds 100 columns
#39028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23743:
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#39029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23744:
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23745:
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23746:
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#39032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23747:
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#39033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23748:
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#39034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23749:
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L

WARNING: line length of 121 exceeds 100 columns
#39035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23750:
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L

WARNING: line length of 121 exceeds 100 columns
#39036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23751:
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L

WARNING: line length of 121 exceeds 100 columns
#39037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23752:
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L

WARNING: line length of 113 exceeds 100 columns
#39038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23753:
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#39039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23754:
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#39040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23755:
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#39041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23756:
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT                                                          0xf

WARNING: line length of 121 exceeds 100 columns
#39042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23757:
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23758:
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23759:
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#39045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23760:
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK                                                            0x00008000L

WARNING: line length of 113 exceeds 100 columns
#39046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23761:
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#39047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23762:
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#39048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23763:
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#39049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23764:
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6

WARNING: line length of 113 exceeds 100 columns
#39050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23765:
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#39051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23766:
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#39052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23767:
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc

WARNING: line length of 113 exceeds 100 columns
#39053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23768:
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe

WARNING: line length of 114 exceeds 100 columns
#39054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23769:
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#39055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23770:
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12

WARNING: line length of 114 exceeds 100 columns
#39056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23771:
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#39057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23772:
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16

WARNING: line length of 114 exceeds 100 columns
#39058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23773:
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18

WARNING: line length of 114 exceeds 100 columns
#39059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23774:
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a

WARNING: line length of 114 exceeds 100 columns
#39060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23775:
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c

WARNING: line length of 114 exceeds 100 columns
#39061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23776:
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e

WARNING: line length of 121 exceeds 100 columns
#39062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23777:
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23778:
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23779:
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L

WARNING: line length of 121 exceeds 100 columns
#39065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23780:
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23781:
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23782:
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#39068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23783:
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L

WARNING: line length of 121 exceeds 100 columns
#39069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23784:
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#39070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23785:
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L

WARNING: line length of 121 exceeds 100 columns
#39071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23786:
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#39072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23787:
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L

WARNING: line length of 121 exceeds 100 columns
#39073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23788:
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#39074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23789:
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#39075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23790:
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#39076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23791:
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L

WARNING: line length of 121 exceeds 100 columns
#39077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23792:
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#39078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23793:
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#39079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23794:
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2

WARNING: line length of 121 exceeds 100 columns
#39080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23795:
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23796:
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#39082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23797:
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#39083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23798:
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2

WARNING: line length of 113 exceeds 100 columns
#39084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23799:
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#39085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23800:
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6

WARNING: line length of 113 exceeds 100 columns
#39086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23801:
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#39087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23802:
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa

WARNING: line length of 113 exceeds 100 columns
#39088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23803:
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#39089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23804:
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe

WARNING: line length of 121 exceeds 100 columns
#39090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23805:
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23806:
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#39092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23807:
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#39093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23808:
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#39094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23809:
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23810:
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#39096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23811:
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#39097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23812:
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L

WARNING: line length of 113 exceeds 100 columns
#39098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23813:
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#39099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23814:
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#39100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23815:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#39101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23816:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#39102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23817:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#39103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23818:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#39104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23819:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#39105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23820:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#39106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23821:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#39107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23822:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#39108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23823:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#39109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23824:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#39110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23825:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#39111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23826:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#39112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23827:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#39113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23828:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#39114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23829:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#39115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23830:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23831:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#39117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23832:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#39118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23833:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23834:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#39120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23835:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#39121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23836:
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#39122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23837:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#39123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23838:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#39124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23839:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#39125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23840:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#39126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23841:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#39127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23842:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23843:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23844:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23845:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#39131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23846:
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#39132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23847:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#39133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23848:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#39134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23849:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#39135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23850:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#39136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23851:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#39137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23852:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#39138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23853:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#39139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23854:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#39140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23855:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23856:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#39142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23857:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#39143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23858:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#39144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23859:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#39145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23860:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#39146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23861:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#39147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23862:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#39148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23863:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23864:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23865:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#39151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23866:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23867:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23868:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#39154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23869:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#39155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23870:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#39156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23871:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#39157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23872:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#39158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23873:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#39159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23874:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#39160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23875:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#39161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23876:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#39162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23877:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#39163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23878:
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#39164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23879:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23880:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#39166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23881:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#39167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23882:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#39168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23883:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#39169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23884:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#39170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23885:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23886:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#39172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23887:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#39173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23888:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#39174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23889:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#39175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23890:
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#39176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23891:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#39177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23892:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#39178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23893:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#39179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23894:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#39180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23895:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23896:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23897:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#39183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23898:
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#39184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23899:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#39185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23900:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#39186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23901:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#39187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23902:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#39188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23903:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#39189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23904:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#39190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23905:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#39191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23906:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#39192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23907:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#39193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23908:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#39194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23909:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#39195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23910:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#39196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23911:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#39197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23912:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#39198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23913:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#39199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23914:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#39200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23915:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#39201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23916:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23917:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23918:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23919:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23920:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23921:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23922:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23923:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23924:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23925:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#39211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23926:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#39212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23927:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#39213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23928:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23929:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23930:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#39216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23931:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#39217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23932:
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#39218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23933:
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#39219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23934:
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23935:
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#39221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23936:
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#39222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23937:
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#39223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23938:
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#39224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23939:
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#39225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23940:
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23941:
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#39227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23942:
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#39228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23943:
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#39229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23944:
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#39230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23945:
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8

WARNING: line length of 114 exceeds 100 columns
#39231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23946:
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14

WARNING: line length of 121 exceeds 100 columns
#39232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23947:
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23948:
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23949:
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23950:
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23951:
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L

WARNING: line length of 121 exceeds 100 columns
#39237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23952:
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L

WARNING: line length of 113 exceeds 100 columns
#39238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23953:
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#39239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23954:
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#39240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23955:
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#39241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23956:
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#39242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23957:
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc

WARNING: line length of 114 exceeds 100 columns
#39243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23958:
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14

WARNING: line length of 114 exceeds 100 columns
#39244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23959:
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15

WARNING: line length of 114 exceeds 100 columns
#39245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23960:
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#39246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23961:
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#39247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23962:
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23963:
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#39249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23964:
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23965:
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23966:
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23967:
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23968:
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L

WARNING: line length of 121 exceeds 100 columns
#39254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23969:
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23970:
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#39256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23971:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23972:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#39258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23973:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#39259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23974:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#39260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23975:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#39261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23976:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#39262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23977:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#39263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23978:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9

WARNING: line length of 113 exceeds 100 columns
#39264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23979:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#39265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23980:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc

WARNING: line length of 113 exceeds 100 columns
#39266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23981:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd

WARNING: line length of 113 exceeds 100 columns
#39267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23982:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#39268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23983:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#39269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23984:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#39270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23985:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12

WARNING: line length of 114 exceeds 100 columns
#39271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23986:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14

WARNING: line length of 114 exceeds 100 columns
#39272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23987:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15

WARNING: line length of 114 exceeds 100 columns
#39273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23988:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16

WARNING: line length of 114 exceeds 100 columns
#39274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23989:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#39275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23990:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19

WARNING: line length of 114 exceeds 100 columns
#39276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23991:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a

WARNING: line length of 114 exceeds 100 columns
#39277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23992:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b

WARNING: line length of 114 exceeds 100 columns
#39278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23993:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#39279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23994:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d

WARNING: line length of 121 exceeds 100 columns
#39280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23995:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23996:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23997:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23998:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:23999:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24000:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24001:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24002:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#39288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24003:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#39289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24004:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24005:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24006:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#39292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24007:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24008:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#39294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24009:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#39295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24010:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24011:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#39297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24012:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#39298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24013:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24014:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#39300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24015:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#39301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24016:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L

WARNING: line length of 121 exceeds 100 columns
#39302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24017:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#39303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24018:
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L

WARNING: line length of 113 exceeds 100 columns
#39304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24019:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#39305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24020:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2

WARNING: line length of 113 exceeds 100 columns
#39306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24021:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#39307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24022:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#39308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24023:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#39309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24024:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#39310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24025:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#39311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24026:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc

WARNING: line length of 113 exceeds 100 columns
#39312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24027:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd

WARNING: line length of 113 exceeds 100 columns
#39313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24028:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe

WARNING: line length of 113 exceeds 100 columns
#39314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24029:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf

WARNING: line length of 114 exceeds 100 columns
#39315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24030:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12

WARNING: line length of 121 exceeds 100 columns
#39316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24031:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24032:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24033:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24034:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24035:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24036:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24037:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24038:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24039:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24040:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#39326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24041:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L

WARNING: line length of 121 exceeds 100 columns
#39327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24042:
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L

WARNING: line length of 113 exceeds 100 columns
#39328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24043:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24044:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3

WARNING: line length of 114 exceeds 100 columns
#39330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24045:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#39331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24046:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11

WARNING: line length of 114 exceeds 100 columns
#39332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24047:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#39333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24048:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#39334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24049:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#39335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24050:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24051:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24052:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24053:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#39339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24054:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24055:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#39341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24056:
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L

WARNING: line length of 113 exceeds 100 columns
#39342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24057:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24058:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3

WARNING: line length of 114 exceeds 100 columns
#39344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24059:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#39345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24060:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11

WARNING: line length of 114 exceeds 100 columns
#39346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24061:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#39347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24062:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#39348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24063:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#39349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24064:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24065:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24066:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24067:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#39353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24068:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24069:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#39355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24070:
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L

WARNING: line length of 113 exceeds 100 columns
#39356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24071:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24072:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3

WARNING: line length of 114 exceeds 100 columns
#39358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24073:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#39359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24074:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11

WARNING: line length of 114 exceeds 100 columns
#39360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24075:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#39361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24076:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#39362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24077:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#39363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24078:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24079:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24080:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24081:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#39367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24082:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24083:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#39369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24084:
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L

WARNING: line length of 113 exceeds 100 columns
#39370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24085:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24086:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3

WARNING: line length of 114 exceeds 100 columns
#39372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24087:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#39373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24088:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11

WARNING: line length of 114 exceeds 100 columns
#39374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24089:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#39375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24090:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#39376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24091:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#39377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24092:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24093:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24094:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24095:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#39381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24096:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24097:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#39383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24098:
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L

WARNING: line length of 113 exceeds 100 columns
#39384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24099:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24100:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3

WARNING: line length of 114 exceeds 100 columns
#39386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24101:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#39387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24102:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11

WARNING: line length of 114 exceeds 100 columns
#39388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24103:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#39389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24104:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#39390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24105:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#39391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24106:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24107:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24108:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24109:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#39395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24110:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24111:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#39397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24112:
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L

WARNING: line length of 113 exceeds 100 columns
#39398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24113:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24114:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#39400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24115:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#39401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24116:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#39402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24117:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24118:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24119:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24120:
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#39406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24121:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24122:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#39408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24123:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#39409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24124:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#39410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24125:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#39411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24126:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6

WARNING: line length of 113 exceeds 100 columns
#39412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24127:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#39413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24128:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#39414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24129:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24130:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24131:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24132:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24133:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24134:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24135:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24136:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24137:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24138:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#39424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24139:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#39425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24140:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24141:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24142:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#39428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24143:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#39429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24144:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#39430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24145:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24146:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24147:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24148:
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#39434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24149:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24150:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#39436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24151:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#39437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24152:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#39438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24153:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#39439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24154:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6

WARNING: line length of 113 exceeds 100 columns
#39440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24155:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#39441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24156:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#39442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24157:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24158:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24159:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24160:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24161:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24162:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24163:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24164:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24165:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24166:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#39452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24167:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#39453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24168:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24169:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24170:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#39456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24171:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#39457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24172:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#39458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24173:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24174:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24175:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24176:
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#39462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24177:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24178:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#39464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24179:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#39465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24180:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#39466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24181:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#39467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24182:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6

WARNING: line length of 113 exceeds 100 columns
#39468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24183:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#39469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24184:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#39470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24185:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24186:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24187:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24188:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24189:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24190:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24191:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24192:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24193:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24194:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#39480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24195:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#39481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24196:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24197:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24198:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#39484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24199:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#39485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24200:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#39486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24201:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24202:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24203:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24204:
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#39490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24205:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24206:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#39492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24207:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#39493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24208:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#39494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24209:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#39495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24210:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6

WARNING: line length of 113 exceeds 100 columns
#39496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24211:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#39497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24212:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#39498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24213:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24214:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24215:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24216:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24217:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24218:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24219:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24220:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24221:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24222:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#39508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24223:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#39509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24224:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24225:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24226:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#39512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24227:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#39513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24228:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#39514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24229:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24230:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24231:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#39517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24232:
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#39518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24233:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24234:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#39520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24235:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#39521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24236:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#39522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24237:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#39523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24238:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6

WARNING: line length of 113 exceeds 100 columns
#39524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24239:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#39525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24240:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#39526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24241:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24242:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24243:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24244:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24245:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24246:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24247:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24248:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24249:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24250:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#39536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24251:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#39537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24252:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24253:
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#39539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24254:
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#39540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24255:
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#39541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24256:
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd

WARNING: line length of 114 exceeds 100 columns
#39542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24257:
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#39543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24258:
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24259:
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24260:
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24261:
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24262:
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#39548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24263:
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#39549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24264:
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#39550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24265:
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#39551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24266:
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd

WARNING: line length of 114 exceeds 100 columns
#39552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24267:
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#39553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24268:
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24269:
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24270:
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24271:
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24272:
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#39558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24273:
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#39559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24274:
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#39560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24275:
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#39561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24276:
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd

WARNING: line length of 114 exceeds 100 columns
#39562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24277:
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#39563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24278:
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24279:
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24280:
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24281:
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24282:
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#39568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24283:
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#39569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24284:
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#39570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24285:
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#39571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24286:
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd

WARNING: line length of 114 exceeds 100 columns
#39572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24287:
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#39573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24288:
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24289:
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24290:
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24291:
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24292:
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#39578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24293:
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#39579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24294:
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#39580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24295:
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#39581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24296:
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#39582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24297:
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24298:
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#39584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24299:
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#39585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24300:
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#39586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24301:
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#39587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24302:
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#39588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24303:
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c

WARNING: line length of 121 exceeds 100 columns
#39589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24304:
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#39590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24305:
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#39591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24306:
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24307:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#39593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24308:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1

WARNING: line length of 113 exceeds 100 columns
#39594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24309:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2

WARNING: line length of 113 exceeds 100 columns
#39595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24310:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#39596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24311:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#39597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24312:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5

WARNING: line length of 113 exceeds 100 columns
#39598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24313:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6

WARNING: line length of 113 exceeds 100 columns
#39599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24314:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7

WARNING: line length of 113 exceeds 100 columns
#39600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24315:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#39601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24316:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9

WARNING: line length of 113 exceeds 100 columns
#39602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24317:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#39603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24318:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#39604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24319:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc

WARNING: line length of 113 exceeds 100 columns
#39605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24320:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd

WARNING: line length of 113 exceeds 100 columns
#39606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24321:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe

WARNING: line length of 113 exceeds 100 columns
#39607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24322:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf

WARNING: line length of 114 exceeds 100 columns
#39608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24323:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10

WARNING: line length of 114 exceeds 100 columns
#39609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24324:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#39610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24325:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#39611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24326:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13

WARNING: line length of 114 exceeds 100 columns
#39612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24327:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#39613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24328:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15

WARNING: line length of 114 exceeds 100 columns
#39614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24329:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#39615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24330:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17

WARNING: line length of 114 exceeds 100 columns
#39616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24331:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#39617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24332:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19

WARNING: line length of 114 exceeds 100 columns
#39618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24333:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#39619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24334:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b

WARNING: line length of 114 exceeds 100 columns
#39620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24335:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e

WARNING: line length of 114 exceeds 100 columns
#39621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24336:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f

WARNING: line length of 121 exceeds 100 columns
#39622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24337:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24338:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24339:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24340:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24341:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24342:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24343:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24344:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24345:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24346:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L

WARNING: line length of 121 exceeds 100 columns
#39632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24347:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#39633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24348:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#39634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24349:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24350:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#39636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24351:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#39637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24352:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#39638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24353:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24354:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#39640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24355:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#39641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24356:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#39642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24357:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24358:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#39644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24359:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#39645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24360:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L

WARNING: line length of 121 exceeds 100 columns
#39646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24361:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24362:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#39648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24363:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#39649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24364:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L

WARNING: line length of 121 exceeds 100 columns
#39650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24365:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L

WARNING: line length of 121 exceeds 100 columns
#39651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24366:
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#39652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24367:
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24368:
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24369:
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24370:
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24371:
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24372:
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24373:
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24374:
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24375:
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24376:
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24377:
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24378:
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24379:
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24380:
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24381:
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#39667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24382:
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#39668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24383:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#39669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24384:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x1

WARNING: line length of 113 exceeds 100 columns
#39670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24385:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x2

WARNING: line length of 113 exceeds 100 columns
#39671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24386:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x3

WARNING: line length of 113 exceeds 100 columns
#39672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24387:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x4

WARNING: line length of 113 exceeds 100 columns
#39673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24388:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#39674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24389:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x6

WARNING: line length of 121 exceeds 100 columns
#39675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24390:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24391:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24392:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#39678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24393:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24394:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24395:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24396:
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000040L

WARNING: line length of 113 exceeds 100 columns
#39682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24397:
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#39683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24398:
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3

WARNING: line length of 113 exceeds 100 columns
#39684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24399:
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#39685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24400:
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#39686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24401:
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6

WARNING: line length of 113 exceeds 100 columns
#39687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24402:
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7

WARNING: line length of 113 exceeds 100 columns
#39688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24403:
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#39689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24404:
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9

WARNING: line length of 121 exceeds 100 columns
#39690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24405:
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24406:
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L

WARNING: line length of 121 exceeds 100 columns
#39692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24407:
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24408:
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24409:
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24410:
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24411:
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24412:
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L

WARNING: line length of 113 exceeds 100 columns
#39698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24413:
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#39699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24414:
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1

WARNING: line length of 113 exceeds 100 columns
#39700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24415:
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#39701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24416:
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#39702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24417:
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6

WARNING: line length of 113 exceeds 100 columns
#39703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24418:
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7

WARNING: line length of 113 exceeds 100 columns
#39704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24419:
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#39705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24420:
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9

WARNING: line length of 113 exceeds 100 columns
#39706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24421:
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa

WARNING: line length of 121 exceeds 100 columns
#39707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24422:
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24423:
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24424:
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24425:
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#39711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24426:
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#39712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24427:
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#39713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24428:
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24429:
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#39715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24430:
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L

WARNING: line length of 114 exceeds 100 columns
#39716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24431:
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18

WARNING: line length of 114 exceeds 100 columns
#39717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24432:
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19

WARNING: line length of 114 exceeds 100 columns
#39718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24433:
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a

WARNING: line length of 114 exceeds 100 columns
#39719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24434:
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b

WARNING: line length of 114 exceeds 100 columns
#39720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24435:
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c

WARNING: line length of 114 exceeds 100 columns
#39721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24436:
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#39722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24437:
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e

WARNING: line length of 121 exceeds 100 columns
#39723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24438:
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24439:
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#39725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24440:
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L

WARNING: line length of 121 exceeds 100 columns
#39726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24441:
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#39727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24442:
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L

WARNING: line length of 121 exceeds 100 columns
#39728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24443:
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#39729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24444:
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L

WARNING: line length of 113 exceeds 100 columns
#39730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24445:
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#39731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24446:
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#39732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24447:
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24448:
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L

WARNING: line length of 113 exceeds 100 columns
#39734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24449:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#39735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24450:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#39736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24451:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#39737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24452:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc

WARNING: line length of 114 exceeds 100 columns
#39738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24453:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#39739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24454:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24455:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24456:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24457:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#39743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24458:
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#39744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24459:
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24460:
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#39746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24461:
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#39747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24462:
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24463:
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#39749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24464:
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L

WARNING: line length of 113 exceeds 100 columns
#39750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24465:
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24466:
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#39752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24467:
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#39753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24468:
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24469:
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#39755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24470:
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L

WARNING: line length of 113 exceeds 100 columns
#39756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24471:
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24472:
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#39758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24473:
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#39759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24474:
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24475:
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#39761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24476:
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L

WARNING: line length of 113 exceeds 100 columns
#39762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24477:
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24478:
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#39764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24479:
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#39765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24480:
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24481:
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#39767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24482:
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L

WARNING: line length of 113 exceeds 100 columns
#39768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24483:
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24484:
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#39770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24485:
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#39771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24486:
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24487:
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#39773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24488:
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L

WARNING: line length of 113 exceeds 100 columns
#39774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24489:
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#39775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24490:
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#39776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24491:
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#39777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24492:
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#39778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24493:
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#39779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24494:
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L

WARNING: line length of 113 exceeds 100 columns
#39780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24495:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#39781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24496:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#39782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24497:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#39783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24498:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#39784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24499:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#39785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24500:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18

WARNING: line length of 121 exceeds 100 columns
#39786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24501:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24502:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24503:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24504:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24505:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24506:
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24507:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#39793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24508:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#39794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24509:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24510:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#39796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24511:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24512:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24513:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24514:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24515:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24516:
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L

WARNING: line length of 113 exceeds 100 columns
#39802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24517:
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#39803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24518:
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#39804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24519:
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#39805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24520:
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#39806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24521:
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#39807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24522:
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24523:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24524:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc

WARNING: line length of 114 exceeds 100 columns
#39810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24525:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#39811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24526:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#39812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24527:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24528:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24529:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24530:
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24531:
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#39817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24532:
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14

WARNING: line length of 121 exceeds 100 columns
#39818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24533:
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24534:
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L

WARNING: line length of 113 exceeds 100 columns
#39820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24535:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#39821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24536:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#39822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24537:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#39823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24538:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#39824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24539:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#39825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24540:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18

WARNING: line length of 121 exceeds 100 columns
#39826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24541:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24542:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24543:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24544:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24545:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24546:
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24547:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#39833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24548:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#39834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24549:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24550:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#39836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24551:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24552:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24553:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24554:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24555:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24556:
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L

WARNING: line length of 113 exceeds 100 columns
#39842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24557:
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#39843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24558:
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#39844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24559:
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#39845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24560:
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#39846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24561:
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#39847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24562:
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24563:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24564:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc

WARNING: line length of 114 exceeds 100 columns
#39850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24565:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#39851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24566:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#39852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24567:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24568:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24569:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24570:
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24571:
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#39857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24572:
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14

WARNING: line length of 121 exceeds 100 columns
#39858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24573:
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24574:
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L

WARNING: line length of 113 exceeds 100 columns
#39860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24575:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#39861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24576:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#39862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24577:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#39863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24578:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#39864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24579:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#39865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24580:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18

WARNING: line length of 121 exceeds 100 columns
#39866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24581:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24582:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24583:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24584:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24585:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24586:
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24587:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#39873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24588:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#39874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24589:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24590:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#39876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24591:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24592:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24593:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24594:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24595:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24596:
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L

WARNING: line length of 113 exceeds 100 columns
#39882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24597:
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#39883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24598:
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#39884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24599:
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#39885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24600:
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#39886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24601:
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#39887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24602:
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24603:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24604:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc

WARNING: line length of 114 exceeds 100 columns
#39890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24605:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#39891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24606:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#39892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24607:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24608:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24609:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24610:
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24611:
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#39897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24612:
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14

WARNING: line length of 121 exceeds 100 columns
#39898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24613:
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24614:
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L

WARNING: line length of 113 exceeds 100 columns
#39900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24615:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#39901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24616:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#39902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24617:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#39903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24618:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#39904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24619:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#39905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24620:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18

WARNING: line length of 121 exceeds 100 columns
#39906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24621:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24622:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24623:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24624:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24625:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24626:
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24627:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#39913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24628:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#39914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24629:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24630:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#39916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24631:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24632:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24633:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24634:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24635:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24636:
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L

WARNING: line length of 113 exceeds 100 columns
#39922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24637:
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#39923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24638:
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#39924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24639:
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#39925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24640:
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#39926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24641:
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#39927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24642:
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24643:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24644:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc

WARNING: line length of 114 exceeds 100 columns
#39930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24645:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#39931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24646:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#39932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24647:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24648:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24649:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24650:
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24651:
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#39937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24652:
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14

WARNING: line length of 121 exceeds 100 columns
#39938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24653:
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24654:
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L

WARNING: line length of 113 exceeds 100 columns
#39940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24655:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#39941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24656:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1

WARNING: line length of 113 exceeds 100 columns
#39942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24657:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#39943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24658:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#39944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24659:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#39945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24660:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18

WARNING: line length of 121 exceeds 100 columns
#39946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24661:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24662:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#39948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24663:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#39949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24664:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24665:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24666:
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#39952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24667:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#39953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24668:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#39954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24669:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#39955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24670:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#39956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24671:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18

WARNING: line length of 121 exceeds 100 columns
#39957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24672:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#39958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24673:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#39959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24674:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24675:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#39961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24676:
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L

WARNING: line length of 113 exceeds 100 columns
#39962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24677:
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0

WARNING: line length of 114 exceeds 100 columns
#39963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24678:
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#39964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24679:
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c

WARNING: line length of 121 exceeds 100 columns
#39965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24680:
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#39966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24681:
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#39967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24682:
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24683:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#39969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24684:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc

WARNING: line length of 114 exceeds 100 columns
#39970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24685:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#39971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24686:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#39972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24687:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24688:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L

WARNING: line length of 121 exceeds 100 columns
#39974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24689:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24690:
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L

WARNING: line length of 113 exceeds 100 columns
#39976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24691:
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#39977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24692:
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14

WARNING: line length of 121 exceeds 100 columns
#39978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24693:
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#39979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24694:
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L

WARNING: line length of 113 exceeds 100 columns
#39980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24695:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#39981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24696:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#39982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24697:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#39983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24698:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#39984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24699:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#39985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24700:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#39986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24701:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#39987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24702:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#39988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24703:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#39989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24704:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#39990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24705:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#39991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24706:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#39992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24707:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#39993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24708:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#39994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24709:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#39995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24710:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#39996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24711:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#39997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24712:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#39998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24713:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#39999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24714:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#40000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24715:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#40001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24716:
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#40002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24717:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#40003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24718:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#40004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24719:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#40005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24720:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#40006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24721:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#40007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24722:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#40008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24723:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24724:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#40010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24725:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#40011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24726:
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#40012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24727:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#40013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24728:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#40014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24729:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#40015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24730:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#40016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24731:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#40017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24732:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#40018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24733:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#40019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24734:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#40020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24735:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#40021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24736:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#40022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24737:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#40023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24738:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#40024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24739:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#40025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24740:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#40026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24741:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#40027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24742:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#40028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24743:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#40029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24744:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24745:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#40031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24746:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#40032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24747:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#40033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24748:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24749:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#40035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24750:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24751:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#40037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24752:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24753:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#40039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24754:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24755:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#40041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24756:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#40042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24757:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#40043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24758:
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#40044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24759:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#40045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24760:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#40046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24761:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#40047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24762:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#40048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24763:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#40049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24764:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#40050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24765:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#40051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24766:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#40052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24767:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#40053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24768:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24769:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#40055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24770:
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24771:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#40057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24772:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#40058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24773:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#40059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24774:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#40060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24775:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24776:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24777:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#40063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24778:
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#40064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24779:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#40065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24780:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#40066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24781:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#40067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24782:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#40068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24783:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#40069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24784:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#40070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24785:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#40071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24786:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#40072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24787:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#40073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24788:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#40074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24789:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#40075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24790:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#40076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24791:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#40077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24792:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#40078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24793:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#40079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24794:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#40080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24795:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#40081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24796:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24797:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24798:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24799:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#40085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24800:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24801:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#40087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24802:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#40088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24803:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24804:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24805:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24806:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24807:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24808:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24809:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#40095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24810:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24811:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#40097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24812:
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#40098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24813:
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#40099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24814:
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#40100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24815:
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#40101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24816:
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#40102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24817:
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#40103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24818:
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#40104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24819:
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#40105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24820:
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#40106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24821:
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#40107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24822:
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24823:
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#40109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24824:
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#40110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24825:
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#40111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24826:
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#40112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24827:
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12

WARNING: line length of 114 exceeds 100 columns
#40113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24828:
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14

WARNING: line length of 114 exceeds 100 columns
#40114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24829:
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#40115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24830:
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c

WARNING: line length of 114 exceeds 100 columns
#40116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24831:
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#40117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24832:
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#40118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24833:
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#40119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24834:
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24835:
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24836:
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#40122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24837:
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24838:
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24839:
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24840:
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24841:
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L

WARNING: line length of 121 exceeds 100 columns
#40127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24842:
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24843:
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#40129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24844:
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24845:
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#40131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24846:
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24847:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#40133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24848:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#40134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24849:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4

WARNING: line length of 114 exceeds 100 columns
#40135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24850:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#40136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24851:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24852:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24853:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#40139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24854:
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#40140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24855:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#40141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24856:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#40142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24857:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#40143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24858:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa

WARNING: line length of 114 exceeds 100 columns
#40144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24859:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#40145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24860:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#40146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24861:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#40147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24862:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#40148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24863:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#40149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24864:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19

WARNING: line length of 121 exceeds 100 columns
#40150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24865:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#40151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24866:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#40152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24867:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24868:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24869:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24870:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24871:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24872:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24873:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24874:
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L

WARNING: line length of 113 exceeds 100 columns
#40160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24875:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#40161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24876:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#40162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24877:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#40163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24878:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24879:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#40165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24880:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#40166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24881:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24882:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#40168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24883:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#40169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24884:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#40170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24885:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#40171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24886:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#40172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24887:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24888:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24889:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24890:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24891:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#40177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24892:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#40178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24893:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 121 exceeds 100 columns
#40179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24894:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24895:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L

WARNING: line length of 113 exceeds 100 columns
#40181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24896:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#40182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24897:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#40183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24898:
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L

WARNING: line length of 113 exceeds 100 columns
#40184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24899:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#40185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24900:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#40186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24901:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24902:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#40188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24903:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24904:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#40190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24905:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#40191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24906:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#40192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24907:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#40193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24908:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#40194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24909:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#40195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24910:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#40196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24911:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#40197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24912:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#40198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24913:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#40199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24914:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#40200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24915:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#40201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24916:
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#40202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24917:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24918:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24919:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24920:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24921:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24922:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24923:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24924:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24925:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24926:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24927:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24928:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24929:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24930:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24931:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24932:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24933:
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24934:
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#40220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24935:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#40221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24936:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#40222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24937:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24938:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#40224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24939:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24940:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#40226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24941:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#40227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24942:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#40228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24943:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#40229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24944:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#40230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24945:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#40231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24946:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#40232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24947:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#40233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24948:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#40234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24949:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#40235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24950:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#40236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24951:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#40237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24952:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#40238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24953:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#40239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24954:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#40240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24955:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24956:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24957:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24958:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24959:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24960:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24961:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24962:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24963:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24964:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24965:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24966:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24967:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24968:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24969:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24970:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24971:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24972:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24973:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#40259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24974:
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24975:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#40261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24976:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#40262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24977:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10

WARNING: line length of 114 exceeds 100 columns
#40263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24978:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#40264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24979:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24980:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#40266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24981:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#40267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24982:
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24983:
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#40269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24984:
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10

WARNING: line length of 121 exceeds 100 columns
#40270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24985:
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#40271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24986:
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#40272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24987:
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#40273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24988:
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4

WARNING: line length of 114 exceeds 100 columns
#40274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24989:
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#40275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24990:
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24991:
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#40277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24992:
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#40278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24993:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#40279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24994:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#40280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24995:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#40281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24996:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#40282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24997:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#40283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24998:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#40284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:24999:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#40285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25000:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#40286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25001:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#40287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25002:
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L

WARNING: line length of 113 exceeds 100 columns
#40288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25003:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#40289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25004:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#40290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25005:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#40291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25006:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#40292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25007:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#40293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25008:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#40294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25009:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#40295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25010:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#40296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25011:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#40297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25012:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25013:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L

WARNING: line length of 121 exceeds 100 columns
#40299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25014:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L

WARNING: line length of 121 exceeds 100 columns
#40300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25015:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25016:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25017:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25018:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25019:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#40305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25020:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#40306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25021:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#40307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25022:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#40308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25023:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf

WARNING: line length of 121 exceeds 100 columns
#40309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25024:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#40310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25025:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#40311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25026:
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L

WARNING: line length of 113 exceeds 100 columns
#40312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25027:
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#40313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25028:
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4

WARNING: line length of 114 exceeds 100 columns
#40314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25029:
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#40315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25030:
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25031:
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25032:
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#40318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25033:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#40319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25034:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#40320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25035:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#40321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25036:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15

WARNING: line length of 121 exceeds 100 columns
#40322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25037:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L

WARNING: line length of 121 exceeds 100 columns
#40323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25038:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#40324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25039:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#40325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25040:
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L

WARNING: line length of 113 exceeds 100 columns
#40326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25041:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#40327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25042:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#40328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25043:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#40329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25044:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc

WARNING: line length of 114 exceeds 100 columns
#40330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25045:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#40331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25046:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14

WARNING: line length of 114 exceeds 100 columns
#40332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25047:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#40333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25048:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#40334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25049:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#40335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25050:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25051:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25052:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#40338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25053:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#40339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25054:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L

WARNING: line length of 121 exceeds 100 columns
#40340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25055:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25056:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#40342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25057:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L

WARNING: line length of 121 exceeds 100 columns
#40343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25058:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#40344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25059:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#40345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25060:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#40346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25061:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#40347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25062:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#40348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25063:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#40349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25064:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#40350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25065:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#40351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25066:
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L

WARNING: line length of 113 exceeds 100 columns
#40352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25067:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#40353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25068:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25069:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#40355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25070:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9

WARNING: line length of 114 exceeds 100 columns
#40356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25071:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#40357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25072:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#40358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25073:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15

WARNING: line length of 114 exceeds 100 columns
#40359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25074:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16

WARNING: line length of 114 exceeds 100 columns
#40360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25075:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17

WARNING: line length of 114 exceeds 100 columns
#40361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25076:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#40362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25077:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19

WARNING: line length of 114 exceeds 100 columns
#40363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25078:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#40364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25079:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25080:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25081:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25082:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L

WARNING: line length of 121 exceeds 100 columns
#40368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25083:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25084:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25085:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#40371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25086:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25087:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25088:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25089:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#40375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25090:
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#40376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25091:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#40377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25092:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#40378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25093:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#40379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25094:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#40380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25095:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#40381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25096:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#40382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25097:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#40383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25098:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#40384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25099:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#40385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25100:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe

WARNING: line length of 114 exceeds 100 columns
#40386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25101:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#40387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25102:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#40388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25103:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13

WARNING: line length of 114 exceeds 100 columns
#40389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25104:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14

WARNING: line length of 114 exceeds 100 columns
#40390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25105:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#40391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25106:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17

WARNING: line length of 114 exceeds 100 columns
#40392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25107:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18

WARNING: line length of 114 exceeds 100 columns
#40393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25108:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#40394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25109:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#40395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25110:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25111:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25112:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25113:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25114:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25115:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25116:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25117:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25118:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25119:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25120:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25121:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25122:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25123:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25124:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25125:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25126:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25127:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25128:
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#40414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25129:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#40415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25130:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#40416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25131:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#40417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25132:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3

WARNING: line length of 121 exceeds 100 columns
#40418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25133:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25134:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25135:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25136:
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L

WARNING: line length of 113 exceeds 100 columns
#40422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25137:
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#40423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25138:
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25139:
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#40425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25140:
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#40426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25141:
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#40427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25142:
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#40428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25143:
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12

WARNING: line length of 114 exceeds 100 columns
#40429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25144:
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14

WARNING: line length of 114 exceeds 100 columns
#40430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25145:
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#40431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25146:
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c

WARNING: line length of 114 exceeds 100 columns
#40432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25147:
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#40433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25148:
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#40434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25149:
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#40435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25150:
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25151:
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25152:
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#40438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25153:
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25154:
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25155:
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25156:
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25157:
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L

WARNING: line length of 121 exceeds 100 columns
#40443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25158:
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25159:
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#40445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25160:
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25161:
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#40447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25162:
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25163:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#40449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25164:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#40450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25165:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4

WARNING: line length of 114 exceeds 100 columns
#40451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25166:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#40452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25167:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25168:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25169:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#40455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25170:
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#40456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25171:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#40457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25172:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#40458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25173:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#40459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25174:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa

WARNING: line length of 114 exceeds 100 columns
#40460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25175:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#40461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25176:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#40462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25177:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#40463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25178:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#40464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25179:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#40465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25180:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19

WARNING: line length of 121 exceeds 100 columns
#40466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25181:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#40467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25182:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#40468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25183:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25184:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25185:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25186:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25187:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25188:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25189:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25190:
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L

WARNING: line length of 113 exceeds 100 columns
#40476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25191:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#40477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25192:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#40478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25193:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#40479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25194:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25195:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#40481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25196:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#40482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25197:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25198:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#40484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25199:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#40485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25200:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#40486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25201:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#40487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25202:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#40488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25203:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25204:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25205:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25206:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25207:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#40493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25208:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#40494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25209:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 121 exceeds 100 columns
#40495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25210:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25211:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L

WARNING: line length of 113 exceeds 100 columns
#40497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25212:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#40498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25213:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#40499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25214:
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L

WARNING: line length of 113 exceeds 100 columns
#40500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25215:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#40501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25216:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#40502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25217:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25218:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#40504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25219:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25220:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#40506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25221:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#40507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25222:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#40508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25223:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#40509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25224:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#40510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25225:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#40511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25226:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#40512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25227:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#40513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25228:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#40514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25229:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#40515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25230:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#40516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25231:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#40517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25232:
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#40518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25233:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25234:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25235:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25236:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25237:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25238:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25239:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25240:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25241:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25242:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25243:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25244:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25245:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25246:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25247:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25248:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25249:
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25250:
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#40536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25251:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#40537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25252:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#40538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25253:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25254:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#40540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25255:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25256:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#40542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25257:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#40543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25258:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#40544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25259:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#40545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25260:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#40546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25261:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#40547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25262:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#40548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25263:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#40549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25264:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#40550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25265:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#40551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25266:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#40552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25267:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#40553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25268:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#40554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25269:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#40555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25270:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#40556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25271:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25272:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25273:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25274:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25275:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25276:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25277:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25278:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25279:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25280:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25281:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25282:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25283:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25284:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25285:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25286:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25287:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25288:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25289:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#40575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25290:
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25291:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#40577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25292:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#40578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25293:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10

WARNING: line length of 114 exceeds 100 columns
#40579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25294:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#40580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25295:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25296:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#40582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25297:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#40583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25298:
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25299:
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#40585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25300:
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10

WARNING: line length of 121 exceeds 100 columns
#40586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25301:
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#40587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25302:
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#40588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25303:
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#40589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25304:
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4

WARNING: line length of 114 exceeds 100 columns
#40590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25305:
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#40591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25306:
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25307:
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#40593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25308:
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#40594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25309:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#40595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25310:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#40596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25311:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#40597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25312:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#40598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25313:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#40599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25314:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#40600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25315:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#40601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25316:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#40602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25317:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#40603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25318:
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L

WARNING: line length of 113 exceeds 100 columns
#40604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25319:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#40605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25320:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#40606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25321:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#40607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25322:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#40608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25323:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#40609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25324:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#40610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25325:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#40611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25326:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#40612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25327:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#40613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25328:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25329:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L

WARNING: line length of 121 exceeds 100 columns
#40615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25330:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L

WARNING: line length of 121 exceeds 100 columns
#40616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25331:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25332:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25333:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25334:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25335:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#40621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25336:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#40622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25337:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#40623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25338:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#40624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25339:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf

WARNING: line length of 121 exceeds 100 columns
#40625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25340:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#40626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25341:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#40627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25342:
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L

WARNING: line length of 113 exceeds 100 columns
#40628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25343:
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#40629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25344:
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4

WARNING: line length of 114 exceeds 100 columns
#40630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25345:
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#40631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25346:
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25347:
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25348:
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#40634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25349:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#40635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25350:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#40636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25351:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#40637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25352:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15

WARNING: line length of 121 exceeds 100 columns
#40638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25353:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L

WARNING: line length of 121 exceeds 100 columns
#40639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25354:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#40640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25355:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#40641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25356:
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L

WARNING: line length of 113 exceeds 100 columns
#40642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25357:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#40643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25358:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#40644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25359:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#40645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25360:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc

WARNING: line length of 114 exceeds 100 columns
#40646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25361:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#40647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25362:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14

WARNING: line length of 114 exceeds 100 columns
#40648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25363:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#40649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25364:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#40650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25365:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#40651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25366:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25367:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25368:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#40654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25369:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#40655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25370:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L

WARNING: line length of 121 exceeds 100 columns
#40656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25371:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25372:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#40658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25373:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L

WARNING: line length of 121 exceeds 100 columns
#40659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25374:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#40660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25375:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#40661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25376:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#40662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25377:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#40663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25378:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#40664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25379:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#40665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25380:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#40666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25381:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#40667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25382:
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L

WARNING: line length of 113 exceeds 100 columns
#40668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25383:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#40669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25384:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25385:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#40671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25386:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9

WARNING: line length of 114 exceeds 100 columns
#40672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25387:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#40673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25388:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#40674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25389:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15

WARNING: line length of 114 exceeds 100 columns
#40675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25390:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16

WARNING: line length of 114 exceeds 100 columns
#40676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25391:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17

WARNING: line length of 114 exceeds 100 columns
#40677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25392:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#40678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25393:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19

WARNING: line length of 114 exceeds 100 columns
#40679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25394:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#40680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25395:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25396:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25397:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25398:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L

WARNING: line length of 121 exceeds 100 columns
#40684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25399:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25400:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25401:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#40687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25402:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25403:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25404:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25405:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#40691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25406:
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#40692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25407:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#40693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25408:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#40694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25409:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#40695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25410:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#40696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25411:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#40697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25412:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#40698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25413:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#40699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25414:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#40700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25415:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#40701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25416:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe

WARNING: line length of 114 exceeds 100 columns
#40702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25417:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#40703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25418:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#40704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25419:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13

WARNING: line length of 114 exceeds 100 columns
#40705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25420:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14

WARNING: line length of 114 exceeds 100 columns
#40706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25421:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#40707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25422:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17

WARNING: line length of 114 exceeds 100 columns
#40708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25423:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18

WARNING: line length of 114 exceeds 100 columns
#40709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25424:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#40710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25425:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#40711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25426:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25427:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25428:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25429:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25430:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25431:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25432:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25433:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25434:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25435:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25436:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25437:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25438:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25439:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25440:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25441:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25442:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25443:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25444:
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#40730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25445:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#40731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25446:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#40732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25447:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#40733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25448:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3

WARNING: line length of 121 exceeds 100 columns
#40734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25449:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25450:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25451:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25452:
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L

WARNING: line length of 113 exceeds 100 columns
#40738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25453:
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#40739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25454:
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25455:
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#40741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25456:
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#40742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25457:
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#40743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25458:
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#40744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25459:
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12

WARNING: line length of 114 exceeds 100 columns
#40745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25460:
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14

WARNING: line length of 114 exceeds 100 columns
#40746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25461:
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#40747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25462:
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c

WARNING: line length of 114 exceeds 100 columns
#40748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25463:
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#40749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25464:
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#40750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25465:
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#40751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25466:
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25467:
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25468:
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#40754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25469:
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25470:
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25471:
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25472:
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25473:
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L

WARNING: line length of 121 exceeds 100 columns
#40759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25474:
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25475:
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#40761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25476:
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25477:
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#40763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25478:
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25479:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#40765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25480:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#40766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25481:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4

WARNING: line length of 114 exceeds 100 columns
#40767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25482:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#40768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25483:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25484:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25485:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#40771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25486:
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#40772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25487:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#40773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25488:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#40774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25489:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#40775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25490:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa

WARNING: line length of 114 exceeds 100 columns
#40776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25491:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#40777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25492:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#40778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25493:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#40779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25494:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#40780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25495:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#40781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25496:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19

WARNING: line length of 121 exceeds 100 columns
#40782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25497:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#40783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25498:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#40784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25499:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25500:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25501:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25502:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25503:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25504:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25505:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#40791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25506:
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L

WARNING: line length of 113 exceeds 100 columns
#40792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25507:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#40793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25508:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#40794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25509:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#40795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25510:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25511:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#40797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25512:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#40798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25513:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25514:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#40800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25515:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#40801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25516:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#40802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25517:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#40803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25518:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#40804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25519:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25520:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25521:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#40807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25522:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25523:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#40809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25524:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#40810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25525:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 121 exceeds 100 columns
#40811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25526:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25527:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L

WARNING: line length of 113 exceeds 100 columns
#40813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25528:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#40814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25529:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#40815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25530:
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L

WARNING: line length of 113 exceeds 100 columns
#40816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25531:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#40817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25532:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#40818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25533:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25534:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#40820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25535:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25536:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#40822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25537:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#40823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25538:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#40824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25539:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#40825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25540:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#40826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25541:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#40827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25542:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#40828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25543:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#40829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25544:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#40830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25545:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#40831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25546:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#40832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25547:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#40833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25548:
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#40834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25549:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25550:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25551:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25552:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25553:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25554:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25555:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25556:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25557:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25558:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25559:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25560:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25561:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25562:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25563:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25564:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25565:
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25566:
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#40852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25567:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#40853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25568:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#40854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25569:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25570:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#40856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25571:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#40857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25572:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#40858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25573:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#40859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25574:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#40860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25575:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#40861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25576:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#40862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25577:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#40863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25578:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#40864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25579:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#40865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25580:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#40866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25581:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#40867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25582:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#40868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25583:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#40869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25584:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#40870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25585:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#40871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25586:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#40872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25587:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25588:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#40874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25589:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25590:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#40876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25591:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25592:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#40878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25593:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#40879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25594:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#40880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25595:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#40881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25596:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#40882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25597:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25598:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25599:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25600:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25601:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#40887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25602:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#40888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25603:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#40889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25604:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#40890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25605:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#40891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25606:
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25607:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#40893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25608:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#40894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25609:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10

WARNING: line length of 114 exceeds 100 columns
#40895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25610:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#40896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25611:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25612:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#40898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25613:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#40899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25614:
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#40900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25615:
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#40901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25616:
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10

WARNING: line length of 121 exceeds 100 columns
#40902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25617:
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#40903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25618:
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#40904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25619:
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#40905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25620:
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4

WARNING: line length of 114 exceeds 100 columns
#40906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25621:
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#40907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25622:
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25623:
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#40909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25624:
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#40910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25625:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#40911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25626:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#40912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25627:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#40913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25628:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#40914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25629:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#40915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25630:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#40916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25631:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#40917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25632:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#40918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25633:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#40919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25634:
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L

WARNING: line length of 113 exceeds 100 columns
#40920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25635:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#40921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25636:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#40922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25637:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#40923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25638:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#40924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25639:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#40925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25640:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#40926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25641:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#40927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25642:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#40928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25643:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#40929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25644:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25645:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L

WARNING: line length of 121 exceeds 100 columns
#40931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25646:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L

WARNING: line length of 121 exceeds 100 columns
#40932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25647:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#40933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25648:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#40934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25649:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#40935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25650:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#40936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25651:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#40937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25652:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#40938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25653:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#40939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25654:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#40940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25655:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf

WARNING: line length of 121 exceeds 100 columns
#40941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25656:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#40942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25657:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#40943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25658:
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L

WARNING: line length of 113 exceeds 100 columns
#40944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25659:
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#40945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25660:
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4

WARNING: line length of 114 exceeds 100 columns
#40946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25661:
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#40947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25662:
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25663:
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L

WARNING: line length of 121 exceeds 100 columns
#40949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25664:
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#40950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25665:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#40951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25666:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#40952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25667:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#40953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25668:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15

WARNING: line length of 121 exceeds 100 columns
#40954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25669:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L

WARNING: line length of 121 exceeds 100 columns
#40955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25670:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#40956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25671:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#40957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25672:
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L

WARNING: line length of 113 exceeds 100 columns
#40958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25673:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#40959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25674:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#40960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25675:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#40961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25676:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc

WARNING: line length of 114 exceeds 100 columns
#40962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25677:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#40963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25678:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14

WARNING: line length of 114 exceeds 100 columns
#40964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25679:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#40965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25680:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#40966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25681:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#40967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25682:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25683:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25684:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#40970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25685:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#40971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25686:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L

WARNING: line length of 121 exceeds 100 columns
#40972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25687:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#40973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25688:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#40974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25689:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L

WARNING: line length of 121 exceeds 100 columns
#40975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25690:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#40976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25691:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#40977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25692:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#40978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25693:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#40979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25694:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#40980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25695:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#40981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25696:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#40982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25697:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#40983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25698:
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L

WARNING: line length of 113 exceeds 100 columns
#40984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25699:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#40985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25700:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4

WARNING: line length of 113 exceeds 100 columns
#40986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25701:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#40987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25702:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9

WARNING: line length of 114 exceeds 100 columns
#40988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25703:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#40989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25704:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#40990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25705:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15

WARNING: line length of 114 exceeds 100 columns
#40991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25706:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16

WARNING: line length of 114 exceeds 100 columns
#40992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25707:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17

WARNING: line length of 114 exceeds 100 columns
#40993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25708:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#40994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25709:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19

WARNING: line length of 114 exceeds 100 columns
#40995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25710:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#40996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25711:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#40997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25712:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#40998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25713:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#40999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25714:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L

WARNING: line length of 121 exceeds 100 columns
#41000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25715:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25716:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25717:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#41003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25718:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25719:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25720:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25721:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#41007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25722:
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#41008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25723:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#41009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25724:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#41010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25725:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#41011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25726:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#41012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25727:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#41013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25728:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#41014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25729:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#41015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25730:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#41016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25731:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#41017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25732:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe

WARNING: line length of 114 exceeds 100 columns
#41018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25733:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#41019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25734:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#41020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25735:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13

WARNING: line length of 114 exceeds 100 columns
#41021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25736:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14

WARNING: line length of 114 exceeds 100 columns
#41022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25737:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#41023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25738:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17

WARNING: line length of 114 exceeds 100 columns
#41024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25739:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18

WARNING: line length of 114 exceeds 100 columns
#41025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25740:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#41026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25741:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#41027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25742:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25743:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25744:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25745:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25746:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25747:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25748:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25749:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25750:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25751:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25752:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25753:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25754:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25755:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25756:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25757:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25758:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#41044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25759:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25760:
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#41046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25761:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#41047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25762:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#41048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25763:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#41049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25764:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3

WARNING: line length of 121 exceeds 100 columns
#41050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25765:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25766:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25767:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25768:
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L

WARNING: line length of 113 exceeds 100 columns
#41054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25769:
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#41055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25770:
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25771:
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#41057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25772:
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#41058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25773:
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#41059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25774:
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#41060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25775:
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12

WARNING: line length of 114 exceeds 100 columns
#41061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25776:
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14

WARNING: line length of 114 exceeds 100 columns
#41062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25777:
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#41063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25778:
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c

WARNING: line length of 114 exceeds 100 columns
#41064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25779:
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#41065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25780:
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#41066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25781:
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#41067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25782:
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25783:
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25784:
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#41070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25785:
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25786:
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25787:
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25788:
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25789:
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L

WARNING: line length of 121 exceeds 100 columns
#41075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25790:
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25791:
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#41077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25792:
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25793:
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#41079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25794:
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#41080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25795:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#41081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25796:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#41082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25797:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4

WARNING: line length of 114 exceeds 100 columns
#41083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25798:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#41084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25799:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25800:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25801:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#41087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25802:
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#41088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25803:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#41089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25804:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#41090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25805:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#41091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25806:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa

WARNING: line length of 114 exceeds 100 columns
#41092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25807:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#41093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25808:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#41094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25809:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#41095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25810:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#41096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25811:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#41097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25812:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19

WARNING: line length of 121 exceeds 100 columns
#41098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25813:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#41099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25814:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#41100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25815:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25816:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25817:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25818:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25819:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25820:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25821:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25822:
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L

WARNING: line length of 113 exceeds 100 columns
#41108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25823:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#41109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25824:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#41110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25825:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#41111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25826:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25827:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#41113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25828:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#41114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25829:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#41115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25830:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#41116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25831:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#41117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25832:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#41118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25833:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#41119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25834:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#41120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25835:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25836:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25837:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25838:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25839:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#41125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25840:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#41126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25841:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 121 exceeds 100 columns
#41127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25842:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25843:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L

WARNING: line length of 113 exceeds 100 columns
#41129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25844:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#41130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25845:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#41131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25846:
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L

WARNING: line length of 113 exceeds 100 columns
#41132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25847:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#41133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25848:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#41134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25849:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25850:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#41136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25851:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#41137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25852:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#41138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25853:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#41139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25854:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#41140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25855:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#41141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25856:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#41142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25857:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#41143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25858:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#41144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25859:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#41145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25860:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#41146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25861:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#41147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25862:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#41148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25863:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#41149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25864:
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#41150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25865:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25866:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25867:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25868:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25869:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25870:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25871:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25872:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25873:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25874:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25875:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25876:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25877:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25878:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25879:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25880:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25881:
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#41167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25882:
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#41168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25883:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#41169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25884:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#41170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25885:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25886:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#41172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25887:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#41173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25888:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#41174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25889:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#41175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25890:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#41176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25891:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#41177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25892:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#41178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25893:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#41179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25894:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#41180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25895:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#41181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25896:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#41182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25897:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#41183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25898:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#41184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25899:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#41185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25900:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#41186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25901:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#41187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25902:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#41188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25903:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25904:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25905:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25906:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25907:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25908:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25909:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25910:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25911:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25912:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25913:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25914:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25915:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25916:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25917:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25918:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25919:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#41205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25920:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25921:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#41207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25922:
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#41208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25923:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#41209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25924:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#41210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25925:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10

WARNING: line length of 114 exceeds 100 columns
#41211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25926:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#41212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25927:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25928:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25929:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#41215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25930:
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#41216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25931:
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#41217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25932:
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10

WARNING: line length of 121 exceeds 100 columns
#41218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25933:
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25934:
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#41220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25935:
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#41221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25936:
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4

WARNING: line length of 114 exceeds 100 columns
#41222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25937:
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#41223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25938:
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25939:
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#41225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25940:
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#41226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25941:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#41227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25942:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#41228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25943:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#41229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25944:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#41230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25945:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#41231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25946:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#41232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25947:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#41233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25948:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#41234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25949:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#41235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25950:
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L

WARNING: line length of 113 exceeds 100 columns
#41236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25951:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#41237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25952:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#41238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25953:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#41239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25954:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#41240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25955:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#41241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25956:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#41242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25957:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#41243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25958:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#41244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25959:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#41245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25960:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25961:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L

WARNING: line length of 121 exceeds 100 columns
#41247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25962:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L

WARNING: line length of 121 exceeds 100 columns
#41248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25963:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25964:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25965:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25966:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25967:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#41253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25968:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#41254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25969:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#41255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25970:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#41256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25971:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf

WARNING: line length of 121 exceeds 100 columns
#41257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25972:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25973:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#41259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25974:
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L

WARNING: line length of 113 exceeds 100 columns
#41260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25975:
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#41261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25976:
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4

WARNING: line length of 114 exceeds 100 columns
#41262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25977:
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#41263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25978:
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25979:
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25980:
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#41266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25981:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#41267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25982:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#41268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25983:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#41269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25984:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15

WARNING: line length of 121 exceeds 100 columns
#41270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25985:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L

WARNING: line length of 121 exceeds 100 columns
#41271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25986:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#41272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25987:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#41273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25988:
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L

WARNING: line length of 113 exceeds 100 columns
#41274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25989:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#41275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25990:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#41276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25991:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#41277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25992:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc

WARNING: line length of 114 exceeds 100 columns
#41278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25993:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#41279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25994:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14

WARNING: line length of 114 exceeds 100 columns
#41280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25995:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#41281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25996:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#41282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25997:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#41283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25998:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:25999:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26000:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#41286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26001:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#41287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26002:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L

WARNING: line length of 121 exceeds 100 columns
#41288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26003:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26004:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#41290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26005:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L

WARNING: line length of 121 exceeds 100 columns
#41291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26006:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#41292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26007:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#41293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26008:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#41294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26009:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#41295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26010:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#41296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26011:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#41297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26012:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#41298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26013:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#41299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26014:
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L

WARNING: line length of 113 exceeds 100 columns
#41300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26015:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#41301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26016:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26017:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#41303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26018:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9

WARNING: line length of 114 exceeds 100 columns
#41304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26019:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#41305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26020:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#41306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26021:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15

WARNING: line length of 114 exceeds 100 columns
#41307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26022:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16

WARNING: line length of 114 exceeds 100 columns
#41308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26023:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17

WARNING: line length of 114 exceeds 100 columns
#41309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26024:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#41310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26025:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19

WARNING: line length of 114 exceeds 100 columns
#41311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26026:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#41312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26027:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26028:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26029:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26030:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L

WARNING: line length of 121 exceeds 100 columns
#41316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26031:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26032:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26033:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#41319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26034:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26035:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26036:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26037:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#41323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26038:
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#41324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26039:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#41325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26040:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#41326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26041:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#41327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26042:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#41328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26043:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#41329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26044:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#41330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26045:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#41331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26046:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#41332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26047:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#41333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26048:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe

WARNING: line length of 114 exceeds 100 columns
#41334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26049:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#41335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26050:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#41336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26051:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13

WARNING: line length of 114 exceeds 100 columns
#41337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26052:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14

WARNING: line length of 114 exceeds 100 columns
#41338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26053:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#41339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26054:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17

WARNING: line length of 114 exceeds 100 columns
#41340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26055:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18

WARNING: line length of 114 exceeds 100 columns
#41341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26056:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#41342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26057:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#41343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26058:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26059:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26060:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26061:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26062:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26063:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26064:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26065:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26066:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26067:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26068:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26069:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26070:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26071:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26072:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26073:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26074:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#41360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26075:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26076:
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#41362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26077:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#41363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26078:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#41364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26079:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#41365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26080:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3

WARNING: line length of 121 exceeds 100 columns
#41366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26081:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26082:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26083:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26084:
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L

WARNING: line length of 113 exceeds 100 columns
#41370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26085:
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#41371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26086:
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26087:
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#41373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26088:
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#41374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26089:
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#41375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26090:
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#41376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26091:
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12

WARNING: line length of 114 exceeds 100 columns
#41377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26092:
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14

WARNING: line length of 114 exceeds 100 columns
#41378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26093:
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#41379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26094:
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c

WARNING: line length of 114 exceeds 100 columns
#41380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26095:
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#41381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26096:
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#41382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26097:
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f

WARNING: line length of 121 exceeds 100 columns
#41383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26098:
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26099:
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26100:
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#41386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26101:
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26102:
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26103:
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26104:
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26105:
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L

WARNING: line length of 121 exceeds 100 columns
#41391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26106:
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26107:
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#41393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26108:
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26109:
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#41395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26110:
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L

WARNING: line length of 113 exceeds 100 columns
#41396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26111:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#41397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26112:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#41398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26113:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4

WARNING: line length of 114 exceeds 100 columns
#41399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26114:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#41400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26115:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26116:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26117:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#41403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26118:
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#41404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26119:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#41405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26120:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#41406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26121:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#41407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26122:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa

WARNING: line length of 114 exceeds 100 columns
#41408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26123:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#41409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26124:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#41410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26125:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11

WARNING: line length of 114 exceeds 100 columns
#41411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26126:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#41412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26127:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#41413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26128:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19

WARNING: line length of 121 exceeds 100 columns
#41414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26129:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#41415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26130:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#41416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26131:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26132:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26133:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26134:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26135:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26136:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26137:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26138:
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L

WARNING: line length of 113 exceeds 100 columns
#41424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26139:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#41425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26140:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#41426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26141:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#41427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26142:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26143:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#41429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26144:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#41430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26145:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#41431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26146:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#41432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26147:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#41433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26148:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#41434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26149:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#41435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26150:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#41436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26151:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26152:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26153:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26154:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26155:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#41441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26156:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#41442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26157:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa

WARNING: line length of 121 exceeds 100 columns
#41443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26158:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26159:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L

WARNING: line length of 113 exceeds 100 columns
#41445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26160:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe

WARNING: line length of 121 exceeds 100 columns
#41446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26161:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#41447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26162:
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L

WARNING: line length of 113 exceeds 100 columns
#41448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26163:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#41449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26164:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#41450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26165:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26166:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#41452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26167:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#41453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26168:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#41454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26169:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#41455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26170:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#41456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26171:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#41457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26172:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#41458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26173:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#41459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26174:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#41460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26175:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#41461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26176:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#41462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26177:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#41463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26178:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#41464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26179:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#41465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26180:
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#41466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26181:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26182:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26183:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26184:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26185:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26186:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26187:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26188:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26189:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26190:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26191:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26192:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26193:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26194:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26195:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26196:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26197:
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#41483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26198:
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#41484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26199:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#41485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26200:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1

WARNING: line length of 113 exceeds 100 columns
#41486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26201:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26202:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#41488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26203:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#41489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26204:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9

WARNING: line length of 113 exceeds 100 columns
#41490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26205:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#41491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26206:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb

WARNING: line length of 113 exceeds 100 columns
#41492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26207:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc

WARNING: line length of 113 exceeds 100 columns
#41493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26208:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#41494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26209:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11

WARNING: line length of 114 exceeds 100 columns
#41495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26210:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12

WARNING: line length of 114 exceeds 100 columns
#41496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26211:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13

WARNING: line length of 114 exceeds 100 columns
#41497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26212:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#41498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26213:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16

WARNING: line length of 114 exceeds 100 columns
#41499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26214:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17

WARNING: line length of 114 exceeds 100 columns
#41500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26215:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#41501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26216:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#41502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26217:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e

WARNING: line length of 114 exceeds 100 columns
#41503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26218:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#41504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26219:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26220:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26221:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26222:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26223:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26224:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26225:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26226:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26227:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26228:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26229:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26230:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26231:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26232:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26233:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26234:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26235:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#41521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26236:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26237:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L

WARNING: line length of 121 exceeds 100 columns
#41523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26238:
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#41524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26239:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#41525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26240:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#41526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26241:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10

WARNING: line length of 114 exceeds 100 columns
#41527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26242:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#41528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26243:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26244:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26245:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#41531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26246:
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#41532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26247:
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8

WARNING: line length of 114 exceeds 100 columns
#41533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26248:
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10

WARNING: line length of 121 exceeds 100 columns
#41534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26249:
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26250:
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#41536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26251:
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#41537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26252:
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4

WARNING: line length of 114 exceeds 100 columns
#41538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26253:
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#41539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26254:
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26255:
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#41541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26256:
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#41542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26257:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#41543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26258:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#41544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26259:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#41545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26260:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#41546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26261:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#41547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26262:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#41548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26263:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L

WARNING: line length of 121 exceeds 100 columns
#41549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26264:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#41550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26265:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#41551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26266:
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L

WARNING: line length of 113 exceeds 100 columns
#41552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26267:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#41553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26268:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#41554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26269:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#41555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26270:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#41556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26271:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#41557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26272:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#41558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26273:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#41559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26274:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#41560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26275:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#41561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26276:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26277:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L

WARNING: line length of 121 exceeds 100 columns
#41563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26278:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L

WARNING: line length of 121 exceeds 100 columns
#41564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26279:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26280:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26281:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26282:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26283:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#41569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26284:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#41570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26285:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#41571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26286:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#41572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26287:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf

WARNING: line length of 121 exceeds 100 columns
#41573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26288:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26289:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#41575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26290:
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L

WARNING: line length of 113 exceeds 100 columns
#41576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26291:
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#41577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26292:
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4

WARNING: line length of 114 exceeds 100 columns
#41578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26293:
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#41579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26294:
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26295:
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26296:
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L

WARNING: line length of 113 exceeds 100 columns
#41582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26297:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#41583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26298:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#41584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26299:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#41585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26300:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15

WARNING: line length of 121 exceeds 100 columns
#41586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26301:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L

WARNING: line length of 121 exceeds 100 columns
#41587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26302:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#41588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26303:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#41589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26304:
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L

WARNING: line length of 113 exceeds 100 columns
#41590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26305:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#41591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26306:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#41592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26307:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#41593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26308:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc

WARNING: line length of 114 exceeds 100 columns
#41594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26309:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#41595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26310:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14

WARNING: line length of 114 exceeds 100 columns
#41596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26311:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#41597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26312:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#41598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26313:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#41599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26314:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26315:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26316:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#41602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26317:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#41603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26318:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L

WARNING: line length of 121 exceeds 100 columns
#41604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26319:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26320:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#41606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26321:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L

WARNING: line length of 121 exceeds 100 columns
#41607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26322:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#41608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26323:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#41609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26324:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#41610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26325:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10

WARNING: line length of 114 exceeds 100 columns
#41611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26326:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14

WARNING: line length of 121 exceeds 100 columns
#41612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26327:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#41613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26328:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#41614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26329:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L

WARNING: line length of 121 exceeds 100 columns
#41615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26330:
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L

WARNING: line length of 113 exceeds 100 columns
#41616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26331:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0

WARNING: line length of 113 exceeds 100 columns
#41617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26332:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4

WARNING: line length of 113 exceeds 100 columns
#41618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26333:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8

WARNING: line length of 113 exceeds 100 columns
#41619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26334:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9

WARNING: line length of 114 exceeds 100 columns
#41620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26335:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#41621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26336:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14

WARNING: line length of 114 exceeds 100 columns
#41622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26337:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15

WARNING: line length of 114 exceeds 100 columns
#41623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26338:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16

WARNING: line length of 114 exceeds 100 columns
#41624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26339:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17

WARNING: line length of 114 exceeds 100 columns
#41625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26340:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18

WARNING: line length of 114 exceeds 100 columns
#41626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26341:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19

WARNING: line length of 114 exceeds 100 columns
#41627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26342:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c

WARNING: line length of 121 exceeds 100 columns
#41628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26343:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26344:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26345:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26346:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L

WARNING: line length of 121 exceeds 100 columns
#41632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26347:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26348:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26349:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#41635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26350:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26351:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26352:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26353:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#41639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26354:
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#41640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26355:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#41641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26356:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#41642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26357:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#41643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26358:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#41644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26359:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#41645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26360:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#41646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26361:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa

WARNING: line length of 113 exceeds 100 columns
#41647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26362:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#41648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26363:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc

WARNING: line length of 113 exceeds 100 columns
#41649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26364:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe

WARNING: line length of 114 exceeds 100 columns
#41650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26365:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#41651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26366:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#41652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26367:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13

WARNING: line length of 114 exceeds 100 columns
#41653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26368:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14

WARNING: line length of 114 exceeds 100 columns
#41654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26369:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#41655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26370:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17

WARNING: line length of 114 exceeds 100 columns
#41656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26371:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18

WARNING: line length of 114 exceeds 100 columns
#41657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26372:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#41658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26373:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e

WARNING: line length of 121 exceeds 100 columns
#41659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26374:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26375:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26376:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L

WARNING: line length of 121 exceeds 100 columns
#41662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26377:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26378:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26379:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26380:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26381:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26382:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26383:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26384:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26385:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26386:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26387:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26388:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26389:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26390:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L

WARNING: line length of 121 exceeds 100 columns
#41676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26391:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26392:
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L

WARNING: line length of 113 exceeds 100 columns
#41678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26393:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#41679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26394:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#41680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26395:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2

WARNING: line length of 113 exceeds 100 columns
#41681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26396:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3

WARNING: line length of 121 exceeds 100 columns
#41682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26397:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26398:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26399:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26400:
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L

WARNING: line length of 113 exceeds 100 columns
#41686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26401:
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#41687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26402:
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#41688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26403:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#41689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26404:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#41690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26405:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#41691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26406:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#41692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26407:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26408:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26409:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#41695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26410:
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#41696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26411:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#41697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26412:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#41698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26413:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#41699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26414:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#41700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26415:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#41701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26416:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#41702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26417:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#41703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26418:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#41704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26419:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#41705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26420:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#41706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26421:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#41707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26422:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#41708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26423:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#41709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26424:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#41710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26425:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#41711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26426:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#41712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26427:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#41713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26428:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#41714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26429:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#41715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26430:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#41716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26431:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#41717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26432:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#41718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26433:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#41719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26434:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#41720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26435:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#41721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26436:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#41722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26437:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#41723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26438:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#41724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26439:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#41725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26440:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#41726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26441:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26442:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26443:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26444:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#41730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26445:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26446:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#41732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26447:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#41733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26448:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26449:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26450:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26451:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26452:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26453:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26454:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#41740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26455:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26456:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26457:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26458:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26459:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26460:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26461:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#41747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26462:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26463:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26464:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26465:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#41751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26466:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#41752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26467:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#41753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26468:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#41754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26469:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26470:
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#41756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26471:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#41757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26472:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#41758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26473:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#41759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26474:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#41760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26475:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#41761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26476:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#41762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26477:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#41763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26478:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#41764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26479:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#41765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26480:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#41766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26481:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#41767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26482:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#41768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26483:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#41769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26484:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#41770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26485:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#41771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26486:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#41772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26487:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#41773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26488:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#41774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26489:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#41775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26490:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#41776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26491:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#41777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26492:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#41778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26493:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#41779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26494:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#41780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26495:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#41781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26496:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#41782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26497:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#41783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26498:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#41784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26499:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#41785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26500:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#41786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26501:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26502:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26503:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26504:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#41790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26505:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26506:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#41792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26507:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#41793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26508:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#41794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26509:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26510:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#41796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26511:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#41797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26512:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26513:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26514:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#41800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26515:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26516:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26517:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#41803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26518:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26519:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#41805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26520:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#41806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26521:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#41807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26522:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#41808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26523:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26524:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26525:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#41811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26526:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#41812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26527:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#41813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26528:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#41814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26529:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#41815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26530:
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#41816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26531:
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#41817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26532:
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#41818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26533:
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#41819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26534:
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26535:
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26536:
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#41822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26537:
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#41823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26538:
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#41824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26539:
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#41825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26540:
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26541:
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26542:
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#41828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26543:
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#41829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26544:
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#41830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26545:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#41831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26546:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#41832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26547:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#41833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26548:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#41834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26549:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26550:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26551:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#41837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26552:
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#41838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26553:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#41839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26554:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#41840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26555:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#41841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26556:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#41842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26557:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26558:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26559:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#41845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26560:
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#41846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26561:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#41847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26562:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#41848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26563:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#41849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26564:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#41850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26565:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26566:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#41852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26567:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26568:
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#41854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26569:
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd

WARNING: line length of 114 exceeds 100 columns
#41855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26570:
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#41856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26571:
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#41857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26572:
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#41858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26573:
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#41859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26574:
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L

WARNING: line length of 113 exceeds 100 columns
#41860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26575:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#41861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26576:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#41862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26577:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#41863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26578:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#41864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26579:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#41865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26580:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#41866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26581:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26582:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26583:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26584:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#41870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26585:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26586:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L

WARNING: line length of 113 exceeds 100 columns
#41872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26587:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#41873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26588:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#41874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26589:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb

WARNING: line length of 114 exceeds 100 columns
#41875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26590:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#41876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26591:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#41877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26592:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26593:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L

WARNING: line length of 121 exceeds 100 columns
#41879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26594:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L

WARNING: line length of 121 exceeds 100 columns
#41880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26595:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#41881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26596:
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#41882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26597:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#41883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26598:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#41884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26599:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#41885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26600:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#41886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26601:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#41887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26602:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L

WARNING: line length of 121 exceeds 100 columns
#41888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26603:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#41889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26604:
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L

WARNING: line length of 113 exceeds 100 columns
#41890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26605:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#41891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26606:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#41892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26607:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#41893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26608:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#41894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26609:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6

WARNING: line length of 113 exceeds 100 columns
#41895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26610:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#41896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26611:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#41897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26612:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#41898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26613:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#41899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26614:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#41900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26615:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26616:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#41902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26617:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#41903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26618:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L

WARNING: line length of 121 exceeds 100 columns
#41904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26619:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#41905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26620:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#41906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26621:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#41907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26622:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#41908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26623:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#41909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26624:
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#41910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26625:
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#41911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26626:
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4

WARNING: line length of 114 exceeds 100 columns
#41912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26627:
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#41913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26628:
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#41914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26629:
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#41915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26630:
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#41916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26631:
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#41917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26632:
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#41918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26633:
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#41919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26634:
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#41920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26635:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#41921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26636:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#41922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26637:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#41923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26638:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#41924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26639:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#41925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26640:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26641:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26642:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26643:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#41929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26644:
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#41930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26645:
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#41931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26646:
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#41932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26647:
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#41933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26648:
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#41934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26649:
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#41935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26650:
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#41936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26651:
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#41937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26652:
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#41938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26653:
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#41939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26654:
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#41940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26655:
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#41941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26656:
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#41942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26657:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#41943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26658:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#41944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26659:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#41945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26660:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc

WARNING: line length of 114 exceeds 100 columns
#41946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26661:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#41947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26662:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#41948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26663:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#41949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26664:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#41950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26665:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#41951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26666:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#41952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26667:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#41953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26668:
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#41954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26669:
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#41955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26670:
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8

WARNING: line length of 121 exceeds 100 columns
#41956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26671:
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26672:
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#41958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26673:
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#41959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26674:
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#41960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26675:
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#41961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26676:
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#41962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26677:
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26678:
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#41964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26679:
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26680:
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#41966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26681:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#41967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26682:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4

WARNING: line length of 113 exceeds 100 columns
#41968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26683:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb

WARNING: line length of 113 exceeds 100 columns
#41969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26684:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#41970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26685:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#41971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26686:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17

WARNING: line length of 114 exceeds 100 columns
#41972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26687:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18

WARNING: line length of 114 exceeds 100 columns
#41973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26688:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#41974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26689:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e

WARNING: line length of 121 exceeds 100 columns
#41975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26690:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26691:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#41977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26692:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#41978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26693:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#41979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26694:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#41980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26695:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L

WARNING: line length of 121 exceeds 100 columns
#41981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26696:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#41982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26697:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#41983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26698:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L

WARNING: line length of 113 exceeds 100 columns
#41984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26699:
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#41985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26700:
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7

WARNING: line length of 121 exceeds 100 columns
#41986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26701:
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#41987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26702:
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L

WARNING: line length of 113 exceeds 100 columns
#41988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26703:
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#41989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26704:
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L

WARNING: line length of 113 exceeds 100 columns
#41990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26705:
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#41991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26706:
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#41992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26707:
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#41993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26708:
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#41994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26709:
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#41995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26710:
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L

WARNING: line length of 113 exceeds 100 columns
#41996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26711:
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#41997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26712:
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#41998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26713:
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#41999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26714:
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#42000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26715:
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#42001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26716:
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#42002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26717:
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#42003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26718:
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#42004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26719:
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#42005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26720:
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26721:
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26722:
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26723:
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26724:
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#42010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26725:
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26726:
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26727:
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26728:
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#42014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26729:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#42015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26730:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#42016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26731:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#42017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26732:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#42018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26733:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#42019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26734:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26735:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#42021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26736:
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#42022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26737:
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#42023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26738:
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#42024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26739:
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#42025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26740:
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#42026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26741:
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf

WARNING: line length of 114 exceeds 100 columns
#42027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26742:
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#42028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26743:
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14

WARNING: line length of 121 exceeds 100 columns
#42029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26744:
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26745:
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#42031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26746:
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26747:
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#42033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26748:
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26749:
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#42035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26750:
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L

WARNING: line length of 113 exceeds 100 columns
#42036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26751:
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#42037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26752:
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#42038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26753:
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#42039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26754:
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26755:
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26756:
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L

WARNING: line length of 113 exceeds 100 columns
#42042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26757:
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#42043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26758:
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#42044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26759:
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#42045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26760:
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#42046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26761:
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#42047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26762:
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#42048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26763:
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#42049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26764:
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#42050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26765:
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6

WARNING: line length of 114 exceeds 100 columns
#42051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26766:
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#42052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26767:
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26768:
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26769:
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26770:
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26771:
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#42057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26772:
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#42058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26773:
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#42059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26774:
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#42060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26775:
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#42061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26776:
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#42062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26777:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#42063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26778:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#42064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26779:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#42065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26780:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#42066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26781:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#42067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26782:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#42068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26783:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#42069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26784:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26785:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26786:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#42072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26787:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26788:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26789:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26790:
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L

WARNING: line length of 113 exceeds 100 columns
#42076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26791:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#42077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26792:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#42078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26793:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#42079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26794:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#42080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26795:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#42081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26796:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e

WARNING: line length of 114 exceeds 100 columns
#42082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26797:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#42083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26798:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26799:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL

WARNING: line length of 121 exceeds 100 columns
#42085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26800:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#42086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26801:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L

WARNING: line length of 121 exceeds 100 columns
#42087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26802:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#42088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26803:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L

WARNING: line length of 121 exceeds 100 columns
#42089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26804:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#42090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26805:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#42091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26806:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#42092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26807:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#42093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26808:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#42094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26809:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26810:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26811:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26812:
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26813:
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#42099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26814:
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#42100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26815:
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2

WARNING: line length of 113 exceeds 100 columns
#42101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26816:
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#42102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26817:
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#42103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26818:
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#42104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26819:
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9

WARNING: line length of 114 exceeds 100 columns
#42105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26820:
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#42106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26821:
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#42107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26822:
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#42108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26823:
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26824:
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26825:
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26826:
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#42112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26827:
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26828:
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26829:
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#42115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26830:
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#42116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26831:
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26832:
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L

WARNING: line length of 113 exceeds 100 columns
#42118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26833:
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#42119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26834:
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#42120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26835:
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#42121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26836:
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b

WARNING: line length of 121 exceeds 100 columns
#42122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26837:
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26838:
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26839:
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26840:
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L

WARNING: line length of 113 exceeds 100 columns
#42126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26841:
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#42127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26842:
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#42128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26843:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#42129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26844:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#42130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26845:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#42131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26846:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#42132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26847:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc

WARNING: line length of 114 exceeds 100 columns
#42133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26848:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#42134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26849:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#42135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26850:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26851:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26852:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#42138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26853:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26854:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26855:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#42141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26856:
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#42142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26857:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#42143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26858:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#42144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26859:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#42145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26860:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#42146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26861:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#42147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26862:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#42148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26863:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#42149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26864:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#42150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26865:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26866:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26867:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26868:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26869:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#42155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26870:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26871:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#42157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26872:
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26873:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#42159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26874:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#42160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26875:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#42161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26876:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9

WARNING: line length of 121 exceeds 100 columns
#42162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26877:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26878:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26879:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26880:
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L

WARNING: line length of 113 exceeds 100 columns
#42166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26881:
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#42167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26882:
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#42168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26883:
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26884:
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L

WARNING: line length of 113 exceeds 100 columns
#42170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26885:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#42171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26886:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#42172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26887:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#42173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26888:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#42174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26889:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#42175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26890:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#42176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26891:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#42177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26892:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#42178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26893:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#42179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26894:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#42180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26895:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#42181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26896:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb

WARNING: line length of 113 exceeds 100 columns
#42182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26897:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#42183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26898:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#42184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26899:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#42185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26900:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf

WARNING: line length of 114 exceeds 100 columns
#42186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26901:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#42187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26902:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#42188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26903:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#42189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26904:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13

WARNING: line length of 114 exceeds 100 columns
#42190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26905:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#42191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26906:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15

WARNING: line length of 114 exceeds 100 columns
#42192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26907:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#42193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26908:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17

WARNING: line length of 114 exceeds 100 columns
#42194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26909:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#42195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26910:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#42196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26911:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a

WARNING: line length of 114 exceeds 100 columns
#42197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26912:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b

WARNING: line length of 114 exceeds 100 columns
#42198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26913:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#42199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26914:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d

WARNING: line length of 114 exceeds 100 columns
#42200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26915:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e

WARNING: line length of 114 exceeds 100 columns
#42201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26916:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f

WARNING: line length of 121 exceeds 100 columns
#42202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26917:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26918:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26919:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26920:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#42206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26921:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26922:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26923:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#42209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26924:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26925:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26926:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#42212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26927:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#42213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26928:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#42214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26929:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26930:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#42216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26931:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#42217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26932:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26933:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26934:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#42220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26935:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#42221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26936:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L

WARNING: line length of 121 exceeds 100 columns
#42222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26937:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26938:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#42224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26939:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#42225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26940:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#42226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26941:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26942:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#42228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26943:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L

WARNING: line length of 121 exceeds 100 columns
#42229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26944:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#42230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26945:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#42231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26946:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L

WARNING: line length of 121 exceeds 100 columns
#42232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26947:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#42233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26948:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#42234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26949:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#42235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26950:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#42236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26951:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#42237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26952:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#42238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26953:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#42239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26954:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#42240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26955:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#42241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26956:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#42242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26957:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#42243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26958:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9

WARNING: line length of 113 exceeds 100 columns
#42244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26959:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#42245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26960:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb

WARNING: line length of 113 exceeds 100 columns
#42246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26961:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#42247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26962:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#42248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26963:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe

WARNING: line length of 113 exceeds 100 columns
#42249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26964:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf

WARNING: line length of 114 exceeds 100 columns
#42250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26965:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#42251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26966:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#42252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26967:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#42253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26968:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#42254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26969:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#42255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26970:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#42256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26971:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#42257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26972:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17

WARNING: line length of 114 exceeds 100 columns
#42258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26973:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#42259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26974:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19

WARNING: line length of 114 exceeds 100 columns
#42260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26975:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#42261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26976:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b

WARNING: line length of 121 exceeds 100 columns
#42262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26977:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26978:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26979:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26980:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#42266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26981:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26982:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26983:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#42269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26984:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26985:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26986:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#42272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26987:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#42273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26988:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L

WARNING: line length of 121 exceeds 100 columns
#42274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26989:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26990:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#42276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26991:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#42277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26992:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26993:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26994:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#42280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26995:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#42281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26996:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#42282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26997:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26998:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L

WARNING: line length of 121 exceeds 100 columns
#42284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:26999:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#42285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27000:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#42286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27001:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27002:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L

WARNING: line length of 121 exceeds 100 columns
#42288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27003:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#42289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27004:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L

WARNING: line length of 113 exceeds 100 columns
#42290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27005:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#42291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27006:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#42292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27007:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#42293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27008:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#42294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27009:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#42295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27010:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#42296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27011:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#42297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27012:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7

WARNING: line length of 113 exceeds 100 columns
#42298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27013:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#42299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27014:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9

WARNING: line length of 113 exceeds 100 columns
#42300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27015:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#42301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27016:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb

WARNING: line length of 113 exceeds 100 columns
#42302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27017:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#42303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27018:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd

WARNING: line length of 113 exceeds 100 columns
#42304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27019:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#42305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27020:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf

WARNING: line length of 114 exceeds 100 columns
#42306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27021:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#42307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27022:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#42308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27023:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#42309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27024:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13

WARNING: line length of 114 exceeds 100 columns
#42310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27025:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#42311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27026:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15

WARNING: line length of 114 exceeds 100 columns
#42312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27027:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#42313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27028:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17

WARNING: line length of 114 exceeds 100 columns
#42314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27029:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18

WARNING: line length of 114 exceeds 100 columns
#42315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27030:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19

WARNING: line length of 114 exceeds 100 columns
#42316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27031:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#42317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27032:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b

WARNING: line length of 114 exceeds 100 columns
#42318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27033:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#42319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27034:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d

WARNING: line length of 121 exceeds 100 columns
#42320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27035:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27036:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27037:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27038:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#42324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27039:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27040:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27041:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#42327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27042:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27043:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27044:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#42330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27045:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#42331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27046:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#42332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27047:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27048:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#42334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27049:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#42335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27050:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27051:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27052:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#42338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27053:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#42339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27054:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#42340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27055:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27056:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#42342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27057:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#42343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27058:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L

WARNING: line length of 121 exceeds 100 columns
#42344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27059:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27060:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#42346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27061:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#42347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27062:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#42348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27063:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#42349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27064:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L

WARNING: line length of 113 exceeds 100 columns
#42350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27065:
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#42351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27066:
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#42352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27067:
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#42353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27068:
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8

WARNING: line length of 113 exceeds 100 columns
#42354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27069:
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc

WARNING: line length of 121 exceeds 100 columns
#42355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27070:
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27071:
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27072:
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27073:
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#42359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27074:
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L

WARNING: line length of 113 exceeds 100 columns
#42360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27075:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#42361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27076:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#42362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27077:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27078:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27079:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#42365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27080:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#42366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27081:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27082:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27083:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#42369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27084:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#42370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27085:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27086:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27087:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#42373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27088:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#42374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27089:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27090:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27091:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#42377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27092:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#42378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27093:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27094:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27095:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#42381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27096:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#42382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27097:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27098:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27099:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#42385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27100:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#42386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27101:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27102:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27103:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#42389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27104:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#42390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27105:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#42391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27106:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#42392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27107:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#42393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27108:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14

WARNING: line length of 114 exceeds 100 columns
#42394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27109:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#42395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27110:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#42396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27111:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17

WARNING: line length of 114 exceeds 100 columns
#42397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27112:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18

WARNING: line length of 114 exceeds 100 columns
#42398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27113:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19

WARNING: line length of 114 exceeds 100 columns
#42399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27114:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#42400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27115:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b

WARNING: line length of 114 exceeds 100 columns
#42401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27116:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#42402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27117:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d

WARNING: line length of 114 exceeds 100 columns
#42403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27118:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e

WARNING: line length of 121 exceeds 100 columns
#42404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27119:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27120:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27121:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#42407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27122:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#42408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27123:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#42409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27124:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27125:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#42411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27126:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#42412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27127:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#42413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27128:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27129:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L

WARNING: line length of 121 exceeds 100 columns
#42415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27130:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#42416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27131:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L

WARNING: line length of 121 exceeds 100 columns
#42417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27132:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#42418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27133:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#42419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27134:
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L

WARNING: line length of 113 exceeds 100 columns
#42420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27135:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#42421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27136:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#42422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27137:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#42423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27138:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#42424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27139:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#42425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27140:
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf

WARNING: line length of 114 exceeds 100 columns
#42426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27141:
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#42427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27142:
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#42428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27143:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27144:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27145:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27146:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27147:
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27148:
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27149:
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27150:
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#42436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27151:
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#42437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27152:
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#42438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27153:
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#42439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27154:
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#42440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27155:
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#42441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27156:
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#42442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27157:
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#42443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27158:
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#42444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27159:
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#42445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27160:
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#42446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27161:
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#42447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27162:
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#42448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27163:
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc

WARNING: line length of 121 exceeds 100 columns
#42449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27164:
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#42450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27165:
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#42451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27166:
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#42452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27167:
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#42453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27168:
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8

WARNING: line length of 121 exceeds 100 columns
#42454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27169:
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27170:
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#42456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27171:
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#42457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27172:
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#42458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27173:
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#42459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27174:
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#42460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27175:
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#42461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27176:
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27177:
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27178:
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27179:
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#42465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27180:
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#42466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27181:
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#42467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27182:
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#42468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27183:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#42469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27184:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#42470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27185:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#42471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27186:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3

WARNING: line length of 121 exceeds 100 columns
#42472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27187:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27188:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27189:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27190:
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L

WARNING: line length of 113 exceeds 100 columns
#42476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27191:
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#42477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27192:
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8

WARNING: line length of 121 exceeds 100 columns
#42478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27193:
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#42479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27194:
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#42480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27195:
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#42481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27196:
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#42482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27197:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#42483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27198:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#42484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27199:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27200:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#42486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27201:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#42487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27202:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#42488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27203:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27204:
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#42490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27205:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#42491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27206:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#42492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27207:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#42493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27208:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#42494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27209:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27210:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27211:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27212:
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L

WARNING: line length of 113 exceeds 100 columns
#42498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27213:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#42499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27214:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#42500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27215:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#42501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27216:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#42502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27217:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18

WARNING: line length of 121 exceeds 100 columns
#42503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27218:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27219:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#42505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27220:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27221:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#42507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27222:
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L

WARNING: line length of 113 exceeds 100 columns
#42508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27223:
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#42509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27224:
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#42510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27225:
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27226:
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#42512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27227:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#42513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27228:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#42514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27229:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#42515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27230:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#42516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27231:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#42517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27232:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#42518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27233:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#42519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27234:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#42520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27235:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#42521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27236:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#42522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27237:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#42523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27238:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#42524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27239:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#42525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27240:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#42526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27241:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#42527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27242:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#42528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27243:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#42529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27244:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27245:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#42531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27246:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#42532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27247:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#42533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27248:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27249:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#42535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27250:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#42536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27251:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#42537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27252:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#42538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27253:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#42539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27254:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#42540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27255:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#42541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27256:
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#42542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27257:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#42543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27258:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#42544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27259:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#42545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27260:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#42546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27261:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#42547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27262:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#42548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27263:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#42549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27264:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#42550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27265:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#42551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27266:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#42552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27267:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#42553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27268:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#42554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27269:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#42555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27270:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#42556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27271:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#42557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27272:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#42558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27273:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27274:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#42560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27275:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#42561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27276:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#42562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27277:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27278:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#42564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27279:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#42565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27280:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#42566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27281:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#42567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27282:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#42568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27283:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#42569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27284:
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 113 exceeds 100 columns
#42570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27285:
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#42571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27286:
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#42572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27287:
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#42573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27288:
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8

WARNING: line length of 121 exceeds 100 columns
#42574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27289:
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27290:
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L

WARNING: line length of 113 exceeds 100 columns
#42576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27291:
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#42577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27292:
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#42578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27293:
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e

WARNING: line length of 121 exceeds 100 columns
#42579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27294:
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27295:
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L

WARNING: line length of 121 exceeds 100 columns
#42581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27296:
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L

WARNING: line length of 114 exceeds 100 columns
#42582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27297:
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#42583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27298:
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#42584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27299:
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#42585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27300:
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#42586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27301:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#42587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27302:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#42588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27303:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#42589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27304:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14

WARNING: line length of 121 exceeds 100 columns
#42590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27305:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27306:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L

WARNING: line length of 121 exceeds 100 columns
#42592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27307:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27308:
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L

WARNING: line length of 113 exceeds 100 columns
#42594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27309:
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#42595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27310:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#42596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27311:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#42597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27312:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#42598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27313:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7

WARNING: line length of 113 exceeds 100 columns
#42599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27314:
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#42600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27315:
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#42601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27316:
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#42602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27317:
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27318:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27319:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27320:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#42606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27321:
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27322:
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27323:
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27324:
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27325:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#42611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27326:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#42612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27327:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#42613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27328:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#42614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27329:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#42615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27330:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#42616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27331:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#42617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27332:
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#42618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27333:
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#42619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27334:
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#42620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27335:
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27336:
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#42622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27337:
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#42623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27338:
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#42624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27339:
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa

WARNING: line length of 113 exceeds 100 columns
#42625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27340:
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#42626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27341:
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18

WARNING: line length of 121 exceeds 100 columns
#42627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27342:
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27343:
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27344:
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#42630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27345:
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#42631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27346:
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#42632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27347:
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#42633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27348:
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#42634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27349:
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#42635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27350:
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#42636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27351:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#42637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27352:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#42638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27353:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#42639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27354:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#42640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27355:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#42641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27356:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27357:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27358:
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#42644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27359:
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#42645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27360:
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#42646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27361:
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#42647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27362:
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#42648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27363:
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#42649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27364:
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L

WARNING: line length of 113 exceeds 100 columns
#42650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27365:
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#42651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27366:
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#42652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27367:
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#42653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27368:
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27369:
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27370:
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#42656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27371:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#42657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27372:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#42658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27373:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2

WARNING: line length of 113 exceeds 100 columns
#42659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27374:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#42660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27375:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#42661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27376:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#42662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27377:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#42663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27378:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#42664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27379:
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#42665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27380:
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#42666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27381:
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18

WARNING: line length of 121 exceeds 100 columns
#42667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27382:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27383:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27384:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27385:
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#42671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27386:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27387:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27388:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#42674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27389:
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27390:
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27391:
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27392:
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L

WARNING: line length of 113 exceeds 100 columns
#42678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27393:
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#42679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27394:
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#42680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27395:
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#42681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27396:
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#42682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27397:
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#42683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27398:
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27399:
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#42685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27400:
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#42686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27401:
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#42687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27402:
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#42688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27403:
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#42689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27404:
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27405:
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#42691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27406:
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#42692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27407:
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#42693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27408:
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa

WARNING: line length of 121 exceeds 100 columns
#42694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27409:
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27410:
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L

WARNING: line length of 113 exceeds 100 columns
#42696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27411:
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#42697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27412:
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#42698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27413:
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#42699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27414:
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27415:
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27416:
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L

WARNING: line length of 113 exceeds 100 columns
#42702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27417:
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#42703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27418:
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#42704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27419:
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#42705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27420:
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27421:
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L

WARNING: line length of 121 exceeds 100 columns
#42707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27422:
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L

WARNING: line length of 113 exceeds 100 columns
#42708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27423:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#42709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27424:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#42710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27425:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#42711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27426:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#42712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27427:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27428:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27429:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L

WARNING: line length of 121 exceeds 100 columns
#42715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27430:
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#42716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27431:
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#42717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27432:
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#42718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27433:
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#42719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27434:
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27435:
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27436:
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#42722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27437:
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#42723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27438:
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4

WARNING: line length of 114 exceeds 100 columns
#42724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27439:
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#42725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27440:
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27441:
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L

WARNING: line length of 121 exceeds 100 columns
#42727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27442:
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#42728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27443:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#42729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27444:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#42730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27445:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#42731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27446:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#42732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27447:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#42733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27448:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#42734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27449:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#42735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27450:
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#42736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27451:
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#42737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27452:
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#42738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27453:
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#42739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27454:
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#42740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27455:
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#42741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27456:
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#42742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27457:
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#42743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27458:
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27459:
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27460:
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L

WARNING: line length of 113 exceeds 100 columns
#42746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27461:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#42747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27462:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#42748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27463:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2

WARNING: line length of 113 exceeds 100 columns
#42749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27464:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#42750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27465:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#42751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27466:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14

WARNING: line length of 121 exceeds 100 columns
#42752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27467:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27468:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27469:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#42755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27470:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27471:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L

WARNING: line length of 121 exceeds 100 columns
#42757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27472:
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#42758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27473:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#42759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27474:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#42760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27475:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#42761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27476:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc

WARNING: line length of 121 exceeds 100 columns
#42762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27477:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27478:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27479:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27480:
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#42766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27481:
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#42767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27482:
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#42768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27483:
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#42769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27484:
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc

WARNING: line length of 114 exceeds 100 columns
#42770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27485:
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#42771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27486:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#42772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27487:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15

WARNING: line length of 114 exceeds 100 columns
#42773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27488:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16

WARNING: line length of 114 exceeds 100 columns
#42774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27489:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17

WARNING: line length of 114 exceeds 100 columns
#42775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27490:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18

WARNING: line length of 114 exceeds 100 columns
#42776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27491:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19

WARNING: line length of 114 exceeds 100 columns
#42777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27492:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#42778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27493:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b

WARNING: line length of 114 exceeds 100 columns
#42779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27494:
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#42780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27495:
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27496:
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27497:
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27498:
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27499:
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#42785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27500:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27501:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#42787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27502:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L

WARNING: line length of 121 exceeds 100 columns
#42788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27503:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L

WARNING: line length of 121 exceeds 100 columns
#42789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27504:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27505:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#42791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27506:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L

WARNING: line length of 121 exceeds 100 columns
#42792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27507:
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L

WARNING: line length of 121 exceeds 100 columns
#42793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27508:
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#42794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27509:
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#42795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27510:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#42796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27511:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#42797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27512:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5

WARNING: line length of 113 exceeds 100 columns
#42798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27513:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#42799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27514:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#42800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27515:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#42801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27516:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#42802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27517:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#42803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27518:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#42804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27519:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#42805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27520:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd

WARNING: line length of 113 exceeds 100 columns
#42806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27521:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe

WARNING: line length of 113 exceeds 100 columns
#42807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27522:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf

WARNING: line length of 114 exceeds 100 columns
#42808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27523:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#42809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27524:
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27525:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#42811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27526:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27527:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#42813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27528:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#42814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27529:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#42815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27530:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#42816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27531:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#42817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27532:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#42818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27533:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#42819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27534:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#42820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27535:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#42821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27536:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#42822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27537:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27538:
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27539:
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#42825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27540:
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#42826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27541:
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#42827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27542:
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27543:
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#42829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27544:
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#42830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27545:
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27546:
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27547:
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#42833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27548:
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#42834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27549:
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#42835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27550:
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27551:
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#42837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27552:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#42838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27553:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#42839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27554:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#42840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27555:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d

WARNING: line length of 121 exceeds 100 columns
#42841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27556:
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27557:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#42843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27558:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#42844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27559:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#42845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27560:
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L

WARNING: line length of 113 exceeds 100 columns
#42846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27561:
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#42847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27562:
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#42848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27563:
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#42849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27564:
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#42850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27565:
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#42851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27566:
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#42852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27567:
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#42853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27568:
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#42854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27569:
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#42855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27570:
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#42856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27571:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#42857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27572:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#42858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27573:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#42859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27574:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#42860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27575:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#42861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27576:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27577:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27578:
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#42864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27579:
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#42865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27580:
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a

WARNING: line length of 121 exceeds 100 columns
#42866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27581:
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#42867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27582:
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#42868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27583:
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#42869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27584:
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#42870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27585:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#42871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27586:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#42872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27587:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#42873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27588:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#42874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27589:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27590:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27591:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#42877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27592:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27593:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#42879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27594:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#42880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27595:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#42881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27596:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#42882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27597:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27598:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27599:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#42885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27600:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27601:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#42887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27602:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#42888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27603:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#42889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27604:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#42890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27605:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27606:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27607:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#42893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27608:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27609:
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#42895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27610:
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8

WARNING: line length of 121 exceeds 100 columns
#42896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27611:
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#42897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27612:
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#42898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27613:
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#42899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27614:
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#42900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27615:
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27616:
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L

WARNING: line length of 113 exceeds 100 columns
#42902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27617:
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#42903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27618:
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#42904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27619:
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#42905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27620:
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#42906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27621:
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#42907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27622:
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#42908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27623:
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#42909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27624:
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf

WARNING: line length of 114 exceeds 100 columns
#42910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27625:
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#42911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27626:
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#42912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27627:
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27628:
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L

WARNING: line length of 113 exceeds 100 columns
#42914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27629:
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#42915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27630:
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L

WARNING: line length of 113 exceeds 100 columns
#42916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27631:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#42917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27632:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#42918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27633:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#42919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27634:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#42920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27635:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27636:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27637:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#42923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27638:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27639:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#42925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27640:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#42926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27641:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#42927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27642:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#42928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27643:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27644:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27645:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#42931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27646:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27647:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#42933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27648:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#42934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27649:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#42935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27650:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#42936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27651:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#42937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27652:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#42938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27653:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#42939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27654:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#42940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27655:
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#42941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27656:
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L

WARNING: line length of 113 exceeds 100 columns
#42942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27657:
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#42943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27658:
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#42944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27659:
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27660:
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27661:
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#42947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27662:
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#42948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27663:
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27664:
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27665:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#42951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27666:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#42952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27667:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#42953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27668:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#42954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27669:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#42955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27670:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#42956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27671:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#42957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27672:
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#42958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27673:
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#42959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27674:
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#42960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27675:
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#42961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27676:
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#42962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27677:
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#42963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27678:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#42964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27679:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#42965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27680:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc

WARNING: line length of 114 exceeds 100 columns
#42966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27681:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#42967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27682:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#42968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27683:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#42969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27684:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#42970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27685:
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#42971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27686:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#42972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27687:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#42973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27688:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#42974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27689:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#42975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27690:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#42976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27691:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#42977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27692:
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#42978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27693:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#42979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27694:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#42980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27695:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#42981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27696:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc

WARNING: line length of 114 exceeds 100 columns
#42982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27697:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#42983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27698:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#42984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27699:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#42985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27700:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#42986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27701:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#42987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27702:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#42988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27703:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#42989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27704:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#42990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27705:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#42991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27706:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#42992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27707:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#42993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27708:
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#42994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27709:
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#42995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27710:
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L

WARNING: line length of 113 exceeds 100 columns
#42996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27711:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#42997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27712:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#42998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27713:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#42999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27714:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#43000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27715:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#43001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27716:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#43002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27717:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#43003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27718:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#43004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27719:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#43005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27720:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#43006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27721:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#43007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27722:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#43008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27723:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#43009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27724:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#43010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27725:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 113 exceeds 100 columns
#43011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27726:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf

WARNING: line length of 114 exceeds 100 columns
#43012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27727:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#43013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27728:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#43014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27729:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12

WARNING: line length of 114 exceeds 100 columns
#43015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27730:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#43016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27731:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#43017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27732:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#43018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27733:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16

WARNING: line length of 114 exceeds 100 columns
#43019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27734:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#43020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27735:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#43021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27736:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#43022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27737:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a

WARNING: line length of 114 exceeds 100 columns
#43023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27738:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b

WARNING: line length of 114 exceeds 100 columns
#43024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27739:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#43025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27740:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27741:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27742:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27743:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27744:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27745:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27746:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27747:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27748:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27749:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27750:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#43036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27751:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#43037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27752:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27753:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27754:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27755:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27756:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27757:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27758:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27759:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27760:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27761:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27762:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#43048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27763:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27764:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27765:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27766:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27767:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#43053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27768:
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#43054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27769:
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#43055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27770:
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#43056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27771:
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#43057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27772:
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27773:
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#43059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27774:
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#43060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27775:
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#43061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27776:
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27777:
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#43063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27778:
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#43064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27779:
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#43065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27780:
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27781:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#43067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27782:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#43068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27783:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#43069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27784:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12

WARNING: line length of 114 exceeds 100 columns
#43070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27785:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#43071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27786:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#43072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27787:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#43073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27788:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#43074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27789:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#43075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27790:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#43076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27791:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19

WARNING: line length of 114 exceeds 100 columns
#43077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27792:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#43078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27793:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b

WARNING: line length of 121 exceeds 100 columns
#43079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27794:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#43080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27795:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27796:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27797:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27798:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27799:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27800:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27801:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#43087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27802:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27803:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27804:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27805:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27806:
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L

WARNING: line length of 113 exceeds 100 columns
#43092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27807:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#43093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27808:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#43094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27809:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#43095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27810:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#43096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27811:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#43097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27812:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#43098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27813:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#43099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27814:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd

WARNING: line length of 114 exceeds 100 columns
#43100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27815:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#43101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27816:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#43102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27817:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14

WARNING: line length of 114 exceeds 100 columns
#43103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27818:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#43104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27819:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#43105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27820:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#43106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27821:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#43107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27822:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d

WARNING: line length of 121 exceeds 100 columns
#43108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27823:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27824:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27825:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27826:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27827:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27828:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27829:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27830:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27831:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27832:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27833:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27834:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27835:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27836:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27837:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#43123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27838:
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L

WARNING: line length of 113 exceeds 100 columns
#43124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27839:
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#43125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27840:
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#43126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27841:
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5

WARNING: line length of 113 exceeds 100 columns
#43127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27842:
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#43128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27843:
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#43129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27844:
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf

WARNING: line length of 114 exceeds 100 columns
#43130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27845:
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10

WARNING: line length of 114 exceeds 100 columns
#43131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27846:
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11

WARNING: line length of 121 exceeds 100 columns
#43132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27847:
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27848:
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27849:
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27850:
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27851:
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27852:
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27853:
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27854:
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L

WARNING: line length of 113 exceeds 100 columns
#43140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27855:
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#43141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27856:
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#43142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27857:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#43143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27858:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#43144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27859:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#43145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27860:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#43146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27861:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#43147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27862:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#43148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27863:
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#43149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27864:
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27865:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27866:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27867:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27868:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27869:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27870:
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27871:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#43157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27872:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#43158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27873:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4

WARNING: line length of 114 exceeds 100 columns
#43159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27874:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10

WARNING: line length of 121 exceeds 100 columns
#43160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27875:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27876:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27877:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#43163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27878:
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27879:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#43165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27880:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#43166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27881:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#43167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27882:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#43168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27883:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#43169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27884:
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#43170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27885:
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#43171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27886:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#43172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27887:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#43173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27888:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27889:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27890:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27891:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27892:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27893:
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27894:
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27895:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#43181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27896:
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27897:
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#43183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27898:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#43184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27899:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#43185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27900:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#43186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27901:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#43187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27902:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#43188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27903:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#43189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27904:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#43190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27905:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#43191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27906:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#43192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27907:
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#43193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27908:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27909:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27910:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27911:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27912:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27913:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27914:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27915:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27916:
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27917:
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#43203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27918:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#43204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27919:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#43205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27920:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#43206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27921:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#43207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27922:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#43208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27923:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#43209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27924:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#43210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27925:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#43211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27926:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#43212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27927:
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#43213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27928:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27929:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27930:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27931:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27932:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27933:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27934:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27935:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27936:
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27937:
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#43223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27938:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#43224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27939:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#43225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27940:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#43226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27941:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#43227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27942:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#43228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27943:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#43229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27944:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#43230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27945:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#43231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27946:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#43232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27947:
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#43233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27948:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27949:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27950:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27951:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27952:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27953:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27954:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27955:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27956:
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27957:
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#43243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27958:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#43244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27959:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#43245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27960:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#43246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27961:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#43247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27962:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#43248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27963:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#43249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27964:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#43250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27965:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#43251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27966:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#43252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27967:
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#43253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27968:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27969:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27970:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27971:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27972:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27973:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27974:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27975:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27976:
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27977:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#43263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27978:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#43264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27979:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#43265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27980:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#43266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27981:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#43267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27982:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#43268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27983:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#43269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27984:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#43270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27985:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#43271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27986:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#43272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27987:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#43273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27988:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb

WARNING: line length of 121 exceeds 100 columns
#43274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27989:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27990:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27991:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27992:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27993:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27994:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27995:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27996:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27997:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27998:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:27999:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#43285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28000:
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L

WARNING: line length of 113 exceeds 100 columns
#43286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28001:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#43287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28002:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#43288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28003:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#43289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28004:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#43290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28005:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#43291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28006:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L

WARNING: line length of 121 exceeds 100 columns
#43292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28007:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L

WARNING: line length of 121 exceeds 100 columns
#43293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28008:
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#43294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28009:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#43295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28010:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7

WARNING: line length of 114 exceeds 100 columns
#43296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28011:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#43297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28012:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#43298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28013:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12

WARNING: line length of 114 exceeds 100 columns
#43299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28014:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13

WARNING: line length of 114 exceeds 100 columns
#43300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28015:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#43301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28016:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#43302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28017:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28018:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28019:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28020:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28021:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28022:
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#43308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28023:
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#43309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28024:
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#43310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28025:
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#43311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28026:
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28027:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#43313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28028:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#43314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28029:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3

WARNING: line length of 113 exceeds 100 columns
#43315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28030:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#43316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28031:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#43317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28032:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6

WARNING: line length of 114 exceeds 100 columns
#43318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28033:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#43319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28034:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28035:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28036:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28037:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28038:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28039:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28040:
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#43326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28041:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#43327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28042:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#43328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28043:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#43329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28044:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#43330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28045:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8

WARNING: line length of 114 exceeds 100 columns
#43331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28046:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#43332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28047:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28048:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28049:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28050:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28051:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#43337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28052:
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28053:
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#43339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28054:
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#43340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28055:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#43341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28056:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#43342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28057:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#43343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28058:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#43344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28059:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#43345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28060:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#43346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28061:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#43347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28062:
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#43348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28063:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#43349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28064:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#43350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28065:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#43351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28066:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#43352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28067:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#43353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28068:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#43354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28069:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#43355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28070:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#43356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28071:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#43357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28072:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#43358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28073:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#43359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28074:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#43360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28075:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#43361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28076:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#43362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28077:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#43363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28078:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#43364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28079:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#43365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28080:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#43366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28081:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#43367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28082:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#43368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28083:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#43369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28084:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#43370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28085:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#43371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28086:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#43372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28087:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#43373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28088:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#43374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28089:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#43375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28090:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#43376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28091:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#43377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28092:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#43378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28093:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28094:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28095:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28096:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28097:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28098:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28099:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28100:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28101:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28102:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28103:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#43389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28104:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#43390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28105:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28106:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28107:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28108:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28109:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28110:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28111:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28112:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28113:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28114:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#43400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28115:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28116:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28117:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28118:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28119:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#43405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28120:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#43406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28121:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#43407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28122:
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#43408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28123:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#43409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28124:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#43410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28125:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#43411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28126:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#43412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28127:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#43413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28128:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#43414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28129:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#43415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28130:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#43416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28131:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#43417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28132:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#43418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28133:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#43419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28134:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#43420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28135:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#43421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28136:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#43422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28137:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#43423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28138:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#43424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28139:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#43425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28140:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#43426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28141:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#43427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28142:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#43428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28143:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#43429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28144:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#43430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28145:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#43431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28146:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#43432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28147:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#43433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28148:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#43434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28149:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#43435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28150:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#43436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28151:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#43437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28152:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#43438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28153:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28154:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28155:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28156:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28157:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28158:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28159:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28160:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28161:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28162:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28163:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#43449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28164:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#43450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28165:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28166:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28167:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28168:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28169:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28170:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28171:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28172:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28173:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28174:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#43460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28175:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28176:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28177:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28178:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28179:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#43465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28180:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#43466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28181:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#43467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28182:
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#43468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28183:
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#43469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28184:
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#43470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28185:
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#43471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28186:
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28187:
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28188:
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#43474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28189:
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#43475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28190:
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#43476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28191:
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#43477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28192:
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28193:
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28194:
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#43480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28195:
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#43481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28196:
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#43482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28197:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#43483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28198:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#43484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28199:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#43485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28200:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#43486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28201:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#43487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28202:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#43488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28203:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#43489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28204:
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#43490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28205:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#43491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28206:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#43492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28207:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#43493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28208:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#43494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28209:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#43495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28210:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#43496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28211:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#43497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28212:
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#43498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28213:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#43499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28214:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#43500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28215:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#43501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28216:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#43502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28217:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#43503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28218:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#43504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28219:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28220:
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#43506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28221:
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd

WARNING: line length of 114 exceeds 100 columns
#43507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28222:
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#43508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28223:
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#43509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28224:
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28225:
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#43511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28226:
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L

WARNING: line length of 113 exceeds 100 columns
#43512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28227:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#43513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28228:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#43514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28229:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#43515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28230:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#43516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28231:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#43517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28232:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#43518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28233:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28234:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28235:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#43521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28236:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#43522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28237:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28238:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L

WARNING: line length of 113 exceeds 100 columns
#43524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28239:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#43525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28240:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#43526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28241:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb

WARNING: line length of 114 exceeds 100 columns
#43527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28242:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#43528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28243:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#43529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28244:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#43530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28245:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L

WARNING: line length of 121 exceeds 100 columns
#43531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28246:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L

WARNING: line length of 121 exceeds 100 columns
#43532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28247:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#43533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28248:
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#43534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28249:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#43535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28250:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#43536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28251:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#43537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28252:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#43538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28253:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#43539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28254:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L

WARNING: line length of 121 exceeds 100 columns
#43540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28255:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28256:
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L

WARNING: line length of 113 exceeds 100 columns
#43542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28257:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#43543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28258:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#43544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28259:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#43545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28260:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#43546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28261:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6

WARNING: line length of 113 exceeds 100 columns
#43547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28262:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#43548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28263:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#43549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28264:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#43550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28265:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#43551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28266:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#43552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28267:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28268:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28269:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28270:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L

WARNING: line length of 121 exceeds 100 columns
#43556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28271:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#43557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28272:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#43558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28273:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#43559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28274:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#43560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28275:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#43561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28276:
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#43562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28277:
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#43563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28278:
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4

WARNING: line length of 114 exceeds 100 columns
#43564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28279:
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#43565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28280:
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#43566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28281:
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#43567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28282:
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#43568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28283:
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#43569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28284:
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28285:
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28286:
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#43572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28287:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#43573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28288:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#43574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28289:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#43575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28290:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#43576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28291:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#43577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28292:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28293:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28294:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28295:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#43581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28296:
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28297:
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#43583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28298:
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#43584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28299:
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#43585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28300:
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#43586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28301:
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#43587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28302:
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#43588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28303:
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#43589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28304:
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#43590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28305:
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#43591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28306:
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#43592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28307:
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#43593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28308:
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#43594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28309:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#43595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28310:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#43596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28311:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#43597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28312:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc

WARNING: line length of 114 exceeds 100 columns
#43598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28313:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#43599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28314:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#43600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28315:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#43601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28316:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#43602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28317:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#43603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28318:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#43604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28319:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#43605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28320:
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#43606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28321:
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#43607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28322:
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8

WARNING: line length of 121 exceeds 100 columns
#43608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28323:
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28324:
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#43610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28325:
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#43611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28326:
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#43612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28327:
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#43613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28328:
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#43614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28329:
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28330:
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28331:
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28332:
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#43618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28333:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#43619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28334:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4

WARNING: line length of 113 exceeds 100 columns
#43620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28335:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb

WARNING: line length of 113 exceeds 100 columns
#43621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28336:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#43622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28337:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#43623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28338:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17

WARNING: line length of 114 exceeds 100 columns
#43624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28339:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18

WARNING: line length of 114 exceeds 100 columns
#43625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28340:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#43626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28341:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e

WARNING: line length of 121 exceeds 100 columns
#43627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28342:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28343:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28344:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#43630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28345:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28346:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28347:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28348:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28349:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28350:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L

WARNING: line length of 113 exceeds 100 columns
#43636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28351:
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#43637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28352:
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7

WARNING: line length of 121 exceeds 100 columns
#43638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28353:
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28354:
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L

WARNING: line length of 113 exceeds 100 columns
#43640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28355:
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#43641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28356:
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L

WARNING: line length of 113 exceeds 100 columns
#43642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28357:
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#43643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28358:
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#43644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28359:
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#43645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28360:
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28361:
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#43647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28362:
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L

WARNING: line length of 113 exceeds 100 columns
#43648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28363:
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#43649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28364:
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#43650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28365:
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#43651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28366:
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#43652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28367:
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#43653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28368:
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#43654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28369:
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#43655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28370:
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#43656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28371:
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#43657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28372:
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#43658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28373:
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28374:
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28375:
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28376:
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28377:
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28378:
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28379:
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28380:
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#43666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28381:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#43667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28382:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#43668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28383:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#43669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28384:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#43670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28385:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#43671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28386:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28387:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#43673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28388:
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#43674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28389:
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#43675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28390:
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#43676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28391:
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#43677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28392:
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#43678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28393:
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf

WARNING: line length of 114 exceeds 100 columns
#43679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28394:
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#43680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28395:
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14

WARNING: line length of 121 exceeds 100 columns
#43681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28396:
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#43682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28397:
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#43683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28398:
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28399:
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#43685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28400:
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28401:
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#43687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28402:
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L

WARNING: line length of 113 exceeds 100 columns
#43688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28403:
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#43689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28404:
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#43690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28405:
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#43691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28406:
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28407:
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28408:
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L

WARNING: line length of 113 exceeds 100 columns
#43694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28409:
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#43695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28410:
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#43696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28411:
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#43697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28412:
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#43698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28413:
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#43699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28414:
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#43700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28415:
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#43701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28416:
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#43702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28417:
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6

WARNING: line length of 114 exceeds 100 columns
#43703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28418:
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#43704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28419:
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28420:
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28421:
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28422:
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28423:
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28424:
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#43710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28425:
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#43711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28426:
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#43712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28427:
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#43713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28428:
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#43714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28429:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#43715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28430:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#43716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28431:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#43717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28432:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#43718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28433:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#43719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28434:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#43720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28435:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#43721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28436:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28437:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28438:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#43724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28439:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28440:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28441:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28442:
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L

WARNING: line length of 113 exceeds 100 columns
#43728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28443:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#43729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28444:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#43730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28445:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#43731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28446:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#43732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28447:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#43733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28448:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e

WARNING: line length of 114 exceeds 100 columns
#43734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28449:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#43735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28450:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28451:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL

WARNING: line length of 121 exceeds 100 columns
#43737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28452:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#43738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28453:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L

WARNING: line length of 121 exceeds 100 columns
#43739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28454:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#43740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28455:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L

WARNING: line length of 121 exceeds 100 columns
#43741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28456:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#43742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28457:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#43743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28458:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#43744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28459:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#43745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28460:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#43746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28461:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28462:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28463:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28464:
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#43750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28465:
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#43751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28466:
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#43752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28467:
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2

WARNING: line length of 113 exceeds 100 columns
#43753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28468:
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#43754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28469:
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#43755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28470:
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#43756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28471:
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9

WARNING: line length of 114 exceeds 100 columns
#43757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28472:
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#43758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28473:
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#43759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28474:
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#43760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28475:
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28476:
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28477:
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28478:
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28479:
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28480:
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28481:
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28482:
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#43768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28483:
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28484:
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L

WARNING: line length of 113 exceeds 100 columns
#43770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28485:
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#43771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28486:
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#43772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28487:
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#43773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28488:
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b

WARNING: line length of 121 exceeds 100 columns
#43774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28489:
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28490:
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28491:
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28492:
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L

WARNING: line length of 113 exceeds 100 columns
#43778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28493:
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#43779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28494:
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#43780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28495:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#43781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28496:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#43782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28497:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#43783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28498:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#43784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28499:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc

WARNING: line length of 114 exceeds 100 columns
#43785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28500:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#43786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28501:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#43787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28502:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28503:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28504:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#43790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28505:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28506:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28507:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#43793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28508:
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#43794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28509:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#43795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28510:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#43796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28511:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#43797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28512:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#43798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28513:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#43799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28514:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#43800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28515:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#43801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28516:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#43802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28517:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28518:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28519:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28520:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28521:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28522:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28523:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#43809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28524:
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#43810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28525:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#43811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28526:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#43812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28527:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#43813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28528:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9

WARNING: line length of 121 exceeds 100 columns
#43814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28529:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28530:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28531:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28532:
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L

WARNING: line length of 113 exceeds 100 columns
#43818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28533:
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#43819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28534:
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#43820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28535:
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#43821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28536:
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L

WARNING: line length of 113 exceeds 100 columns
#43822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28537:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#43823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28538:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#43824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28539:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#43825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28540:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#43826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28541:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#43827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28542:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#43828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28543:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#43829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28544:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#43830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28545:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#43831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28546:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#43832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28547:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#43833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28548:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb

WARNING: line length of 113 exceeds 100 columns
#43834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28549:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#43835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28550:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#43836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28551:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#43837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28552:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf

WARNING: line length of 114 exceeds 100 columns
#43838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28553:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#43839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28554:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#43840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28555:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#43841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28556:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13

WARNING: line length of 114 exceeds 100 columns
#43842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28557:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#43843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28558:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15

WARNING: line length of 114 exceeds 100 columns
#43844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28559:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#43845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28560:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17

WARNING: line length of 114 exceeds 100 columns
#43846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28561:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#43847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28562:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#43848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28563:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a

WARNING: line length of 114 exceeds 100 columns
#43849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28564:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b

WARNING: line length of 114 exceeds 100 columns
#43850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28565:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#43851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28566:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d

WARNING: line length of 114 exceeds 100 columns
#43852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28567:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e

WARNING: line length of 114 exceeds 100 columns
#43853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28568:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f

WARNING: line length of 121 exceeds 100 columns
#43854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28569:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28570:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28571:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28572:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28573:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28574:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28575:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28576:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28577:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28578:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28579:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#43865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28580:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#43866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28581:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28582:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28583:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28584:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28585:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28586:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28587:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28588:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28589:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28590:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28591:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#43877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28592:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28593:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28594:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28595:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28596:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#43882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28597:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#43883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28598:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L

WARNING: line length of 121 exceeds 100 columns
#43884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28599:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#43885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28600:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#43886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28601:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#43887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28602:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#43888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28603:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#43889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28604:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#43890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28605:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#43891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28606:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#43892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28607:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#43893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28608:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#43894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28609:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#43895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28610:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9

WARNING: line length of 113 exceeds 100 columns
#43896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28611:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#43897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28612:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb

WARNING: line length of 113 exceeds 100 columns
#43898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28613:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#43899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28614:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#43900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28615:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe

WARNING: line length of 113 exceeds 100 columns
#43901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28616:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf

WARNING: line length of 114 exceeds 100 columns
#43902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28617:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#43903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28618:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#43904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28619:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#43905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28620:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#43906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28621:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#43907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28622:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#43908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28623:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#43909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28624:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17

WARNING: line length of 114 exceeds 100 columns
#43910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28625:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#43911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28626:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19

WARNING: line length of 114 exceeds 100 columns
#43912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28627:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#43913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28628:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b

WARNING: line length of 121 exceeds 100 columns
#43914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28629:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28630:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28631:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28632:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28633:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28634:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28635:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28636:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28637:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28638:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28639:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#43925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28640:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L

WARNING: line length of 121 exceeds 100 columns
#43926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28641:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28642:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28643:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28644:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28645:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28646:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28647:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28648:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28649:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28650:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28651:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#43937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28652:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28653:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28654:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28655:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28656:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L

WARNING: line length of 113 exceeds 100 columns
#43942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28657:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#43943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28658:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#43944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28659:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#43945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28660:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#43946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28661:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#43947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28662:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#43948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28663:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#43949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28664:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7

WARNING: line length of 113 exceeds 100 columns
#43950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28665:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#43951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28666:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9

WARNING: line length of 113 exceeds 100 columns
#43952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28667:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#43953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28668:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb

WARNING: line length of 113 exceeds 100 columns
#43954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28669:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#43955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28670:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd

WARNING: line length of 113 exceeds 100 columns
#43956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28671:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#43957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28672:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf

WARNING: line length of 114 exceeds 100 columns
#43958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28673:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#43959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28674:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#43960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28675:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#43961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28676:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13

WARNING: line length of 114 exceeds 100 columns
#43962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28677:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#43963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28678:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15

WARNING: line length of 114 exceeds 100 columns
#43964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28679:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#43965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28680:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17

WARNING: line length of 114 exceeds 100 columns
#43966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28681:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18

WARNING: line length of 114 exceeds 100 columns
#43967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28682:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19

WARNING: line length of 114 exceeds 100 columns
#43968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28683:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#43969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28684:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b

WARNING: line length of 114 exceeds 100 columns
#43970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28685:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#43971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28686:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d

WARNING: line length of 121 exceeds 100 columns
#43972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28687:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#43973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28688:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#43974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28689:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#43975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28690:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#43976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28691:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#43977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28692:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#43978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28693:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#43979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28694:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#43980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28695:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#43981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28696:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#43982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28697:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#43983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28698:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#43984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28699:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#43985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28700:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#43986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28701:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#43987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28702:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#43988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28703:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#43989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28704:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#43990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28705:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#43991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28706:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#43992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28707:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#43993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28708:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#43994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28709:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#43995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28710:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L

WARNING: line length of 121 exceeds 100 columns
#43996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28711:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#43997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28712:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#43998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28713:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#43999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28714:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#44000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28715:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#44001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28716:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L

WARNING: line length of 113 exceeds 100 columns
#44002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28717:
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#44003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28718:
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#44004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28719:
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#44005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28720:
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8

WARNING: line length of 113 exceeds 100 columns
#44006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28721:
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc

WARNING: line length of 121 exceeds 100 columns
#44007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28722:
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28723:
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28724:
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28725:
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#44011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28726:
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L

WARNING: line length of 113 exceeds 100 columns
#44012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28727:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#44013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28728:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#44014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28729:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28730:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28731:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#44017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28732:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#44018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28733:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28734:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28735:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#44021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28736:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#44022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28737:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28738:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28739:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#44025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28740:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#44026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28741:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28742:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28743:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#44029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28744:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#44030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28745:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28746:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28747:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#44033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28748:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28749:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28750:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28751:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#44037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28752:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28753:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28754:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28755:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#44041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28756:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#44042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28757:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#44043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28758:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#44044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28759:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#44045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28760:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14

WARNING: line length of 114 exceeds 100 columns
#44046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28761:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#44047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28762:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#44048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28763:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17

WARNING: line length of 114 exceeds 100 columns
#44049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28764:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18

WARNING: line length of 114 exceeds 100 columns
#44050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28765:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19

WARNING: line length of 114 exceeds 100 columns
#44051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28766:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#44052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28767:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b

WARNING: line length of 114 exceeds 100 columns
#44053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28768:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#44054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28769:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d

WARNING: line length of 114 exceeds 100 columns
#44055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28770:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e

WARNING: line length of 121 exceeds 100 columns
#44056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28771:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28772:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28773:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#44059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28774:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#44060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28775:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#44061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28776:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#44062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28777:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#44063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28778:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#44064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28779:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#44065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28780:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#44066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28781:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L

WARNING: line length of 121 exceeds 100 columns
#44067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28782:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#44068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28783:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L

WARNING: line length of 121 exceeds 100 columns
#44069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28784:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#44070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28785:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#44071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28786:
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L

WARNING: line length of 113 exceeds 100 columns
#44072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28787:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#44073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28788:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#44074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28789:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#44075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28790:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#44076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28791:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#44077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28792:
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf

WARNING: line length of 114 exceeds 100 columns
#44078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28793:
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#44079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28794:
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#44080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28795:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28796:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28797:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28798:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28799:
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28800:
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#44086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28801:
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28802:
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#44088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28803:
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#44089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28804:
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#44090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28805:
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#44091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28806:
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#44092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28807:
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#44093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28808:
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#44094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28809:
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#44095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28810:
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#44096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28811:
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#44097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28812:
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#44098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28813:
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#44099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28814:
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#44100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28815:
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc

WARNING: line length of 121 exceeds 100 columns
#44101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28816:
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#44102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28817:
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#44103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28818:
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#44104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28819:
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#44105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28820:
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8

WARNING: line length of 121 exceeds 100 columns
#44106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28821:
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28822:
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#44108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28823:
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#44109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28824:
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#44110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28825:
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#44111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28826:
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#44112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28827:
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#44113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28828:
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28829:
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28830:
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28831:
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#44117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28832:
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#44118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28833:
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#44119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28834:
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#44120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28835:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#44121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28836:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#44122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28837:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#44123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28838:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3

WARNING: line length of 121 exceeds 100 columns
#44124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28839:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28840:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28841:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28842:
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L

WARNING: line length of 113 exceeds 100 columns
#44128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28843:
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#44129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28844:
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8

WARNING: line length of 121 exceeds 100 columns
#44130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28845:
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#44131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28846:
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#44132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28847:
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#44133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28848:
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#44134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28849:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#44135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28850:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#44136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28851:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28852:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#44138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28853:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#44139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28854:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#44140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28855:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28856:
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#44142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28857:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#44143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28858:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#44144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28859:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#44145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28860:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#44146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28861:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28862:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28863:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28864:
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L

WARNING: line length of 113 exceeds 100 columns
#44150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28865:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#44151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28866:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#44152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28867:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#44153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28868:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#44154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28869:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18

WARNING: line length of 121 exceeds 100 columns
#44155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28870:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28871:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#44157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28872:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28873:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#44159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28874:
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L

WARNING: line length of 113 exceeds 100 columns
#44160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28875:
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#44161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28876:
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#44162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28877:
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28878:
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#44164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28879:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#44165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28880:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#44166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28881:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#44167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28882:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#44168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28883:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#44169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28884:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#44170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28885:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#44171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28886:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#44172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28887:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#44173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28888:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#44174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28889:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#44175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28890:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#44176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28891:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#44177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28892:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#44178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28893:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#44179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28894:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#44180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28895:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#44181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28896:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28897:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#44183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28898:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#44184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28899:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#44185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28900:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28901:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#44187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28902:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#44188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28903:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#44189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28904:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#44190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28905:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#44191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28906:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#44192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28907:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#44193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28908:
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#44194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28909:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#44195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28910:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#44196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28911:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#44197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28912:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#44198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28913:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#44199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28914:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#44200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28915:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#44201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28916:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#44202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28917:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#44203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28918:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#44204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28919:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#44205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28920:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#44206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28921:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#44207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28922:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#44208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28923:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#44209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28924:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#44210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28925:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28926:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#44212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28927:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#44213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28928:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#44214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28929:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28930:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#44216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28931:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#44217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28932:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#44218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28933:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#44219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28934:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#44220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28935:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#44221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28936:
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 113 exceeds 100 columns
#44222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28937:
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#44223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28938:
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#44224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28939:
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#44225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28940:
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8

WARNING: line length of 121 exceeds 100 columns
#44226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28941:
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28942:
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L

WARNING: line length of 113 exceeds 100 columns
#44228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28943:
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#44229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28944:
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#44230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28945:
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e

WARNING: line length of 121 exceeds 100 columns
#44231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28946:
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28947:
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L

WARNING: line length of 121 exceeds 100 columns
#44233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28948:
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L

WARNING: line length of 114 exceeds 100 columns
#44234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28949:
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#44235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28950:
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#44236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28951:
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#44237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28952:
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#44238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28953:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#44239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28954:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#44240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28955:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#44241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28956:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14

WARNING: line length of 121 exceeds 100 columns
#44242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28957:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28958:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L

WARNING: line length of 121 exceeds 100 columns
#44244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28959:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28960:
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L

WARNING: line length of 113 exceeds 100 columns
#44246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28961:
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#44247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28962:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#44248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28963:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#44249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28964:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#44250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28965:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7

WARNING: line length of 113 exceeds 100 columns
#44251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28966:
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#44252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28967:
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#44253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28968:
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#44254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28969:
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28970:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28971:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28972:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28973:
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28974:
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28975:
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28976:
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#44262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28977:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#44263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28978:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#44264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28979:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#44265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28980:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#44266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28981:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#44267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28982:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#44268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28983:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#44269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28984:
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#44270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28985:
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#44271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28986:
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#44272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28987:
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28988:
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#44274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28989:
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#44275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28990:
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#44276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28991:
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa

WARNING: line length of 113 exceeds 100 columns
#44277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28992:
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#44278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28993:
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18

WARNING: line length of 121 exceeds 100 columns
#44279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28994:
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28995:
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28996:
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#44282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28997:
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#44283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28998:
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#44284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:28999:
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#44285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29000:
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#44286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29001:
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#44287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29002:
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#44288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29003:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#44289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29004:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#44290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29005:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#44291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29006:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#44292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29007:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#44293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29008:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#44294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29009:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#44295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29010:
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#44296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29011:
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#44297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29012:
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#44298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29013:
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#44299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29014:
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#44300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29015:
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#44301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29016:
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L

WARNING: line length of 113 exceeds 100 columns
#44302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29017:
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#44303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29018:
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#44304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29019:
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#44305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29020:
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29021:
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29022:
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#44308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29023:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#44309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29024:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#44310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29025:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2

WARNING: line length of 113 exceeds 100 columns
#44311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29026:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#44312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29027:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#44313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29028:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#44314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29029:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#44315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29030:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#44316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29031:
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#44317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29032:
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#44318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29033:
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18

WARNING: line length of 121 exceeds 100 columns
#44319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29034:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29035:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29036:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29037:
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#44323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29038:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29039:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29040:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29041:
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29042:
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29043:
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29044:
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L

WARNING: line length of 113 exceeds 100 columns
#44330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29045:
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#44331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29046:
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#44332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29047:
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#44333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29048:
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#44334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29049:
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#44335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29050:
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29051:
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#44337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29052:
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#44338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29053:
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#44339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29054:
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#44340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29055:
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#44341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29056:
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29057:
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#44343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29058:
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#44344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29059:
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#44345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29060:
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa

WARNING: line length of 121 exceeds 100 columns
#44346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29061:
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29062:
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L

WARNING: line length of 113 exceeds 100 columns
#44348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29063:
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#44349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29064:
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#44350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29065:
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#44351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29066:
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29067:
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29068:
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L

WARNING: line length of 113 exceeds 100 columns
#44354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29069:
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#44355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29070:
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#44356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29071:
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#44357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29072:
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29073:
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L

WARNING: line length of 121 exceeds 100 columns
#44359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29074:
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L

WARNING: line length of 113 exceeds 100 columns
#44360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29075:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#44361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29076:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#44362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29077:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#44363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29078:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#44364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29079:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29080:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29081:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L

WARNING: line length of 121 exceeds 100 columns
#44367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29082:
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#44368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29083:
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#44369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29084:
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#44370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29085:
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#44371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29086:
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29087:
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29088:
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#44374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29089:
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#44375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29090:
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4

WARNING: line length of 114 exceeds 100 columns
#44376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29091:
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#44377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29092:
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29093:
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L

WARNING: line length of 121 exceeds 100 columns
#44379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29094:
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#44380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29095:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#44381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29096:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#44382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29097:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#44383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29098:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#44384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29099:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#44385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29100:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#44386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29101:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#44387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29102:
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#44388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29103:
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#44389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29104:
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#44390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29105:
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#44391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29106:
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#44392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29107:
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#44393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29108:
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#44394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29109:
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#44395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29110:
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29111:
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29112:
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L

WARNING: line length of 113 exceeds 100 columns
#44398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29113:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#44399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29114:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#44400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29115:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2

WARNING: line length of 113 exceeds 100 columns
#44401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29116:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#44402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29117:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#44403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29118:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14

WARNING: line length of 121 exceeds 100 columns
#44404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29119:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29120:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29121:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29122:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29123:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L

WARNING: line length of 121 exceeds 100 columns
#44409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29124:
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#44410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29125:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#44411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29126:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#44412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29127:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#44413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29128:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc

WARNING: line length of 121 exceeds 100 columns
#44414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29129:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29130:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29131:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29132:
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#44418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29133:
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#44419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29134:
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#44420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29135:
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#44421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29136:
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc

WARNING: line length of 114 exceeds 100 columns
#44422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29137:
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#44423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29138:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#44424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29139:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15

WARNING: line length of 114 exceeds 100 columns
#44425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29140:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16

WARNING: line length of 114 exceeds 100 columns
#44426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29141:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17

WARNING: line length of 114 exceeds 100 columns
#44427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29142:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18

WARNING: line length of 114 exceeds 100 columns
#44428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29143:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19

WARNING: line length of 114 exceeds 100 columns
#44429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29144:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#44430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29145:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b

WARNING: line length of 114 exceeds 100 columns
#44431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29146:
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#44432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29147:
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29148:
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29149:
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29150:
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29151:
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29152:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#44438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29153:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#44439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29154:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L

WARNING: line length of 121 exceeds 100 columns
#44440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29155:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L

WARNING: line length of 121 exceeds 100 columns
#44441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29156:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#44442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29157:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#44443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29158:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L

WARNING: line length of 121 exceeds 100 columns
#44444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29159:
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L

WARNING: line length of 121 exceeds 100 columns
#44445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29160:
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#44446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29161:
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#44447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29162:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#44448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29163:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#44449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29164:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5

WARNING: line length of 113 exceeds 100 columns
#44450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29165:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#44451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29166:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#44452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29167:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#44453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29168:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#44454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29169:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#44455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29170:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#44456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29171:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#44457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29172:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd

WARNING: line length of 113 exceeds 100 columns
#44458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29173:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe

WARNING: line length of 113 exceeds 100 columns
#44459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29174:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf

WARNING: line length of 114 exceeds 100 columns
#44460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29175:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29176:
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29177:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29178:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29179:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29180:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29181:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29182:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29183:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#44469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29184:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#44470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29185:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#44471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29186:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29187:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29188:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#44474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29189:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#44475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29190:
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29191:
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#44477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29192:
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#44478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29193:
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#44479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29194:
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29195:
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#44481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29196:
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#44482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29197:
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29198:
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29199:
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#44485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29200:
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#44486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29201:
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#44487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29202:
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29203:
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#44489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29204:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#44490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29205:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#44491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29206:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#44492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29207:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d

WARNING: line length of 121 exceeds 100 columns
#44493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29208:
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29209:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#44495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29210:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#44496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29211:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#44497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29212:
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L

WARNING: line length of 113 exceeds 100 columns
#44498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29213:
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#44499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29214:
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#44500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29215:
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#44501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29216:
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#44502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29217:
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#44503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29218:
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#44504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29219:
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#44505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29220:
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#44506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29221:
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#44507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29222:
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#44508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29223:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#44509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29224:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#44510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29225:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#44511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29226:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#44512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29227:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#44513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29228:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29229:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#44515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29230:
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#44516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29231:
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#44517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29232:
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a

WARNING: line length of 121 exceeds 100 columns
#44518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29233:
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#44519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29234:
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#44520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29235:
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#44521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29236:
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#44522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29237:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#44523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29238:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#44524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29239:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#44525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29240:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#44526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29241:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29242:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#44528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29243:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#44529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29244:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#44530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29245:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#44531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29246:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#44532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29247:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#44533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29248:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#44534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29249:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29250:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#44536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29251:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#44537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29252:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#44538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29253:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#44539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29254:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#44540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29255:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#44541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29256:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#44542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29257:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29258:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#44544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29259:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#44545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29260:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#44546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29261:
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#44547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29262:
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8

WARNING: line length of 121 exceeds 100 columns
#44548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29263:
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#44549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29264:
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#44550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29265:
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#44551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29266:
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#44552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29267:
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29268:
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L

WARNING: line length of 113 exceeds 100 columns
#44554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29269:
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#44555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29270:
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#44556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29271:
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#44557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29272:
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29273:
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29274:
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#44560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29275:
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#44561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29276:
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf

WARNING: line length of 114 exceeds 100 columns
#44562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29277:
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#44563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29278:
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#44564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29279:
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L

WARNING: line length of 121 exceeds 100 columns
#44565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29280:
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L

WARNING: line length of 113 exceeds 100 columns
#44566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29281:
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#44567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29282:
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L

WARNING: line length of 113 exceeds 100 columns
#44568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29283:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#44569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29284:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#44570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29285:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#44571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29286:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#44572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29287:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29288:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#44574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29289:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#44575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29290:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#44576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29291:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#44577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29292:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#44578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29293:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#44579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29294:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#44580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29295:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29296:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#44582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29297:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#44583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29298:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#44584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29299:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#44585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29300:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#44586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29301:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#44587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29302:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#44588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29303:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#44589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29304:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#44590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29305:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#44591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29306:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#44592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29307:
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#44593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29308:
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L

WARNING: line length of 113 exceeds 100 columns
#44594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29309:
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#44595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29310:
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#44596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29311:
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29312:
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29313:
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#44599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29314:
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#44600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29315:
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29316:
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29317:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#44603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29318:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#44604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29319:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#44605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29320:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#44606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29321:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#44607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29322:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#44608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29323:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#44609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29324:
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#44610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29325:
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#44611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29326:
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#44612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29327:
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29328:
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29329:
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#44615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29330:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#44616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29331:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#44617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29332:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc

WARNING: line length of 114 exceeds 100 columns
#44618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29333:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#44619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29334:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#44620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29335:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#44621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29336:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#44622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29337:
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#44623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29338:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#44624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29339:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#44625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29340:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#44626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29341:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#44627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29342:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#44628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29343:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#44629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29344:
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#44630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29345:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#44631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29346:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#44632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29347:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#44633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29348:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc

WARNING: line length of 114 exceeds 100 columns
#44634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29349:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#44635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29350:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#44636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29351:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#44637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29352:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#44638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29353:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#44639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29354:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#44640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29355:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#44641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29356:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#44642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29357:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#44643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29358:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#44644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29359:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#44645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29360:
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#44646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29361:
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#44647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29362:
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L

WARNING: line length of 113 exceeds 100 columns
#44648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29363:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#44649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29364:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#44650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29365:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#44651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29366:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#44652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29367:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#44653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29368:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#44654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29369:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#44655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29370:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#44656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29371:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#44657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29372:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#44658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29373:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#44659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29374:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#44660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29375:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#44661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29376:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#44662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29377:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 113 exceeds 100 columns
#44663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29378:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf

WARNING: line length of 114 exceeds 100 columns
#44664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29379:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#44665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29380:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#44666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29381:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12

WARNING: line length of 114 exceeds 100 columns
#44667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29382:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#44668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29383:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#44669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29384:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#44670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29385:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16

WARNING: line length of 114 exceeds 100 columns
#44671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29386:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#44672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29387:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#44673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29388:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#44674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29389:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a

WARNING: line length of 114 exceeds 100 columns
#44675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29390:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b

WARNING: line length of 114 exceeds 100 columns
#44676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29391:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#44677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29392:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29393:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29394:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29395:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#44681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29396:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29397:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29398:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29399:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29400:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29401:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#44687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29402:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#44688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29403:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#44689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29404:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29405:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29406:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#44692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29407:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#44693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29408:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29409:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#44695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29410:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#44696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29411:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#44697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29412:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#44698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29413:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#44699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29414:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#44700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29415:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#44701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29416:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#44702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29417:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#44703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29418:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#44704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29419:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#44705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29420:
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#44706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29421:
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#44707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29422:
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29423:
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29424:
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29425:
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#44711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29426:
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29427:
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29428:
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29429:
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#44715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29430:
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29431:
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29432:
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29433:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#44719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29434:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#44720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29435:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#44721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29436:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12

WARNING: line length of 114 exceeds 100 columns
#44722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29437:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#44723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29438:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#44724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29439:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#44725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29440:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#44726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29441:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#44727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29442:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#44728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29443:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19

WARNING: line length of 114 exceeds 100 columns
#44729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29444:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#44730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29445:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b

WARNING: line length of 121 exceeds 100 columns
#44731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29446:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29447:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29448:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#44734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29449:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#44735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29450:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#44736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29451:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#44737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29452:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#44738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29453:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#44739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29454:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#44740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29455:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#44741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29456:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#44742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29457:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#44743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29458:
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L

WARNING: line length of 113 exceeds 100 columns
#44744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29459:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#44745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29460:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#44746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29461:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#44747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29462:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#44748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29463:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#44749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29464:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#44750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29465:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#44751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29466:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd

WARNING: line length of 114 exceeds 100 columns
#44752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29467:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#44753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29468:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#44754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29469:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14

WARNING: line length of 114 exceeds 100 columns
#44755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29470:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#44756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29471:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#44757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29472:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#44758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29473:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#44759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29474:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d

WARNING: line length of 121 exceeds 100 columns
#44760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29475:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29476:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29477:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29478:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29479:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29480:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#44766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29481:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29482:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29483:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29484:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#44770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29485:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#44771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29486:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#44772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29487:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#44773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29488:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#44774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29489:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#44775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29490:
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L

WARNING: line length of 113 exceeds 100 columns
#44776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29491:
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#44777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29492:
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#44778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29493:
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5

WARNING: line length of 113 exceeds 100 columns
#44779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29494:
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#44780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29495:
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#44781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29496:
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf

WARNING: line length of 114 exceeds 100 columns
#44782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29497:
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10

WARNING: line length of 114 exceeds 100 columns
#44783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29498:
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11

WARNING: line length of 121 exceeds 100 columns
#44784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29499:
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29500:
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29501:
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29502:
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29503:
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29504:
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#44790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29505:
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29506:
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L

WARNING: line length of 113 exceeds 100 columns
#44792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29507:
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#44793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29508:
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#44794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29509:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#44795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29510:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#44796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29511:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#44797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29512:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#44798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29513:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#44799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29514:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#44800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29515:
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#44801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29516:
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29517:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29518:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#44804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29519:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29520:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29521:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#44807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29522:
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29523:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#44809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29524:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#44810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29525:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4

WARNING: line length of 114 exceeds 100 columns
#44811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29526:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10

WARNING: line length of 121 exceeds 100 columns
#44812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29527:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29528:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29529:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#44815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29530:
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29531:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#44817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29532:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#44818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29533:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#44819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29534:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#44820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29535:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#44821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29536:
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#44822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29537:
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#44823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29538:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#44824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29539:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#44825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29540:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29541:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29542:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29543:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#44829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29544:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29545:
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29546:
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29547:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#44833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29548:
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29549:
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#44835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29550:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#44836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29551:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#44837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29552:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#44838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29553:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#44839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29554:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#44840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29555:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#44841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29556:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#44842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29557:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#44843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29558:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29559:
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#44845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29560:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29561:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29562:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29563:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29564:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29565:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29566:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29567:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#44853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29568:
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29569:
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#44855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29570:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#44856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29571:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#44857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29572:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#44858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29573:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#44859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29574:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#44860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29575:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#44861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29576:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#44862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29577:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#44863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29578:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#44864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29579:
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#44865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29580:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29581:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29582:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29583:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29584:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29585:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29586:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29587:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#44873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29588:
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29589:
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#44875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29590:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#44876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29591:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#44877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29592:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#44878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29593:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#44879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29594:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#44880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29595:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#44881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29596:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#44882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29597:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#44883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29598:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#44884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29599:
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#44885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29600:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29601:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29602:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29603:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29604:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29605:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29606:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29607:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#44893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29608:
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29609:
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#44895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29610:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#44896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29611:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#44897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29612:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#44898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29613:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#44899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29614:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#44900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29615:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#44901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29616:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#44902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29617:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#44903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29618:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#44904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29619:
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#44905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29620:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29621:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29622:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29623:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29624:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29625:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#44911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29626:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#44912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29627:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#44913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29628:
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29629:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#44915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29630:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#44916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29631:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#44917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29632:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#44918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29633:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#44919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29634:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#44920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29635:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#44921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29636:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#44922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29637:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#44923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29638:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#44924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29639:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#44925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29640:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb

WARNING: line length of 121 exceeds 100 columns
#44926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29641:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29642:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29643:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29644:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#44930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29645:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29646:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29647:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29648:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29649:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#44935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29650:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#44936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29651:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#44937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29652:
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L

WARNING: line length of 113 exceeds 100 columns
#44938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29653:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#44939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29654:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#44940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29655:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#44941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29656:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#44942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29657:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#44943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29658:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L

WARNING: line length of 121 exceeds 100 columns
#44944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29659:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L

WARNING: line length of 121 exceeds 100 columns
#44945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29660:
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#44946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29661:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#44947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29662:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7

WARNING: line length of 114 exceeds 100 columns
#44948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29663:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#44949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29664:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#44950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29665:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12

WARNING: line length of 114 exceeds 100 columns
#44951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29666:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13

WARNING: line length of 114 exceeds 100 columns
#44952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29667:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#44953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29668:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#44954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29669:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#44955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29670:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#44956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29671:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#44957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29672:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L

WARNING: line length of 121 exceeds 100 columns
#44958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29673:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#44959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29674:
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#44960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29675:
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#44961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29676:
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#44962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29677:
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#44963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29678:
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29679:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#44965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29680:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#44966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29681:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3

WARNING: line length of 113 exceeds 100 columns
#44967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29682:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#44968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29683:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#44969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29684:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6

WARNING: line length of 114 exceeds 100 columns
#44970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29685:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#44971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29686:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29687:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29688:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#44974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29689:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#44975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29690:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#44976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29691:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#44977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29692:
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#44978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29693:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#44979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29694:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#44980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29695:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#44981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29696:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#44982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29697:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8

WARNING: line length of 114 exceeds 100 columns
#44983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29698:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#44984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29699:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#44985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29700:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#44986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29701:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#44987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29702:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#44988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29703:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#44989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29704:
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#44990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29705:
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#44991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29706:
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#44992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29707:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#44993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29708:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#44994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29709:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#44995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29710:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#44996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29711:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#44997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29712:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#44998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29713:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#44999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29714:
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#45000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29715:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#45001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29716:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#45002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29717:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#45003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29718:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#45004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29719:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#45005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29720:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#45006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29721:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#45007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29722:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#45008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29723:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#45009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29724:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#45010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29725:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#45011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29726:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#45012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29727:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#45013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29728:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#45014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29729:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#45015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29730:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#45016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29731:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#45017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29732:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#45018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29733:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#45019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29734:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#45020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29735:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#45021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29736:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#45022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29737:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#45023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29738:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#45024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29739:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#45025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29740:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#45026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29741:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#45027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29742:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#45028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29743:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#45029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29744:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#45030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29745:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29746:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29747:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29748:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#45034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29749:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29750:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29751:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29752:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29753:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29754:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#45040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29755:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#45041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29756:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29757:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29758:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#45044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29759:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#45045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29760:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29761:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#45047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29762:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#45048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29763:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#45049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29764:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29765:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#45051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29766:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#45052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29767:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29768:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29769:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#45055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29770:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29771:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#45057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29772:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#45058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29773:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#45059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29774:
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#45060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29775:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#45061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29776:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#45062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29777:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#45063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29778:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#45064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29779:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#45065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29780:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#45066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29781:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#45067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29782:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#45068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29783:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#45069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29784:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#45070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29785:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#45071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29786:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#45072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29787:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#45073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29788:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#45074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29789:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#45075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29790:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#45076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29791:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#45077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29792:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#45078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29793:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#45079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29794:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#45080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29795:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#45081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29796:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#45082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29797:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#45083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29798:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#45084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29799:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#45085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29800:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#45086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29801:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#45087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29802:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#45088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29803:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#45089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29804:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#45090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29805:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29806:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29807:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29808:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#45094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29809:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29810:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29811:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29812:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29813:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29814:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#45100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29815:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#45101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29816:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29817:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29818:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#45104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29819:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#45105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29820:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29821:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#45107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29822:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#45108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29823:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#45109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29824:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29825:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#45111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29826:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#45112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29827:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29828:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29829:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#45115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29830:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29831:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#45117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29832:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#45118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29833:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#45119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29834:
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#45120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29835:
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#45121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29836:
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#45122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29837:
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#45123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29838:
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29839:
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29840:
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#45126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29841:
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#45127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29842:
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#45128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29843:
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#45129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29844:
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29845:
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29846:
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#45132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29847:
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#45133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29848:
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#45134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29849:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#45135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29850:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#45136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29851:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#45137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29852:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#45138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29853:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#45139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29854:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#45140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29855:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#45141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29856:
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#45142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29857:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#45143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29858:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#45144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29859:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#45145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29860:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#45146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29861:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#45147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29862:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#45148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29863:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#45149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29864:
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#45150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29865:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#45151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29866:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#45152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29867:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#45153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29868:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#45154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29869:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#45155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29870:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#45156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29871:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29872:
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#45158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29873:
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd

WARNING: line length of 114 exceeds 100 columns
#45159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29874:
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#45160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29875:
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#45161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29876:
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#45162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29877:
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#45163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29878:
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L

WARNING: line length of 113 exceeds 100 columns
#45164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29879:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#45165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29880:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#45166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29881:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#45167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29882:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#45168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29883:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#45169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29884:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#45170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29885:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29886:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29887:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#45173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29888:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#45174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29889:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29890:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L

WARNING: line length of 113 exceeds 100 columns
#45176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29891:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#45177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29892:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#45178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29893:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb

WARNING: line length of 114 exceeds 100 columns
#45179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29894:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#45180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29895:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#45181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29896:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#45182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29897:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L

WARNING: line length of 121 exceeds 100 columns
#45183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29898:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L

WARNING: line length of 121 exceeds 100 columns
#45184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29899:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#45185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29900:
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#45186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29901:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#45187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29902:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#45188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29903:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#45189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29904:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#45190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29905:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#45191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29906:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L

WARNING: line length of 121 exceeds 100 columns
#45192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29907:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#45193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29908:
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L

WARNING: line length of 113 exceeds 100 columns
#45194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29909:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#45195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29910:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#45196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29911:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#45197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29912:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#45198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29913:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6

WARNING: line length of 113 exceeds 100 columns
#45199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29914:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#45200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29915:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#45201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29916:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#45202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29917:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#45203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29918:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#45204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29919:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29920:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29921:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29922:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L

WARNING: line length of 121 exceeds 100 columns
#45208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29923:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#45209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29924:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#45210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29925:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#45211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29926:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#45212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29927:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#45213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29928:
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#45214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29929:
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#45215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29930:
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4

WARNING: line length of 114 exceeds 100 columns
#45216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29931:
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#45217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29932:
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#45218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29933:
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#45219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29934:
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#45220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29935:
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#45221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29936:
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29937:
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#45223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29938:
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#45224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29939:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#45225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29940:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#45226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29941:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#45227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29942:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#45228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29943:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#45229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29944:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29945:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29946:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29947:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#45233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29948:
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29949:
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#45235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29950:
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#45236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29951:
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#45237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29952:
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#45238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29953:
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#45239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29954:
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#45240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29955:
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#45241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29956:
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#45242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29957:
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#45243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29958:
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#45244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29959:
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#45245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29960:
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#45246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29961:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#45247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29962:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#45248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29963:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#45249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29964:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc

WARNING: line length of 114 exceeds 100 columns
#45250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29965:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#45251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29966:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#45252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29967:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#45253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29968:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#45254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29969:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#45255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29970:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#45256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29971:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#45257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29972:
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#45258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29973:
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#45259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29974:
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8

WARNING: line length of 121 exceeds 100 columns
#45260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29975:
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29976:
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#45262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29977:
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#45263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29978:
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#45264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29979:
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#45265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29980:
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#45266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29981:
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29982:
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29983:
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29984:
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#45270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29985:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#45271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29986:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4

WARNING: line length of 113 exceeds 100 columns
#45272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29987:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb

WARNING: line length of 113 exceeds 100 columns
#45273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29988:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#45274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29989:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#45275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29990:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17

WARNING: line length of 114 exceeds 100 columns
#45276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29991:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18

WARNING: line length of 114 exceeds 100 columns
#45277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29992:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#45278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29993:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e

WARNING: line length of 121 exceeds 100 columns
#45279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29994:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29995:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29996:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29997:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29998:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#45284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:29999:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30000:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30001:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30002:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L

WARNING: line length of 113 exceeds 100 columns
#45288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30003:
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#45289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30004:
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7

WARNING: line length of 121 exceeds 100 columns
#45290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30005:
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30006:
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L

WARNING: line length of 113 exceeds 100 columns
#45292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30007:
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#45293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30008:
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L

WARNING: line length of 113 exceeds 100 columns
#45294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30009:
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#45295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30010:
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#45296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30011:
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#45297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30012:
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30013:
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#45299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30014:
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L

WARNING: line length of 113 exceeds 100 columns
#45300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30015:
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#45301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30016:
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#45302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30017:
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#45303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30018:
+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#45304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30019:
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#45305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30020:
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#45306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30021:
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#45307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30022:
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#45308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30023:
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#45309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30024:
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#45310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30025:
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30026:
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30027:
+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30028:
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#45314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30029:
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30030:
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30031:
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30032:
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#45318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30033:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#45319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30034:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#45320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30035:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#45321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30036:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#45322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30037:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#45323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30038:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30039:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#45325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30040:
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#45326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30041:
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#45327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30042:
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#45328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30043:
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#45329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30044:
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#45330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30045:
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf

WARNING: line length of 114 exceeds 100 columns
#45331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30046:
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#45332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30047:
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14

WARNING: line length of 121 exceeds 100 columns
#45333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30048:
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#45334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30049:
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#45335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30050:
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30051:
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#45337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30052:
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#45338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30053:
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#45339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30054:
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L

WARNING: line length of 113 exceeds 100 columns
#45340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30055:
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#45341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30056:
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#45342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30057:
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#45343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30058:
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30059:
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30060:
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L

WARNING: line length of 113 exceeds 100 columns
#45346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30061:
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#45347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30062:
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#45348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30063:
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#45349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30064:
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#45350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30065:
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#45351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30066:
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#45352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30067:
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#45353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30068:
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#45354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30069:
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6

WARNING: line length of 114 exceeds 100 columns
#45355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30070:
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#45356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30071:
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30072:
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30073:
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30074:
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30075:
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30076:
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#45362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30077:
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#45363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30078:
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#45364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30079:
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#45365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30080:
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#45366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30081:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#45367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30082:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#45368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30083:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#45369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30084:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#45370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30085:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#45371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30086:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#45372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30087:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#45373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30088:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30089:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30090:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#45376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30091:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30092:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30093:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30094:
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L

WARNING: line length of 113 exceeds 100 columns
#45380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30095:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#45381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30096:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#45382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30097:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#45383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30098:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#45384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30099:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#45385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30100:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e

WARNING: line length of 114 exceeds 100 columns
#45386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30101:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#45387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30102:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30103:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL

WARNING: line length of 121 exceeds 100 columns
#45389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30104:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#45390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30105:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L

WARNING: line length of 121 exceeds 100 columns
#45391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30106:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#45392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30107:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L

WARNING: line length of 121 exceeds 100 columns
#45393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30108:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#45394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30109:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#45395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30110:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#45396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30111:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#45397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30112:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#45398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30113:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30114:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30115:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30116:
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30117:
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#45403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30118:
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#45404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30119:
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2

WARNING: line length of 113 exceeds 100 columns
#45405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30120:
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#45406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30121:
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#45407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30122:
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#45408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30123:
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9

WARNING: line length of 114 exceeds 100 columns
#45409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30124:
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#45410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30125:
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#45411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30126:
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#45412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30127:
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30128:
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30129:
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30130:
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#45416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30131:
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30132:
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30133:
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#45419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30134:
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#45420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30135:
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30136:
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L

WARNING: line length of 113 exceeds 100 columns
#45422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30137:
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#45423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30138:
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#45424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30139:
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#45425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30140:
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b

WARNING: line length of 121 exceeds 100 columns
#45426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30141:
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30142:
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30143:
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30144:
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L

WARNING: line length of 113 exceeds 100 columns
#45430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30145:
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#45431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30146:
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#45432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30147:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#45433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30148:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#45434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30149:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#45435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30150:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#45436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30151:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc

WARNING: line length of 114 exceeds 100 columns
#45437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30152:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#45438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30153:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#45439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30154:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30155:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30156:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#45442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30157:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30158:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30159:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#45445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30160:
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#45446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30161:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#45447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30162:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#45448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30163:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#45449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30164:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#45450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30165:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#45451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30166:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#45452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30167:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#45453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30168:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#45454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30169:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30170:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30171:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30172:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30173:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#45459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30174:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30175:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#45461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30176:
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#45462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30177:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#45463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30178:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#45464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30179:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#45465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30180:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9

WARNING: line length of 121 exceeds 100 columns
#45466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30181:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30182:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30183:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30184:
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L

WARNING: line length of 113 exceeds 100 columns
#45470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30185:
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#45471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30186:
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#45472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30187:
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#45473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30188:
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L

WARNING: line length of 113 exceeds 100 columns
#45474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30189:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#45475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30190:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#45476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30191:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#45477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30192:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#45478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30193:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#45479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30194:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#45480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30195:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#45481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30196:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#45482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30197:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#45483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30198:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#45484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30199:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#45485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30200:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb

WARNING: line length of 113 exceeds 100 columns
#45486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30201:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#45487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30202:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#45488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30203:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#45489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30204:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf

WARNING: line length of 114 exceeds 100 columns
#45490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30205:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#45491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30206:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#45492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30207:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#45493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30208:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13

WARNING: line length of 114 exceeds 100 columns
#45494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30209:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#45495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30210:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15

WARNING: line length of 114 exceeds 100 columns
#45496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30211:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#45497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30212:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17

WARNING: line length of 114 exceeds 100 columns
#45498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30213:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#45499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30214:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#45500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30215:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a

WARNING: line length of 114 exceeds 100 columns
#45501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30216:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b

WARNING: line length of 114 exceeds 100 columns
#45502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30217:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#45503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30218:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d

WARNING: line length of 114 exceeds 100 columns
#45504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30219:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e

WARNING: line length of 114 exceeds 100 columns
#45505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30220:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f

WARNING: line length of 121 exceeds 100 columns
#45506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30221:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30222:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30223:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30224:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#45510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30225:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30226:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30227:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30228:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30229:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30230:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#45516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30231:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#45517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30232:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30233:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30234:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#45520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30235:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#45521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30236:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#45522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30237:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30238:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#45524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30239:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#45525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30240:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L

WARNING: line length of 121 exceeds 100 columns
#45526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30241:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30242:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#45528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30243:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#45529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30244:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30245:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30246:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#45532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30247:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30248:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#45534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30249:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#45535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30250:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L

WARNING: line length of 121 exceeds 100 columns
#45536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30251:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#45537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30252:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#45538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30253:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#45539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30254:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#45540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30255:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#45541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30256:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#45542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30257:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#45543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30258:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#45544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30259:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#45545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30260:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#45546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30261:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#45547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30262:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9

WARNING: line length of 113 exceeds 100 columns
#45548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30263:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#45549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30264:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb

WARNING: line length of 113 exceeds 100 columns
#45550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30265:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#45551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30266:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#45552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30267:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe

WARNING: line length of 113 exceeds 100 columns
#45553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30268:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf

WARNING: line length of 114 exceeds 100 columns
#45554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30269:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#45555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30270:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#45556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30271:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#45557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30272:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#45558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30273:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#45559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30274:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#45560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30275:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#45561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30276:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17

WARNING: line length of 114 exceeds 100 columns
#45562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30277:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#45563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30278:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19

WARNING: line length of 114 exceeds 100 columns
#45564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30279:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#45565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30280:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b

WARNING: line length of 121 exceeds 100 columns
#45566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30281:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30282:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30283:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30284:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#45570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30285:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30286:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30287:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30288:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30289:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30290:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#45576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30291:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#45577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30292:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30293:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30294:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#45580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30295:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#45581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30296:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#45582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30297:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30298:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#45584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30299:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#45585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30300:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#45586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30301:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30302:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L

WARNING: line length of 121 exceeds 100 columns
#45588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30303:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#45589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30304:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30305:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30306:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L

WARNING: line length of 121 exceeds 100 columns
#45592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30307:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30308:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L

WARNING: line length of 113 exceeds 100 columns
#45594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30309:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#45595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30310:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#45596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30311:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#45597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30312:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#45598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30313:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#45599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30314:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#45600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30315:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#45601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30316:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7

WARNING: line length of 113 exceeds 100 columns
#45602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30317:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#45603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30318:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9

WARNING: line length of 113 exceeds 100 columns
#45604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30319:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#45605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30320:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb

WARNING: line length of 113 exceeds 100 columns
#45606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30321:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#45607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30322:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd

WARNING: line length of 113 exceeds 100 columns
#45608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30323:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#45609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30324:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf

WARNING: line length of 114 exceeds 100 columns
#45610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30325:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#45611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30326:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#45612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30327:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#45613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30328:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13

WARNING: line length of 114 exceeds 100 columns
#45614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30329:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#45615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30330:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15

WARNING: line length of 114 exceeds 100 columns
#45616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30331:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#45617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30332:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17

WARNING: line length of 114 exceeds 100 columns
#45618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30333:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18

WARNING: line length of 114 exceeds 100 columns
#45619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30334:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19

WARNING: line length of 114 exceeds 100 columns
#45620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30335:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#45621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30336:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b

WARNING: line length of 114 exceeds 100 columns
#45622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30337:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#45623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30338:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d

WARNING: line length of 121 exceeds 100 columns
#45624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30339:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30340:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30341:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30342:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#45628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30343:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30344:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30345:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30346:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30347:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30348:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#45634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30349:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#45635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30350:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30351:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30352:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#45638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30353:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#45639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30354:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#45640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30355:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30356:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#45642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30357:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#45643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30358:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#45644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30359:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30360:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#45646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30361:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#45647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30362:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30363:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30364:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#45650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30365:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30366:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#45652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30367:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#45653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30368:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L

WARNING: line length of 113 exceeds 100 columns
#45654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30369:
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#45655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30370:
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#45656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30371:
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#45657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30372:
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8

WARNING: line length of 113 exceeds 100 columns
#45658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30373:
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc

WARNING: line length of 121 exceeds 100 columns
#45659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30374:
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30375:
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30376:
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30377:
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#45663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30378:
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L

WARNING: line length of 113 exceeds 100 columns
#45664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30379:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#45665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30380:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#45666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30381:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30382:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30383:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#45669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30384:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#45670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30385:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30386:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30387:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#45673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30388:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#45674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30389:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30390:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30391:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#45677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30392:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#45678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30393:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30394:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30395:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#45681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30396:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#45682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30397:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30398:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30399:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#45685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30400:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#45686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30401:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30402:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30403:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#45689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30404:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#45690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30405:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30406:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#45692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30407:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#45693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30408:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#45694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30409:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#45695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30410:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#45696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30411:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#45697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30412:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14

WARNING: line length of 114 exceeds 100 columns
#45698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30413:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#45699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30414:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#45700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30415:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17

WARNING: line length of 114 exceeds 100 columns
#45701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30416:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18

WARNING: line length of 114 exceeds 100 columns
#45702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30417:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19

WARNING: line length of 114 exceeds 100 columns
#45703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30418:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#45704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30419:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b

WARNING: line length of 114 exceeds 100 columns
#45705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30420:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#45706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30421:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d

WARNING: line length of 114 exceeds 100 columns
#45707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30422:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e

WARNING: line length of 121 exceeds 100 columns
#45708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30423:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#45709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30424:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30425:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#45711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30426:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#45712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30427:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#45713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30428:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30429:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#45715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30430:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#45716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30431:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30432:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30433:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L

WARNING: line length of 121 exceeds 100 columns
#45719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30434:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30435:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L

WARNING: line length of 121 exceeds 100 columns
#45721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30436:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#45722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30437:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#45723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30438:
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L

WARNING: line length of 113 exceeds 100 columns
#45724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30439:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#45725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30440:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#45726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30441:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#45727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30442:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#45728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30443:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#45729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30444:
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf

WARNING: line length of 114 exceeds 100 columns
#45730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30445:
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#45731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30446:
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#45732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30447:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30448:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30449:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30450:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30451:
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30452:
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#45738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30453:
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30454:
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#45740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30455:
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#45741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30456:
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#45742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30457:
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#45743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30458:
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#45744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30459:
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#45745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30460:
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#45746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30461:
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#45747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30462:
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#45748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30463:
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#45749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30464:
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#45750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30465:
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#45751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30466:
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#45752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30467:
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc

WARNING: line length of 121 exceeds 100 columns
#45753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30468:
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#45754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30469:
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#45755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30470:
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#45756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30471:
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#45757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30472:
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8

WARNING: line length of 121 exceeds 100 columns
#45758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30473:
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30474:
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#45760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30475:
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#45761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30476:
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#45762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30477:
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#45763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30478:
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#45764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30479:
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#45765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30480:
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30481:
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30482:
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30483:
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#45769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30484:
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#45770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30485:
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#45771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30486:
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#45772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30487:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#45773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30488:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#45774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30489:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#45775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30490:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3

WARNING: line length of 121 exceeds 100 columns
#45776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30491:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30492:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30493:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30494:
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L

WARNING: line length of 113 exceeds 100 columns
#45780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30495:
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#45781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30496:
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8

WARNING: line length of 121 exceeds 100 columns
#45782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30497:
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#45783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30498:
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#45784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30499:
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#45785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30500:
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#45786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30501:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#45787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30502:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#45788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30503:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#45789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30504:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#45790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30505:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#45791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30506:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#45792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30507:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#45793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30508:
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#45794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30509:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#45795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30510:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#45796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30511:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#45797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30512:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#45798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30513:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30514:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30515:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30516:
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L

WARNING: line length of 113 exceeds 100 columns
#45802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30517:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#45803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30518:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#45804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30519:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#45805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30520:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#45806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30521:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18

WARNING: line length of 121 exceeds 100 columns
#45807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30522:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30523:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#45809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30524:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30525:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#45811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30526:
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L

WARNING: line length of 113 exceeds 100 columns
#45812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30527:
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#45813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30528:
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#45814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30529:
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#45815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30530:
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#45816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30531:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#45817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30532:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#45818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30533:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#45819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30534:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#45820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30535:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#45821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30536:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#45822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30537:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#45823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30538:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#45824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30539:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#45825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30540:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#45826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30541:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#45827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30542:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#45828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30543:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#45829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30544:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#45830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30545:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#45831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30546:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#45832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30547:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#45833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30548:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30549:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#45835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30550:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#45836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30551:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30552:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30553:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#45839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30554:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#45840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30555:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30556:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#45842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30557:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30558:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#45844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30559:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#45845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30560:
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#45846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30561:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#45847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30562:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#45848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30563:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#45849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30564:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#45850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30565:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#45851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30566:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#45852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30567:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#45853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30568:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#45854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30569:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#45855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30570:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#45856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30571:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#45857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30572:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#45858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30573:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#45859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30574:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#45860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30575:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#45861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30576:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#45862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30577:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30578:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#45864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30579:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#45865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30580:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#45866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30581:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30582:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#45868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30583:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#45869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30584:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#45870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30585:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#45871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30586:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#45872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30587:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#45873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30588:
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 113 exceeds 100 columns
#45874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30589:
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#45875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30590:
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#45876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30591:
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#45877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30592:
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8

WARNING: line length of 121 exceeds 100 columns
#45878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30593:
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30594:
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L

WARNING: line length of 113 exceeds 100 columns
#45880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30595:
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#45881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30596:
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#45882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30597:
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e

WARNING: line length of 121 exceeds 100 columns
#45883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30598:
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#45884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30599:
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L

WARNING: line length of 121 exceeds 100 columns
#45885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30600:
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L

WARNING: line length of 114 exceeds 100 columns
#45886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30601:
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#45887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30602:
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#45888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30603:
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#45889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30604:
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#45890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30605:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#45891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30606:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#45892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30607:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#45893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30608:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14

WARNING: line length of 121 exceeds 100 columns
#45894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30609:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30610:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L

WARNING: line length of 121 exceeds 100 columns
#45896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30611:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30612:
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L

WARNING: line length of 113 exceeds 100 columns
#45898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30613:
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#45899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30614:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#45900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30615:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#45901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30616:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#45902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30617:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7

WARNING: line length of 113 exceeds 100 columns
#45903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30618:
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#45904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30619:
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#45905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30620:
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#45906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30621:
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30622:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30623:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30624:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30625:
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30626:
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30627:
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#45913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30628:
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#45914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30629:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#45915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30630:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#45916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30631:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#45917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30632:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#45918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30633:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#45919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30634:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#45920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30635:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#45921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30636:
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#45922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30637:
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#45923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30638:
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#45924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30639:
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30640:
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#45926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30641:
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#45927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30642:
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#45928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30643:
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa

WARNING: line length of 113 exceeds 100 columns
#45929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30644:
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#45930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30645:
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18

WARNING: line length of 121 exceeds 100 columns
#45931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30646:
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30647:
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30648:
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#45934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30649:
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#45935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30650:
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#45936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30651:
+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#45937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30652:
+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#45938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30653:
+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#45939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30654:
+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#45940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30655:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#45941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30656:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#45942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30657:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#45943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30658:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#45944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30659:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#45945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30660:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#45946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30661:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#45947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30662:
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#45948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30663:
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#45949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30664:
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#45950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30665:
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#45951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30666:
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#45952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30667:
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#45953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30668:
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L

WARNING: line length of 113 exceeds 100 columns
#45954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30669:
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#45955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30670:
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#45956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30671:
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#45957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30672:
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30673:
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30674:
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#45960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30675:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#45961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30676:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#45962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30677:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2

WARNING: line length of 113 exceeds 100 columns
#45963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30678:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#45964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30679:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#45965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30680:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#45966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30681:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#45967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30682:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#45968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30683:
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#45969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30684:
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#45970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30685:
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18

WARNING: line length of 121 exceeds 100 columns
#45971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30686:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#45972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30687:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#45973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30688:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#45974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30689:
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#45975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30690:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#45976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30691:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#45977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30692:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#45978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30693:
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#45979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30694:
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#45980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30695:
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#45981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30696:
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L

WARNING: line length of 113 exceeds 100 columns
#45982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30697:
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#45983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30698:
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#45984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30699:
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#45985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30700:
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#45986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30701:
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#45987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30702:
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#45988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30703:
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#45989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30704:
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#45990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30705:
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#45991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30706:
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#45992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30707:
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#45993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30708:
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#45994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30709:
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#45995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30710:
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#45996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30711:
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#45997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30712:
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa

WARNING: line length of 121 exceeds 100 columns
#45998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30713:
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#45999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30714:
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L

WARNING: line length of 113 exceeds 100 columns
#46000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30715:
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#46001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30716:
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#46002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30717:
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#46003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30718:
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30719:
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30720:
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L

WARNING: line length of 113 exceeds 100 columns
#46006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30721:
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#46007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30722:
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#46008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30723:
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#46009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30724:
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30725:
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L

WARNING: line length of 121 exceeds 100 columns
#46011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30726:
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L

WARNING: line length of 113 exceeds 100 columns
#46012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30727:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#46013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30728:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#46014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30729:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#46015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30730:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#46016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30731:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30732:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30733:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L

WARNING: line length of 121 exceeds 100 columns
#46019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30734:
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#46020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30735:
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#46021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30736:
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#46022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30737:
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#46023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30738:
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30739:
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30740:
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#46026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30741:
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#46027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30742:
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4

WARNING: line length of 114 exceeds 100 columns
#46028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30743:
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#46029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30744:
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30745:
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L

WARNING: line length of 121 exceeds 100 columns
#46031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30746:
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#46032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30747:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#46033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30748:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#46034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30749:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#46035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30750:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#46036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30751:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#46037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30752:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#46038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30753:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#46039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30754:
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#46040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30755:
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#46041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30756:
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#46042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30757:
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#46043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30758:
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#46044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30759:
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#46045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30760:
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#46046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30761:
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#46047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30762:
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30763:
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30764:
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L

WARNING: line length of 113 exceeds 100 columns
#46050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30765:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#46051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30766:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#46052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30767:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2

WARNING: line length of 113 exceeds 100 columns
#46053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30768:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#46054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30769:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#46055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30770:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14

WARNING: line length of 121 exceeds 100 columns
#46056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30771:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30772:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30773:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30774:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30775:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L

WARNING: line length of 121 exceeds 100 columns
#46061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30776:
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#46062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30777:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#46063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30778:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#46064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30779:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#46065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30780:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc

WARNING: line length of 121 exceeds 100 columns
#46066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30781:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30782:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30783:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30784:
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#46070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30785:
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#46071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30786:
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#46072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30787:
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#46073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30788:
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc

WARNING: line length of 114 exceeds 100 columns
#46074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30789:
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#46075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30790:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#46076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30791:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15

WARNING: line length of 114 exceeds 100 columns
#46077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30792:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16

WARNING: line length of 114 exceeds 100 columns
#46078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30793:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17

WARNING: line length of 114 exceeds 100 columns
#46079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30794:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18

WARNING: line length of 114 exceeds 100 columns
#46080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30795:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19

WARNING: line length of 114 exceeds 100 columns
#46081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30796:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#46082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30797:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b

WARNING: line length of 114 exceeds 100 columns
#46083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30798:
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#46084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30799:
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30800:
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30801:
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30802:
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30803:
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30804:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30805:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#46091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30806:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L

WARNING: line length of 121 exceeds 100 columns
#46092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30807:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L

WARNING: line length of 121 exceeds 100 columns
#46093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30808:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30809:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#46095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30810:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L

WARNING: line length of 121 exceeds 100 columns
#46096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30811:
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L

WARNING: line length of 121 exceeds 100 columns
#46097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30812:
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#46098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30813:
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#46099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30814:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#46100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30815:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#46101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30816:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5

WARNING: line length of 113 exceeds 100 columns
#46102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30817:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#46103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30818:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#46104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30819:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#46105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30820:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#46106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30821:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#46107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30822:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#46108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30823:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#46109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30824:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd

WARNING: line length of 113 exceeds 100 columns
#46110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30825:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe

WARNING: line length of 113 exceeds 100 columns
#46111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30826:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf

WARNING: line length of 114 exceeds 100 columns
#46112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30827:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#46113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30828:
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30829:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30830:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30831:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30832:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30833:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30834:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30835:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#46121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30836:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#46122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30837:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#46123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30838:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30839:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30840:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30841:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30842:
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30843:
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#46129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30844:
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#46130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30845:
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#46131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30846:
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30847:
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#46133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30848:
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#46134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30849:
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30850:
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30851:
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#46137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30852:
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#46138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30853:
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#46139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30854:
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30855:
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#46141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30856:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#46142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30857:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#46143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30858:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#46144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30859:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d

WARNING: line length of 121 exceeds 100 columns
#46145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30860:
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30861:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30862:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30863:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#46149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30864:
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L

WARNING: line length of 113 exceeds 100 columns
#46150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30865:
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#46151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30866:
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#46152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30867:
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#46153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30868:
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#46154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30869:
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#46155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30870:
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#46156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30871:
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#46157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30872:
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#46158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30873:
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#46159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30874:
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#46160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30875:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#46161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30876:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#46162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30877:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#46163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30878:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#46164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30879:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#46165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30880:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30881:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#46167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30882:
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#46168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30883:
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#46169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30884:
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a

WARNING: line length of 121 exceeds 100 columns
#46170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30885:
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#46171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30886:
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#46172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30887:
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#46173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30888:
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#46174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30889:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#46175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30890:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#46176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30891:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#46177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30892:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#46178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30893:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30894:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#46180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30895:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#46181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30896:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#46182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30897:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#46183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30898:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#46184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30899:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#46185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30900:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#46186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30901:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30902:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#46188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30903:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#46189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30904:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#46190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30905:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#46191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30906:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#46192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30907:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#46193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30908:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#46194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30909:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30910:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#46196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30911:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#46197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30912:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#46198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30913:
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#46199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30914:
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8

WARNING: line length of 121 exceeds 100 columns
#46200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30915:
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#46201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30916:
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#46202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30917:
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#46203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30918:
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#46204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30919:
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#46205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30920:
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L

WARNING: line length of 113 exceeds 100 columns
#46206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30921:
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#46207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30922:
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#46208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30923:
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#46209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30924:
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30925:
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30926:
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#46212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30927:
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#46213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30928:
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf

WARNING: line length of 114 exceeds 100 columns
#46214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30929:
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#46215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30930:
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#46216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30931:
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30932:
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L

WARNING: line length of 113 exceeds 100 columns
#46218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30933:
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#46219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30934:
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L

WARNING: line length of 113 exceeds 100 columns
#46220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30935:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#46221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30936:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#46222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30937:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#46223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30938:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#46224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30939:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30940:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#46226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30941:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#46227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30942:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#46228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30943:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#46229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30944:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#46230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30945:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#46231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30946:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#46232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30947:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30948:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#46234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30949:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#46235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30950:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#46236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30951:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#46237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30952:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#46238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30953:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#46239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30954:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#46240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30955:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30956:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#46242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30957:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#46243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30958:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#46244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30959:
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#46245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30960:
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L

WARNING: line length of 113 exceeds 100 columns
#46246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30961:
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#46247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30962:
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#46248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30963:
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30964:
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30965:
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#46251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30966:
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#46252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30967:
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30968:
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30969:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#46255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30970:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#46256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30971:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#46257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30972:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#46258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30973:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#46259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30974:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30975:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#46261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30976:
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#46262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30977:
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#46263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30978:
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#46264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30979:
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30980:
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30981:
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#46267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30982:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#46268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30983:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#46269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30984:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc

WARNING: line length of 114 exceeds 100 columns
#46270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30985:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#46271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30986:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#46272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30987:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#46273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30988:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#46274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30989:
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#46275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30990:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#46276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30991:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#46277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30992:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#46278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30993:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#46279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30994:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#46280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30995:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#46281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30996:
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#46282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30997:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#46283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30998:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#46284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:30999:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#46285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31000:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc

WARNING: line length of 114 exceeds 100 columns
#46286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31001:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#46287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31002:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#46288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31003:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#46289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31004:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#46290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31005:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#46291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31006:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#46292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31007:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#46293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31008:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#46294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31009:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#46295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31010:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#46296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31011:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#46297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31012:
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#46298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31013:
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#46299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31014:
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L

WARNING: line length of 113 exceeds 100 columns
#46300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31015:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#46301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31016:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#46302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31017:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#46303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31018:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#46304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31019:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#46305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31020:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#46306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31021:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#46307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31022:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#46308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31023:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#46309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31024:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#46310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31025:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#46311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31026:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#46312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31027:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#46313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31028:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#46314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31029:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 113 exceeds 100 columns
#46315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31030:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf

WARNING: line length of 114 exceeds 100 columns
#46316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31031:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#46317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31032:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#46318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31033:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12

WARNING: line length of 114 exceeds 100 columns
#46319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31034:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#46320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31035:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#46321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31036:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#46322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31037:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16

WARNING: line length of 114 exceeds 100 columns
#46323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31038:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#46324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31039:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#46325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31040:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#46326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31041:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a

WARNING: line length of 114 exceeds 100 columns
#46327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31042:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b

WARNING: line length of 114 exceeds 100 columns
#46328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31043:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#46329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31044:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31045:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31046:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31047:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#46333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31048:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31049:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31050:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31051:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31052:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31053:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#46339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31054:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#46340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31055:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#46341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31056:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31057:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31058:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31059:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31060:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31061:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#46347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31062:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#46348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31063:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#46349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31064:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31065:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#46351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31066:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#46352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31067:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#46353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31068:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31069:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#46355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31070:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#46356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31071:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#46357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31072:
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#46358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31073:
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#46359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31074:
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#46360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31075:
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31076:
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31077:
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#46363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31078:
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#46364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31079:
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31080:
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31081:
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#46367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31082:
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#46368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31083:
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31084:
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31085:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#46371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31086:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#46372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31087:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#46373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31088:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12

WARNING: line length of 114 exceeds 100 columns
#46374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31089:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#46375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31090:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#46376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31091:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#46377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31092:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#46378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31093:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#46379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31094:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#46380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31095:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19

WARNING: line length of 114 exceeds 100 columns
#46381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31096:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#46382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31097:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b

WARNING: line length of 121 exceeds 100 columns
#46383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31098:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31099:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31100:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#46386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31101:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#46387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31102:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#46388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31103:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31104:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#46390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31105:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#46391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31106:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#46392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31107:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31108:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#46394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31109:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#46395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31110:
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L

WARNING: line length of 113 exceeds 100 columns
#46396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31111:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#46397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31112:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#46398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31113:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#46399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31114:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#46400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31115:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#46401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31116:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#46402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31117:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#46403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31118:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd

WARNING: line length of 114 exceeds 100 columns
#46404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31119:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#46405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31120:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#46406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31121:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14

WARNING: line length of 114 exceeds 100 columns
#46407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31122:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#46408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31123:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#46409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31124:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#46410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31125:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#46411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31126:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d

WARNING: line length of 121 exceeds 100 columns
#46412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31127:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31128:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31129:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31130:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31131:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31132:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#46418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31133:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31134:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31135:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31136:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#46422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31137:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31138:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#46424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31139:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31140:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#46426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31141:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#46427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31142:
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L

WARNING: line length of 113 exceeds 100 columns
#46428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31143:
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#46429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31144:
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#46430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31145:
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5

WARNING: line length of 113 exceeds 100 columns
#46431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31146:
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#46432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31147:
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#46433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31148:
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf

WARNING: line length of 114 exceeds 100 columns
#46434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31149:
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10

WARNING: line length of 114 exceeds 100 columns
#46435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31150:
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11

WARNING: line length of 121 exceeds 100 columns
#46436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31151:
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31152:
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31153:
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31154:
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31155:
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31156:
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31157:
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31158:
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L

WARNING: line length of 113 exceeds 100 columns
#46444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31159:
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#46445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31160:
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#46446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31161:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#46447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31162:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#46448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31163:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#46449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31164:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#46450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31165:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#46451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31166:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#46452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31167:
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#46453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31168:
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31169:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31170:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#46456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31171:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31172:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31173:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31174:
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31175:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#46461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31176:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#46462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31177:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4

WARNING: line length of 114 exceeds 100 columns
#46463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31178:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10

WARNING: line length of 121 exceeds 100 columns
#46464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31179:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31180:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31181:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#46467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31182:
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31183:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#46469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31184:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#46470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31185:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#46471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31186:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#46472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31187:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#46473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31188:
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#46474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31189:
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#46475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31190:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#46476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31191:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#46477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31192:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31193:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31194:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31195:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#46481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31196:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31197:
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31198:
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31199:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#46485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31200:
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31201:
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#46487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31202:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#46488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31203:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#46489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31204:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#46490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31205:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#46491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31206:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#46492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31207:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#46493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31208:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#46494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31209:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#46495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31210:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#46496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31211:
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#46497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31212:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31213:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31214:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31215:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31216:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31217:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31218:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31219:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31220:
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31221:
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#46507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31222:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#46508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31223:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#46509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31224:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#46510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31225:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#46511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31226:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#46512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31227:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#46513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31228:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#46514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31229:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#46515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31230:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#46516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31231:
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#46517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31232:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31233:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31234:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31235:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31236:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31237:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31238:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31239:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31240:
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31241:
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#46527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31242:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#46528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31243:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#46529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31244:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#46530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31245:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#46531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31246:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#46532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31247:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#46533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31248:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#46534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31249:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#46535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31250:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#46536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31251:
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#46537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31252:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31253:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31254:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31255:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31256:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31257:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31258:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31259:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31260:
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31261:
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#46547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31262:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#46548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31263:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#46549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31264:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#46550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31265:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#46551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31266:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#46552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31267:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#46553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31268:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#46554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31269:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#46555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31270:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#46556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31271:
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#46557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31272:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31273:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31274:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31275:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31276:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31277:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31278:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31279:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31280:
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31281:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#46567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31282:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#46568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31283:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#46569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31284:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#46570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31285:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#46571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31286:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#46572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31287:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#46573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31288:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#46574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31289:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#46575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31290:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#46576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31291:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#46577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31292:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb

WARNING: line length of 121 exceeds 100 columns
#46578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31293:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31294:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31295:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31296:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#46582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31297:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31298:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31299:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31300:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31301:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31302:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#46588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31303:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#46589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31304:
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L

WARNING: line length of 113 exceeds 100 columns
#46590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31305:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#46591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31306:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#46592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31307:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#46593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31308:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#46594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31309:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#46595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31310:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L

WARNING: line length of 121 exceeds 100 columns
#46596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31311:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L

WARNING: line length of 121 exceeds 100 columns
#46597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31312:
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#46598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31313:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#46599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31314:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7

WARNING: line length of 114 exceeds 100 columns
#46600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31315:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#46601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31316:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#46602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31317:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12

WARNING: line length of 114 exceeds 100 columns
#46603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31318:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13

WARNING: line length of 114 exceeds 100 columns
#46604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31319:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#46605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31320:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#46606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31321:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31322:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31323:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#46609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31324:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L

WARNING: line length of 121 exceeds 100 columns
#46610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31325:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#46611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31326:
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#46612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31327:
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#46613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31328:
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#46614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31329:
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#46615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31330:
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31331:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#46617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31332:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#46618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31333:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3

WARNING: line length of 113 exceeds 100 columns
#46619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31334:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#46620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31335:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#46621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31336:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6

WARNING: line length of 114 exceeds 100 columns
#46622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31337:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#46623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31338:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31339:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31340:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#46626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31341:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31342:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31343:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31344:
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#46630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31345:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#46631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31346:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#46632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31347:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#46633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31348:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#46634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31349:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8

WARNING: line length of 114 exceeds 100 columns
#46635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31350:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#46636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31351:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31352:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31353:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31354:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#46640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31355:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#46641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31356:
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31357:
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#46643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31358:
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#46644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31359:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#46645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31360:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#46646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31361:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#46647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31362:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#46648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31363:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#46649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31364:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#46650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31365:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#46651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31366:
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#46652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31367:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#46653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31368:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#46654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31369:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#46655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31370:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#46656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31371:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#46657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31372:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#46658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31373:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#46659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31374:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#46660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31375:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#46661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31376:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#46662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31377:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#46663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31378:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#46664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31379:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#46665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31380:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#46666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31381:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#46667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31382:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#46668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31383:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#46669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31384:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#46670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31385:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#46671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31386:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#46672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31387:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#46673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31388:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#46674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31389:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#46675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31390:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#46676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31391:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#46677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31392:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#46678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31393:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#46679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31394:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#46680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31395:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#46681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31396:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#46682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31397:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31398:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31399:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31400:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#46686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31401:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31402:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31403:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31404:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31405:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31406:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#46692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31407:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#46693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31408:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#46694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31409:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31410:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31411:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31412:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31413:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#46699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31414:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#46700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31415:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#46701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31416:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31417:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#46703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31418:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#46704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31419:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#46705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31420:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31421:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#46707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31422:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#46708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31423:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#46709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31424:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#46710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31425:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#46711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31426:
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#46712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31427:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#46713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31428:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#46714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31429:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#46715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31430:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#46716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31431:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#46717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31432:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#46718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31433:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#46719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31434:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#46720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31435:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#46721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31436:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#46722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31437:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#46723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31438:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#46724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31439:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#46725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31440:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#46726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31441:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#46727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31442:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#46728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31443:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#46729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31444:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#46730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31445:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#46731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31446:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#46732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31447:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#46733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31448:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#46734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31449:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#46735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31450:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#46736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31451:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#46737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31452:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#46738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31453:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#46739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31454:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#46740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31455:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#46741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31456:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#46742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31457:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31458:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31459:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31460:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#46746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31461:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31462:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#46748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31463:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31464:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#46750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31465:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31466:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#46752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31467:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#46753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31468:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#46754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31469:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31470:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31471:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31472:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31473:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#46759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31474:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#46760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31475:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#46761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31476:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31477:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#46763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31478:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#46764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31479:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#46765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31480:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31481:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#46767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31482:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#46768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31483:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#46769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31484:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#46770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31485:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#46771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31486:
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#46772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31487:
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#46773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31488:
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#46774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31489:
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#46775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31490:
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31491:
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31492:
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#46778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31493:
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#46779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31494:
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#46780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31495:
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#46781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31496:
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31497:
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31498:
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#46784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31499:
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#46785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31500:
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#46786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31501:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#46787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31502:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#46788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31503:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#46789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31504:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#46790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31505:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#46791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31506:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#46792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31507:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#46793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31508:
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#46794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31509:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#46795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31510:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#46796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31511:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#46797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31512:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#46798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31513:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#46799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31514:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#46800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31515:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#46801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31516:
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#46802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31517:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#46803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31518:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#46804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31519:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#46805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31520:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#46806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31521:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#46807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31522:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#46808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31523:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31524:
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#46810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31525:
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd

WARNING: line length of 114 exceeds 100 columns
#46811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31526:
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#46812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31527:
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#46813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31528:
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31529:
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#46815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31530:
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L

WARNING: line length of 113 exceeds 100 columns
#46816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31531:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#46817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31532:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#46818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31533:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#46819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31534:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#46820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31535:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#46821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31536:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#46822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31537:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31538:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31539:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#46825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31540:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#46826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31541:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31542:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L

WARNING: line length of 113 exceeds 100 columns
#46828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31543:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#46829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31544:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#46830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31545:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb

WARNING: line length of 114 exceeds 100 columns
#46831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31546:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#46832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31547:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#46833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31548:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#46834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31549:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L

WARNING: line length of 121 exceeds 100 columns
#46835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31550:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L

WARNING: line length of 121 exceeds 100 columns
#46836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31551:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#46837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31552:
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#46838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31553:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#46839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31554:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#46840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31555:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#46841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31556:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#46842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31557:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#46843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31558:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L

WARNING: line length of 121 exceeds 100 columns
#46844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31559:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31560:
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L

WARNING: line length of 113 exceeds 100 columns
#46846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31561:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#46847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31562:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#46848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31563:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#46849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31564:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#46850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31565:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6

WARNING: line length of 113 exceeds 100 columns
#46851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31566:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#46852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31567:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#46853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31568:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#46854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31569:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#46855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31570:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#46856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31571:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31572:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#46858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31573:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#46859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31574:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L

WARNING: line length of 121 exceeds 100 columns
#46860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31575:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#46861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31576:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#46862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31577:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#46863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31578:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#46864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31579:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#46865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31580:
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#46866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31581:
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#46867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31582:
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4

WARNING: line length of 114 exceeds 100 columns
#46868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31583:
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#46869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31584:
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#46870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31585:
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#46871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31586:
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#46872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31587:
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#46873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31588:
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31589:
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#46875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31590:
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#46876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31591:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#46877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31592:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#46878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31593:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#46879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31594:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#46880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31595:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#46881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31596:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31597:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31598:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31599:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#46885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31600:
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#46886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31601:
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#46887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31602:
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#46888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31603:
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#46889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31604:
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#46890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31605:
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#46891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31606:
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#46892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31607:
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#46893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31608:
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#46894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31609:
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#46895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31610:
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#46896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31611:
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#46897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31612:
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#46898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31613:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#46899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31614:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#46900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31615:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#46901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31616:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc

WARNING: line length of 114 exceeds 100 columns
#46902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31617:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#46903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31618:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#46904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31619:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#46905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31620:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#46906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31621:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#46907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31622:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#46908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31623:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#46909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31624:
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#46910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31625:
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#46911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31626:
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8

WARNING: line length of 121 exceeds 100 columns
#46912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31627:
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31628:
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#46914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31629:
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#46915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31630:
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#46916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31631:
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#46917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31632:
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#46918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31633:
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31634:
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31635:
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31636:
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#46922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31637:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#46923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31638:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4

WARNING: line length of 113 exceeds 100 columns
#46924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31639:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb

WARNING: line length of 113 exceeds 100 columns
#46925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31640:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#46926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31641:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#46927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31642:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17

WARNING: line length of 114 exceeds 100 columns
#46928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31643:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18

WARNING: line length of 114 exceeds 100 columns
#46929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31644:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#46930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31645:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e

WARNING: line length of 121 exceeds 100 columns
#46931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31646:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31647:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31648:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#46934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31649:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31650:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#46936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31651:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L

WARNING: line length of 121 exceeds 100 columns
#46937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31652:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31653:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#46939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31654:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L

WARNING: line length of 113 exceeds 100 columns
#46940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31655:
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#46941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31656:
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7

WARNING: line length of 121 exceeds 100 columns
#46942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31657:
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#46943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31658:
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L

WARNING: line length of 113 exceeds 100 columns
#46944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31659:
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#46945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31660:
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L

WARNING: line length of 113 exceeds 100 columns
#46946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31661:
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#46947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31662:
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#46948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31663:
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#46949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31664:
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31665:
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#46951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31666:
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L

WARNING: line length of 113 exceeds 100 columns
#46952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31667:
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#46953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31668:
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#46954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31669:
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#46955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31670:
+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#46956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31671:
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#46957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31672:
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#46958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31673:
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#46959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31674:
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#46960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31675:
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#46961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31676:
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31677:
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31678:
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31679:
+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#46965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31680:
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#46966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31681:
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#46967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31682:
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#46968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31683:
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#46969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31684:
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#46970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31685:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#46971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31686:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#46972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31687:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#46973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31688:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#46974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31689:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#46975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31690:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31691:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#46977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31692:
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#46978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31693:
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#46979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31694:
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#46980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31695:
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#46981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31696:
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#46982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31697:
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf

WARNING: line length of 114 exceeds 100 columns
#46983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31698:
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#46984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31699:
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14

WARNING: line length of 121 exceeds 100 columns
#46985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31700:
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#46986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31701:
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#46987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31702:
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#46988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31703:
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#46989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31704:
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#46990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31705:
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#46991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31706:
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L

WARNING: line length of 113 exceeds 100 columns
#46992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31707:
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#46993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31708:
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#46994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31709:
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#46995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31710:
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#46996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31711:
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#46997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31712:
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L

WARNING: line length of 113 exceeds 100 columns
#46998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31713:
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#46999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31714:
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#47000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31715:
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#47001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31716:
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#47002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31717:
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#47003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31718:
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#47004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31719:
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#47005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31720:
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#47006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31721:
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6

WARNING: line length of 114 exceeds 100 columns
#47007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31722:
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#47008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31723:
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31724:
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31725:
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31726:
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31727:
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31728:
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#47014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31729:
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#47015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31730:
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#47016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31731:
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#47017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31732:
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#47018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31733:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#47019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31734:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#47020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31735:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#47021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31736:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#47022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31737:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#47023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31738:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#47024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31739:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#47025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31740:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31741:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31742:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#47028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31743:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31744:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31745:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31746:
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L

WARNING: line length of 113 exceeds 100 columns
#47032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31747:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#47033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31748:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#47034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31749:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#47035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31750:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#47036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31751:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#47037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31752:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e

WARNING: line length of 114 exceeds 100 columns
#47038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31753:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#47039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31754:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31755:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL

WARNING: line length of 121 exceeds 100 columns
#47041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31756:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#47042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31757:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L

WARNING: line length of 121 exceeds 100 columns
#47043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31758:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#47044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31759:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L

WARNING: line length of 121 exceeds 100 columns
#47045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31760:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#47046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31761:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#47047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31762:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#47048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31763:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#47049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31764:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#47050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31765:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31766:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31767:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31768:
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31769:
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#47055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31770:
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#47056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31771:
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2

WARNING: line length of 113 exceeds 100 columns
#47057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31772:
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#47058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31773:
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#47059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31774:
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#47060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31775:
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9

WARNING: line length of 114 exceeds 100 columns
#47061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31776:
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#47062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31777:
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#47063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31778:
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#47064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31779:
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31780:
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31781:
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31782:
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#47068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31783:
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31784:
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31785:
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#47071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31786:
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#47072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31787:
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31788:
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L

WARNING: line length of 113 exceeds 100 columns
#47074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31789:
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#47075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31790:
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#47076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31791:
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#47077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31792:
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b

WARNING: line length of 121 exceeds 100 columns
#47078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31793:
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31794:
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31795:
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31796:
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L

WARNING: line length of 113 exceeds 100 columns
#47082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31797:
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#47083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31798:
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#47084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31799:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#47085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31800:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#47086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31801:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#47087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31802:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#47088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31803:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc

WARNING: line length of 114 exceeds 100 columns
#47089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31804:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#47090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31805:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#47091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31806:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31807:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31808:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#47094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31809:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31810:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31811:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#47097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31812:
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#47098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31813:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#47099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31814:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#47100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31815:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#47101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31816:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#47102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31817:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#47103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31818:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#47104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31819:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#47105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31820:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#47106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31821:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31822:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31823:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31824:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31825:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#47111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31826:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31827:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#47113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31828:
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31829:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#47115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31830:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#47116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31831:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#47117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31832:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9

WARNING: line length of 121 exceeds 100 columns
#47118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31833:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31834:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31835:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31836:
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L

WARNING: line length of 113 exceeds 100 columns
#47122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31837:
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#47123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31838:
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#47124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31839:
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31840:
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L

WARNING: line length of 113 exceeds 100 columns
#47126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31841:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#47127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31842:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#47128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31843:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#47129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31844:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#47130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31845:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#47131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31846:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#47132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31847:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#47133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31848:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#47134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31849:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#47135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31850:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#47136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31851:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#47137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31852:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb

WARNING: line length of 113 exceeds 100 columns
#47138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31853:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#47139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31854:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#47140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31855:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#47141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31856:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf

WARNING: line length of 114 exceeds 100 columns
#47142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31857:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#47143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31858:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#47144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31859:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#47145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31860:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13

WARNING: line length of 114 exceeds 100 columns
#47146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31861:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#47147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31862:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15

WARNING: line length of 114 exceeds 100 columns
#47148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31863:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#47149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31864:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17

WARNING: line length of 114 exceeds 100 columns
#47150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31865:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#47151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31866:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#47152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31867:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a

WARNING: line length of 114 exceeds 100 columns
#47153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31868:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b

WARNING: line length of 114 exceeds 100 columns
#47154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31869:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#47155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31870:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d

WARNING: line length of 114 exceeds 100 columns
#47156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31871:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e

WARNING: line length of 114 exceeds 100 columns
#47157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31872:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f

WARNING: line length of 121 exceeds 100 columns
#47158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31873:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31874:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31875:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31876:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#47162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31877:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31878:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31879:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31880:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31881:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31882:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#47168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31883:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#47169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31884:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#47170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31885:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31886:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#47172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31887:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#47173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31888:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31889:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31890:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#47176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31891:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#47177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31892:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L

WARNING: line length of 121 exceeds 100 columns
#47178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31893:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31894:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#47180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31895:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#47181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31896:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#47182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31897:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31898:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#47184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31899:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L

WARNING: line length of 121 exceeds 100 columns
#47185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31900:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#47186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31901:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#47187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31902:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L

WARNING: line length of 121 exceeds 100 columns
#47188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31903:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#47189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31904:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#47190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31905:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#47191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31906:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#47192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31907:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#47193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31908:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#47194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31909:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#47195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31910:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#47196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31911:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#47197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31912:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#47198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31913:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#47199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31914:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9

WARNING: line length of 113 exceeds 100 columns
#47200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31915:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#47201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31916:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb

WARNING: line length of 113 exceeds 100 columns
#47202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31917:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#47203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31918:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#47204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31919:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe

WARNING: line length of 113 exceeds 100 columns
#47205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31920:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf

WARNING: line length of 114 exceeds 100 columns
#47206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31921:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#47207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31922:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#47208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31923:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#47209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31924:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#47210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31925:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#47211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31926:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#47212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31927:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#47213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31928:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17

WARNING: line length of 114 exceeds 100 columns
#47214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31929:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#47215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31930:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19

WARNING: line length of 114 exceeds 100 columns
#47216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31931:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#47217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31932:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b

WARNING: line length of 121 exceeds 100 columns
#47218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31933:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31934:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31935:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31936:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#47222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31937:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31938:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31939:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31940:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31941:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31942:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#47228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31943:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#47229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31944:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L

WARNING: line length of 121 exceeds 100 columns
#47230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31945:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31946:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#47232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31947:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#47233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31948:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31949:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31950:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#47236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31951:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#47237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31952:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#47238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31953:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31954:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L

WARNING: line length of 121 exceeds 100 columns
#47240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31955:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#47241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31956:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#47242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31957:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31958:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L

WARNING: line length of 121 exceeds 100 columns
#47244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31959:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#47245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31960:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L

WARNING: line length of 113 exceeds 100 columns
#47246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31961:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#47247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31962:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#47248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31963:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#47249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31964:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#47250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31965:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#47251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31966:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#47252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31967:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#47253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31968:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7

WARNING: line length of 113 exceeds 100 columns
#47254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31969:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#47255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31970:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9

WARNING: line length of 113 exceeds 100 columns
#47256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31971:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#47257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31972:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb

WARNING: line length of 113 exceeds 100 columns
#47258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31973:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#47259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31974:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd

WARNING: line length of 113 exceeds 100 columns
#47260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31975:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#47261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31976:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf

WARNING: line length of 114 exceeds 100 columns
#47262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31977:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#47263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31978:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#47264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31979:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#47265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31980:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13

WARNING: line length of 114 exceeds 100 columns
#47266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31981:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#47267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31982:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15

WARNING: line length of 114 exceeds 100 columns
#47268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31983:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#47269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31984:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17

WARNING: line length of 114 exceeds 100 columns
#47270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31985:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18

WARNING: line length of 114 exceeds 100 columns
#47271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31986:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19

WARNING: line length of 114 exceeds 100 columns
#47272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31987:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#47273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31988:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b

WARNING: line length of 114 exceeds 100 columns
#47274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31989:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#47275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31990:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d

WARNING: line length of 121 exceeds 100 columns
#47276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31991:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31992:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31993:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31994:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#47280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31995:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31996:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31997:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31998:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:31999:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32000:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#47286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32001:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#47287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32002:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#47288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32003:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32004:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#47290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32005:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#47291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32006:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32007:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32008:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#47294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32009:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#47295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32010:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#47296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32011:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32012:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#47298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32013:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#47299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32014:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L

WARNING: line length of 121 exceeds 100 columns
#47300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32015:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32016:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#47302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32017:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#47303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32018:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#47304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32019:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#47305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32020:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L

WARNING: line length of 113 exceeds 100 columns
#47306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32021:
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#47307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32022:
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#47308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32023:
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#47309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32024:
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8

WARNING: line length of 113 exceeds 100 columns
#47310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32025:
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc

WARNING: line length of 121 exceeds 100 columns
#47311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32026:
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32027:
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32028:
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32029:
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#47315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32030:
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L

WARNING: line length of 113 exceeds 100 columns
#47316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32031:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#47317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32032:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#47318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32033:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32034:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32035:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#47321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32036:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#47322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32037:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32038:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32039:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#47325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32040:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#47326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32041:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32042:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32043:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#47329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32044:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#47330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32045:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32046:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32047:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#47333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32048:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#47334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32049:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32050:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32051:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#47337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32052:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#47338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32053:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32054:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32055:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#47341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32056:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#47342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32057:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32058:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32059:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#47345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32060:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#47346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32061:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#47347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32062:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#47348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32063:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#47349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32064:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14

WARNING: line length of 114 exceeds 100 columns
#47350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32065:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#47351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32066:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#47352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32067:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17

WARNING: line length of 114 exceeds 100 columns
#47353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32068:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18

WARNING: line length of 114 exceeds 100 columns
#47354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32069:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19

WARNING: line length of 114 exceeds 100 columns
#47355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32070:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#47356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32071:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b

WARNING: line length of 114 exceeds 100 columns
#47357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32072:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#47358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32073:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d

WARNING: line length of 114 exceeds 100 columns
#47359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32074:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e

WARNING: line length of 121 exceeds 100 columns
#47360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32075:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32076:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32077:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#47363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32078:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#47364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32079:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#47365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32080:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32081:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#47367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32082:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#47368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32083:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#47369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32084:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32085:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L

WARNING: line length of 121 exceeds 100 columns
#47371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32086:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#47372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32087:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L

WARNING: line length of 121 exceeds 100 columns
#47373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32088:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#47374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32089:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#47375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32090:
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L

WARNING: line length of 113 exceeds 100 columns
#47376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32091:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#47377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32092:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#47378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32093:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#47379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32094:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#47380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32095:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#47381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32096:
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf

WARNING: line length of 114 exceeds 100 columns
#47382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32097:
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#47383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32098:
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#47384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32099:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32100:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32101:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32102:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32103:
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32104:
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32105:
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32106:
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#47392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32107:
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#47393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32108:
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#47394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32109:
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#47395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32110:
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#47396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32111:
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#47397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32112:
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#47398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32113:
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#47399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32114:
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#47400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32115:
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#47401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32116:
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#47402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32117:
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#47403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32118:
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#47404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32119:
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc

WARNING: line length of 121 exceeds 100 columns
#47405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32120:
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#47406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32121:
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#47407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32122:
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#47408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32123:
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#47409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32124:
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8

WARNING: line length of 121 exceeds 100 columns
#47410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32125:
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32126:
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#47412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32127:
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#47413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32128:
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#47414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32129:
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#47415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32130:
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#47416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32131:
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#47417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32132:
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32133:
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32134:
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32135:
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#47421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32136:
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#47422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32137:
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#47423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32138:
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#47424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32139:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#47425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32140:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#47426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32141:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#47427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32142:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3

WARNING: line length of 121 exceeds 100 columns
#47428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32143:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32144:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32145:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32146:
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L

WARNING: line length of 113 exceeds 100 columns
#47432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32147:
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#47433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32148:
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8

WARNING: line length of 121 exceeds 100 columns
#47434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32149:
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#47435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32150:
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#47436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32151:
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#47437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32152:
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#47438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32153:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#47439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32154:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#47440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32155:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32156:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#47442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32157:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#47443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32158:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#47444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32159:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32160:
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#47446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32161:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#47447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32162:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#47448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32163:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#47449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32164:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#47450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32165:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32166:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32167:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32168:
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L

WARNING: line length of 113 exceeds 100 columns
#47454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32169:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#47455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32170:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#47456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32171:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#47457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32172:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#47458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32173:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18

WARNING: line length of 121 exceeds 100 columns
#47459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32174:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32175:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#47461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32176:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32177:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#47463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32178:
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L

WARNING: line length of 113 exceeds 100 columns
#47464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32179:
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#47465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32180:
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#47466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32181:
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32182:
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#47468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32183:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#47469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32184:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#47470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32185:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#47471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32186:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#47472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32187:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#47473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32188:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#47474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32189:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#47475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32190:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#47476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32191:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#47477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32192:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#47478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32193:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#47479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32194:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#47480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32195:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#47481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32196:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#47482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32197:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#47483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32198:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#47484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32199:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#47485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32200:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32201:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#47487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32202:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#47488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32203:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#47489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32204:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32205:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#47491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32206:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#47492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32207:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#47493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32208:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#47494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32209:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#47495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32210:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#47496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32211:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#47497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32212:
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#47498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32213:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#47499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32214:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#47500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32215:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#47501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32216:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#47502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32217:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#47503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32218:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#47504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32219:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#47505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32220:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#47506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32221:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#47507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32222:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#47508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32223:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#47509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32224:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#47510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32225:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#47511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32226:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#47512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32227:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#47513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32228:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#47514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32229:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32230:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#47516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32231:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#47517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32232:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#47518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32233:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32234:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#47520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32235:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#47521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32236:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#47522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32237:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#47523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32238:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#47524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32239:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#47525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32240:
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 113 exceeds 100 columns
#47526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32241:
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#47527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32242:
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#47528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32243:
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#47529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32244:
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8

WARNING: line length of 121 exceeds 100 columns
#47530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32245:
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32246:
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L

WARNING: line length of 113 exceeds 100 columns
#47532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32247:
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#47533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32248:
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#47534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32249:
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e

WARNING: line length of 121 exceeds 100 columns
#47535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32250:
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32251:
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L

WARNING: line length of 121 exceeds 100 columns
#47537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32252:
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L

WARNING: line length of 114 exceeds 100 columns
#47538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32253:
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#47539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32254:
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#47540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32255:
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#47541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32256:
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#47542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32257:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#47543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32258:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#47544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32259:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#47545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32260:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14

WARNING: line length of 121 exceeds 100 columns
#47546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32261:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32262:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L

WARNING: line length of 121 exceeds 100 columns
#47548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32263:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32264:
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L

WARNING: line length of 113 exceeds 100 columns
#47550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32265:
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#47551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32266:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#47552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32267:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#47553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32268:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#47554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32269:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7

WARNING: line length of 113 exceeds 100 columns
#47555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32270:
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#47556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32271:
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#47557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32272:
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#47558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32273:
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32274:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32275:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32276:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32277:
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32278:
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32279:
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32280:
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32281:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#47567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32282:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#47568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32283:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#47569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32284:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#47570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32285:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#47571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32286:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#47572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32287:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#47573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32288:
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#47574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32289:
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#47575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32290:
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#47576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32291:
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32292:
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#47578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32293:
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#47579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32294:
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#47580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32295:
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa

WARNING: line length of 113 exceeds 100 columns
#47581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32296:
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#47582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32297:
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18

WARNING: line length of 121 exceeds 100 columns
#47583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32298:
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32299:
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32300:
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#47586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32301:
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#47587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32302:
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#47588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32303:
+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#47589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32304:
+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#47590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32305:
+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#47591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32306:
+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#47592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32307:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#47593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32308:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#47594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32309:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#47595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32310:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#47596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32311:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#47597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32312:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32313:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32314:
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#47600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32315:
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#47601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32316:
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#47602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32317:
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#47603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32318:
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#47604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32319:
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#47605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32320:
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L

WARNING: line length of 113 exceeds 100 columns
#47606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32321:
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#47607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32322:
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#47608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32323:
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#47609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32324:
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32325:
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32326:
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#47612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32327:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#47613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32328:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#47614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32329:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2

WARNING: line length of 113 exceeds 100 columns
#47615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32330:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#47616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32331:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#47617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32332:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#47618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32333:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#47619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32334:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#47620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32335:
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#47621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32336:
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#47622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32337:
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18

WARNING: line length of 121 exceeds 100 columns
#47623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32338:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32339:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32340:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32341:
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#47627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32342:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32343:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32344:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32345:
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32346:
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32347:
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32348:
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L

WARNING: line length of 113 exceeds 100 columns
#47634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32349:
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#47635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32350:
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#47636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32351:
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#47637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32352:
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#47638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32353:
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#47639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32354:
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32355:
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#47641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32356:
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#47642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32357:
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#47643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32358:
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#47644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32359:
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#47645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32360:
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32361:
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#47647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32362:
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#47648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32363:
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#47649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32364:
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa

WARNING: line length of 121 exceeds 100 columns
#47650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32365:
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32366:
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L

WARNING: line length of 113 exceeds 100 columns
#47652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32367:
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#47653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32368:
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#47654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32369:
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#47655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32370:
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32371:
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32372:
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L

WARNING: line length of 113 exceeds 100 columns
#47658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32373:
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#47659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32374:
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#47660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32375:
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#47661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32376:
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32377:
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L

WARNING: line length of 121 exceeds 100 columns
#47663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32378:
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L

WARNING: line length of 113 exceeds 100 columns
#47664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32379:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#47665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32380:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#47666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32381:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#47667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32382:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#47668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32383:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32384:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32385:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L

WARNING: line length of 121 exceeds 100 columns
#47671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32386:
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#47672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32387:
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#47673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32388:
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#47674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32389:
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#47675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32390:
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32391:
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32392:
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#47678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32393:
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#47679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32394:
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4

WARNING: line length of 114 exceeds 100 columns
#47680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32395:
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#47681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32396:
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32397:
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L

WARNING: line length of 121 exceeds 100 columns
#47683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32398:
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#47684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32399:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#47685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32400:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#47686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32401:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#47687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32402:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#47688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32403:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#47689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32404:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#47690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32405:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#47691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32406:
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#47692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32407:
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#47693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32408:
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#47694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32409:
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#47695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32410:
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#47696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32411:
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#47697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32412:
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#47698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32413:
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#47699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32414:
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32415:
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32416:
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L

WARNING: line length of 113 exceeds 100 columns
#47702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32417:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#47703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32418:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#47704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32419:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2

WARNING: line length of 113 exceeds 100 columns
#47705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32420:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#47706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32421:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#47707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32422:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14

WARNING: line length of 121 exceeds 100 columns
#47708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32423:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32424:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32425:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32426:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32427:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L

WARNING: line length of 121 exceeds 100 columns
#47713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32428:
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#47714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32429:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#47715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32430:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#47716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32431:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#47717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32432:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc

WARNING: line length of 121 exceeds 100 columns
#47718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32433:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32434:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32435:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32436:
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#47722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32437:
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#47723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32438:
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#47724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32439:
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#47725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32440:
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc

WARNING: line length of 114 exceeds 100 columns
#47726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32441:
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#47727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32442:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#47728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32443:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15

WARNING: line length of 114 exceeds 100 columns
#47729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32444:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16

WARNING: line length of 114 exceeds 100 columns
#47730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32445:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17

WARNING: line length of 114 exceeds 100 columns
#47731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32446:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18

WARNING: line length of 114 exceeds 100 columns
#47732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32447:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19

WARNING: line length of 114 exceeds 100 columns
#47733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32448:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#47734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32449:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b

WARNING: line length of 114 exceeds 100 columns
#47735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32450:
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#47736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32451:
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32452:
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32453:
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32454:
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32455:
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32456:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32457:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#47743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32458:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L

WARNING: line length of 121 exceeds 100 columns
#47744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32459:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L

WARNING: line length of 121 exceeds 100 columns
#47745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32460:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32461:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#47747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32462:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L

WARNING: line length of 121 exceeds 100 columns
#47748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32463:
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L

WARNING: line length of 121 exceeds 100 columns
#47749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32464:
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#47750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32465:
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#47751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32466:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#47752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32467:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#47753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32468:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5

WARNING: line length of 113 exceeds 100 columns
#47754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32469:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#47755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32470:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#47756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32471:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#47757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32472:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#47758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32473:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#47759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32474:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#47760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32475:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#47761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32476:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd

WARNING: line length of 113 exceeds 100 columns
#47762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32477:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe

WARNING: line length of 113 exceeds 100 columns
#47763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32478:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf

WARNING: line length of 114 exceeds 100 columns
#47764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32479:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#47765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32480:
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32481:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32482:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32483:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32484:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32485:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32486:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32487:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#47773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32488:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#47774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32489:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#47775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32490:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32491:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#47777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32492:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#47778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32493:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32494:
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32495:
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#47781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32496:
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#47782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32497:
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#47783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32498:
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32499:
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#47785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32500:
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#47786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32501:
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32502:
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32503:
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#47789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32504:
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#47790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32505:
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#47791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32506:
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32507:
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#47793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32508:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#47794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32509:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#47795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32510:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#47796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32511:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d

WARNING: line length of 121 exceeds 100 columns
#47797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32512:
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32513:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#47799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32514:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#47800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32515:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#47801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32516:
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L

WARNING: line length of 113 exceeds 100 columns
#47802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32517:
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#47803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32518:
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#47804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32519:
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#47805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32520:
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#47806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32521:
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#47807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32522:
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#47808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32523:
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#47809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32524:
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#47810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32525:
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#47811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32526:
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#47812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32527:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#47813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32528:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#47814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32529:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#47815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32530:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#47816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32531:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#47817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32532:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32533:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32534:
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#47820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32535:
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#47821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32536:
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a

WARNING: line length of 121 exceeds 100 columns
#47822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32537:
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#47823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32538:
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#47824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32539:
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#47825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32540:
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#47826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32541:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#47827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32542:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#47828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32543:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#47829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32544:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#47830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32545:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32546:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32547:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#47833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32548:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32549:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#47835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32550:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#47836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32551:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#47837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32552:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#47838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32553:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32554:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32555:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#47841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32556:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32557:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#47843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32558:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#47844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32559:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#47845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32560:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#47846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32561:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32562:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32563:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#47849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32564:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32565:
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#47851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32566:
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8

WARNING: line length of 121 exceeds 100 columns
#47852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32567:
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#47853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32568:
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#47854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32569:
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#47855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32570:
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#47856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32571:
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32572:
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L

WARNING: line length of 113 exceeds 100 columns
#47858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32573:
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#47859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32574:
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#47860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32575:
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#47861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32576:
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32577:
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32578:
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#47864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32579:
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#47865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32580:
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf

WARNING: line length of 114 exceeds 100 columns
#47866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32581:
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#47867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32582:
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#47868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32583:
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32584:
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L

WARNING: line length of 113 exceeds 100 columns
#47870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32585:
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#47871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32586:
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L

WARNING: line length of 113 exceeds 100 columns
#47872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32587:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#47873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32588:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#47874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32589:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#47875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32590:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#47876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32591:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32592:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32593:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#47879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32594:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32595:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#47881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32596:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#47882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32597:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#47883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32598:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#47884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32599:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32600:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32601:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#47887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32602:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32603:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#47889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32604:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#47890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32605:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#47891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32606:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#47892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32607:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#47893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32608:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#47894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32609:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#47895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32610:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#47896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32611:
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#47897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32612:
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L

WARNING: line length of 113 exceeds 100 columns
#47898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32613:
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#47899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32614:
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#47900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32615:
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32616:
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32617:
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#47903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32618:
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#47904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32619:
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32620:
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32621:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#47907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32622:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#47908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32623:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#47909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32624:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#47910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32625:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#47911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32626:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32627:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#47913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32628:
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#47914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32629:
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#47915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32630:
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#47916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32631:
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#47917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32632:
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#47918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32633:
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#47919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32634:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#47920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32635:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#47921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32636:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc

WARNING: line length of 114 exceeds 100 columns
#47922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32637:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#47923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32638:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#47924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32639:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#47925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32640:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#47926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32641:
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#47927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32642:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#47928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32643:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#47929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32644:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#47930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32645:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#47931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32646:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#47932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32647:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#47933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32648:
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#47934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32649:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#47935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32650:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#47936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32651:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#47937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32652:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc

WARNING: line length of 114 exceeds 100 columns
#47938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32653:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#47939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32654:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#47940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32655:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#47941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32656:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#47942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32657:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#47943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32658:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#47944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32659:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#47945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32660:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#47946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32661:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#47947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32662:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#47948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32663:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#47949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32664:
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#47950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32665:
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#47951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32666:
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L

WARNING: line length of 113 exceeds 100 columns
#47952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32667:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#47953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32668:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#47954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32669:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#47955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32670:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#47956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32671:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#47957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32672:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#47958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32673:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#47959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32674:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#47960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32675:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#47961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32676:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#47962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32677:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#47963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32678:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#47964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32679:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#47965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32680:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#47966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32681:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 113 exceeds 100 columns
#47967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32682:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf

WARNING: line length of 114 exceeds 100 columns
#47968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32683:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#47969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32684:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#47970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32685:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12

WARNING: line length of 114 exceeds 100 columns
#47971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32686:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#47972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32687:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#47973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32688:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#47974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32689:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16

WARNING: line length of 114 exceeds 100 columns
#47975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32690:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#47976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32691:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#47977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32692:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#47978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32693:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a

WARNING: line length of 114 exceeds 100 columns
#47979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32694:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b

WARNING: line length of 114 exceeds 100 columns
#47980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32695:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#47981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32696:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#47982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32697:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#47983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32698:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#47984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32699:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#47985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32700:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#47986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32701:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#47987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32702:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#47988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32703:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#47989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32704:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#47990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32705:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#47991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32706:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#47992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32707:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#47993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32708:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#47994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32709:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#47995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32710:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#47996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32711:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#47997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32712:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#47998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32713:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#47999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32714:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32715:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32716:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32717:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32718:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#48004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32719:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32720:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32721:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32722:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32723:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#48009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32724:
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#48010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32725:
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#48011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32726:
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#48012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32727:
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32728:
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32729:
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#48015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32730:
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#48016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32731:
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32732:
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32733:
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#48019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32734:
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#48020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32735:
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32736:
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32737:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#48023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32738:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#48024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32739:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#48025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32740:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12

WARNING: line length of 114 exceeds 100 columns
#48026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32741:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#48027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32742:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#48028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32743:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#48029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32744:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#48030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32745:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#48031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32746:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#48032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32747:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19

WARNING: line length of 114 exceeds 100 columns
#48033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32748:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#48034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32749:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b

WARNING: line length of 121 exceeds 100 columns
#48035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32750:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32751:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32752:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32753:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32754:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32755:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32756:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32757:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#48043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32758:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32759:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32760:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32761:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32762:
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L

WARNING: line length of 113 exceeds 100 columns
#48048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32763:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#48049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32764:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#48050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32765:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#48051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32766:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#48052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32767:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#48053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32768:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#48054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32769:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#48055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32770:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd

WARNING: line length of 114 exceeds 100 columns
#48056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32771:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#48057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32772:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#48058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32773:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14

WARNING: line length of 114 exceeds 100 columns
#48059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32774:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#48060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32775:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#48061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32776:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#48062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32777:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#48063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32778:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d

WARNING: line length of 121 exceeds 100 columns
#48064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32779:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32780:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32781:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32782:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32783:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32784:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32785:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32786:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32787:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32788:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32789:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32790:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32791:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32792:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32793:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#48079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32794:
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L

WARNING: line length of 113 exceeds 100 columns
#48080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32795:
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#48081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32796:
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#48082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32797:
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5

WARNING: line length of 113 exceeds 100 columns
#48083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32798:
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#48084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32799:
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#48085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32800:
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf

WARNING: line length of 114 exceeds 100 columns
#48086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32801:
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10

WARNING: line length of 114 exceeds 100 columns
#48087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32802:
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11

WARNING: line length of 121 exceeds 100 columns
#48088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32803:
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32804:
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32805:
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32806:
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32807:
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32808:
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#48094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32809:
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32810:
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L

WARNING: line length of 113 exceeds 100 columns
#48096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32811:
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#48097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32812:
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#48098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32813:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#48099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32814:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#48100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32815:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#48101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32816:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#48102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32817:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#48103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32818:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#48104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32819:
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#48105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32820:
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32821:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32822:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32823:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32824:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32825:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#48111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32826:
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32827:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#48113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32828:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#48114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32829:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4

WARNING: line length of 114 exceeds 100 columns
#48115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32830:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10

WARNING: line length of 121 exceeds 100 columns
#48116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32831:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32832:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32833:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#48119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32834:
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32835:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#48121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32836:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#48122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32837:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#48123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32838:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#48124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32839:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#48125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32840:
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#48126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32841:
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#48127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32842:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#48128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32843:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#48129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32844:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32845:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32846:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32847:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32848:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32849:
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32850:
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32851:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#48137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32852:
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32853:
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#48139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32854:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#48140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32855:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#48141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32856:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#48142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32857:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#48143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32858:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#48144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32859:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#48145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32860:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#48146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32861:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#48147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32862:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#48148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32863:
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#48149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32864:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32865:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32866:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32867:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32868:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32869:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32870:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32871:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32872:
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32873:
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#48159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32874:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#48160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32875:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#48161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32876:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#48162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32877:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#48163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32878:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#48164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32879:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#48165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32880:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#48166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32881:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#48167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32882:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#48168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32883:
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#48169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32884:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32885:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32886:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32887:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32888:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32889:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32890:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32891:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32892:
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32893:
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#48179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32894:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#48180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32895:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#48181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32896:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#48182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32897:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#48183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32898:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#48184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32899:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#48185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32900:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#48186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32901:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#48187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32902:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#48188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32903:
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#48189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32904:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32905:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32906:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32907:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32908:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32909:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32910:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32911:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32912:
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32913:
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#48199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32914:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#48200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32915:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#48201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32916:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#48202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32917:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#48203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32918:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#48204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32919:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#48205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32920:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#48206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32921:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#48207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32922:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#48208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32923:
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#48209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32924:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32925:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32926:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32927:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32928:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32929:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32930:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32931:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32932:
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32933:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#48219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32934:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#48220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32935:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#48221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32936:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#48222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32937:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#48223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32938:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#48224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32939:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#48225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32940:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#48226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32941:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#48227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32942:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#48228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32943:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#48229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32944:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb

WARNING: line length of 121 exceeds 100 columns
#48230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32945:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32946:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32947:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32948:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32949:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32950:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32951:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32952:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32953:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32954:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32955:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#48241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32956:
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L

WARNING: line length of 113 exceeds 100 columns
#48242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32957:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#48243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32958:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#48244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32959:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#48245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32960:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#48246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32961:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#48247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32962:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L

WARNING: line length of 121 exceeds 100 columns
#48248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32963:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L

WARNING: line length of 121 exceeds 100 columns
#48249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32964:
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#48250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32965:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#48251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32966:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7

WARNING: line length of 114 exceeds 100 columns
#48252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32967:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#48253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32968:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#48254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32969:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12

WARNING: line length of 114 exceeds 100 columns
#48255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32970:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13

WARNING: line length of 114 exceeds 100 columns
#48256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32971:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#48257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32972:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#48258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32973:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32974:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32975:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32976:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32977:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32978:
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#48264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32979:
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#48265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32980:
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#48266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32981:
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32982:
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32983:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#48269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32984:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#48270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32985:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3

WARNING: line length of 113 exceeds 100 columns
#48271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32986:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#48272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32987:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#48273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32988:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6

WARNING: line length of 114 exceeds 100 columns
#48274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32989:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#48275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32990:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32991:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32992:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32993:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32994:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32995:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32996:
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#48282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32997:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#48283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32998:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#48284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:32999:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#48285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33000:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#48286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33001:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8

WARNING: line length of 114 exceeds 100 columns
#48287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33002:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#48288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33003:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33004:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33005:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33006:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33007:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#48293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33008:
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33009:
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#48295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33010:
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#48296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33011:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#48297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33012:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#48298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33013:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#48299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33014:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#48300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33015:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#48301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33016:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#48302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33017:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#48303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33018:
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#48304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33019:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#48305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33020:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#48306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33021:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#48307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33022:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#48308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33023:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#48309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33024:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#48310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33025:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#48311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33026:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#48312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33027:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#48313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33028:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#48314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33029:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#48315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33030:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#48316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33031:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#48317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33032:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#48318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33033:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#48319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33034:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#48320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33035:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#48321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33036:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#48322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33037:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#48323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33038:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#48324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33039:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#48325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33040:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#48326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33041:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#48327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33042:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#48328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33043:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#48329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33044:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#48330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33045:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#48331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33046:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#48332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33047:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#48333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33048:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#48334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33049:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33050:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33051:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33052:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33053:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33054:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33055:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33056:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33057:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33058:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33059:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#48345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33060:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#48346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33061:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33062:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33063:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33064:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33065:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33066:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33067:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33068:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33069:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33070:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#48356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33071:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33072:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33073:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33074:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33075:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#48361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33076:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#48362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33077:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#48363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33078:
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#48364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33079:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#48365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33080:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#48366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33081:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#48367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33082:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#48368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33083:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#48369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33084:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#48370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33085:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#48371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33086:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#48372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33087:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#48373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33088:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#48374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33089:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#48375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33090:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#48376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33091:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#48377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33092:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#48378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33093:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#48379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33094:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#48380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33095:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#48381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33096:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#48382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33097:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#48383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33098:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#48384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33099:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#48385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33100:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#48386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33101:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#48387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33102:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#48388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33103:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#48389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33104:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#48390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33105:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#48391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33106:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#48392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33107:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#48393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33108:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#48394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33109:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33110:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33111:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33112:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33113:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33114:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33115:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33116:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33117:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33118:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33119:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#48405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33120:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#48406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33121:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33122:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33123:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33124:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33125:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33126:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33127:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33128:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33129:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33130:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#48416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33131:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33132:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33133:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33134:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33135:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#48421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33136:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#48422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33137:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#48423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33138:
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#48424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33139:
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#48425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33140:
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#48426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33141:
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#48427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33142:
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33143:
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33144:
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#48430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33145:
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#48431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33146:
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#48432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33147:
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#48433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33148:
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33149:
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33150:
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#48436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33151:
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#48437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33152:
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#48438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33153:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#48439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33154:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#48440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33155:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#48441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33156:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#48442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33157:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#48443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33158:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#48444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33159:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#48445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33160:
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#48446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33161:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#48447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33162:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#48448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33163:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#48449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33164:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#48450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33165:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#48451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33166:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#48452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33167:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#48453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33168:
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#48454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33169:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#48455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33170:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#48456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33171:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#48457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33172:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#48458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33173:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#48459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33174:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#48460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33175:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33176:
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#48462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33177:
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd

WARNING: line length of 114 exceeds 100 columns
#48463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33178:
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#48464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33179:
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#48465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33180:
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33181:
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#48467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33182:
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L

WARNING: line length of 113 exceeds 100 columns
#48468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33183:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#48469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33184:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#48470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33185:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#48471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33186:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#48472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33187:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#48473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33188:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#48474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33189:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33190:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33191:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#48477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33192:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#48478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33193:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33194:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L

WARNING: line length of 113 exceeds 100 columns
#48480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33195:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#48481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33196:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#48482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33197:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb

WARNING: line length of 114 exceeds 100 columns
#48483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33198:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#48484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33199:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#48485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33200:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#48486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33201:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L

WARNING: line length of 121 exceeds 100 columns
#48487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33202:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L

WARNING: line length of 121 exceeds 100 columns
#48488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33203:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#48489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33204:
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#48490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33205:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#48491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33206:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#48492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33207:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#48493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33208:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#48494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33209:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#48495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33210:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L

WARNING: line length of 121 exceeds 100 columns
#48496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33211:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#48497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33212:
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L

WARNING: line length of 113 exceeds 100 columns
#48498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33213:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#48499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33214:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#48500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33215:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#48501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33216:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#48502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33217:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6

WARNING: line length of 113 exceeds 100 columns
#48503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33218:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#48504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33219:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#48505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33220:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#48506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33221:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#48507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33222:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#48508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33223:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33224:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33225:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33226:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L

WARNING: line length of 121 exceeds 100 columns
#48512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33227:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#48513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33228:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#48514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33229:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#48515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33230:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#48516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33231:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#48517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33232:
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#48518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33233:
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#48519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33234:
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4

WARNING: line length of 114 exceeds 100 columns
#48520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33235:
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#48521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33236:
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#48522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33237:
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#48523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33238:
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#48524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33239:
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#48525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33240:
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33241:
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33242:
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#48528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33243:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#48529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33244:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#48530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33245:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#48531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33246:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#48532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33247:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#48533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33248:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33249:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33250:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33251:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#48537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33252:
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33253:
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#48539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33254:
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#48540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33255:
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#48541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33256:
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#48542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33257:
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#48543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33258:
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#48544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33259:
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#48545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33260:
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#48546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33261:
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#48547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33262:
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#48548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33263:
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#48549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33264:
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#48550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33265:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#48551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33266:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#48552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33267:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#48553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33268:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc

WARNING: line length of 114 exceeds 100 columns
#48554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33269:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#48555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33270:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#48556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33271:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#48557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33272:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#48558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33273:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#48559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33274:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#48560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33275:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#48561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33276:
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#48562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33277:
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#48563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33278:
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8

WARNING: line length of 121 exceeds 100 columns
#48564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33279:
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33280:
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#48566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33281:
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#48567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33282:
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#48568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33283:
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#48569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33284:
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#48570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33285:
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33286:
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33287:
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33288:
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#48574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33289:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#48575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33290:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4

WARNING: line length of 113 exceeds 100 columns
#48576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33291:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb

WARNING: line length of 113 exceeds 100 columns
#48577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33292:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#48578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33293:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#48579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33294:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17

WARNING: line length of 114 exceeds 100 columns
#48580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33295:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18

WARNING: line length of 114 exceeds 100 columns
#48581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33296:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#48582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33297:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e

WARNING: line length of 121 exceeds 100 columns
#48583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33298:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33299:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33300:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#48586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33301:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33302:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33303:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33304:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33305:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33306:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L

WARNING: line length of 113 exceeds 100 columns
#48592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33307:
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#48593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33308:
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7

WARNING: line length of 121 exceeds 100 columns
#48594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33309:
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33310:
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L

WARNING: line length of 113 exceeds 100 columns
#48596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33311:
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#48597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33312:
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L

WARNING: line length of 113 exceeds 100 columns
#48598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33313:
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#48599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33314:
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#48600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33315:
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#48601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33316:
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33317:
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#48603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33318:
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L

WARNING: line length of 113 exceeds 100 columns
#48604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33319:
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#48605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33320:
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#48606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33321:
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#48607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33322:
+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#48608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33323:
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#48609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33324:
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#48610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33325:
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#48611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33326:
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#48612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33327:
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#48613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33328:
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#48614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33329:
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33330:
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33331:
+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33332:
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33333:
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33334:
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33335:
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33336:
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#48622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33337:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#48623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33338:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#48624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33339:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#48625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33340:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#48626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33341:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#48627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33342:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33343:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#48629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33344:
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#48630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33345:
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#48631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33346:
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#48632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33347:
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#48633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33348:
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#48634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33349:
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf

WARNING: line length of 114 exceeds 100 columns
#48635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33350:
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#48636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33351:
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14

WARNING: line length of 121 exceeds 100 columns
#48637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33352:
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#48638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33353:
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L

WARNING: line length of 121 exceeds 100 columns
#48639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33354:
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33355:
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#48641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33356:
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#48642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33357:
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#48643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33358:
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L

WARNING: line length of 113 exceeds 100 columns
#48644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33359:
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#48645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33360:
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#48646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33361:
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8

WARNING: line length of 121 exceeds 100 columns
#48647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33362:
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33363:
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33364:
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L

WARNING: line length of 113 exceeds 100 columns
#48650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33365:
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#48651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33366:
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#48652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33367:
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#48653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33368:
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL

WARNING: line length of 113 exceeds 100 columns
#48654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33369:
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#48655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33370:
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#48656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33371:
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#48657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33372:
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#48658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33373:
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6

WARNING: line length of 114 exceeds 100 columns
#48659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33374:
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#48660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33375:
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33376:
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33377:
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33378:
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33379:
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33380:
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#48666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33381:
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#48667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33382:
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#48668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33383:
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#48669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33384:
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#48670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33385:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#48671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33386:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#48672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33387:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#48673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33388:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#48674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33389:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#48675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33390:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#48676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33391:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#48677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33392:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33393:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33394:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#48680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33395:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33396:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33397:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33398:
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L

WARNING: line length of 113 exceeds 100 columns
#48684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33399:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#48685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33400:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#48686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33401:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa

WARNING: line length of 114 exceeds 100 columns
#48687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33402:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#48688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33403:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#48689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33404:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e

WARNING: line length of 114 exceeds 100 columns
#48690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33405:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#48691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33406:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33407:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL

WARNING: line length of 121 exceeds 100 columns
#48693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33408:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#48694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33409:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L

WARNING: line length of 121 exceeds 100 columns
#48695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33410:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#48696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33411:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L

WARNING: line length of 121 exceeds 100 columns
#48697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33412:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#48698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33413:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#48699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33414:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#48700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33415:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#48701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33416:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#48702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33417:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33418:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33419:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33420:
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33421:
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#48707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33422:
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#48708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33423:
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2

WARNING: line length of 113 exceeds 100 columns
#48709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33424:
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#48710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33425:
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#48711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33426:
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#48712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33427:
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9

WARNING: line length of 114 exceeds 100 columns
#48713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33428:
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#48714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33429:
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#48715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33430:
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#48716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33431:
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33432:
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33433:
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33434:
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33435:
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33436:
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33437:
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33438:
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#48724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33439:
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33440:
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L

WARNING: line length of 113 exceeds 100 columns
#48726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33441:
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0

WARNING: line length of 114 exceeds 100 columns
#48727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33442:
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#48728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33443:
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#48729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33444:
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b

WARNING: line length of 121 exceeds 100 columns
#48730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33445:
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33446:
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33447:
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33448:
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L

WARNING: line length of 113 exceeds 100 columns
#48734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33449:
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4

WARNING: line length of 121 exceeds 100 columns
#48735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33450:
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#48736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33451:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#48737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33452:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#48738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33453:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#48739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33454:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#48740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33455:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc

WARNING: line length of 114 exceeds 100 columns
#48741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33456:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#48742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33457:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#48743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33458:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33459:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33460:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#48746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33461:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33462:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33463:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L

WARNING: line length of 121 exceeds 100 columns
#48749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33464:
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#48750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33465:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#48751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33466:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#48752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33467:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#48753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33468:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#48754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33469:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#48755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33470:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#48756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33471:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#48757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33472:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#48758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33473:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33474:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33475:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33476:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33477:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33478:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33479:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L

WARNING: line length of 121 exceeds 100 columns
#48765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33480:
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#48766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33481:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#48767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33482:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#48768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33483:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8

WARNING: line length of 113 exceeds 100 columns
#48769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33484:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9

WARNING: line length of 121 exceeds 100 columns
#48770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33485:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33486:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33487:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33488:
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L

WARNING: line length of 113 exceeds 100 columns
#48774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33489:
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#48775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33490:
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#48776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33491:
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#48777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33492:
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L

WARNING: line length of 113 exceeds 100 columns
#48778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33493:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#48779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33494:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#48780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33495:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#48781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33496:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#48782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33497:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#48783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33498:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#48784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33499:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#48785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33500:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#48786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33501:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#48787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33502:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#48788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33503:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#48789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33504:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb

WARNING: line length of 113 exceeds 100 columns
#48790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33505:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#48791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33506:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#48792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33507:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#48793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33508:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf

WARNING: line length of 114 exceeds 100 columns
#48794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33509:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#48795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33510:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11

WARNING: line length of 114 exceeds 100 columns
#48796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33511:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#48797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33512:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13

WARNING: line length of 114 exceeds 100 columns
#48798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33513:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#48799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33514:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15

WARNING: line length of 114 exceeds 100 columns
#48800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33515:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#48801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33516:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17

WARNING: line length of 114 exceeds 100 columns
#48802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33517:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#48803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33518:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#48804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33519:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a

WARNING: line length of 114 exceeds 100 columns
#48805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33520:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b

WARNING: line length of 114 exceeds 100 columns
#48806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33521:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#48807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33522:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d

WARNING: line length of 114 exceeds 100 columns
#48808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33523:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e

WARNING: line length of 114 exceeds 100 columns
#48809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33524:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f

WARNING: line length of 121 exceeds 100 columns
#48810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33525:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33526:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33527:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33528:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33529:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33530:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33531:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33532:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33533:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33534:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33535:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#48821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33536:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#48822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33537:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33538:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33539:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33540:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#48826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33541:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33542:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33543:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33544:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33545:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33546:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33547:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#48833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33548:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33549:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33550:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33551:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33552:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L

WARNING: line length of 121 exceeds 100 columns
#48838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33553:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#48839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33554:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L

WARNING: line length of 121 exceeds 100 columns
#48840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33555:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#48841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33556:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#48842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33557:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#48843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33558:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#48844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33559:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#48845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33560:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#48846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33561:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#48847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33562:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#48848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33563:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#48849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33564:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7

WARNING: line length of 113 exceeds 100 columns
#48850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33565:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#48851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33566:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9

WARNING: line length of 113 exceeds 100 columns
#48852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33567:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#48853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33568:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb

WARNING: line length of 113 exceeds 100 columns
#48854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33569:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#48855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33570:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#48856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33571:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe

WARNING: line length of 113 exceeds 100 columns
#48857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33572:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf

WARNING: line length of 114 exceeds 100 columns
#48858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33573:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#48859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33574:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11

WARNING: line length of 114 exceeds 100 columns
#48860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33575:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12

WARNING: line length of 114 exceeds 100 columns
#48861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33576:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13

WARNING: line length of 114 exceeds 100 columns
#48862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33577:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#48863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33578:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15

WARNING: line length of 114 exceeds 100 columns
#48864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33579:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#48865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33580:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17

WARNING: line length of 114 exceeds 100 columns
#48866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33581:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#48867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33582:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19

WARNING: line length of 114 exceeds 100 columns
#48868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33583:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#48869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33584:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b

WARNING: line length of 121 exceeds 100 columns
#48870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33585:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33586:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33587:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33588:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33589:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33590:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33591:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33592:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33593:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33594:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33595:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#48881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33596:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L

WARNING: line length of 121 exceeds 100 columns
#48882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33597:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33598:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33599:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33600:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#48886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33601:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33602:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33603:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33604:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33605:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33606:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33607:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#48893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33608:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33609:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33610:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33611:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33612:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L

WARNING: line length of 113 exceeds 100 columns
#48898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33613:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#48899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33614:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#48900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33615:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#48901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33616:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#48902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33617:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#48903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33618:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5

WARNING: line length of 113 exceeds 100 columns
#48904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33619:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#48905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33620:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7

WARNING: line length of 113 exceeds 100 columns
#48906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33621:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#48907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33622:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9

WARNING: line length of 113 exceeds 100 columns
#48908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33623:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#48909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33624:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb

WARNING: line length of 113 exceeds 100 columns
#48910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33625:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc

WARNING: line length of 113 exceeds 100 columns
#48911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33626:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd

WARNING: line length of 113 exceeds 100 columns
#48912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33627:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe

WARNING: line length of 113 exceeds 100 columns
#48913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33628:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf

WARNING: line length of 114 exceeds 100 columns
#48914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33629:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#48915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33630:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11

WARNING: line length of 114 exceeds 100 columns
#48916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33631:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#48917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33632:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13

WARNING: line length of 114 exceeds 100 columns
#48918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33633:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#48919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33634:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15

WARNING: line length of 114 exceeds 100 columns
#48920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33635:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16

WARNING: line length of 114 exceeds 100 columns
#48921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33636:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17

WARNING: line length of 114 exceeds 100 columns
#48922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33637:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18

WARNING: line length of 114 exceeds 100 columns
#48923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33638:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19

WARNING: line length of 114 exceeds 100 columns
#48924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33639:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#48925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33640:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b

WARNING: line length of 114 exceeds 100 columns
#48926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33641:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#48927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33642:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d

WARNING: line length of 121 exceeds 100 columns
#48928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33643:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33644:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#48930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33645:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33646:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#48932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33647:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33648:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#48934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33649:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#48935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33650:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#48936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33651:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#48937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33652:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#48938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33653:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#48939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33654:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#48940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33655:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#48941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33656:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#48942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33657:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#48943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33658:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L

WARNING: line length of 121 exceeds 100 columns
#48944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33659:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#48945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33660:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#48946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33661:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#48947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33662:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#48948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33663:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#48949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33664:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#48950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33665:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#48951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33666:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L

WARNING: line length of 121 exceeds 100 columns
#48952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33667:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L

WARNING: line length of 121 exceeds 100 columns
#48953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33668:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#48954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33669:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#48955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33670:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#48956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33671:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#48957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33672:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L

WARNING: line length of 113 exceeds 100 columns
#48958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33673:
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#48959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33674:
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#48960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33675:
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#48961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33676:
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8

WARNING: line length of 113 exceeds 100 columns
#48962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33677:
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc

WARNING: line length of 121 exceeds 100 columns
#48963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33678:
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#48964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33679:
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#48965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33680:
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#48966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33681:
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#48967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33682:
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L

WARNING: line length of 113 exceeds 100 columns
#48968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33683:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#48969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33684:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#48970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33685:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33686:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33687:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#48973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33688:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#48974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33689:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33690:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33691:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#48977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33692:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#48978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33693:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33694:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33695:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#48981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33696:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#48982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33697:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33698:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33699:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#48985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33700:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#48986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33701:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33702:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33703:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#48989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33704:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#48990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33705:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33706:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33707:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0

WARNING: line length of 114 exceeds 100 columns
#48993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33708:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#48994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33709:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#48995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33710:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#48996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33711:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#48997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33712:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#48998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33713:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11

WARNING: line length of 114 exceeds 100 columns
#48999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33714:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12

WARNING: line length of 114 exceeds 100 columns
#49000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33715:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13

WARNING: line length of 114 exceeds 100 columns
#49001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33716:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14

WARNING: line length of 114 exceeds 100 columns
#49002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33717:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15

WARNING: line length of 114 exceeds 100 columns
#49003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33718:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16

WARNING: line length of 114 exceeds 100 columns
#49004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33719:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17

WARNING: line length of 114 exceeds 100 columns
#49005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33720:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18

WARNING: line length of 114 exceeds 100 columns
#49006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33721:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19

WARNING: line length of 114 exceeds 100 columns
#49007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33722:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a

WARNING: line length of 114 exceeds 100 columns
#49008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33723:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b

WARNING: line length of 114 exceeds 100 columns
#49009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33724:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c

WARNING: line length of 114 exceeds 100 columns
#49010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33725:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d

WARNING: line length of 114 exceeds 100 columns
#49011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33726:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e

WARNING: line length of 121 exceeds 100 columns
#49012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33727:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33728:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33729:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#49015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33730:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#49016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33731:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#49017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33732:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#49018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33733:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L

WARNING: line length of 121 exceeds 100 columns
#49019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33734:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L

WARNING: line length of 121 exceeds 100 columns
#49020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33735:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L

WARNING: line length of 121 exceeds 100 columns
#49021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33736:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#49022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33737:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L

WARNING: line length of 121 exceeds 100 columns
#49023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33738:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L

WARNING: line length of 121 exceeds 100 columns
#49024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33739:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L

WARNING: line length of 121 exceeds 100 columns
#49025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33740:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#49026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33741:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#49027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33742:
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L

WARNING: line length of 113 exceeds 100 columns
#49028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33743:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#49029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33744:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#49030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33745:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#49031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33746:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#49032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33747:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#49033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33748:
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf

WARNING: line length of 114 exceeds 100 columns
#49034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33749:
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#49035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33750:
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#49036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33751:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33752:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33753:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33754:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33755:
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33756:
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#49042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33757:
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33758:
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#49044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33759:
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#49045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33760:
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#49046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33761:
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#49047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33762:
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#49048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33763:
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#49049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33764:
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#49050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33765:
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#49051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33766:
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#49052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33767:
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc

WARNING: line length of 121 exceeds 100 columns
#49053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33768:
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#49054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33769:
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#49055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33770:
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#49056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33771:
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc

WARNING: line length of 121 exceeds 100 columns
#49057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33772:
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#49058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33773:
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#49059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33774:
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#49060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33775:
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#49061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33776:
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8

WARNING: line length of 121 exceeds 100 columns
#49062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33777:
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33778:
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#49064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33779:
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33780:
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#49066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33781:
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#49067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33782:
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#49068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33783:
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#49069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33784:
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33785:
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33786:
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33787:
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#49073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33788:
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#49074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33789:
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0

WARNING: line length of 121 exceeds 100 columns
#49075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33790:
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#49076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33791:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#49077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33792:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#49078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33793:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#49079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33794:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3

WARNING: line length of 121 exceeds 100 columns
#49080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33795:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33796:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33797:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33798:
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L

WARNING: line length of 113 exceeds 100 columns
#49084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33799:
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#49085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33800:
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8

WARNING: line length of 121 exceeds 100 columns
#49086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33801:
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#49087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33802:
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#49088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33803:
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#49089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33804:
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L

WARNING: line length of 113 exceeds 100 columns
#49090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33805:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#49091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33806:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#49092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33807:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33808:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#49094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33809:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#49095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33810:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#49096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33811:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33812:
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#49098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33813:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#49099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33814:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#49100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33815:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#49101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33816:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#49102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33817:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33818:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33819:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33820:
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L

WARNING: line length of 113 exceeds 100 columns
#49106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33821:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#49107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33822:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#49108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33823:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#49109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33824:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#49110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33825:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18

WARNING: line length of 121 exceeds 100 columns
#49111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33826:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33827:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L

WARNING: line length of 121 exceeds 100 columns
#49113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33828:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33829:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#49115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33830:
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L

WARNING: line length of 113 exceeds 100 columns
#49116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33831:
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0

WARNING: line length of 114 exceeds 100 columns
#49117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33832:
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#49118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33833:
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33834:
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#49120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33835:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#49121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33836:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#49122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33837:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#49123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33838:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#49124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33839:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#49125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33840:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#49126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33841:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#49127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33842:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#49128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33843:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#49129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33844:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#49130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33845:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#49131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33846:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#49132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33847:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#49133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33848:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#49134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33849:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#49135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33850:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#49136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33851:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#49137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33852:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33853:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#49139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33854:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#49140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33855:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#49141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33856:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33857:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#49143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33858:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#49144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33859:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#49145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33860:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#49146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33861:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#49147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33862:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#49148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33863:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#49149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33864:
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#49150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33865:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#49151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33866:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#49152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33867:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#49153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33868:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#49154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33869:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#49155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33870:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#49156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33871:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#49157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33872:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#49158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33873:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#49159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33874:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17

WARNING: line length of 114 exceeds 100 columns
#49160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33875:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#49161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33876:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#49162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33877:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b

WARNING: line length of 114 exceeds 100 columns
#49163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33878:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c

WARNING: line length of 121 exceeds 100 columns
#49164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33879:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#49165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33880:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L

WARNING: line length of 121 exceeds 100 columns
#49166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33881:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33882:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#49168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33883:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#49169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33884:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#49170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33885:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33886:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#49172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33887:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L

WARNING: line length of 121 exceeds 100 columns
#49173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33888:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#49174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33889:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L

WARNING: line length of 121 exceeds 100 columns
#49175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33890:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#49176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33891:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#49177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33892:
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L

WARNING: line length of 113 exceeds 100 columns
#49178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33893:
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#49179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33894:
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#49180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33895:
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#49181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33896:
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8

WARNING: line length of 121 exceeds 100 columns
#49182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33897:
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33898:
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L

WARNING: line length of 113 exceeds 100 columns
#49184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33899:
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#49185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33900:
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#49186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33901:
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e

WARNING: line length of 121 exceeds 100 columns
#49187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33902:
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33903:
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L

WARNING: line length of 121 exceeds 100 columns
#49189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33904:
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L

WARNING: line length of 114 exceeds 100 columns
#49190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33905:
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#49191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33906:
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#49192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33907:
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#49193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33908:
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#49194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33909:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#49195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33910:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#49196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33911:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#49197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33912:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14

WARNING: line length of 121 exceeds 100 columns
#49198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33913:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33914:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L

WARNING: line length of 121 exceeds 100 columns
#49200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33915:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33916:
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L

WARNING: line length of 113 exceeds 100 columns
#49202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33917:
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33918:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#49204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33919:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#49205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33920:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#49206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33921:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7

WARNING: line length of 113 exceeds 100 columns
#49207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33922:
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#49208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33923:
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#49209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33924:
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#49210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33925:
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33926:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33927:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33928:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33929:
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33930:
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33931:
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33932:
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#49218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33933:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#49219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33934:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#49220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33935:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#49221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33936:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#49222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33937:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#49223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33938:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#49224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33939:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#49225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33940:
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#49226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33941:
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33942:
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4

WARNING: line length of 121 exceeds 100 columns
#49228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33943:
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33944:
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L

WARNING: line length of 113 exceeds 100 columns
#49230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33945:
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#49231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33946:
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8

WARNING: line length of 113 exceeds 100 columns
#49232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33947:
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa

WARNING: line length of 113 exceeds 100 columns
#49233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33948:
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc

WARNING: line length of 114 exceeds 100 columns
#49234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33949:
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18

WARNING: line length of 121 exceeds 100 columns
#49235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33950:
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33951:
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33952:
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#49238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33953:
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#49239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33954:
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#49240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33955:
+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#49241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33956:
+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#49242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33957:
+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#49243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33958:
+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#49244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33959:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#49245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33960:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#49246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33961:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#49247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33962:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#49248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33963:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#49249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33964:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#49250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33965:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#49251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33966:
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L

WARNING: line length of 113 exceeds 100 columns
#49252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33967:
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#49253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33968:
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#49254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33969:
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#49255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33970:
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#49256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33971:
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#49257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33972:
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L

WARNING: line length of 113 exceeds 100 columns
#49258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33973:
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#49259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33974:
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1

WARNING: line length of 113 exceeds 100 columns
#49260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33975:
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2

WARNING: line length of 121 exceeds 100 columns
#49261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33976:
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33977:
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33978:
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L

WARNING: line length of 113 exceeds 100 columns
#49264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33979:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33980:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#49266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33981:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2

WARNING: line length of 113 exceeds 100 columns
#49267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33982:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3

WARNING: line length of 113 exceeds 100 columns
#49268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33983:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#49269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33984:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#49270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33985:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#49271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33986:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#49272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33987:
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#49273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33988:
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#49274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33989:
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18

WARNING: line length of 121 exceeds 100 columns
#49275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33990:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33991:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33992:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33993:
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L

WARNING: line length of 121 exceeds 100 columns
#49279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33994:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33995:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33996:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33997:
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33998:
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:33999:
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34000:
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L

WARNING: line length of 113 exceeds 100 columns
#49286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34001:
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#49287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34002:
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L

WARNING: line length of 113 exceeds 100 columns
#49288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34003:
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#49289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34004:
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#49290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34005:
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#49291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34006:
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34007:
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#49293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34008:
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#49294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34009:
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#49295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34010:
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#49296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34011:
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14

WARNING: line length of 121 exceeds 100 columns
#49297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34012:
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34013:
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L

WARNING: line length of 121 exceeds 100 columns
#49299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34014:
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#49300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34015:
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#49301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34016:
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa

WARNING: line length of 121 exceeds 100 columns
#49302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34017:
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34018:
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L

WARNING: line length of 113 exceeds 100 columns
#49304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34019:
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#49305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34020:
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#49306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34021:
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#49307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34022:
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34023:
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34024:
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L

WARNING: line length of 113 exceeds 100 columns
#49310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34025:
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#49311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34026:
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#49312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34027:
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#49313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34028:
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34029:
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L

WARNING: line length of 121 exceeds 100 columns
#49315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34030:
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L

WARNING: line length of 113 exceeds 100 columns
#49316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34031:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#49317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34032:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#49318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34033:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#49319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34034:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#49320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34035:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34036:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34037:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L

WARNING: line length of 121 exceeds 100 columns
#49323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34038:
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L

WARNING: line length of 113 exceeds 100 columns
#49324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34039:
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#49325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34040:
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#49326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34041:
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#49327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34042:
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34043:
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34044:
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#49330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34045:
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#49331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34046:
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4

WARNING: line length of 114 exceeds 100 columns
#49332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34047:
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#49333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34048:
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34049:
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L

WARNING: line length of 121 exceeds 100 columns
#49335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34050:
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L

WARNING: line length of 113 exceeds 100 columns
#49336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34051:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#49337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34052:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#49338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34053:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#49339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34054:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#49340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34055:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#49341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34056:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#49342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34057:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#49343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34058:
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#49344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34059:
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#49345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34060:
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#49346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34061:
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#49347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34062:
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L

WARNING: line length of 113 exceeds 100 columns
#49348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34063:
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#49349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34064:
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#49350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34065:
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#49351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34066:
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34067:
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34068:
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L

WARNING: line length of 113 exceeds 100 columns
#49354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34069:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34070:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#49356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34071:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2

WARNING: line length of 113 exceeds 100 columns
#49357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34072:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#49358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34073:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#49359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34074:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14

WARNING: line length of 121 exceeds 100 columns
#49360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34075:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34076:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34077:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34078:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34079:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L

WARNING: line length of 121 exceeds 100 columns
#49365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34080:
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#49366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34081:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0

WARNING: line length of 113 exceeds 100 columns
#49367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34082:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#49368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34083:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#49369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34084:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc

WARNING: line length of 121 exceeds 100 columns
#49370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34085:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34086:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34087:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34088:
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#49374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34089:
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#49375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34090:
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#49376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34091:
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#49377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34092:
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc

WARNING: line length of 114 exceeds 100 columns
#49378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34093:
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#49379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34094:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#49380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34095:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15

WARNING: line length of 114 exceeds 100 columns
#49381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34096:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16

WARNING: line length of 114 exceeds 100 columns
#49382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34097:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17

WARNING: line length of 114 exceeds 100 columns
#49383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34098:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18

WARNING: line length of 114 exceeds 100 columns
#49384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34099:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19

WARNING: line length of 114 exceeds 100 columns
#49385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34100:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#49386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34101:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b

WARNING: line length of 114 exceeds 100 columns
#49387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34102:
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#49388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34103:
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34104:
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34105:
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34106:
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34107:
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34108:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#49394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34109:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#49395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34110:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L

WARNING: line length of 121 exceeds 100 columns
#49396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34111:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L

WARNING: line length of 121 exceeds 100 columns
#49397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34112:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#49398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34113:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#49399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34114:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L

WARNING: line length of 121 exceeds 100 columns
#49400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34115:
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L

WARNING: line length of 121 exceeds 100 columns
#49401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34116:
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#49402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34117:
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#49403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34118:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#49404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34119:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#49405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34120:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5

WARNING: line length of 113 exceeds 100 columns
#49406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34121:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#49407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34122:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#49408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34123:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#49409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34124:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#49410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34125:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#49411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34126:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#49412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34127:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#49413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34128:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd

WARNING: line length of 113 exceeds 100 columns
#49414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34129:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe

WARNING: line length of 113 exceeds 100 columns
#49415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34130:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf

WARNING: line length of 114 exceeds 100 columns
#49416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34131:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#49417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34132:
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34133:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34134:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34135:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34136:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34137:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34138:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34139:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#49425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34140:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#49426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34141:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#49427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34142:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34143:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34144:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34145:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#49431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34146:
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34147:
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#49433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34148:
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#49434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34149:
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#49435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34150:
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34151:
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#49437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34152:
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#49438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34153:
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34154:
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34155:
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#49441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34156:
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#49442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34157:
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#49443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34158:
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34159:
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#49445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34160:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#49446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34161:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#49447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34162:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#49448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34163:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d

WARNING: line length of 121 exceeds 100 columns
#49449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34164:
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34165:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#49451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34166:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#49452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34167:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#49453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34168:
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L

WARNING: line length of 113 exceeds 100 columns
#49454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34169:
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#49455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34170:
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#49456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34171:
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#49457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34172:
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#49458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34173:
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#49459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34174:
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#49460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34175:
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#49461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34176:
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#49462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34177:
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#49463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34178:
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#49464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34179:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#49465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34180:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#49466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34181:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#49467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34182:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10

WARNING: line length of 121 exceeds 100 columns
#49468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34183:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#49469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34184:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34185:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#49471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34186:
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#49472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34187:
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#49473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34188:
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a

WARNING: line length of 121 exceeds 100 columns
#49474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34189:
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#49475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34190:
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#49476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34191:
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#49477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34192:
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#49478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34193:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#49479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34194:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#49480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34195:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#49481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34196:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#49482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34197:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34198:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#49484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34199:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#49485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34200:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#49486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34201:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#49487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34202:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#49488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34203:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#49489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34204:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#49490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34205:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34206:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#49492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34207:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#49493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34208:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#49494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34209:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#49495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34210:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#49496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34211:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#49497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34212:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#49498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34213:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34214:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#49500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34215:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L

WARNING: line length of 121 exceeds 100 columns
#49501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34216:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#49502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34217:
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34218:
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8

WARNING: line length of 121 exceeds 100 columns
#49504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34219:
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#49505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34220:
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L

WARNING: line length of 113 exceeds 100 columns
#49506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34221:
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#49507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34222:
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#49508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34223:
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34224:
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L

WARNING: line length of 113 exceeds 100 columns
#49510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34225:
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#49511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34226:
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#49512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34227:
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#49513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34228:
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34229:
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34230:
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L

WARNING: line length of 113 exceeds 100 columns
#49516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34231:
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#49517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34232:
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf

WARNING: line length of 114 exceeds 100 columns
#49518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34233:
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#49519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34234:
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#49520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34235:
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L

WARNING: line length of 121 exceeds 100 columns
#49521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34236:
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L

WARNING: line length of 113 exceeds 100 columns
#49522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34237:
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#49523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34238:
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L

WARNING: line length of 113 exceeds 100 columns
#49524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34239:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#49525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34240:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#49526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34241:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#49527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34242:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#49528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34243:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34244:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#49530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34245:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#49531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34246:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#49532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34247:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#49533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34248:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#49534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34249:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#49535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34250:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#49536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34251:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34252:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#49538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34253:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#49539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34254:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#49540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34255:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#49541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34256:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8

WARNING: line length of 114 exceeds 100 columns
#49542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34257:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#49543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34258:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18

WARNING: line length of 121 exceeds 100 columns
#49544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34259:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#49545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34260:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#49546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34261:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L

WARNING: line length of 121 exceeds 100 columns
#49547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34262:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L

WARNING: line length of 113 exceeds 100 columns
#49548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34263:
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#49549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34264:
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L

WARNING: line length of 113 exceeds 100 columns
#49550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34265:
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#49551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34266:
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#49552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34267:
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34268:
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34269:
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#49555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34270:
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#49556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34271:
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34272:
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34273:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#49559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34274:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#49560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34275:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#49561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34276:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#49562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34277:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#49563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34278:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#49564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34279:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#49565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34280:
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#49566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34281:
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#49567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34282:
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#49568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34283:
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34284:
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34285:
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34286:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#49572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34287:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#49573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34288:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc

WARNING: line length of 114 exceeds 100 columns
#49574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34289:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#49575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34290:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14

WARNING: line length of 114 exceeds 100 columns
#49576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34291:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#49577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34292:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#49578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34293:
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#49579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34294:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#49580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34295:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#49581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34296:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#49582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34297:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#49583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34298:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#49584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34299:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#49585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34300:
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#49586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34301:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34302:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#49588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34303:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#49589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34304:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc

WARNING: line length of 114 exceeds 100 columns
#49590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34305:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#49591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34306:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#49592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34307:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#49593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34308:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#49594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34309:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#49595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34310:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#49596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34311:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#49597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34312:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#49598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34313:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#49599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34314:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#49600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34315:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#49601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34316:
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#49602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34317:
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#49603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34318:
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L

WARNING: line length of 113 exceeds 100 columns
#49604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34319:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#49605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34320:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#49606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34321:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#49607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34322:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#49608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34323:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#49609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34324:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#49610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34325:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#49611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34326:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#49612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34327:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#49613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34328:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#49614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34329:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#49615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34330:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#49616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34331:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#49617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34332:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#49618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34333:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 113 exceeds 100 columns
#49619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34334:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf

WARNING: line length of 114 exceeds 100 columns
#49620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34335:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10

WARNING: line length of 114 exceeds 100 columns
#49621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34336:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#49622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34337:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12

WARNING: line length of 114 exceeds 100 columns
#49623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34338:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#49624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34339:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14

WARNING: line length of 114 exceeds 100 columns
#49625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34340:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#49626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34341:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16

WARNING: line length of 114 exceeds 100 columns
#49627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34342:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#49628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34343:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18

WARNING: line length of 114 exceeds 100 columns
#49629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34344:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#49630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34345:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a

WARNING: line length of 114 exceeds 100 columns
#49631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34346:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b

WARNING: line length of 114 exceeds 100 columns
#49632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34347:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#49633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34348:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34349:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34350:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34351:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#49637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34352:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34353:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34354:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34355:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34356:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34357:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#49643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34358:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#49644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34359:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#49645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34360:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34361:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34362:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34363:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L

WARNING: line length of 121 exceeds 100 columns
#49649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34364:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34365:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#49651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34366:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#49652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34367:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#49653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34368:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#49654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34369:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#49655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34370:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#49656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34371:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#49657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34372:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#49658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34373:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#49659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34374:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#49660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34375:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#49661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34376:
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#49662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34377:
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#49663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34378:
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#49664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34379:
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34380:
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34381:
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#49667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34382:
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#49668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34383:
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34384:
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34385:
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#49671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34386:
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#49672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34387:
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34388:
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34389:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#49675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34390:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#49676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34391:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#49677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34392:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12

WARNING: line length of 114 exceeds 100 columns
#49678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34393:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13

WARNING: line length of 114 exceeds 100 columns
#49679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34394:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#49680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34395:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15

WARNING: line length of 114 exceeds 100 columns
#49681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34396:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#49682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34397:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17

WARNING: line length of 114 exceeds 100 columns
#49683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34398:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#49684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34399:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19

WARNING: line length of 114 exceeds 100 columns
#49685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34400:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#49686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34401:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b

WARNING: line length of 121 exceeds 100 columns
#49687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34402:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34403:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34404:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#49690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34405:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#49691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34406:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L

WARNING: line length of 121 exceeds 100 columns
#49692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34407:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#49693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34408:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L

WARNING: line length of 121 exceeds 100 columns
#49694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34409:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#49695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34410:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L

WARNING: line length of 121 exceeds 100 columns
#49696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34411:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#49697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34412:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#49698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34413:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#49699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34414:
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L

WARNING: line length of 113 exceeds 100 columns
#49700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34415:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#49701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34416:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1

WARNING: line length of 113 exceeds 100 columns
#49702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34417:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#49703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34418:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#49704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34419:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#49705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34420:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#49706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34421:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#49707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34422:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd

WARNING: line length of 114 exceeds 100 columns
#49708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34423:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10

WARNING: line length of 114 exceeds 100 columns
#49709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34424:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#49710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34425:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14

WARNING: line length of 114 exceeds 100 columns
#49711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34426:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#49712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34427:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#49713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34428:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#49714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34429:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#49715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34430:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d

WARNING: line length of 121 exceeds 100 columns
#49716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34431:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34432:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34433:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34434:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34435:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34436:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#49722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34437:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34438:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34439:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34440:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#49726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34441:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#49727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34442:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#49728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34443:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#49729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34444:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#49730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34445:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#49731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34446:
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L

WARNING: line length of 113 exceeds 100 columns
#49732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34447:
+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#49733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34448:
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#49734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34449:
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5

WARNING: line length of 113 exceeds 100 columns
#49735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34450:
+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#49736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34451:
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#49737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34452:
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf

WARNING: line length of 114 exceeds 100 columns
#49738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34453:
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10

WARNING: line length of 114 exceeds 100 columns
#49739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34454:
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11

WARNING: line length of 121 exceeds 100 columns
#49740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34455:
+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34456:
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34457:
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34458:
+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34459:
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34460:
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#49746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34461:
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34462:
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L

WARNING: line length of 113 exceeds 100 columns
#49748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34463:
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34464:
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#49750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34465:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#49751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34466:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#49752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34467:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#49753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34468:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#49754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34469:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#49755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34470:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#49756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34471:
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#49757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34472:
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34473:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34474:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#49760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34475:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34476:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34477:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#49763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34478:
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34479:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0

WARNING: line length of 113 exceeds 100 columns
#49765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34480:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1

WARNING: line length of 113 exceeds 100 columns
#49766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34481:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4

WARNING: line length of 114 exceeds 100 columns
#49767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34482:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10

WARNING: line length of 121 exceeds 100 columns
#49768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34483:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34484:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34485:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#49771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34486:
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34487:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34488:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#49774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34489:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#49775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34490:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#49776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34491:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#49777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34492:
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#49778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34493:
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6

WARNING: line length of 113 exceeds 100 columns
#49779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34494:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#49780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34495:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#49781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34496:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34497:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34498:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34499:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#49785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34500:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34501:
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34502:
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34503:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#49789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34504:
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34505:
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34506:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#49792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34507:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#49793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34508:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#49794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34509:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#49795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34510:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#49796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34511:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#49797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34512:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#49798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34513:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#49799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34514:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#49800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34515:
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#49801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34516:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34517:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34518:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34519:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34520:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34521:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34522:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34523:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34524:
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34525:
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34526:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#49812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34527:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#49813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34528:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6

WARNING: line length of 113 exceeds 100 columns
#49814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34529:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7

WARNING: line length of 113 exceeds 100 columns
#49815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34530:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#49816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34531:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#49817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34532:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#49818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34533:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe

WARNING: line length of 114 exceeds 100 columns
#49819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34534:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#49820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34535:
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#49821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34536:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34537:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34538:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34539:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34540:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34541:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34542:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34543:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34544:
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34545:
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#49831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34546:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#49832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34547:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#49833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34548:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#49834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34549:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#49835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34550:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#49836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34551:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#49837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34552:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#49838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34553:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#49839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34554:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#49840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34555:
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#49841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34556:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34557:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34558:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34559:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34560:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34561:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34562:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34563:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34564:
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34565:
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#49851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34566:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#49852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34567:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#49853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34568:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#49854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34569:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7

WARNING: line length of 113 exceeds 100 columns
#49855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34570:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#49856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34571:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#49857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34572:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#49858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34573:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe

WARNING: line length of 114 exceeds 100 columns
#49859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34574:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#49860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34575:
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#49861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34576:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34577:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34578:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34579:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34580:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34581:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34582:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34583:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34584:
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34585:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#49871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34586:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#49872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34587:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#49873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34588:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#49874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34589:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#49875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34590:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#49876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34591:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#49877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34592:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7

WARNING: line length of 113 exceeds 100 columns
#49878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34593:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#49879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34594:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#49880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34595:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#49881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34596:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb

WARNING: line length of 121 exceeds 100 columns
#49882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34597:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34598:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34599:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34600:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#49886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34601:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34602:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34603:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34604:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34605:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#49891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34606:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#49892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34607:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#49893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34608:
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L

WARNING: line length of 113 exceeds 100 columns
#49894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34609:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#49895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34610:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#49896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34611:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#49897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34612:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#49898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34613:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#49899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34614:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L

WARNING: line length of 121 exceeds 100 columns
#49900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34615:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L

WARNING: line length of 121 exceeds 100 columns
#49901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34616:
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#49902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34617:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#49903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34618:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7

WARNING: line length of 114 exceeds 100 columns
#49904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34619:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#49905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34620:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#49906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34621:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12

WARNING: line length of 114 exceeds 100 columns
#49907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34622:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13

WARNING: line length of 114 exceeds 100 columns
#49908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34623:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14

WARNING: line length of 121 exceeds 100 columns
#49909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34624:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#49910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34625:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#49911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34626:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#49912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34627:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#49913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34628:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L

WARNING: line length of 121 exceeds 100 columns
#49914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34629:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#49915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34630:
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#49916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34631:
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0

WARNING: line length of 114 exceeds 100 columns
#49917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34632:
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#49918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34633:
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#49919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34634:
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34635:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#49921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34636:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#49922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34637:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3

WARNING: line length of 113 exceeds 100 columns
#49923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34638:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#49924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34639:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5

WARNING: line length of 113 exceeds 100 columns
#49925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34640:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6

WARNING: line length of 114 exceeds 100 columns
#49926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34641:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#49927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34642:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34643:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34644:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#49930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34645:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#49931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34646:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#49932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34647:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#49933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34648:
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#49934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34649:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34650:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1

WARNING: line length of 113 exceeds 100 columns
#49936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34651:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#49937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34652:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#49938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34653:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8

WARNING: line length of 114 exceeds 100 columns
#49939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34654:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#49940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34655:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34656:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#49942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34657:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#49943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34658:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#49944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34659:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#49945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34660:
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#49946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34661:
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34662:
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7

WARNING: line length of 121 exceeds 100 columns
#49948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34663:
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34664:
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L

WARNING: line length of 113 exceeds 100 columns
#49950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34665:
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#49951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34666:
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#49952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34667:
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#49953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34668:
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#49954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34669:
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#49955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34670:
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5

WARNING: line length of 121 exceeds 100 columns
#49956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34671:
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#49957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34672:
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L

WARNING: line length of 113 exceeds 100 columns
#49958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34673:
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#49959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34674:
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L

WARNING: line length of 113 exceeds 100 columns
#49960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34675:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#49961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34676:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#49962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34677:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe

WARNING: line length of 113 exceeds 100 columns
#49963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34678:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf

WARNING: line length of 121 exceeds 100 columns
#49964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34679:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34680:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34681:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34682:
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L

WARNING: line length of 113 exceeds 100 columns
#49968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34683:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34684:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#49970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34685:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#49971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34686:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#49972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34687:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#49973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34688:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#49974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34689:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#49975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34690:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L

WARNING: line length of 113 exceeds 100 columns
#49976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34691:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#49977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34692:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#49978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34693:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe

WARNING: line length of 113 exceeds 100 columns
#49979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34694:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf

WARNING: line length of 121 exceeds 100 columns
#49980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34695:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34696:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34697:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34698:
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L

WARNING: line length of 113 exceeds 100 columns
#49984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34699:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#49985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34700:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#49986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34701:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#49987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34702:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#49988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34703:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#49989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34704:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#49990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34705:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#49991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34706:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L

WARNING: line length of 113 exceeds 100 columns
#49992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34707:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#49993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34708:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#49994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34709:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe

WARNING: line length of 113 exceeds 100 columns
#49995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34710:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf

WARNING: line length of 121 exceeds 100 columns
#49996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34711:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#49997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34712:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#49998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34713:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L

WARNING: line length of 121 exceeds 100 columns
#49999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34714:
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L

WARNING: line length of 113 exceeds 100 columns
#50000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34715:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#50001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34716:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#50002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34717:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#50003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34718:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#50004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34719:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#50005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34720:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#50006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34721:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#50007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34722:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L

WARNING: line length of 113 exceeds 100 columns
#50008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34723:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#50009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34724:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#50010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34725:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#50011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34726:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#50012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34727:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#50013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34728:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#50014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34729:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#50015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34730:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L

WARNING: line length of 113 exceeds 100 columns
#50016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34731:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#50017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34732:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#50018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34733:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#50019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34734:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#50020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34735:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#50021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34736:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#50022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34737:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#50023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34738:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L

WARNING: line length of 114 exceeds 100 columns
#50024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34739:
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#50025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34740:
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#50026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34741:
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd

WARNING: line length of 113 exceeds 100 columns
#50027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34742:
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe

WARNING: line length of 114 exceeds 100 columns
#50028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34743:
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#50029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34744:
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34745:
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#50031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34746:
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L

WARNING: line length of 113 exceeds 100 columns
#50032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34747:
+#define DCIO_SPARE__DCIO_SPARE__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#50033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34748:
+#define DCIO_SPARE__DCIO_SPARE_MASK                                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34749:
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#50035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34750:
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#50036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34751:
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT                                                        0x4

WARNING: line length of 113 exceeds 100 columns
#50037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34752:
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#50038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34753:
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#50039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34754:
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT                                                        0x7

WARNING: line length of 113 exceeds 100 columns
#50040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34755:
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#50041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34756:
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT                                                        0x9

WARNING: line length of 113 exceeds 100 columns
#50042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34757:
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT                                                        0xa

WARNING: line length of 121 exceeds 100 columns
#50043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34758:
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34759:
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34760:
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK                                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34761:
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34762:
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34763:
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK                                                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#50049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34764:
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34765:
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK                                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34766:
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK                                                          0x00000400L

WARNING: line length of 113 exceeds 100 columns
#50052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34767:
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#50053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34768:
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34769:
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#50055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34770:
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK                                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#50056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34771:
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0

WARNING: line length of 113 exceeds 100 columns
#50057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34772:
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4

WARNING: line length of 121 exceeds 100 columns
#50058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34773:
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#50059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34774:
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L

WARNING: line length of 113 exceeds 100 columns
#50060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34775:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#50061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34776:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8

WARNING: line length of 114 exceeds 100 columns
#50062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34777:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14

WARNING: line length of 114 exceeds 100 columns
#50063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34778:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#50064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34779:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#50065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34780:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L

WARNING: line length of 121 exceeds 100 columns
#50066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34781:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L

WARNING: line length of 121 exceeds 100 columns
#50067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34782:
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L

WARNING: line length of 113 exceeds 100 columns
#50068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34783:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4

WARNING: line length of 113 exceeds 100 columns
#50069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34784:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#50070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34785:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14

WARNING: line length of 114 exceeds 100 columns
#50071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34786:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#50072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34787:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L

WARNING: line length of 121 exceeds 100 columns
#50073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34788:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#50074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34789:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L

WARNING: line length of 121 exceeds 100 columns
#50075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34790:
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L

WARNING: line length of 113 exceeds 100 columns
#50076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34791:
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34792:
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#50078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34793:
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#50079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34794:
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#50080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34795:
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#50081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34796:
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#50082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34797:
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0x6

WARNING: line length of 113 exceeds 100 columns
#50083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34798:
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#50084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34799:
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x9

WARNING: line length of 113 exceeds 100 columns
#50085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34800:
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#50086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34801:
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0xb

WARNING: line length of 113 exceeds 100 columns
#50087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34802:
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0xc

WARNING: line length of 113 exceeds 100 columns
#50088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34803:
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xd

WARNING: line length of 113 exceeds 100 columns
#50089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34804:
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xe

WARNING: line length of 114 exceeds 100 columns
#50090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34805:
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10

WARNING: line length of 114 exceeds 100 columns
#50091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34806:
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11

WARNING: line length of 121 exceeds 100 columns
#50092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34807:
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34808:
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34809:
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#50095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34810:
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34811:
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34812:
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34813:
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34814:
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34815:
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34816:
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#50102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34817:
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#50103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34818:
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34819:
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34820:
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34821:
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34822:
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L

WARNING: line length of 113 exceeds 100 columns
#50108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34823:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#50109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34824:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#50110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34825:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2

WARNING: line length of 113 exceeds 100 columns
#50111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34826:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#50112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34827:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#50113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34828:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6

WARNING: line length of 113 exceeds 100 columns
#50114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34829:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#50115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34830:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#50116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34831:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#50117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34832:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc

WARNING: line length of 113 exceeds 100 columns
#50118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34833:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd

WARNING: line length of 113 exceeds 100 columns
#50119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34834:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe

WARNING: line length of 114 exceeds 100 columns
#50120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34835:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#50121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34836:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11

WARNING: line length of 114 exceeds 100 columns
#50122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34837:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12

WARNING: line length of 114 exceeds 100 columns
#50123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34838:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#50124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34839:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15

WARNING: line length of 114 exceeds 100 columns
#50125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34840:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16

WARNING: line length of 114 exceeds 100 columns
#50126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34841:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#50127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34842:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#50128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34843:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#50129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34844:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c

WARNING: line length of 121 exceeds 100 columns
#50130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34845:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34846:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34847:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#50133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34848:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34849:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34850:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#50136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34851:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34852:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34853:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#50139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34854:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34855:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34856:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#50142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34857:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34858:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34859:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#50145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34860:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34861:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34862:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#50148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34863:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34864:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34865:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#50151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34866:
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34867:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#50153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34868:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#50154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34869:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#50155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34870:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#50156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34871:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15

WARNING: line length of 114 exceeds 100 columns
#50157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34872:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16

WARNING: line length of 114 exceeds 100 columns
#50158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34873:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17

WARNING: line length of 121 exceeds 100 columns
#50159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34874:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34875:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34876:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34877:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34878:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34879:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34880:
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L

WARNING: line length of 113 exceeds 100 columns
#50166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34881:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#50167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34882:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#50168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34883:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#50169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34884:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#50170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34885:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#50171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34886:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16

WARNING: line length of 114 exceeds 100 columns
#50172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34887:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17

WARNING: line length of 121 exceeds 100 columns
#50173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34888:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34889:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34890:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34891:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34892:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34893:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34894:
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L

WARNING: line length of 113 exceeds 100 columns
#50180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34895:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#50181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34896:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#50182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34897:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#50183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34898:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#50184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34899:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15

WARNING: line length of 114 exceeds 100 columns
#50185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34900:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16

WARNING: line length of 114 exceeds 100 columns
#50186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34901:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17

WARNING: line length of 121 exceeds 100 columns
#50187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34902:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34903:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34904:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34905:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34906:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34907:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34908:
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L

WARNING: line length of 113 exceeds 100 columns
#50194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34909:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#50195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34910:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#50196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34911:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#50197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34912:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#50198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34913:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#50199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34914:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe

WARNING: line length of 114 exceeds 100 columns
#50200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34915:
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#50201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34916:
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#50202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34917:
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16

WARNING: line length of 114 exceeds 100 columns
#50203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34918:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#50204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34919:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#50205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34920:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34921:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34922:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34923:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34924:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34925:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34926:
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34927:
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34928:
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34929:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#50215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34930:
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34931:
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34932:
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34933:
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34934:
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34935:
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34936:
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#50222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34937:
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34938:
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34939:
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34940:
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34941:
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34942:
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34943:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#50229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34944:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#50230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34945:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#50231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34946:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#50232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34947:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#50233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34948:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe

WARNING: line length of 114 exceeds 100 columns
#50234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34949:
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#50235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34950:
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#50236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34951:
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16

WARNING: line length of 114 exceeds 100 columns
#50237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34952:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#50238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34953:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#50239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34954:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34955:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34956:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34957:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34958:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34959:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34960:
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34961:
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34962:
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34963:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#50249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34964:
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34965:
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34966:
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34967:
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34968:
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34969:
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34970:
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#50256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34971:
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34972:
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34973:
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34974:
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34975:
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34976:
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34977:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#50263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34978:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#50264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34979:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#50265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34980:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#50266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34981:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#50267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34982:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe

WARNING: line length of 114 exceeds 100 columns
#50268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34983:
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#50269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34984:
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#50270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34985:
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16

WARNING: line length of 114 exceeds 100 columns
#50271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34986:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#50272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34987:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#50273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34988:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34989:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34990:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34991:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34992:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34993:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34994:
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34995:
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34996:
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34997:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#50283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34998:
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:34999:
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35000:
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35001:
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35002:
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35003:
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35004:
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#50290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35005:
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35006:
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35007:
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35008:
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35009:
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35010:
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35011:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#50297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35012:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#50298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35013:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#50299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35014:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#50300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35015:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#50301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35016:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe

WARNING: line length of 114 exceeds 100 columns
#50302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35017:
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#50303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35018:
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#50304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35019:
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16

WARNING: line length of 114 exceeds 100 columns
#50305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35020:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#50306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35021:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#50307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35022:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35023:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35024:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35025:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35026:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35027:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35028:
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35029:
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35030:
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35031:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#50317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35032:
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35033:
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35034:
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35035:
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35036:
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35037:
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35038:
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#50324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35039:
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35040:
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35041:
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35042:
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35043:
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35044:
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35045:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#50331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35046:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#50332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35047:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#50333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35048:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8

WARNING: line length of 113 exceeds 100 columns
#50334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35049:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc

WARNING: line length of 113 exceeds 100 columns
#50335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35050:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe

WARNING: line length of 114 exceeds 100 columns
#50336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35051:
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10

WARNING: line length of 114 exceeds 100 columns
#50337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35052:
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#50338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35053:
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16

WARNING: line length of 114 exceeds 100 columns
#50339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35054:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18

WARNING: line length of 114 exceeds 100 columns
#50340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35055:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c

WARNING: line length of 121 exceeds 100 columns
#50341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35056:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35057:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35058:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35059:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35060:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35061:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35062:
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35063:
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35064:
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35065:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#50351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35066:
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35067:
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35068:
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35069:
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35070:
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35071:
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35072:
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#50358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35073:
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35074:
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35075:
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35076:
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8

WARNING: line length of 121 exceeds 100 columns
#50362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35077:
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35078:
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35079:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#50365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35080:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6

WARNING: line length of 113 exceeds 100 columns
#50366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35081:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#50367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35082:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#50368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35083:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe

WARNING: line length of 114 exceeds 100 columns
#50369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35084:
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#50370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35085:
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14

WARNING: line length of 114 exceeds 100 columns
#50371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35086:
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16

WARNING: line length of 114 exceeds 100 columns
#50372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35087:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18

WARNING: line length of 114 exceeds 100 columns
#50373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35088:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#50374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35089:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35090:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35091:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35092:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35093:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35094:
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35095:
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35096:
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35097:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#50383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35098:
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35099:
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#50385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35100:
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#50386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35101:
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35102:
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35103:
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#50389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35104:
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8

WARNING: line length of 121 exceeds 100 columns
#50390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35105:
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35106:
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35107:
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#50393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35108:
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#50394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35109:
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35110:
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L

WARNING: line length of 113 exceeds 100 columns
#50396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35111:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#50397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35112:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#50398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35113:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#50399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35114:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#50400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35115:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#50401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35116:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9

WARNING: line length of 113 exceeds 100 columns
#50402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35117:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb

WARNING: line length of 113 exceeds 100 columns
#50403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35118:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc

WARNING: line length of 114 exceeds 100 columns
#50404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35119:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#50405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35120:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11

WARNING: line length of 114 exceeds 100 columns
#50406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35121:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13

WARNING: line length of 114 exceeds 100 columns
#50407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35122:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14

WARNING: line length of 114 exceeds 100 columns
#50408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35123:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#50409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35124:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#50410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35125:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#50411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35126:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#50412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35127:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35128:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35129:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35130:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#50416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35131:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35132:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35133:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L

WARNING: line length of 121 exceeds 100 columns
#50419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35134:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L

WARNING: line length of 121 exceeds 100 columns
#50420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35135:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35136:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35137:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L

WARNING: line length of 121 exceeds 100 columns
#50423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35138:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#50424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35139:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35140:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35141:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#50427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35142:
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#50428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35143:
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#50429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35144:
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#50430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35145:
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#50431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35146:
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18

WARNING: line length of 121 exceeds 100 columns
#50432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35147:
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35148:
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35149:
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35150:
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L

WARNING: line length of 113 exceeds 100 columns
#50436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35151:
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#50437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35152:
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#50438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35153:
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#50439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35154:
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#50440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35155:
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35156:
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35157:
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35158:
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L

WARNING: line length of 113 exceeds 100 columns
#50444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35159:
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#50445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35160:
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#50446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35161:
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#50447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35162:
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18

WARNING: line length of 121 exceeds 100 columns
#50448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35163:
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35164:
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35165:
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35166:
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L

WARNING: line length of 113 exceeds 100 columns
#50452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35167:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35168:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#50454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35169:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6

WARNING: line length of 113 exceeds 100 columns
#50455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35170:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#50456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35171:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9

WARNING: line length of 113 exceeds 100 columns
#50457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35172:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa

WARNING: line length of 114 exceeds 100 columns
#50458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35173:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10

WARNING: line length of 114 exceeds 100 columns
#50459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35174:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11

WARNING: line length of 114 exceeds 100 columns
#50460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35175:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12

WARNING: line length of 114 exceeds 100 columns
#50461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35176:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#50462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35177:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15

WARNING: line length of 114 exceeds 100 columns
#50463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35178:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16

WARNING: line length of 114 exceeds 100 columns
#50464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35179:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18

WARNING: line length of 114 exceeds 100 columns
#50465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35180:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19

WARNING: line length of 114 exceeds 100 columns
#50466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35181:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#50467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35182:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c

WARNING: line length of 114 exceeds 100 columns
#50468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35183:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d

WARNING: line length of 114 exceeds 100 columns
#50469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35184:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e

WARNING: line length of 121 exceeds 100 columns
#50470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35185:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35186:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35187:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#50473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35188:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35189:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35190:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#50476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35191:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35192:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35193:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#50479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35194:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35195:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35196:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#50482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35197:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35198:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35199:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#50485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35200:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#50486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35201:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L

WARNING: line length of 121 exceeds 100 columns
#50487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35202:
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#50488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35203:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#50489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35204:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#50490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35205:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#50491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35206:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#50492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35207:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#50493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35208:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#50494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35209:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35210:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35211:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35212:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35213:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#50499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35214:
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L

WARNING: line length of 113 exceeds 100 columns
#50500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35215:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#50501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35216:
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#50502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35217:
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#50503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35218:
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#50504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35219:
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6

WARNING: line length of 113 exceeds 100 columns
#50505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35220:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8

WARNING: line length of 113 exceeds 100 columns
#50506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35221:
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9

WARNING: line length of 113 exceeds 100 columns
#50507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35222:
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa

WARNING: line length of 114 exceeds 100 columns
#50508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35223:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10

WARNING: line length of 114 exceeds 100 columns
#50509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35224:
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11

WARNING: line length of 114 exceeds 100 columns
#50510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35225:
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#50511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35226:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14

WARNING: line length of 114 exceeds 100 columns
#50512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35227:
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15

WARNING: line length of 114 exceeds 100 columns
#50513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35228:
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#50514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35229:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18

WARNING: line length of 114 exceeds 100 columns
#50515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35230:
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19

WARNING: line length of 114 exceeds 100 columns
#50516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35231:
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a

WARNING: line length of 114 exceeds 100 columns
#50517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35232:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#50518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35233:
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d

WARNING: line length of 114 exceeds 100 columns
#50519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35234:
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e

WARNING: line length of 121 exceeds 100 columns
#50520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35235:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35236:
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35237:
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#50523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35238:
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35239:
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35240:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35241:
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35242:
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#50528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35243:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35244:
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35245:
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#50531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35246:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35247:
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35248:
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35249:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35250:
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35251:
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L

WARNING: line length of 121 exceeds 100 columns
#50537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35252:
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#50538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35253:
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L

WARNING: line length of 121 exceeds 100 columns
#50539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35254:
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L

WARNING: line length of 113 exceeds 100 columns
#50540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35255:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#50541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35256:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#50542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35257:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#50543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35258:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#50544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35259:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#50545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35260:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#50546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35261:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35262:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35263:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35264:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35265:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#50551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35266:
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L

WARNING: line length of 114 exceeds 100 columns
#50552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35267:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#50553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35268:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15

WARNING: line length of 114 exceeds 100 columns
#50554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35269:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#50555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35270:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#50556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35271:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d

WARNING: line length of 121 exceeds 100 columns
#50557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35272:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35273:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L

WARNING: line length of 121 exceeds 100 columns
#50559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35274:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35275:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L

WARNING: line length of 121 exceeds 100 columns
#50561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35276:
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L

WARNING: line length of 113 exceeds 100 columns
#50562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35277:
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#50563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35278:
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4

WARNING: line length of 114 exceeds 100 columns
#50564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35279:
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#50565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35280:
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#50566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35281:
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18

WARNING: line length of 114 exceeds 100 columns
#50567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35282:
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c

WARNING: line length of 121 exceeds 100 columns
#50568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35283:
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#50569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35284:
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#50570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35285:
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#50571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35286:
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#50572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35287:
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#50573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35288:
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#50574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35289:
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35290:
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#50576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35291:
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#50577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35292:
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#50578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35293:
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#50579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35294:
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#50580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35295:
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#50581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35296:
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L

WARNING: line length of 121 exceeds 100 columns
#50582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35297:
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L

WARNING: line length of 121 exceeds 100 columns
#50583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35298:
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#50584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35299:
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9

WARNING: line length of 113 exceeds 100 columns
#50585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35300:
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#50586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35301:
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#50587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35302:
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe

WARNING: line length of 114 exceeds 100 columns
#50588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35303:
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#50589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35304:
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#50590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35305:
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#50591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35306:
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35307:
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#50593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35308:
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L

WARNING: line length of 121 exceeds 100 columns
#50594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35309:
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#50595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35310:
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#50596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35311:
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#50597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35312:
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L

WARNING: line length of 114 exceeds 100 columns
#50598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35313:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#50599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35314:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15

WARNING: line length of 114 exceeds 100 columns
#50600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35315:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19

WARNING: line length of 114 exceeds 100 columns
#50601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35316:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#50602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35317:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d

WARNING: line length of 121 exceeds 100 columns
#50603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35318:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35319:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L

WARNING: line length of 121 exceeds 100 columns
#50605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35320:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35321:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L

WARNING: line length of 121 exceeds 100 columns
#50607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35322:
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L

WARNING: line length of 113 exceeds 100 columns
#50608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35323:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3

WARNING: line length of 113 exceeds 100 columns
#50609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35324:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#50610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35325:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5

WARNING: line length of 113 exceeds 100 columns
#50611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35326:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6

WARNING: line length of 113 exceeds 100 columns
#50612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35327:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7

WARNING: line length of 113 exceeds 100 columns
#50613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35328:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8

WARNING: line length of 113 exceeds 100 columns
#50614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35329:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9

WARNING: line length of 121 exceeds 100 columns
#50615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35330:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35331:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35332:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35333:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35334:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#50620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35335:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35336:
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L

WARNING: line length of 113 exceeds 100 columns
#50622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35337:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#50623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35338:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#50624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35339:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#50625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35340:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#50626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35341:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#50627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35342:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#50628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35343:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc

WARNING: line length of 114 exceeds 100 columns
#50629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35344:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#50630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35345:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11

WARNING: line length of 114 exceeds 100 columns
#50631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35346:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#50632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35347:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13

WARNING: line length of 114 exceeds 100 columns
#50633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35348:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14

WARNING: line length of 114 exceeds 100 columns
#50634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35349:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15

WARNING: line length of 114 exceeds 100 columns
#50635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35350:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#50636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35351:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#50637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35352:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19

WARNING: line length of 114 exceeds 100 columns
#50638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35353:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#50639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35354:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b

WARNING: line length of 114 exceeds 100 columns
#50640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35355:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c

WARNING: line length of 114 exceeds 100 columns
#50641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35356:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d

WARNING: line length of 114 exceeds 100 columns
#50642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35357:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e

WARNING: line length of 121 exceeds 100 columns
#50643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35358:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#50644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35359:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#50645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35360:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L

WARNING: line length of 121 exceeds 100 columns
#50646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35361:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#50647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35362:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#50648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35363:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#50649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35364:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#50650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35365:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35366:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35367:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#50653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35368:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L

WARNING: line length of 121 exceeds 100 columns
#50654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35369:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35370:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35371:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#50657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35372:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35373:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35374:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#50660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35375:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L

WARNING: line length of 121 exceeds 100 columns
#50661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35376:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L

WARNING: line length of 121 exceeds 100 columns
#50662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35377:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L

WARNING: line length of 121 exceeds 100 columns
#50663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35378:
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#50664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35379:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#50665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35380:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#50666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35381:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#50667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35382:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3

WARNING: line length of 113 exceeds 100 columns
#50668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35383:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#50669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35384:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#50670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35385:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#50671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35386:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7

WARNING: line length of 113 exceeds 100 columns
#50672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35387:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#50673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35388:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x10

WARNING: line length of 113 exceeds 100 columns
#50674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35389:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa

WARNING: line length of 113 exceeds 100 columns
#50675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35390:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb

WARNING: line length of 113 exceeds 100 columns
#50676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35391:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xd

WARNING: line length of 113 exceeds 100 columns
#50677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35392:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe

WARNING: line length of 114 exceeds 100 columns
#50678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35393:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12

WARNING: line length of 114 exceeds 100 columns
#50679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35394:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14

WARNING: line length of 114 exceeds 100 columns
#50680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35395:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19

WARNING: line length of 114 exceeds 100 columns
#50681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35396:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a

WARNING: line length of 114 exceeds 100 columns
#50682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35397:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b

WARNING: line length of 114 exceeds 100 columns
#50683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35398:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c

WARNING: line length of 114 exceeds 100 columns
#50684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35399:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d

WARNING: line length of 114 exceeds 100 columns
#50685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35400:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e

WARNING: line length of 121 exceeds 100 columns
#50686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35401:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35402:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35403:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#50689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35404:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35405:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35406:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35407:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35408:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L

WARNING: line length of 121 exceeds 100 columns
#50694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35409:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35410:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00030000L

WARNING: line length of 121 exceeds 100 columns
#50696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35411:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L

WARNING: line length of 121 exceeds 100 columns
#50697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35412:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00001800L

WARNING: line length of 121 exceeds 100 columns
#50698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35413:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35414:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#50700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35415:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#50701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35416:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L

WARNING: line length of 121 exceeds 100 columns
#50702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35417:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35418:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L

WARNING: line length of 121 exceeds 100 columns
#50704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35419:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L

WARNING: line length of 121 exceeds 100 columns
#50705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35420:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L

WARNING: line length of 121 exceeds 100 columns
#50706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35421:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L

WARNING: line length of 121 exceeds 100 columns
#50707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35422:
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#50708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35423:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#50709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35424:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#50710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35425:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#50711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35426:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#50712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35427:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9

WARNING: line length of 113 exceeds 100 columns
#50713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35428:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#50714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35429:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#50715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35430:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd

WARNING: line length of 113 exceeds 100 columns
#50716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35431:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe

WARNING: line length of 114 exceeds 100 columns
#50717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35432:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#50718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35433:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11

WARNING: line length of 114 exceeds 100 columns
#50719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35434:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12

WARNING: line length of 114 exceeds 100 columns
#50720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35435:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13

WARNING: line length of 114 exceeds 100 columns
#50721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35436:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14

WARNING: line length of 114 exceeds 100 columns
#50722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35437:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#50723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35438:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19

WARNING: line length of 114 exceeds 100 columns
#50724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35439:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a

WARNING: line length of 114 exceeds 100 columns
#50725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35440:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b

WARNING: line length of 114 exceeds 100 columns
#50726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35441:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#50727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35442:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d

WARNING: line length of 114 exceeds 100 columns
#50728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35443:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e

WARNING: line length of 121 exceeds 100 columns
#50729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35444:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#50730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35445:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#50731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35446:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#50732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35447:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35448:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35449:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#50735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35450:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35451:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35452:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35453:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35454:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35455:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L

WARNING: line length of 121 exceeds 100 columns
#50741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35456:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L

WARNING: line length of 121 exceeds 100 columns
#50742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35457:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35458:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35459:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35460:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L

WARNING: line length of 121 exceeds 100 columns
#50746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35461:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L

WARNING: line length of 121 exceeds 100 columns
#50747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35462:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#50748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35463:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L

WARNING: line length of 121 exceeds 100 columns
#50749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35464:
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L

WARNING: line length of 113 exceeds 100 columns
#50750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35465:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#50751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35466:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#50752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35467:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#50753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35468:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#50754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35469:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#50755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35470:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5

WARNING: line length of 113 exceeds 100 columns
#50756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35471:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6

WARNING: line length of 113 exceeds 100 columns
#50757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35472:
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#50758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35473:
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9

WARNING: line length of 113 exceeds 100 columns
#50759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35474:
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa

WARNING: line length of 113 exceeds 100 columns
#50760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35475:
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb

WARNING: line length of 113 exceeds 100 columns
#50761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35476:
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#50762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35477:
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd

WARNING: line length of 113 exceeds 100 columns
#50763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35478:
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe

WARNING: line length of 113 exceeds 100 columns
#50764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35479:
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf

WARNING: line length of 114 exceeds 100 columns
#50765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35480:
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10

WARNING: line length of 114 exceeds 100 columns
#50766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35481:
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11

WARNING: line length of 114 exceeds 100 columns
#50767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35482:
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12

WARNING: line length of 114 exceeds 100 columns
#50768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35483:
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13

WARNING: line length of 121 exceeds 100 columns
#50769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35484:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35485:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35486:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#50772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35487:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35488:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35489:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35490:
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35491:
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35492:
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35493:
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#50779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35494:
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#50780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35495:
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35496:
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35497:
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35498:
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L

WARNING: line length of 121 exceeds 100 columns
#50784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35499:
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35500:
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35501:
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#50787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35502:
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L

WARNING: line length of 113 exceeds 100 columns
#50788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35503:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#50789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35504:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#50790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35505:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#50791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35506:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3

WARNING: line length of 113 exceeds 100 columns
#50792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35507:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#50793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35508:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#50794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35509:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6

WARNING: line length of 113 exceeds 100 columns
#50795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35510:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#50796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35511:
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9

WARNING: line length of 113 exceeds 100 columns
#50797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35512:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe

WARNING: line length of 113 exceeds 100 columns
#50798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35513:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf

WARNING: line length of 114 exceeds 100 columns
#50799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35514:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#50800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35515:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11

WARNING: line length of 114 exceeds 100 columns
#50801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35516:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12

WARNING: line length of 114 exceeds 100 columns
#50802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35517:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13

WARNING: line length of 121 exceeds 100 columns
#50803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35518:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35519:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35520:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#50806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35521:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35522:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35523:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35524:
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#50810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35525:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35526:
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35527:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35528:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#50814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35529:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35530:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35531:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L

WARNING: line length of 121 exceeds 100 columns
#50817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35532:
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L

WARNING: line length of 113 exceeds 100 columns
#50818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35533:
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#50819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35534:
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1

WARNING: line length of 113 exceeds 100 columns
#50820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35535:
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2

WARNING: line length of 113 exceeds 100 columns
#50821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35536:
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3

WARNING: line length of 113 exceeds 100 columns
#50822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35537:
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4

WARNING: line length of 113 exceeds 100 columns
#50823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35538:
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5

WARNING: line length of 113 exceeds 100 columns
#50824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35539:
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#50825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35540:
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9

WARNING: line length of 113 exceeds 100 columns
#50826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35541:
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa

WARNING: line length of 113 exceeds 100 columns
#50827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35542:
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb

WARNING: line length of 113 exceeds 100 columns
#50828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35543:
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#50829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35544:
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#50830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35545:
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10

WARNING: line length of 114 exceeds 100 columns
#50831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35546:
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12

WARNING: line length of 114 exceeds 100 columns
#50832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35547:
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14

WARNING: line length of 114 exceeds 100 columns
#50833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35548:
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16

WARNING: line length of 114 exceeds 100 columns
#50834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35549:
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18

WARNING: line length of 114 exceeds 100 columns
#50835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35550:
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a

WARNING: line length of 121 exceeds 100 columns
#50836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35551:
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35552:
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35553:
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#50839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35554:
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35555:
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35556:
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#50842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35557:
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#50843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35558:
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#50844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35559:
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#50845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35560:
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L

WARNING: line length of 121 exceeds 100 columns
#50846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35561:
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35562:
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35563:
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#50849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35564:
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#50850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35565:
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L

WARNING: line length of 121 exceeds 100 columns
#50851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35566:
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#50852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35567:
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L

WARNING: line length of 121 exceeds 100 columns
#50853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35568:
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L

WARNING: line length of 113 exceeds 100 columns
#50854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35569:
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35570:
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#50856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35571:
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#50857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35572:
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc

WARNING: line length of 114 exceeds 100 columns
#50858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35573:
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10

WARNING: line length of 114 exceeds 100 columns
#50859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35574:
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14

WARNING: line length of 121 exceeds 100 columns
#50860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35575:
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#50861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35576:
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#50862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35577:
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#50863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35578:
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#50864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35579:
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#50865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35580:
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#50866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35581:
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#50867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35582:
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2

WARNING: line length of 113 exceeds 100 columns
#50868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35583:
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#50869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35584:
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6

WARNING: line length of 113 exceeds 100 columns
#50870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35585:
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#50871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35586:
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa

WARNING: line length of 113 exceeds 100 columns
#50872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35587:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc

WARNING: line length of 113 exceeds 100 columns
#50873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35588:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd

WARNING: line length of 113 exceeds 100 columns
#50874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35589:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe

WARNING: line length of 113 exceeds 100 columns
#50875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35590:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf

WARNING: line length of 114 exceeds 100 columns
#50876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35591:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#50877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35592:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11

WARNING: line length of 114 exceeds 100 columns
#50878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35593:
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12

WARNING: line length of 114 exceeds 100 columns
#50879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35594:
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13

WARNING: line length of 114 exceeds 100 columns
#50880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35595:
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14

WARNING: line length of 114 exceeds 100 columns
#50881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35596:
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#50882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35597:
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16

WARNING: line length of 114 exceeds 100 columns
#50883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35598:
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17

WARNING: line length of 114 exceeds 100 columns
#50884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35599:
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#50885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35600:
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19

WARNING: line length of 114 exceeds 100 columns
#50886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35601:
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#50887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35602:
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b

WARNING: line length of 114 exceeds 100 columns
#50888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35603:
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#50889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35604:
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#50890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35605:
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L

WARNING: line length of 121 exceeds 100 columns
#50891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35606:
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#50892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35607:
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#50893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35608:
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#50894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35609:
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L

WARNING: line length of 121 exceeds 100 columns
#50895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35610:
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#50896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35611:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#50897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35612:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L

WARNING: line length of 121 exceeds 100 columns
#50898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35613:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L

WARNING: line length of 121 exceeds 100 columns
#50899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35614:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L

WARNING: line length of 121 exceeds 100 columns
#50900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35615:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#50901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35616:
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L

WARNING: line length of 121 exceeds 100 columns
#50902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35617:
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L

WARNING: line length of 121 exceeds 100 columns
#50903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35618:
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L

WARNING: line length of 121 exceeds 100 columns
#50904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35619:
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#50905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35620:
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L

WARNING: line length of 121 exceeds 100 columns
#50906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35621:
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L

WARNING: line length of 121 exceeds 100 columns
#50907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35622:
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L

WARNING: line length of 121 exceeds 100 columns
#50908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35623:
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#50909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35624:
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#50910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35625:
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#50911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35626:
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L

WARNING: line length of 121 exceeds 100 columns
#50912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35627:
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#50913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35628:
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L

WARNING: line length of 113 exceeds 100 columns
#50914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35629:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#50915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35630:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#50916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35631:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#50917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35632:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#50918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35633:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#50919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35634:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5

WARNING: line length of 121 exceeds 100 columns
#50920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35635:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#50921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35636:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#50922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35637:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#50923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35638:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#50924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35639:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#50925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35640:
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L

WARNING: line length of 113 exceeds 100 columns
#50926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35641:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35642:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35643:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35644:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35645:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35646:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35647:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35648:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35649:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35650:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35651:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35652:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35653:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35654:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35655:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35656:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35657:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35658:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35659:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#50945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35660:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35661:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35662:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35663:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35664:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35665:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35666:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35667:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35668:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35669:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35670:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35671:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35672:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35673:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35674:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35675:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35676:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35677:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35678:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35679:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35680:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35681:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35682:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35683:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35684:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35685:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35686:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35687:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35688:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35689:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35690:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35691:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35692:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35693:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35694:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35695:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35696:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35697:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35698:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35699:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35700:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35701:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35702:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35703:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35704:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35705:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35706:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35707:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35708:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35709:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35710:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35711:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35712:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#50998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35713:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#50999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35714:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35715:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35716:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35717:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35718:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35719:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35720:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35721:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35722:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35723:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35724:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35725:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35726:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35727:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35728:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35729:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35730:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35731:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35732:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35733:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35734:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35735:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35736:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35737:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35738:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35739:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35740:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35741:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35742:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35743:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35744:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35745:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35746:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35747:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35748:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35749:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35750:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35751:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35752:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35753:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35754:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35755:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35756:
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35757:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35758:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35759:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35760:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35761:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35762:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35763:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35764:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35765:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35766:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35767:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35768:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35769:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35770:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35771:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35772:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35773:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35774:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35775:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35776:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35777:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35778:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35779:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35780:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35781:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35782:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35783:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35784:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35785:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35786:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35787:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35788:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35789:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35790:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35791:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35792:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35793:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35794:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35795:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35796:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35797:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35798:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35799:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35800:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35801:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35802:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35803:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35804:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35805:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35806:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35807:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35808:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35809:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35810:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35811:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35812:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35813:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35814:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35815:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35816:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35817:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35818:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35819:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35820:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35821:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35822:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35823:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35824:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35825:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35826:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35827:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35828:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35829:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35830:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35831:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35832:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35833:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35834:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35835:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35836:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35837:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35838:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35839:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35840:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35841:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35842:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35843:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35844:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35845:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35846:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35847:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35848:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35849:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35850:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35851:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35852:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35853:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35854:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35855:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35856:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35857:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35858:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35859:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35860:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35861:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35862:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35863:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35864:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35865:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35866:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35867:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35868:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35869:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35870:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35871:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35872:
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35873:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35874:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35875:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35876:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35877:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35878:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35879:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35880:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35881:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35882:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35883:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35884:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35885:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35886:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35887:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35888:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35889:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35890:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35891:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35892:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35893:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35894:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35895:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35896:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35897:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35898:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35899:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35900:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35901:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35902:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35903:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35904:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35905:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35906:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35907:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35908:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35909:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35910:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35911:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35912:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35913:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35914:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35915:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35916:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35917:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35918:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35919:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35920:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35921:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35922:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35923:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35924:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35925:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35926:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35927:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35928:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35929:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35930:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35931:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35932:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35933:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35934:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35935:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35936:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35937:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35938:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35939:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35940:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35941:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35942:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35943:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35944:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35945:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35946:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35947:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35948:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35949:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35950:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35951:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35952:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35953:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35954:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35955:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35956:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35957:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35958:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35959:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35960:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35961:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35962:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35963:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35964:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35965:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35966:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35967:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35968:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35969:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35970:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35971:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35972:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35973:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35974:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35975:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35976:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35977:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35978:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35979:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35980:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35981:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35982:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35983:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35984:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35985:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35986:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35987:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35988:
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35989:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35990:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35991:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35992:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35993:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35994:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35995:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35996:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35997:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35998:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:35999:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36000:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36001:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36002:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36003:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36004:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36005:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36006:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36007:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#51293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36008:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36009:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36010:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36011:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36012:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36013:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36014:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36015:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36016:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36017:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36018:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36019:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36020:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36021:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36022:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36023:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36024:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36025:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36026:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36027:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36028:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36029:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36030:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36031:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36032:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36033:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36034:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36035:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36036:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36037:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36038:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36039:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36040:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36041:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36042:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36043:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36044:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36045:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36046:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36047:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36048:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36049:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36050:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36051:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36052:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36053:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36054:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36055:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36056:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36057:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36058:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36059:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36060:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36061:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36062:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36063:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36064:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36065:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36066:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36067:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36068:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36069:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36070:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36071:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36072:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36073:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36074:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36075:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36076:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36077:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36078:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36079:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36080:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36081:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36082:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36083:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36084:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36085:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36086:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36087:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36088:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36089:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36090:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36091:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36092:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36093:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36094:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36095:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36096:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36097:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36098:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36099:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36100:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36101:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36102:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36103:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#51389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36104:
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36105:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#51391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36106:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#51392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36107:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#51393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36108:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36109:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36110:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L

WARNING: line length of 113 exceeds 100 columns
#51396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36111:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3

WARNING: line length of 113 exceeds 100 columns
#51397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36112:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#51398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36113:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#51399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36114:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#51400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36115:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#51401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36116:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#51402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36117:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#51403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36118:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36119:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#51405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36120:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#51406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36121:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#51407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36122:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#51408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36123:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#51409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36124:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#51410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36125:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6

WARNING: line length of 113 exceeds 100 columns
#51411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36126:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8

WARNING: line length of 113 exceeds 100 columns
#51412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36127:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc

WARNING: line length of 113 exceeds 100 columns
#51413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36128:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe

WARNING: line length of 114 exceeds 100 columns
#51414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36129:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#51415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36130:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#51416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36131:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16

WARNING: line length of 121 exceeds 100 columns
#51417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36132:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36133:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36134:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#51420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36135:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36136:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#51422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36137:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#51423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36138:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36139:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#51425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36140:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L

WARNING: line length of 113 exceeds 100 columns
#51426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36141:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#51427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36142:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#51428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36143:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#51429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36144:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9

WARNING: line length of 114 exceeds 100 columns
#51430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36145:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#51431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36146:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#51432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36147:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36148:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#51434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36149:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36150:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L

WARNING: line length of 121 exceeds 100 columns
#51436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36151:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36152:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#51438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36153:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#51439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36154:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#51440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36155:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#51441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36156:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#51442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36157:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#51443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36158:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#51444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36159:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#51445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36160:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#51446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36161:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#51447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36162:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#51448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36163:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a

WARNING: line length of 121 exceeds 100 columns
#51449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36164:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36165:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36166:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36167:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#51453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36168:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#51454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36169:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36170:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#51456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36171:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#51457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36172:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#51458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36173:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#51459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36174:
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L

WARNING: line length of 113 exceeds 100 columns
#51460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36175:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36176:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#51462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36177:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#51463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36178:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#51464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36179:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#51465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36180:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#51466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36181:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36182:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#51468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36183:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#51469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36184:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#51470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36185:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36186:
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#51472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36187:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#51473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36188:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#51474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36189:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#51475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36190:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#51476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36191:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36192:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36193:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#51479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36194:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#51480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36195:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#51481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36196:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#51482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36197:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#51483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36198:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#51484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36199:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36200:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36201:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#51487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36202:
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#51488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36203:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#51489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36204:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#51490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36205:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#51491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36206:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36207:
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#51493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36208:
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13

WARNING: line length of 114 exceeds 100 columns
#51494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36209:
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14

WARNING: line length of 114 exceeds 100 columns
#51495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36210:
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15

WARNING: line length of 114 exceeds 100 columns
#51496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36211:
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e

WARNING: line length of 114 exceeds 100 columns
#51497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36212:
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#51498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36213:
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36214:
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#51500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36215:
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#51501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36216:
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#51502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36217:
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L

WARNING: line length of 121 exceeds 100 columns
#51503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36218:
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#51504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36219:
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0

WARNING: line length of 114 exceeds 100 columns
#51505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36220:
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#51506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36221:
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#51507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36222:
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36223:
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#51509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36224:
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#51510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36225:
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#51511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36226:
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#51512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36227:
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36228:
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L

WARNING: line length of 113 exceeds 100 columns
#51514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36229:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#51515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36230:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#51516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36231:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#51517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36232:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#51518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36233:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f

WARNING: line length of 121 exceeds 100 columns
#51519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36234:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36235:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36236:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36237:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#51523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36238:
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#51524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36239:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#51525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36240:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8

WARNING: line length of 114 exceeds 100 columns
#51526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36241:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#51527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36242:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#51528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36243:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#51529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36244:
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L

WARNING: line length of 113 exceeds 100 columns
#51530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36245:
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#51531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36246:
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36247:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#51533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36248:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8

WARNING: line length of 114 exceeds 100 columns
#51534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36249:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#51535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36250:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36251:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36252:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L

WARNING: line length of 113 exceeds 100 columns
#51538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36253:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3

WARNING: line length of 113 exceeds 100 columns
#51539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36254:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#51540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36255:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#51541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36256:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#51542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36257:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#51543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36258:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#51544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36259:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#51545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36260:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36261:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#51547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36262:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#51548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36263:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#51549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36264:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#51550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36265:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#51551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36266:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#51552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36267:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6

WARNING: line length of 113 exceeds 100 columns
#51553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36268:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8

WARNING: line length of 113 exceeds 100 columns
#51554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36269:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc

WARNING: line length of 113 exceeds 100 columns
#51555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36270:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe

WARNING: line length of 114 exceeds 100 columns
#51556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36271:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10

WARNING: line length of 114 exceeds 100 columns
#51557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36272:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14

WARNING: line length of 114 exceeds 100 columns
#51558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36273:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16

WARNING: line length of 121 exceeds 100 columns
#51559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36274:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36275:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36276:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#51562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36277:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36278:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#51564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36279:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L

WARNING: line length of 121 exceeds 100 columns
#51565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36280:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36281:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#51567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36282:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L

WARNING: line length of 113 exceeds 100 columns
#51568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36283:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#51569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36284:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#51570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36285:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#51571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36286:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9

WARNING: line length of 114 exceeds 100 columns
#51572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36287:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#51573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36288:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#51574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36289:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36290:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#51576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36291:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36292:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L

WARNING: line length of 121 exceeds 100 columns
#51578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36293:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36294:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#51580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36295:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#51581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36296:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#51582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36297:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8

WARNING: line length of 113 exceeds 100 columns
#51583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36298:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#51584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36299:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#51585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36300:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#51586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36301:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11

WARNING: line length of 114 exceeds 100 columns
#51587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36302:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#51588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36303:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#51589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36304:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19

WARNING: line length of 114 exceeds 100 columns
#51590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36305:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a

WARNING: line length of 121 exceeds 100 columns
#51591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36306:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36307:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36308:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36309:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#51595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36310:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#51596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36311:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36312:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#51598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36313:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#51599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36314:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#51600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36315:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#51601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36316:
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L

WARNING: line length of 113 exceeds 100 columns
#51602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36317:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36318:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#51604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36319:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2

WARNING: line length of 113 exceeds 100 columns
#51605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36320:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3

WARNING: line length of 113 exceeds 100 columns
#51606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36321:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#51607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36322:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8

WARNING: line length of 121 exceeds 100 columns
#51608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36323:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36324:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#51610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36325:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#51611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36326:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#51612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36327:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36328:
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#51614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36329:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#51615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36330:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#51616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36331:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#51617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36332:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#51618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36333:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36334:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36335:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#51621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36336:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#51622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36337:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#51623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36338:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#51624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36339:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#51625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36340:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#51626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36341:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36342:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36343:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#51629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36344:
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#51630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36345:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#51631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36346:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#51632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36347:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#51633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36348:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36349:
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#51635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36350:
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13

WARNING: line length of 114 exceeds 100 columns
#51636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36351:
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14

WARNING: line length of 114 exceeds 100 columns
#51637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36352:
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15

WARNING: line length of 114 exceeds 100 columns
#51638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36353:
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e

WARNING: line length of 114 exceeds 100 columns
#51639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36354:
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#51640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36355:
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36356:
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L

WARNING: line length of 121 exceeds 100 columns
#51642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36357:
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#51643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36358:
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#51644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36359:
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L

WARNING: line length of 121 exceeds 100 columns
#51645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36360:
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#51646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36361:
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0

WARNING: line length of 114 exceeds 100 columns
#51647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36362:
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#51648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36363:
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#51649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36364:
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36365:
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#51651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36366:
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#51652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36367:
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#51653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36368:
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#51654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36369:
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36370:
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L

WARNING: line length of 113 exceeds 100 columns
#51656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36371:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#51657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36372:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#51658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36373:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#51659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36374:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#51660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36375:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f

WARNING: line length of 121 exceeds 100 columns
#51661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36376:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36377:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36378:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36379:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#51665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36380:
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#51666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36381:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#51667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36382:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8

WARNING: line length of 114 exceeds 100 columns
#51668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36383:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#51669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36384:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#51670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36385:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L

WARNING: line length of 121 exceeds 100 columns
#51671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36386:
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L

WARNING: line length of 113 exceeds 100 columns
#51672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36387:
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#51673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36388:
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36389:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#51675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36390:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#51676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36391:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#51677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36392:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36393:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36394:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#51680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36395:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#51681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36396:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#51682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36397:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#51683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36398:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#51684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36399:
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#51685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36400:
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#51686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36401:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36402:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36403:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36404:
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L

WARNING: line length of 121 exceeds 100 columns
#51690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36405:
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#51691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36406:
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#51692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36407:
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#51693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36408:
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#51694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36409:
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36410:
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36411:
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#51697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36412:
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#51698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36413:
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#51699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36414:
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#51700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36415:
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36416:
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36417:
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#51703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36418:
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#51704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36419:
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#51705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36420:
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#51706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36421:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#51707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36422:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1

WARNING: line length of 113 exceeds 100 columns
#51708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36423:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2

WARNING: line length of 113 exceeds 100 columns
#51709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36424:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3

WARNING: line length of 113 exceeds 100 columns
#51710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36425:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4

WARNING: line length of 113 exceeds 100 columns
#51711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36426:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#51712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36427:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6

WARNING: line length of 113 exceeds 100 columns
#51713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36428:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#51714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36429:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#51715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36430:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9

WARNING: line length of 113 exceeds 100 columns
#51716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36431:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa

WARNING: line length of 113 exceeds 100 columns
#51717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36432:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb

WARNING: line length of 114 exceeds 100 columns
#51718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36433:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#51719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36434:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11

WARNING: line length of 114 exceeds 100 columns
#51720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36435:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12

WARNING: line length of 114 exceeds 100 columns
#51721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36436:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13

WARNING: line length of 114 exceeds 100 columns
#51722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36437:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14

WARNING: line length of 114 exceeds 100 columns
#51723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36438:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15

WARNING: line length of 114 exceeds 100 columns
#51724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36439:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16

WARNING: line length of 114 exceeds 100 columns
#51725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36440:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17

WARNING: line length of 114 exceeds 100 columns
#51726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36441:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#51727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36442:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19

WARNING: line length of 114 exceeds 100 columns
#51728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36443:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a

WARNING: line length of 114 exceeds 100 columns
#51729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36444:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b

WARNING: line length of 121 exceeds 100 columns
#51730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36445:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#51731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36446:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#51732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36447:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#51733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36448:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#51734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36449:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#51735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36450:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#51736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36451:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#51737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36452:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#51738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36453:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36454:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#51740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36455:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#51741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36456:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#51742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36457:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#51743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36458:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#51744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36459:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#51745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36460:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#51746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36461:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#51747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36462:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L

WARNING: line length of 121 exceeds 100 columns
#51748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36463:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#51749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36464:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#51750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36465:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#51751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36466:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#51752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36467:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#51753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36468:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L

WARNING: line length of 113 exceeds 100 columns
#51754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36469:
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#51755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36470:
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#51756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36471:
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#51757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36472:
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#51758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36473:
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#51759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36474:
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#51760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36475:
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#51761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36476:
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36477:
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#51763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36478:
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#51764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36479:
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#51765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36480:
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#51766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36481:
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb

WARNING: line length of 113 exceeds 100 columns
#51767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36482:
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#51768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36483:
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#51769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36484:
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe

WARNING: line length of 113 exceeds 100 columns
#51770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36485:
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf

WARNING: line length of 114 exceeds 100 columns
#51771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36486:
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#51772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36487:
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#51773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36488:
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#51774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36489:
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#51775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36490:
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#51776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36491:
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#51777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36492:
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#51778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36493:
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#51779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36494:
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36495:
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#51781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36496:
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#51782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36497:
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36498:
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36499:
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#51785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36500:
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#51786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36501:
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36502:
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36503:
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#51789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36504:
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#51790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36505:
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#51791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36506:
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36507:
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#51793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36508:
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#51794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36509:
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#51795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36510:
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36511:
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#51797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36512:
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#51798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36513:
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#51799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36514:
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#51800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36515:
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36516:
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#51802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36517:
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#51803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36518:
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#51804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36519:
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36520:
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36521:
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#51807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36522:
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#51808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36523:
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36524:
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36525:
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#51811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36526:
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#51812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36527:
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36528:
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36529:
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#51815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36530:
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#51816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36531:
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#51817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36532:
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36533:
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#51819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36534:
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36535:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36536:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#51822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36537:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#51823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36538:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#51824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36539:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#51825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36540:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#51826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36541:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#51827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36542:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36543:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#51829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36544:
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#51830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36545:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36546:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#51832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36547:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#51833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36548:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#51834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36549:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36550:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36551:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#51837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36552:
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#51838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36553:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36554:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#51840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36555:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#51841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36556:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#51842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36557:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36558:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36559:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#51845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36560:
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#51846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36561:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36562:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#51848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36563:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#51849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36564:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#51850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36565:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36566:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36567:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#51853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36568:
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#51854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36569:
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#51855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36570:
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#51856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36571:
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#51857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36572:
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#51858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36573:
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#51859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36574:
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#51860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36575:
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#51861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36576:
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36577:
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36578:
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36579:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#51865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36580:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#51866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36581:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#51867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36582:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#51868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36583:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#51869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36584:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#51870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36585:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36586:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#51872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36587:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#51873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36588:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36589:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36590:
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36591:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#51877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36592:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#51878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36593:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#51879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36594:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#51880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36595:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#51881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36596:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#51882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36597:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36598:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#51884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36599:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#51885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36600:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36601:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36602:
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36603:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#51889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36604:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#51890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36605:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#51891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36606:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#51892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36607:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#51893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36608:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#51894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36609:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36610:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#51896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36611:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#51897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36612:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36613:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36614:
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36615:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#51901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36616:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#51902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36617:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#51903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36618:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#51904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36619:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#51905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36620:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#51906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36621:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36622:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#51908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36623:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#51909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36624:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36625:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36626:
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36627:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#51913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36628:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#51914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36629:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#51915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36630:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#51916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36631:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#51917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36632:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#51918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36633:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36634:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#51920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36635:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#51921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36636:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36637:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36638:
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36639:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36640:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#51926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36641:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#51927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36642:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#51928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36643:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#51929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36644:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#51930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36645:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36646:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#51932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36647:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#51933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36648:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36649:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36650:
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36651:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#51937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36652:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#51938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36653:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#51939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36654:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#51940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36655:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#51941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36656:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#51942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36657:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#51943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36658:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#51944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36659:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#51945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36660:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#51946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36661:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#51947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36662:
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#51948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36663:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#51949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36664:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#51950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36665:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#51951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36666:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10

WARNING: line length of 114 exceeds 100 columns
#51952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36667:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14

WARNING: line length of 114 exceeds 100 columns
#51953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36668:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#51954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36669:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#51955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36670:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#51956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36671:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L

WARNING: line length of 121 exceeds 100 columns
#51957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36672:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#51958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36673:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L

WARNING: line length of 121 exceeds 100 columns
#51959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36674:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#51960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36675:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#51961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36676:
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#51962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36677:
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#51963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36678:
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36679:
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#51965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36680:
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36681:
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#51967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36682:
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36683:
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#51969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36684:
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36685:
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#51971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36686:
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36687:
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#51973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36688:
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#51974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36689:
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#51975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36690:
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#51976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36691:
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#51977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36692:
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#51978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36693:
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#51979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36694:
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#51980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36695:
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#51981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36696:
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#51982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36697:
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#51983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36698:
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#51984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36699:
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#51985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36700:
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#51986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36701:
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#51987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36702:
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#51988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36703:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#51989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36704:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#51990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36705:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#51991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36706:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#51992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36707:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#51993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36708:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#51994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36709:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#51995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36710:
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#51996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36711:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#51997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36712:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#51998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36713:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#51999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36714:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#52000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36715:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#52001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36716:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#52002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36717:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#52003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36718:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#52004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36719:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#52005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36720:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#52006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36721:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#52007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36722:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#52008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36723:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#52009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36724:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#52010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36725:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#52011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36726:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#52012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36727:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36728:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#52014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36729:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#52015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36730:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#52016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36731:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36732:
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36733:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#52019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36734:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#52020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36735:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#52021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36736:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#52022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36737:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#52023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36738:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36739:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36740:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36741:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#52027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36742:
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36743:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36744:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#52030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36745:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#52031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36746:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#52032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36747:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#52033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36748:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#52034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36749:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#52035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36750:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#52036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36751:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36752:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#52038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36753:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#52039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36754:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#52040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36755:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#52041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36756:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#52042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36757:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#52043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36758:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#52044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36759:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36760:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36761:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#52047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36762:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#52048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36763:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#52049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36764:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36765:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#52051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36766:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#52052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36767:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#52053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36768:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#52054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36769:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#52055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36770:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36771:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#52057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36772:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36773:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#52059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36774:
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#52060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36775:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#52061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36776:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#52062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36777:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#52063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36778:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#52064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36779:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#52065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36780:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#52066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36781:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36782:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#52068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36783:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#52069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36784:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#52070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36785:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#52071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36786:
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#52072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36787:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#52073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36788:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#52074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36789:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#52075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36790:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#52076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36791:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36792:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36793:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#52079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36794:
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#52080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36795:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#52081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36796:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#52082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36797:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#52083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36798:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#52084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36799:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#52085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36800:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#52086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36801:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#52087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36802:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#52088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36803:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#52089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36804:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#52090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36805:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#52091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36806:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#52092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36807:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#52093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36808:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#52094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36809:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#52095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36810:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#52096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36811:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#52097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36812:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36813:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36814:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36815:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36816:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36817:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#52103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36818:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#52104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36819:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#52105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36820:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36821:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#52107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36822:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36823:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#52109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36824:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#52110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36825:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#52111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36826:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#52112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36827:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#52113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36828:
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36829:
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#52115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36830:
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36831:
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#52117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36832:
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#52118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36833:
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36834:
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36835:
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#52121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36836:
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36837:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36838:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#52124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36839:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#52125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36840:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36841:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36842:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#52128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36843:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#52129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36844:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#52130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36845:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#52131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36846:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#52132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36847:
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#52133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36848:
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#52134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36849:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36850:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36851:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36852:
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L

WARNING: line length of 121 exceeds 100 columns
#52138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36853:
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#52139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36854:
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#52140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36855:
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#52141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36856:
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36857:
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36858:
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36859:
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#52145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36860:
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#52146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36861:
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#52147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36862:
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#52148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36863:
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36864:
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36865:
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#52151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36866:
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36867:
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#52153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36868:
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#52154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36869:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#52155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36870:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1

WARNING: line length of 113 exceeds 100 columns
#52156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36871:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2

WARNING: line length of 113 exceeds 100 columns
#52157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36872:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3

WARNING: line length of 113 exceeds 100 columns
#52158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36873:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4

WARNING: line length of 113 exceeds 100 columns
#52159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36874:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#52160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36875:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6

WARNING: line length of 113 exceeds 100 columns
#52161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36876:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#52162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36877:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#52163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36878:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9

WARNING: line length of 113 exceeds 100 columns
#52164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36879:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa

WARNING: line length of 113 exceeds 100 columns
#52165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36880:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb

WARNING: line length of 114 exceeds 100 columns
#52166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36881:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#52167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36882:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11

WARNING: line length of 114 exceeds 100 columns
#52168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36883:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12

WARNING: line length of 114 exceeds 100 columns
#52169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36884:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13

WARNING: line length of 114 exceeds 100 columns
#52170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36885:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14

WARNING: line length of 114 exceeds 100 columns
#52171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36886:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15

WARNING: line length of 114 exceeds 100 columns
#52172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36887:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16

WARNING: line length of 114 exceeds 100 columns
#52173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36888:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17

WARNING: line length of 114 exceeds 100 columns
#52174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36889:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#52175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36890:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19

WARNING: line length of 114 exceeds 100 columns
#52176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36891:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a

WARNING: line length of 114 exceeds 100 columns
#52177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36892:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b

WARNING: line length of 121 exceeds 100 columns
#52178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36893:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36894:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36895:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36896:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36897:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36898:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#52184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36899:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#52185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36900:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#52186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36901:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36902:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#52188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36903:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36904:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#52190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36905:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#52191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36906:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#52192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36907:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#52193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36908:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#52194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36909:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#52195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36910:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L

WARNING: line length of 121 exceeds 100 columns
#52196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36911:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36912:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#52198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36913:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#52199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36914:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#52200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36915:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36916:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L

WARNING: line length of 113 exceeds 100 columns
#52202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36917:
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#52203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36918:
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#52204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36919:
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#52205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36920:
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#52206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36921:
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#52207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36922:
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#52208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36923:
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#52209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36924:
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36925:
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#52211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36926:
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#52212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36927:
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36928:
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#52214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36929:
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb

WARNING: line length of 113 exceeds 100 columns
#52215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36930:
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#52216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36931:
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#52217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36932:
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe

WARNING: line length of 113 exceeds 100 columns
#52218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36933:
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf

WARNING: line length of 114 exceeds 100 columns
#52219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36934:
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36935:
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#52221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36936:
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36937:
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#52223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36938:
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#52224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36939:
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#52225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36940:
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#52226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36941:
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#52227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36942:
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36943:
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#52229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36944:
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36945:
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36946:
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36947:
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#52233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36948:
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#52234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36949:
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36950:
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36951:
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#52237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36952:
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#52238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36953:
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#52239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36954:
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36955:
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#52241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36956:
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#52242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36957:
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#52243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36958:
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36959:
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#52245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36960:
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#52246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36961:
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#52247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36962:
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#52248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36963:
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36964:
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#52250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36965:
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#52251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36966:
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#52252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36967:
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36968:
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36969:
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#52255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36970:
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#52256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36971:
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36972:
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36973:
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#52259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36974:
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#52260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36975:
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36976:
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36977:
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#52263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36978:
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#52264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36979:
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#52265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36980:
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36981:
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#52267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36982:
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36983:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36984:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#52270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36985:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#52271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36986:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#52272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36987:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#52273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36988:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#52274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36989:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#52275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36990:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36991:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#52277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36992:
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#52278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36993:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36994:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#52280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36995:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36996:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#52282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36997:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36998:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:36999:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#52285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37000:
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#52286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37001:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37002:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#52288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37003:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37004:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#52290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37005:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37006:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37007:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#52293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37008:
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#52294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37009:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37010:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#52296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37011:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#52297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37012:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#52298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37013:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37014:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37015:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#52301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37016:
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#52302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37017:
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#52303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37018:
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#52304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37019:
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37020:
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37021:
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37022:
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37023:
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37024:
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37025:
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37026:
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37027:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37028:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37029:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37030:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37031:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37032:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37033:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37034:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37035:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37036:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37037:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37038:
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37039:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37040:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37041:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37042:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37043:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37044:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37045:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37046:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37047:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37048:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37049:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37050:
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37051:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37052:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37053:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37054:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37055:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37056:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37057:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37058:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37059:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37060:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37061:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37062:
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37063:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37064:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37065:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37066:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37067:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37068:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37069:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37070:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37071:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37072:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37073:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37074:
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37075:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37076:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37077:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37078:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37079:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#52365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37080:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#52366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37081:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37082:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37083:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37084:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37085:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37086:
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37087:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37088:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#52374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37089:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#52375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37090:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37091:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#52377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37092:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#52378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37093:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37094:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37095:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37096:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37097:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37098:
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37099:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37100:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#52386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37101:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#52387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37102:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37103:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#52389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37104:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#52390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37105:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37106:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37107:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37108:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37109:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37110:
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37111:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#52397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37112:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#52398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37113:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#52399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37114:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10

WARNING: line length of 114 exceeds 100 columns
#52400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37115:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14

WARNING: line length of 114 exceeds 100 columns
#52401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37116:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#52402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37117:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#52403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37118:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37119:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L

WARNING: line length of 121 exceeds 100 columns
#52405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37120:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37121:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L

WARNING: line length of 121 exceeds 100 columns
#52407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37122:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#52408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37123:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#52409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37124:
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#52410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37125:
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#52411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37126:
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37127:
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#52413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37128:
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37129:
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37130:
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37131:
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37132:
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37133:
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37134:
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37135:
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37136:
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37137:
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#52423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37138:
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37139:
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37140:
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37141:
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#52427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37142:
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#52428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37143:
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37144:
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37145:
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37146:
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37147:
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37148:
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37149:
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37150:
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37151:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37152:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37153:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37154:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37155:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37156:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37157:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37158:
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37159:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#52445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37160:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#52446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37161:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#52447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37162:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#52448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37163:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#52449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37164:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#52450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37165:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#52451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37166:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#52452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37167:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#52453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37168:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#52454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37169:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#52455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37170:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#52456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37171:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#52457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37172:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#52458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37173:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#52459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37174:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#52460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37175:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37176:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#52462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37177:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#52463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37178:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#52464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37179:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37180:
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37181:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#52467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37182:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#52468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37183:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#52469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37184:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#52470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37185:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#52471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37186:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37187:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37188:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37189:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#52475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37190:
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37191:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37192:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#52478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37193:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#52479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37194:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#52480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37195:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#52481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37196:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#52482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37197:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#52483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37198:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#52484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37199:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37200:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#52486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37201:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#52487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37202:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#52488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37203:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#52489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37204:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#52490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37205:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#52491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37206:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#52492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37207:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37208:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37209:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#52495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37210:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#52496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37211:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#52497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37212:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37213:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#52499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37214:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#52500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37215:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#52501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37216:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#52502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37217:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#52503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37218:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37219:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#52505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37220:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37221:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#52507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37222:
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#52508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37223:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#52509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37224:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#52510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37225:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#52511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37226:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#52512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37227:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#52513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37228:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#52514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37229:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37230:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#52516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37231:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#52517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37232:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#52518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37233:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#52519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37234:
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#52520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37235:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#52521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37236:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#52522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37237:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#52523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37238:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#52524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37239:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37240:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37241:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#52527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37242:
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#52528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37243:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#52529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37244:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#52530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37245:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#52531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37246:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#52532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37247:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#52533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37248:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#52534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37249:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#52535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37250:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#52536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37251:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#52537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37252:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#52538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37253:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#52539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37254:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#52540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37255:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#52541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37256:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#52542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37257:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#52543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37258:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#52544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37259:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#52545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37260:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37261:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37262:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37263:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37264:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37265:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#52551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37266:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#52552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37267:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#52553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37268:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37269:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#52555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37270:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37271:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#52557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37272:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#52558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37273:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#52559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37274:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#52560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37275:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#52561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37276:
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37277:
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#52563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37278:
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37279:
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#52565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37280:
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#52566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37281:
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37282:
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37283:
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#52569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37284:
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37285:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37286:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#52572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37287:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#52573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37288:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37289:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37290:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#52576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37291:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#52577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37292:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#52578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37293:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#52579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37294:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#52580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37295:
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#52581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37296:
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#52582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37297:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37298:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37299:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37300:
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L

WARNING: line length of 121 exceeds 100 columns
#52586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37301:
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#52587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37302:
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#52588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37303:
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#52589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37304:
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37305:
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37306:
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37307:
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#52593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37308:
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#52594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37309:
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#52595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37310:
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#52596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37311:
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37312:
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37313:
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#52599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37314:
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37315:
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#52601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37316:
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#52602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37317:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#52603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37318:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1

WARNING: line length of 113 exceeds 100 columns
#52604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37319:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2

WARNING: line length of 113 exceeds 100 columns
#52605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37320:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3

WARNING: line length of 113 exceeds 100 columns
#52606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37321:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4

WARNING: line length of 113 exceeds 100 columns
#52607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37322:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#52608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37323:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6

WARNING: line length of 113 exceeds 100 columns
#52609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37324:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#52610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37325:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#52611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37326:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9

WARNING: line length of 113 exceeds 100 columns
#52612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37327:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa

WARNING: line length of 113 exceeds 100 columns
#52613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37328:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb

WARNING: line length of 114 exceeds 100 columns
#52614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37329:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#52615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37330:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11

WARNING: line length of 114 exceeds 100 columns
#52616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37331:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12

WARNING: line length of 114 exceeds 100 columns
#52617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37332:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13

WARNING: line length of 114 exceeds 100 columns
#52618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37333:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14

WARNING: line length of 114 exceeds 100 columns
#52619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37334:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15

WARNING: line length of 114 exceeds 100 columns
#52620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37335:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16

WARNING: line length of 114 exceeds 100 columns
#52621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37336:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17

WARNING: line length of 114 exceeds 100 columns
#52622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37337:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#52623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37338:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19

WARNING: line length of 114 exceeds 100 columns
#52624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37339:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a

WARNING: line length of 114 exceeds 100 columns
#52625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37340:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b

WARNING: line length of 121 exceeds 100 columns
#52626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37341:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37342:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37343:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37344:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37345:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37346:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#52632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37347:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#52633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37348:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#52634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37349:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37350:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#52636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37351:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37352:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#52638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37353:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#52639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37354:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#52640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37355:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#52641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37356:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#52642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37357:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#52643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37358:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L

WARNING: line length of 121 exceeds 100 columns
#52644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37359:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37360:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#52646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37361:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#52647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37362:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#52648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37363:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37364:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L

WARNING: line length of 113 exceeds 100 columns
#52650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37365:
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#52651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37366:
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#52652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37367:
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#52653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37368:
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#52654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37369:
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#52655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37370:
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#52656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37371:
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#52657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37372:
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37373:
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#52659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37374:
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#52660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37375:
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37376:
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#52662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37377:
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb

WARNING: line length of 113 exceeds 100 columns
#52663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37378:
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#52664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37379:
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#52665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37380:
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe

WARNING: line length of 113 exceeds 100 columns
#52666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37381:
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf

WARNING: line length of 114 exceeds 100 columns
#52667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37382:
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37383:
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#52669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37384:
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37385:
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#52671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37386:
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#52672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37387:
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#52673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37388:
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#52674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37389:
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#52675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37390:
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37391:
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#52677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37392:
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37393:
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37394:
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37395:
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#52681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37396:
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#52682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37397:
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37398:
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37399:
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#52685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37400:
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#52686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37401:
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#52687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37402:
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37403:
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#52689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37404:
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#52690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37405:
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#52691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37406:
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37407:
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#52693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37408:
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#52694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37409:
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#52695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37410:
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#52696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37411:
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37412:
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#52698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37413:
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#52699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37414:
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#52700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37415:
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37416:
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37417:
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#52703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37418:
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#52704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37419:
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37420:
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37421:
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#52707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37422:
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#52708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37423:
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37424:
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37425:
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#52711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37426:
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#52712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37427:
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#52713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37428:
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37429:
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#52715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37430:
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37431:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37432:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#52718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37433:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#52719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37434:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#52720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37435:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#52721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37436:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#52722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37437:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#52723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37438:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37439:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#52725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37440:
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#52726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37441:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37442:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#52728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37443:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37444:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#52730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37445:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37446:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37447:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#52733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37448:
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#52734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37449:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37450:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#52736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37451:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37452:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#52738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37453:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37454:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37455:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#52741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37456:
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#52742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37457:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37458:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#52744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37459:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#52745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37460:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#52746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37461:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37462:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37463:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#52749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37464:
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#52750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37465:
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#52751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37466:
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#52752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37467:
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37468:
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37469:
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37470:
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#52756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37471:
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#52757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37472:
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37473:
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37474:
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37475:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37476:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37477:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37478:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37479:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37480:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37481:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37482:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37483:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37484:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37485:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37486:
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37487:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37488:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37489:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37490:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37491:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37492:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37493:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37494:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37495:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37496:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37497:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37498:
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37499:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37500:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37501:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37502:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37503:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37504:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37505:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37506:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37507:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37508:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37509:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37510:
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37511:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37512:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37513:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37514:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37515:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#52801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37516:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#52802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37517:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37518:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37519:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37520:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37521:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37522:
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37523:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37524:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#52810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37525:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#52811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37526:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37527:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#52813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37528:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#52814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37529:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37530:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37531:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37532:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37533:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37534:
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37535:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37536:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#52822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37537:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#52823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37538:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37539:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#52825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37540:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#52826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37541:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37542:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37543:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37544:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37545:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37546:
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37547:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#52833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37548:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#52834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37549:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#52835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37550:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#52836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37551:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#52837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37552:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#52838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37553:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#52839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37554:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#52840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37555:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#52841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37556:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#52842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37557:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#52843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37558:
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#52844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37559:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#52845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37560:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#52846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37561:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#52847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37562:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10

WARNING: line length of 114 exceeds 100 columns
#52848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37563:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14

WARNING: line length of 114 exceeds 100 columns
#52849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37564:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#52850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37565:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#52851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37566:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37567:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L

WARNING: line length of 121 exceeds 100 columns
#52853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37568:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#52854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37569:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L

WARNING: line length of 121 exceeds 100 columns
#52855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37570:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#52856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37571:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#52857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37572:
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#52858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37573:
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#52859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37574:
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37575:
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#52861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37576:
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37577:
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37578:
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37579:
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37580:
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37581:
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37582:
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37583:
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#52869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37584:
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#52870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37585:
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#52871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37586:
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#52872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37587:
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#52873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37588:
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#52874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37589:
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#52875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37590:
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#52876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37591:
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37592:
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37593:
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37594:
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37595:
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37596:
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37597:
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#52883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37598:
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37599:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37600:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37601:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37602:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37603:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37604:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#52890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37605:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#52891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37606:
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#52892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37607:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#52893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37608:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#52894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37609:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#52895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37610:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#52896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37611:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#52897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37612:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#52898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37613:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#52899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37614:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#52900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37615:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#52901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37616:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#52902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37617:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#52903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37618:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#52904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37619:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#52905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37620:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#52906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37621:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#52907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37622:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#52908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37623:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37624:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#52910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37625:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#52911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37626:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#52912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37627:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37628:
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37629:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#52915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37630:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#52916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37631:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#52917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37632:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#52918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37633:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#52919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37634:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37635:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37636:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37637:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#52923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37638:
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#52924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37639:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#52925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37640:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#52926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37641:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#52927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37642:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#52928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37643:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#52929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37644:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#52930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37645:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#52931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37646:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#52932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37647:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#52933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37648:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#52934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37649:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#52935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37650:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#52936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37651:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#52937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37652:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#52938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37653:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#52939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37654:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#52940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37655:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37656:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37657:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#52943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37658:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#52944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37659:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#52945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37660:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#52946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37661:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#52947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37662:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#52948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37663:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#52949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37664:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#52950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37665:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#52951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37666:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#52952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37667:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#52953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37668:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#52954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37669:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#52955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37670:
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#52956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37671:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#52957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37672:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#52958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37673:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#52959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37674:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#52960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37675:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#52961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37676:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#52962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37677:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#52963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37678:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#52964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37679:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#52965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37680:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#52966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37681:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#52967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37682:
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#52968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37683:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#52969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37684:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#52970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37685:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#52971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37686:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#52972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37687:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37688:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37689:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#52975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37690:
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#52976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37691:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#52977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37692:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#52978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37693:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#52979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37694:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#52980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37695:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#52981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37696:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#52982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37697:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#52983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37698:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#52984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37699:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#52985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37700:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#52986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37701:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#52987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37702:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#52988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37703:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#52989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37704:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#52990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37705:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#52991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37706:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#52992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37707:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#52993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37708:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#52994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37709:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#52995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37710:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#52996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37711:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#52997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37712:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#52998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37713:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#52999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37714:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#53000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37715:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#53001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37716:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37717:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#53003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37718:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37719:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#53005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37720:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#53006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37721:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#53007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37722:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#53008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37723:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#53009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37724:
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37725:
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#53011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37726:
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37727:
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#53013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37728:
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#53014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37729:
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37730:
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#53016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37731:
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#53017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37732:
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37733:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37734:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#53020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37735:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#53021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37736:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37737:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37738:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L

WARNING: line length of 113 exceeds 100 columns
#53024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37739:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#53025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37740:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#53026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37741:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#53027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37742:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#53028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37743:
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#53029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37744:
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18

WARNING: line length of 121 exceeds 100 columns
#53030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37745:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37746:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37747:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37748:
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37749:
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#53035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37750:
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L

WARNING: line length of 113 exceeds 100 columns
#53036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37751:
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#53037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37752:
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#53038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37753:
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37754:
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37755:
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#53041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37756:
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#53042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37757:
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#53043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37758:
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#53044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37759:
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37760:
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37761:
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#53047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37762:
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37763:
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#53049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37764:
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#53050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37765:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#53051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37766:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1

WARNING: line length of 113 exceeds 100 columns
#53052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37767:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2

WARNING: line length of 113 exceeds 100 columns
#53053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37768:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3

WARNING: line length of 113 exceeds 100 columns
#53054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37769:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4

WARNING: line length of 113 exceeds 100 columns
#53055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37770:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#53056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37771:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6

WARNING: line length of 113 exceeds 100 columns
#53057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37772:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#53058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37773:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#53059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37774:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9

WARNING: line length of 113 exceeds 100 columns
#53060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37775:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa

WARNING: line length of 113 exceeds 100 columns
#53061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37776:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb

WARNING: line length of 114 exceeds 100 columns
#53062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37777:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#53063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37778:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11

WARNING: line length of 114 exceeds 100 columns
#53064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37779:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12

WARNING: line length of 114 exceeds 100 columns
#53065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37780:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13

WARNING: line length of 114 exceeds 100 columns
#53066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37781:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14

WARNING: line length of 114 exceeds 100 columns
#53067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37782:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15

WARNING: line length of 114 exceeds 100 columns
#53068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37783:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16

WARNING: line length of 114 exceeds 100 columns
#53069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37784:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17

WARNING: line length of 114 exceeds 100 columns
#53070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37785:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#53071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37786:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19

WARNING: line length of 114 exceeds 100 columns
#53072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37787:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a

WARNING: line length of 114 exceeds 100 columns
#53073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37788:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b

WARNING: line length of 121 exceeds 100 columns
#53074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37789:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37790:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#53076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37791:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#53077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37792:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#53078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37793:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37794:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#53080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37795:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#53081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37796:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#53082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37797:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37798:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#53084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37799:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37800:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#53086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37801:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#53087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37802:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#53088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37803:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L

WARNING: line length of 121 exceeds 100 columns
#53089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37804:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L

WARNING: line length of 121 exceeds 100 columns
#53090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37805:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L

WARNING: line length of 121 exceeds 100 columns
#53091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37806:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L

WARNING: line length of 121 exceeds 100 columns
#53092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37807:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L

WARNING: line length of 121 exceeds 100 columns
#53093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37808:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L

WARNING: line length of 121 exceeds 100 columns
#53094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37809:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#53095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37810:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L

WARNING: line length of 121 exceeds 100 columns
#53096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37811:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L

WARNING: line length of 121 exceeds 100 columns
#53097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37812:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L

WARNING: line length of 113 exceeds 100 columns
#53098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37813:
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#53099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37814:
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#53100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37815:
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#53101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37816:
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#53102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37817:
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c

WARNING: line length of 121 exceeds 100 columns
#53103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37818:
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#53104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37819:
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#53105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37820:
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#53106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37821:
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#53107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37822:
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#53108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37823:
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37824:
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#53110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37825:
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb

WARNING: line length of 113 exceeds 100 columns
#53111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37826:
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#53112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37827:
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd

WARNING: line length of 113 exceeds 100 columns
#53113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37828:
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe

WARNING: line length of 113 exceeds 100 columns
#53114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37829:
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf

WARNING: line length of 114 exceeds 100 columns
#53115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37830:
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#53116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37831:
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#53117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37832:
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37833:
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#53119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37834:
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#53120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37835:
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#53121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37836:
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#53122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37837:
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#53123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37838:
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37839:
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#53125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37840:
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#53126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37841:
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37842:
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37843:
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#53129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37844:
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#53130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37845:
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37846:
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37847:
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#53133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37848:
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#53134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37849:
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#53135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37850:
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37851:
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#53137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37852:
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10

WARNING: line length of 121 exceeds 100 columns
#53138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37853:
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#53139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37854:
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37855:
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#53141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37856:
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#53142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37857:
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18

WARNING: line length of 121 exceeds 100 columns
#53143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37858:
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#53144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37859:
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37860:
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#53146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37861:
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#53147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37862:
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#53148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37863:
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37864:
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37865:
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#53151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37866:
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37867:
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37868:
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37869:
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#53155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37870:
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#53156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37871:
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37872:
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37873:
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#53159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37874:
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#53160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37875:
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#53161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37876:
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37877:
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#53163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37878:
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37879:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#53165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37880:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#53166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37881:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#53167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37882:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18

WARNING: line length of 114 exceeds 100 columns
#53168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37883:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#53169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37884:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#53170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37885:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#53171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37886:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37887:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#53173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37888:
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#53174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37889:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#53175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37890:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#53176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37891:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#53177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37892:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#53178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37893:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#53179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37894:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#53180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37895:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#53181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37896:
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#53182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37897:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#53183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37898:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#53184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37899:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#53185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37900:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#53186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37901:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#53187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37902:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#53188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37903:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#53189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37904:
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#53190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37905:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#53191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37906:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8

WARNING: line length of 114 exceeds 100 columns
#53192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37907:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10

WARNING: line length of 114 exceeds 100 columns
#53193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37908:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#53194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37909:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#53195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37910:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#53196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37911:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#53197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37912:
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#53198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37913:
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#53199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37914:
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8

WARNING: line length of 114 exceeds 100 columns
#53200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37915:
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#53201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37916:
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#53202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37917:
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#53203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37918:
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#53204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37919:
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#53205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37920:
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37921:
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37922:
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37923:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37924:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#53210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37925:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#53211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37926:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#53212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37927:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#53213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37928:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#53214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37929:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37930:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#53216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37931:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#53217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37932:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37933:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37934:
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37935:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37936:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#53222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37937:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#53223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37938:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#53224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37939:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#53225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37940:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#53226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37941:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37942:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#53228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37943:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#53229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37944:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37945:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37946:
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37947:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37948:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#53234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37949:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#53235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37950:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#53236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37951:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#53237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37952:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#53238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37953:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37954:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#53240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37955:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#53241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37956:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37957:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37958:
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37959:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37960:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#53246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37961:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#53247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37962:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#53248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37963:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15

WARNING: line length of 114 exceeds 100 columns
#53249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37964:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a

WARNING: line length of 121 exceeds 100 columns
#53250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37965:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37966:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#53252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37967:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#53253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37968:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37969:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37970:
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37971:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37972:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5

WARNING: line length of 113 exceeds 100 columns
#53258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37973:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa

WARNING: line length of 114 exceeds 100 columns
#53259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37974:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#53260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37975:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#53261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37976:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#53262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37977:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37978:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#53264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37979:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#53265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37980:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37981:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37982:
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37983:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#53269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37984:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#53270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37985:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#53271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37986:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#53272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37987:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#53273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37988:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#53274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37989:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37990:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#53276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37991:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#53277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37992:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37993:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37994:
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37995:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#53281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37996:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#53282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37997:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa

WARNING: line length of 114 exceeds 100 columns
#53283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37998:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#53284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:37999:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15

WARNING: line length of 114 exceeds 100 columns
#53285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38000:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#53286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38001:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#53287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38002:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L

WARNING: line length of 121 exceeds 100 columns
#53288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38003:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L

WARNING: line length of 121 exceeds 100 columns
#53289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38004:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#53290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38005:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L

WARNING: line length of 121 exceeds 100 columns
#53291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38006:
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L

WARNING: line length of 113 exceeds 100 columns
#53292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38007:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38008:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#53294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38009:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8

WARNING: line length of 114 exceeds 100 columns
#53295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38010:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10

WARNING: line length of 114 exceeds 100 columns
#53296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38011:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14

WARNING: line length of 114 exceeds 100 columns
#53297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38012:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18

WARNING: line length of 114 exceeds 100 columns
#53298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38013:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c

WARNING: line length of 121 exceeds 100 columns
#53299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38014:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38015:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L

WARNING: line length of 121 exceeds 100 columns
#53301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38016:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38017:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L

WARNING: line length of 121 exceeds 100 columns
#53303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38018:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L

WARNING: line length of 121 exceeds 100 columns
#53304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38019:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#53305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38020:
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L

WARNING: line length of 113 exceeds 100 columns
#53306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38021:
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#53307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38022:
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38023:
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#53309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38024:
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38025:
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#53311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38026:
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38027:
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#53313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38028:
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38029:
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#53315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38030:
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38031:
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#53317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38032:
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38033:
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#53319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38034:
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#53320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38035:
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38036:
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38037:
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#53323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38038:
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#53324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38039:
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#53325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38040:
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38041:
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#53327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38042:
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38043:
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#53329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38044:
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38045:
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#53331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38046:
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#53332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38047:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#53333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38048:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#53334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38049:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#53335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38050:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#53336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38051:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#53337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38052:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 116 exceeds 100 columns
#53338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38053:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0

WARNING: line length of 122 exceeds 100 columns
#53339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38054:
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38055:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#53341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38056:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#53342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38057:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#53343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38058:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#53344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38059:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#53345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38060:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#53346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38061:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#53347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38062:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#53348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38063:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#53349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38064:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#53350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38065:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#53351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38066:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38067:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#53353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38068:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38069:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#53355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38070:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#53356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38071:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#53357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38072:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#53358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38073:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#53359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38074:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#53360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38075:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#53361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38076:
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#53362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38077:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38078:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#53364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38079:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#53365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38080:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#53366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38081:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#53367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38082:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38083:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#53369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38084:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#53370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38085:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#53371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38086:
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#53372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38087:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38088:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#53374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38089:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#53375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38090:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#53376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38091:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#53377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38092:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#53378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38093:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#53379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38094:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#53380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38095:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#53381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38096:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#53382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38097:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#53383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38098:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#53384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38099:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#53385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38100:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#53386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38101:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#53387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38102:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#53388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38103:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38104:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#53390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38105:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#53391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38106:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#53392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38107:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#53393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38108:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38109:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#53395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38110:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#53396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38111:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#53397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38112:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#53398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38113:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#53399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38114:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#53400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38115:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#53401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38116:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#53402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38117:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#53403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38118:
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#53404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38119:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#53405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38120:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#53406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38121:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#53407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38122:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#53408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38123:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#53409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38124:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#53410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38125:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38126:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#53412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38127:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#53413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38128:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#53414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38129:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#53415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38130:
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#53416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38131:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#53417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38132:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#53418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38133:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#53419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38134:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#53420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38135:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38136:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#53422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38137:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#53423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38138:
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#53424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38139:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#53425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38140:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#53426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38141:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#53427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38142:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#53428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38143:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#53429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38144:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#53430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38145:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#53431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38146:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#53432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38147:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#53433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38148:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#53434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38149:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#53435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38150:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#53436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38151:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#53437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38152:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#53438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38153:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#53439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38154:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#53440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38155:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#53441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38156:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38157:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#53443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38158:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#53444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38159:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#53445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38160:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38161:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#53447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38162:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#53448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38163:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#53449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38164:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38165:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#53451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38166:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38167:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#53453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38168:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#53454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38169:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#53455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38170:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#53456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38171:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#53457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38172:
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38173:
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#53459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38174:
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38175:
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#53461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38176:
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#53462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38177:
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38178:
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#53464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38179:
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#53465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38180:
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38181:
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#53467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38182:
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#53468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38183:
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#53469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38184:
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#53470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38185:
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38186:
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38187:
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38188:
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L

WARNING: line length of 113 exceeds 100 columns
#53474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38189:
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#53475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38190:
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa

WARNING: line length of 113 exceeds 100 columns
#53476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38191:
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc

WARNING: line length of 114 exceeds 100 columns
#53477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38192:
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#53478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38193:
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12

WARNING: line length of 114 exceeds 100 columns
#53479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38194:
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14

WARNING: line length of 121 exceeds 100 columns
#53480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38195:
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#53481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38196:
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38197:
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L

WARNING: line length of 121 exceeds 100 columns
#53483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38198:
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L

WARNING: line length of 121 exceeds 100 columns
#53484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38199:
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#53485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38200:
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L

WARNING: line length of 113 exceeds 100 columns
#53486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38201:
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#53487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38202:
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#53488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38203:
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8

WARNING: line length of 113 exceeds 100 columns
#53489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38204:
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc

WARNING: line length of 114 exceeds 100 columns
#53490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38205:
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10

WARNING: line length of 114 exceeds 100 columns
#53491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38206:
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14

WARNING: line length of 114 exceeds 100 columns
#53492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38207:
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#53493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38208:
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38209:
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#53495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38210:
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38211:
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L

WARNING: line length of 121 exceeds 100 columns
#53497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38212:
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L

WARNING: line length of 121 exceeds 100 columns
#53498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38213:
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L

WARNING: line length of 121 exceeds 100 columns
#53499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38214:
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#53500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38215:
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0

WARNING: line length of 121 exceeds 100 columns
#53501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38216:
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#53502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38217:
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#53503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38218:
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#53504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38219:
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL

WARNING: line length of 121 exceeds 100 columns
#53505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38220:
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L

WARNING: line length of 113 exceeds 100 columns
#53506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38221:
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#53507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38222:
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#53508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38223:
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#53509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38224:
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#53510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38225:
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0

WARNING: line length of 114 exceeds 100 columns
#53511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38226:
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#53512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38227:
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#53513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38228:
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#53514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38229:
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#53515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38230:
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4

WARNING: line length of 121 exceeds 100 columns
#53516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38231:
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38232:
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L

WARNING: line length of 113 exceeds 100 columns
#53518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38233:
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#53519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38234:
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#53520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38235:
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8

WARNING: line length of 121 exceeds 100 columns
#53521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38236:
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38237:
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38238:
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L

WARNING: line length of 113 exceeds 100 columns
#53524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38239:
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#53525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38240:
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#53526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38241:
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38242:
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38243:
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#53529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38244:
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10

WARNING: line length of 121 exceeds 100 columns
#53530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38245:
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38246:
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38247:
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0

WARNING: line length of 114 exceeds 100 columns
#53533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38248:
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10

WARNING: line length of 121 exceeds 100 columns
#53534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38249:
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38250:
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38251:
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0

WARNING: line length of 114 exceeds 100 columns
#53537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38252:
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38253:
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38254:
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38255:
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#53541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38256:
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#53542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38257:
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#53543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38258:
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14

WARNING: line length of 121 exceeds 100 columns
#53544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38259:
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38260:
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#53546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38261:
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L

WARNING: line length of 121 exceeds 100 columns
#53547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38262:
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L

WARNING: line length of 113 exceeds 100 columns
#53548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38263:
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#53549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38264:
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#53550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38265:
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#53551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38266:
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#53552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38267:
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#53553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38268:
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#53554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38269:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#53555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38270:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#53556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38271:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#53557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38272:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#53558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38273:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14

WARNING: line length of 121 exceeds 100 columns
#53559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38274:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38275:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38276:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#53562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38277:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#53563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38278:
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L

WARNING: line length of 113 exceeds 100 columns
#53564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38279:
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#53565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38280:
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4

WARNING: line length of 114 exceeds 100 columns
#53566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38281:
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10

WARNING: line length of 121 exceeds 100 columns
#53567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38282:
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38283:
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L

WARNING: line length of 121 exceeds 100 columns
#53569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38284:
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L

WARNING: line length of 113 exceeds 100 columns
#53570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38285:
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38286:
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L

WARNING: line length of 113 exceeds 100 columns
#53572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38287:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#53573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38288:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#53574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38289:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#53575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38290:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#53576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38291:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#53577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38292:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#53578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38293:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#53579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38294:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#53580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38295:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#53581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38296:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#53582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38297:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#53583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38298:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38299:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#53585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38300:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38301:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#53587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38302:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#53588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38303:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#53589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38304:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#53590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38305:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#53591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38306:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#53592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38307:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#53593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38308:
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#53594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38309:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38310:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#53596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38311:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#53597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38312:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#53598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38313:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#53599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38314:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38315:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#53601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38316:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#53602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38317:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#53603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38318:
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#53604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38319:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#53605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38320:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#53606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38321:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#53607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38322:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#53608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38323:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#53609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38324:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#53610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38325:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#53611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38326:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#53612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38327:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#53613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38328:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#53614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38329:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#53615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38330:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#53616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38331:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#53617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38332:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#53618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38333:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#53619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38334:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#53620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38335:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38336:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#53622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38337:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#53623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38338:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#53624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38339:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#53625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38340:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38341:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#53627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38342:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#53628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38343:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#53629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38344:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#53630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38345:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#53631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38346:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#53632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38347:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#53633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38348:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#53634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38349:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#53635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38350:
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#53636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38351:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#53637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38352:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#53638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38353:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#53639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38354:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#53640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38355:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#53641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38356:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#53642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38357:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38358:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#53644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38359:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#53645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38360:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#53646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38361:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#53647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38362:
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#53648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38363:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#53649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38364:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#53650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38365:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#53651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38366:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#53652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38367:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38368:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#53654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38369:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#53655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38370:
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#53656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38371:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#53657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38372:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#53658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38373:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#53659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38374:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#53660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38375:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#53661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38376:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#53662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38377:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#53663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38378:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#53664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38379:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#53665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38380:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#53666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38381:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#53667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38382:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#53668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38383:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#53669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38384:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#53670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38385:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#53671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38386:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#53672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38387:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#53673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38388:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#53674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38389:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#53675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38390:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#53676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38391:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#53677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38392:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38393:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#53679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38394:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#53680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38395:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#53681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38396:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38397:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#53683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38398:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#53684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38399:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#53685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38400:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#53686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38401:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#53687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38402:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#53688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38403:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#53689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38404:
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38405:
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#53691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38406:
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38407:
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#53693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38408:
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#53694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38409:
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38410:
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#53696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38411:
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#53697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38412:
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#53698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38413:
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#53699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38414:
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#53700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38415:
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0

WARNING: line length of 114 exceeds 100 columns
#53701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38416:
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18

WARNING: line length of 121 exceeds 100 columns
#53702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38417:
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38418:
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L

WARNING: line length of 113 exceeds 100 columns
#53704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38419:
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#53705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38420:
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L

WARNING: line length of 113 exceeds 100 columns
#53706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38421:
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38422:
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38423:
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38424:
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38425:
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38426:
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38427:
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38428:
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38429:
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38430:
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38431:
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38432:
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38433:
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38434:
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38435:
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38436:
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38437:
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38438:
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38439:
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38440:
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38441:
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38442:
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38443:
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38444:
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38445:
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38446:
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38447:
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38448:
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38449:
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38450:
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38451:
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38452:
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38453:
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38454:
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38455:
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38456:
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38457:
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38458:
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38459:
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38460:
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38461:
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38462:
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38463:
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38464:
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38465:
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#53751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38466:
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38467:
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38468:
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38469:
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0

WARNING: line length of 113 exceeds 100 columns
#53755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38470:
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#53756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38471:
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#53757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38472:
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18

WARNING: line length of 114 exceeds 100 columns
#53758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38473:
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c

WARNING: line length of 121 exceeds 100 columns
#53759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38474:
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L

WARNING: line length of 121 exceeds 100 columns
#53760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38475:
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#53761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38476:
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#53762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38477:
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L

WARNING: line length of 121 exceeds 100 columns
#53763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38478:
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L

WARNING: line length of 113 exceeds 100 columns
#53764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38479:
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#53765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38480:
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#53766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38481:
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#53767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38482:
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38483:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#53769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38484:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#53770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38485:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc

WARNING: line length of 114 exceeds 100 columns
#53771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38486:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#53772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38487:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L

WARNING: line length of 121 exceeds 100 columns
#53773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38488:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#53774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38489:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#53775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38490:
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L

WARNING: line length of 113 exceeds 100 columns
#53776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38491:
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#53777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38492:
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14

WARNING: line length of 121 exceeds 100 columns
#53778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38493:
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#53779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38494:
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#53780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38495:
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#53781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38496:
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14

WARNING: line length of 121 exceeds 100 columns
#53782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38497:
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#53783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38498:
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#53784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38499:
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#53785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38500:
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14

WARNING: line length of 121 exceeds 100 columns
#53786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38501:
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#53787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38502:
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#53788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38503:
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#53789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38504:
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38505:
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#53791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38506:
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38507:
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#53793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38508:
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38509:
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#53795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38510:
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38511:
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#53797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38512:
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38513:
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#53799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38514:
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38515:
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38516:
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38517:
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#53803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38518:
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#53804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38519:
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38520:
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38521:
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38522:
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38523:
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#53809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38524:
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#53810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38525:
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38526:
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38527:
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38528:
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38529:
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#53815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38530:
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#53816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38531:
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38532:
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38533:
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38534:
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#53820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38535:
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38536:
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#53822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38537:
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38538:
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#53824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38539:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38540:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#53826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38541:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#53827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38542:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#53828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38543:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38544:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38545:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38546:
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38547:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38548:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#53834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38549:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#53835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38550:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#53836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38551:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38552:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38553:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38554:
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38555:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38556:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#53842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38557:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#53843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38558:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#53844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38559:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38560:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38561:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38562:
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38563:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38564:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#53850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38565:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#53851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38566:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#53852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38567:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38568:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38569:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38570:
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38571:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#53857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38572:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#53858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38573:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#53859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38574:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#53860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38575:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38576:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38577:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38578:
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38579:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38580:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38581:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38582:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38583:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38584:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38585:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38586:
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38587:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38588:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38589:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38590:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38591:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38592:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38593:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38594:
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38595:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38596:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38597:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38598:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38599:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38600:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38601:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38602:
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38603:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38604:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38605:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38606:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38607:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38608:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38609:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38610:
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38611:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38612:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38613:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38614:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38615:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38616:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38617:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38618:
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38619:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38620:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38621:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38622:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38623:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38624:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38625:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38626:
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38627:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38628:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38629:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38630:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38631:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38632:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38633:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38634:
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38635:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38636:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38637:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38638:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38639:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38640:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38641:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38642:
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38643:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38644:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38645:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38646:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38647:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38648:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38649:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38650:
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38651:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38652:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38653:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38654:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38655:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38656:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38657:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38658:
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38659:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38660:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38661:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38662:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38663:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38664:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38665:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38666:
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38667:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#53953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38668:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#53954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38669:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#53955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38670:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#53956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38671:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#53957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38672:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#53958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38673:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#53959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38674:
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#53960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38675:
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#53961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38676:
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14

WARNING: line length of 121 exceeds 100 columns
#53962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38677:
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#53963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38678:
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#53964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38679:
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#53965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38680:
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14

WARNING: line length of 121 exceeds 100 columns
#53966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38681:
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#53967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38682:
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#53968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38683:
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#53969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38684:
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14

WARNING: line length of 121 exceeds 100 columns
#53970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38685:
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#53971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38686:
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#53972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38687:
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#53973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38688:
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38689:
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#53975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38690:
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38691:
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#53977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38692:
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38693:
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#53979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38694:
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38695:
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#53981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38696:
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38697:
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#53983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38698:
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38699:
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38700:
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38701:
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#53987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38702:
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#53988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38703:
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38704:
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38705:
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38706:
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38707:
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#53993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38708:
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#53994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38709:
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#53995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38710:
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#53996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38711:
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#53997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38712:
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#53998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38713:
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#53999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38714:
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#54000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38715:
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#54001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38716:
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38717:
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#54003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38718:
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#54004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38719:
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#54005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38720:
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#54006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38721:
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#54007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38722:
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#54008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38723:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#54009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38724:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#54010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38725:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#54011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38726:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#54012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38727:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38728:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38729:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38730:
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38731:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#54017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38732:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#54018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38733:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#54019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38734:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#54020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38735:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38736:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38737:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38738:
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38739:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#54025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38740:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#54026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38741:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#54027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38742:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#54028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38743:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38744:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38745:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38746:
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38747:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#54033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38748:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#54034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38749:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#54035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38750:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#54036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38751:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38752:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38753:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38754:
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38755:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#54041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38756:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#54042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38757:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#54043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38758:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#54044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38759:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38760:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38761:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38762:
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38763:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38764:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38765:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38766:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38767:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38768:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38769:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38770:
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38771:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38772:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38773:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38774:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38775:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38776:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38777:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38778:
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38779:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38780:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38781:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38782:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38783:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38784:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38785:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38786:
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38787:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38788:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38789:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38790:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38791:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38792:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38793:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38794:
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38795:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38796:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38797:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38798:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38799:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38800:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38801:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38802:
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38803:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38804:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38805:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38806:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38807:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38808:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38809:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38810:
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38811:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38812:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38813:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38814:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38815:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38816:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38817:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38818:
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38819:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38820:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38821:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38822:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38823:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38824:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38825:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38826:
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38827:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38828:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38829:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38830:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38831:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38832:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38833:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38834:
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38835:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38836:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38837:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38838:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38839:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38840:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38841:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38842:
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38843:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38844:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38845:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38846:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38847:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38848:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38849:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38850:
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38851:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38852:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc

WARNING: line length of 114 exceeds 100 columns
#54138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38853:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38854:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c

WARNING: line length of 121 exceeds 100 columns
#54140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38855:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#54141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38856:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#54142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38857:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#54143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38858:
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L

WARNING: line length of 113 exceeds 100 columns
#54144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38859:
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#54145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38860:
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK                                                                     0x00000001L

WARNING: line length of 113 exceeds 100 columns
#54146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38861:
+#define DCHVM_CTRL1__DUMMY1__SHIFT                                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#54147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38862:
+#define DCHVM_CTRL1__DUMMY1_MASK                                                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38863:
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#54149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38864:
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#54150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38865:
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT                                                          0x4

WARNING: line length of 113 exceeds 100 columns
#54151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38866:
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#54152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38867:
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#54153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38868:
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT                                                         0xa

WARNING: line length of 113 exceeds 100 columns
#54154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38869:
+#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS__SHIFT                                                               0xc

WARNING: line length of 121 exceeds 100 columns
#54155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38870:
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38871:
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38872:
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK                                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38873:
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK                                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#54159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38874:
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#54160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38875:
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK                                                           0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#54161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38876:
+#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS_MASK                                                                 0x00001000L

WARNING: line length of 113 exceeds 100 columns
#54162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38877:
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#54163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38878:
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT                                                         0x2

WARNING: line length of 113 exceeds 100 columns
#54164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38879:
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#54165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38880:
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38881:
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK                                                           0x0000000CL

WARNING: line length of 121 exceeds 100 columns
#54167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38882:
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK                                                        0x00000030L

WARNING: line length of 113 exceeds 100 columns
#54168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38883:
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#54169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38884:
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT                                                         0x1

WARNING: line length of 121 exceeds 100 columns
#54170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38885:
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38886:
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK                                                           0x00000002L

WARNING: line length of 113 exceeds 100 columns
#54172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38887:
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#54173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38888:
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT                                                       0x1

WARNING: line length of 121 exceeds 100 columns
#54174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38889:
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38890:
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK                                                         0x00000002L

WARNING: line length of 113 exceeds 100 columns
#54176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38891:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#54177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38892:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4

WARNING: line length of 113 exceeds 100 columns
#54178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38893:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8

WARNING: line length of 113 exceeds 100 columns
#54179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38894:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc

WARNING: line length of 114 exceeds 100 columns
#54180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38895:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10

WARNING: line length of 121 exceeds 100 columns
#54181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38896:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38897:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38898:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38899:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#54185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38900:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L

WARNING: line length of 115 exceeds 100 columns
#54186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38901:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#54187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38902:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L

WARNING: line length of 113 exceeds 100 columns
#54188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38903:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#54189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38904:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L

WARNING: line length of 113 exceeds 100 columns
#54190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38905:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#54191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38906:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#54192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38907:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8

WARNING: line length of 114 exceeds 100 columns
#54193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38908:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10

WARNING: line length of 114 exceeds 100 columns
#54194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38909:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14

WARNING: line length of 116 exceeds 100 columns
#54195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38910:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#54196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38911:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c

WARNING: line length of 121 exceeds 100 columns
#54197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38912:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38913:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38914:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#54200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38915:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#54201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38916:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#54202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38917:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#54203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38918:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L

WARNING: line length of 115 exceeds 100 columns
#54204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38919:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#54205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38920:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#54206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38921:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#54207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38922:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4

WARNING: line length of 113 exceeds 100 columns
#54208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38923:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#54209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38924:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#54210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38925:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f

WARNING: line length of 121 exceeds 100 columns
#54211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38926:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38927:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38928:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38929:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L

WARNING: line length of 121 exceeds 100 columns
#54215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38930:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#54216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38931:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#54217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38932:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#54218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38933:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#54219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38934:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38935:
+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#54221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38936:
+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#54222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38937:
+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38938:
+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#54224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38939:
+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#54225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38940:
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#54226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38941:
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#54227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38942:
+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38943:
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#54229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38944:
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#54230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38945:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#54231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38946:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#54232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38947:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#54233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38948:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18

WARNING: line length of 121 exceeds 100 columns
#54234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38949:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38950:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38951:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#54237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38952:
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#54238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38953:
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#54239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38954:
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2

WARNING: line length of 121 exceeds 100 columns
#54240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38955:
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38956:
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L

WARNING: line length of 113 exceeds 100 columns
#54242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38957:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#54243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38958:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#54244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38959:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd

WARNING: line length of 114 exceeds 100 columns
#54245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38960:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#54246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38961:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38962:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38963:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#54249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38964:
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38965:
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#54251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38966:
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#54252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38967:
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#54253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38968:
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#54254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38969:
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#54255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38970:
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38971:
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38972:
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38973:
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#54259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38974:
+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8

WARNING: line length of 114 exceeds 100 columns
#54260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38975:
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#54261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38976:
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19

WARNING: line length of 121 exceeds 100 columns
#54262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38977:
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38978:
+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38979:
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#54265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38980:
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L

WARNING: line length of 113 exceeds 100 columns
#54266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38981:
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#54267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38982:
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#54268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38983:
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#54269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38984:
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#54270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38985:
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#54271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38986:
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc

WARNING: line length of 121 exceeds 100 columns
#54272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38987:
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38988:
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#54274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38989:
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#54275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38990:
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L

WARNING: line length of 113 exceeds 100 columns
#54276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38991:
+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#54277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38992:
+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38993:
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#54279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38994:
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#54280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38995:
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#54281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38996:
+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#54282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38997:
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#54283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38998:
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#54284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:38999:
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#54285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39000:
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#54286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39001:
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#54287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39002:
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#54288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39003:
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39004:
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39005:
+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#54291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39006:
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#54292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39007:
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#54293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39008:
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#54294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39009:
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#54295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39010:
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#54296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39011:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#54297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39012:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#54298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39013:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#54299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39014:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#54300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39015:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#54301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39016:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39017:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#54303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39018:
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#54304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39019:
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#54305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39020:
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#54306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39021:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#54307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39022:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#54308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39023:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#54309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39024:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#54310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39025:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#54311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39026:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#54312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39027:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#54313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39028:
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#54314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39029:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#54315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39030:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#54316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39031:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#54317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39032:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#54318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39033:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#54319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39034:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#54320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39035:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#54321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39036:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#54322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39037:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#54323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39038:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#54324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39039:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#54325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39040:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#54326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39041:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#54327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39042:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#54328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39043:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#54329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39044:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#54330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39045:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#54331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39046:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#54332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39047:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#54333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39048:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#54334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39049:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#54335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39050:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#54336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39051:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#54337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39052:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#54338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39053:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#54339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39054:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#54340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39055:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#54341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39056:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#54342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39057:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#54343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39058:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#54344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39059:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39060:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39061:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39062:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39063:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39064:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#54350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39065:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#54351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39066:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39067:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39068:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39069:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39070:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#54356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39071:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#54357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39072:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#54358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39073:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#54359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39074:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#54360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39075:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#54361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39076:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#54362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39077:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#54363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39078:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#54364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39079:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#54365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39080:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#54366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39081:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#54367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39082:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#54368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39083:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#54369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39084:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#54370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39085:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#54371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39086:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#54372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39087:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#54373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39088:
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#54374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39089:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#54375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39090:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#54376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39091:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#54377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39092:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#54378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39093:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#54379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39094:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#54380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39095:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#54381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39096:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#54382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39097:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#54383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39098:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#54384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39099:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#54385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39100:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#54386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39101:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#54387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39102:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#54388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39103:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#54389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39104:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#54390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39105:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#54391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39106:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#54392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39107:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#54393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39108:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#54394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39109:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#54395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39110:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#54396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39111:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#54397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39112:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#54398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39113:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#54399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39114:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#54400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39115:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#54401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39116:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#54402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39117:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#54403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39118:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#54404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39119:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39120:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39121:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39122:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39123:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39124:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#54410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39125:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#54411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39126:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39127:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39128:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39129:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39130:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#54416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39131:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#54417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39132:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#54418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39133:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#54419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39134:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#54420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39135:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#54421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39136:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#54422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39137:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#54423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39138:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#54424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39139:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#54425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39140:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#54426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39141:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#54427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39142:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#54428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39143:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#54429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39144:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#54430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39145:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#54431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39146:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#54432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39147:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#54433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39148:
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#54434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39149:
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#54435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39150:
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#54436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39151:
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#54437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39152:
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39153:
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39154:
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#54440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39155:
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#54441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39156:
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#54442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39157:
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#54443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39158:
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39159:
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39160:
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#54446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39161:
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#54447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39162:
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#54448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39163:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#54449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39164:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#54450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39165:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#54451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39166:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#54452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39167:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#54453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39168:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#54454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39169:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#54455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39170:
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#54456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39171:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#54457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39172:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#54458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39173:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#54459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39174:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#54460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39175:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#54461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39176:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#54462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39177:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#54463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39178:
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#54464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39179:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#54465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39180:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#54466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39181:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#54467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39182:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#54468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39183:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#54469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39184:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#54470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39185:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#54471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39186:
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#54472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39187:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#54473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39188:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#54474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39189:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#54475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39190:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39191:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39192:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#54478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39193:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#54479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39194:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#54480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39195:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8

WARNING: line length of 113 exceeds 100 columns
#54481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39196:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc

WARNING: line length of 121 exceeds 100 columns
#54482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39197:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39198:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39199:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39200:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#54486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39201:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#54487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39202:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4

WARNING: line length of 121 exceeds 100 columns
#54488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39203:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39204:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L

WARNING: line length of 120 exceeds 100 columns
#54490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39205:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#54491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39206:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4

WARNING: line length of 126 exceeds 100 columns
#54492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39207:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L

WARNING: line length of 127 exceeds 100 columns
#54493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39208:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#54494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39209:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#54495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39210:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#54496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39211:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#54497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39212:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39213:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#54499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39214:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#54500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39215:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39216:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39217:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39218:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39219:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39220:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39221:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39222:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39223:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39224:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39225:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39226:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39227:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39228:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39229:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39230:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39231:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#54517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39232:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39233:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#54519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39234:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#54520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39235:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39236:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39237:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39238:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39239:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39240:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39241:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39242:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39243:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39244:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39245:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39246:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39247:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39248:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39249:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39250:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39251:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39252:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39253:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39254:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39255:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39256:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39257:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39258:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39259:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39260:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39261:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39262:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39263:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39264:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39265:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39266:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39267:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39268:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39269:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39270:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39271:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39272:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39273:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39274:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39275:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39276:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39277:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39278:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39279:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39280:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39281:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39282:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39283:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39284:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39285:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39286:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39287:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39288:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39289:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39290:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39291:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39292:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39293:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39294:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39295:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39296:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39297:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39298:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39299:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39300:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39301:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39302:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39303:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39304:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39305:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39306:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39307:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39308:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39309:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39310:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39311:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39312:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39313:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39314:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39315:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39316:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39317:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39318:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39319:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39320:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39321:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39322:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39323:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39324:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39325:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39326:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39327:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39328:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39329:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39330:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39331:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39332:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39333:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39334:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39335:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39336:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39337:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39338:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39339:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39340:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39341:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39342:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39343:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39344:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39345:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39346:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39347:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39348:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39349:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39350:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39351:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39352:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39353:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39354:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39355:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39356:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39357:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39358:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39359:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39360:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39361:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39362:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39363:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39364:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39365:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39366:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39367:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39368:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39369:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39370:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39371:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39372:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39373:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39374:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39375:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39376:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39377:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39378:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39379:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39380:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39381:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39382:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39383:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39384:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39385:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39386:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39387:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39388:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39389:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39390:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39391:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39392:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39393:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39394:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39395:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39396:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39397:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39398:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39399:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39400:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39401:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39402:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39403:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39404:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39405:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39406:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39407:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39408:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39409:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39410:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39411:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39412:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39413:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39414:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39415:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39416:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39417:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39418:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39419:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39420:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39421:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39422:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39423:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39424:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39425:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39426:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39427:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39428:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39429:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39430:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39431:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39432:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39433:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#54719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39434:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#54720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39435:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#54721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39436:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#54722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39437:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#54723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39438:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#54724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39439:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#54725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39440:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39441:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#54727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39442:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#54728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39443:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#54729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39444:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39445:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39446:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39447:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39448:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39449:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39450:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39451:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39452:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39453:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39454:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39455:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#54741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39456:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#54742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39457:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#54743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39458:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#54744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39459:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#54745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39460:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#54746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39461:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#54747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39462:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#54748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39463:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#54749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39464:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#54750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39465:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#54751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39466:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39467:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39468:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39469:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39470:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39471:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39472:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39473:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39474:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39475:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39476:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39477:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#54763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39478:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#54764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39479:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#54765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39480:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#54766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39481:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#54767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39482:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#54768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39483:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#54769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39484:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#54770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39485:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#54771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39486:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#54772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39487:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#54773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39488:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39489:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39490:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39491:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39492:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39493:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39494:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39495:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39496:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39497:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39498:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39499:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#54785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39500:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#54786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39501:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#54787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39502:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#54788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39503:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#54789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39504:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#54790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39505:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#54791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39506:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#54792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39507:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#54793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39508:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#54794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39509:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#54795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39510:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39511:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39512:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39513:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39514:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39515:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39516:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39517:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39518:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39519:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39520:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39521:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#54807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39522:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#54808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39523:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#54809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39524:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#54810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39525:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#54811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39526:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#54812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39527:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#54813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39528:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#54814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39529:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#54815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39530:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#54816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39531:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#54817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39532:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39533:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39534:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39535:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39536:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39537:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39538:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39539:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39540:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39541:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39542:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39543:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#54829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39544:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#54830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39545:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#54831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39546:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#54832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39547:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#54833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39548:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#54834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39549:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#54835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39550:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#54836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39551:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#54837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39552:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#54838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39553:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#54839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39554:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39555:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39556:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39557:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39558:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39559:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#54845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39560:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#54846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39561:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39562:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#54848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39563:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#54849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39564:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39565:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#54851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39566:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#54852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39567:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#54853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39568:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39569:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39570:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L

WARNING: line length of 113 exceeds 100 columns
#54856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39571:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#54857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39572:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#54858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39573:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#54859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39574:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#54860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39575:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#54861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39576:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5

WARNING: line length of 113 exceeds 100 columns
#54862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39577:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8

WARNING: line length of 114 exceeds 100 columns
#54863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39578:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#54864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39579:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d

WARNING: line length of 121 exceeds 100 columns
#54865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39580:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39581:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39582:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39583:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#54869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39584:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39585:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#54871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39586:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#54872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39587:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#54873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39588:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L

WARNING: line length of 113 exceeds 100 columns
#54874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39589:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0

WARNING: line length of 118 exceeds 100 columns
#54875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39590:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4

WARNING: line length of 118 exceeds 100 columns
#54876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39591:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc

WARNING: line length of 114 exceeds 100 columns
#54877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39592:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#54878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39593:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L

WARNING: line length of 124 exceeds 100 columns
#54879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39594:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L

WARNING: line length of 124 exceeds 100 columns
#54880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39595:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L

WARNING: line length of 121 exceeds 100 columns
#54881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39596:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L

WARNING: line length of 113 exceeds 100 columns
#54882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39597:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#54883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39598:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4

WARNING: line length of 113 exceeds 100 columns
#54884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39599:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#54885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39600:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc

WARNING: line length of 117 exceeds 100 columns
#54886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39601:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#54887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39602:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39603:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#54889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39604:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39605:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L

WARNING: line length of 122 exceeds 100 columns
#54891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39606:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39607:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0

WARNING: line length of 114 exceeds 100 columns
#54893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39608:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10

WARNING: line length of 121 exceeds 100 columns
#54894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39609:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39610:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39611:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0

WARNING: line length of 114 exceeds 100 columns
#54897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39612:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#54898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39613:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39614:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39615:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#54901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39616:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#54902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39617:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8

WARNING: line length of 121 exceeds 100 columns
#54903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39618:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39619:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#54905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39620:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L

WARNING: line length of 115 exceeds 100 columns
#54906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39621:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0

WARNING: line length of 129 exceeds 100 columns
#54907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39622:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4

WARNING: line length of 121 exceeds 100 columns
#54908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39623:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L

WARNING: line length of 135 exceeds 100 columns
#54909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39624:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#54910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39625:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#54911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39626:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4

WARNING: line length of 121 exceeds 100 columns
#54912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39627:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39628:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L

WARNING: line length of 113 exceeds 100 columns
#54914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39629:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#54915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39630:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#54916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39631:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#54917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39632:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39633:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#54919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39634:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#54920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39635:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#54921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39636:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#54922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39637:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#54923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39638:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#54924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39639:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#54925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39640:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#54926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39641:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#54927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39642:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#54928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39643:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#54929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39644:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L

WARNING: line length of 121 exceeds 100 columns
#54930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39645:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#54931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39646:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L

WARNING: line length of 113 exceeds 100 columns
#54932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39647:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#54933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39648:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39649:
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#54935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39650:
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4

WARNING: line length of 121 exceeds 100 columns
#54936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39651:
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39652:
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L

WARNING: line length of 113 exceeds 100 columns
#54938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39653:
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#54939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39654:
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#54940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39655:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#54941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39656:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#54942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39657:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#54943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39658:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#54944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39659:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#54945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39660:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39661:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39662:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#54948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39663:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#54949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39664:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L

WARNING: line length of 113 exceeds 100 columns
#54950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39665:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#54951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39666:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#54952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39667:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#54953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39668:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#54954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39669:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#54955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39670:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#54956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39671:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#54957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39672:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#54958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39673:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#54959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39674:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L

WARNING: line length of 113 exceeds 100 columns
#54960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39675:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#54961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39676:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L

WARNING: line length of 113 exceeds 100 columns
#54962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39677:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#54963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39678:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#54964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39679:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#54965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39680:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#54966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39681:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#54967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39682:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#54968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39683:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#54969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39684:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#54970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39685:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#54971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39686:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#54972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39687:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#54973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39688:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#54974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39689:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#54975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39690:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#54976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39691:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#54977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39692:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#54978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39693:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#54979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39694:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#54980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39695:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#54981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39696:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#54982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39697:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#54983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39698:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#54984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39699:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#54985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39700:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#54986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39701:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#54987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39702:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#54988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39703:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#54989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39704:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#54990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39705:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#54991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39706:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#54992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39707:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#54993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39708:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#54994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39709:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#54995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39710:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#54996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39711:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#54997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39712:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#54998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39713:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#54999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39714:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39715:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39716:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39717:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#55003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39718:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39719:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39720:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39721:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#55007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39722:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39723:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39724:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39725:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#55011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39726:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#55012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39727:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#55013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39728:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc

WARNING: line length of 114 exceeds 100 columns
#55014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39729:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#55015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39730:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14

WARNING: line length of 114 exceeds 100 columns
#55016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39731:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18

WARNING: line length of 114 exceeds 100 columns
#55017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39732:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#55018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39733:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39734:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L

WARNING: line length of 121 exceeds 100 columns
#55020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39735:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L

WARNING: line length of 121 exceeds 100 columns
#55021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39736:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L

WARNING: line length of 121 exceeds 100 columns
#55022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39737:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L

WARNING: line length of 121 exceeds 100 columns
#55023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39738:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L

WARNING: line length of 121 exceeds 100 columns
#55024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39739:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#55025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39740:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L

WARNING: line length of 113 exceeds 100 columns
#55026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39741:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39742:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39743:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39744:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39745:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39746:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39747:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39748:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39749:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#55035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39750:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#55036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39751:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39752:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39753:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39754:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39755:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39756:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39757:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39758:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39759:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39760:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39761:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39762:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39763:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39764:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39765:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39766:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39767:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39768:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39769:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39770:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39771:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#55057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39772:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39773:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#55059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39774:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#55060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39775:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2

WARNING: line length of 113 exceeds 100 columns
#55061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39776:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#55062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39777:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#55063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39778:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5

WARNING: line length of 113 exceeds 100 columns
#55064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39779:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6

WARNING: line length of 113 exceeds 100 columns
#55065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39780:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7

WARNING: line length of 121 exceeds 100 columns
#55066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39781:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39782:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39783:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39784:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39785:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39786:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#55072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39787:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#55073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39788:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L

WARNING: line length of 113 exceeds 100 columns
#55074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39789:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#55075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39790:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2

WARNING: line length of 113 exceeds 100 columns
#55076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39791:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#55077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39792:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#55078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39793:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#55079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39794:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#55080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39795:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10

WARNING: line length of 114 exceeds 100 columns
#55081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39796:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12

WARNING: line length of 114 exceeds 100 columns
#55082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39797:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#55083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39798:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18

WARNING: line length of 114 exceeds 100 columns
#55084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39799:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#55085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39800:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#55086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39801:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#55087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39802:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39803:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#55089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39804:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L

WARNING: line length of 121 exceeds 100 columns
#55090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39805:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39806:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#55092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39807:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L

WARNING: line length of 121 exceeds 100 columns
#55093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39808:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L

WARNING: line length of 121 exceeds 100 columns
#55094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39809:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#55095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39810:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L

WARNING: line length of 121 exceeds 100 columns
#55096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39811:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#55097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39812:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#55098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39813:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#55099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39814:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#55100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39815:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#55101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39816:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#55102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39817:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#55103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39818:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#55104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39819:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11

WARNING: line length of 114 exceeds 100 columns
#55105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39820:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#55106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39821:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15

WARNING: line length of 121 exceeds 100 columns
#55107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39822:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39823:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39824:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L

WARNING: line length of 121 exceeds 100 columns
#55110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39825:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#55111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39826:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#55112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39827:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#55113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39828:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L

WARNING: line length of 121 exceeds 100 columns
#55114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39829:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#55115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39830:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L

WARNING: line length of 113 exceeds 100 columns
#55116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39831:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#55117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39832:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39833:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#55119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39834:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#55120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39835:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39836:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L

WARNING: line length of 113 exceeds 100 columns
#55122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39837:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39838:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39839:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#55125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39840:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4

WARNING: line length of 113 exceeds 100 columns
#55126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39841:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8

WARNING: line length of 113 exceeds 100 columns
#55127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39842:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc

WARNING: line length of 114 exceeds 100 columns
#55128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39843:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10

WARNING: line length of 121 exceeds 100 columns
#55129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39844:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39845:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39846:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39847:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#55133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39848:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L

WARNING: line length of 115 exceeds 100 columns
#55134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39849:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#55135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39850:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L

WARNING: line length of 113 exceeds 100 columns
#55136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39851:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#55137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39852:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L

WARNING: line length of 113 exceeds 100 columns
#55138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39853:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#55139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39854:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#55140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39855:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8

WARNING: line length of 114 exceeds 100 columns
#55141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39856:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10

WARNING: line length of 114 exceeds 100 columns
#55142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39857:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14

WARNING: line length of 116 exceeds 100 columns
#55143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39858:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#55144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39859:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c

WARNING: line length of 121 exceeds 100 columns
#55145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39860:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39861:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39862:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#55148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39863:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#55149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39864:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#55150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39865:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#55151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39866:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L

WARNING: line length of 115 exceeds 100 columns
#55152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39867:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#55153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39868:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#55154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39869:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#55155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39870:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4

WARNING: line length of 113 exceeds 100 columns
#55156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39871:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#55157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39872:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#55158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39873:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f

WARNING: line length of 121 exceeds 100 columns
#55159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39874:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39875:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39876:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39877:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L

WARNING: line length of 121 exceeds 100 columns
#55163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39878:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#55164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39879:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#55165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39880:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#55166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39881:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#55167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39882:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39883:
+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#55169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39884:
+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#55170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39885:
+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39886:
+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#55172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39887:
+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#55173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39888:
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#55174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39889:
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#55175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39890:
+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39891:
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#55177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39892:
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#55178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39893:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#55179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39894:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#55180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39895:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#55181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39896:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18

WARNING: line length of 121 exceeds 100 columns
#55182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39897:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39898:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39899:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#55185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39900:
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#55186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39901:
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#55187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39902:
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2

WARNING: line length of 121 exceeds 100 columns
#55188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39903:
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39904:
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L

WARNING: line length of 113 exceeds 100 columns
#55190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39905:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#55191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39906:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#55192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39907:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd

WARNING: line length of 114 exceeds 100 columns
#55193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39908:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#55194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39909:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39910:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39911:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#55197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39912:
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39913:
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#55199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39914:
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#55200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39915:
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#55201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39916:
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#55202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39917:
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#55203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39918:
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39919:
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39920:
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39921:
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#55207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39922:
+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8

WARNING: line length of 114 exceeds 100 columns
#55208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39923:
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#55209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39924:
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19

WARNING: line length of 121 exceeds 100 columns
#55210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39925:
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39926:
+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39927:
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#55213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39928:
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L

WARNING: line length of 113 exceeds 100 columns
#55214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39929:
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#55215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39930:
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#55216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39931:
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#55217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39932:
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#55218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39933:
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#55219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39934:
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc

WARNING: line length of 121 exceeds 100 columns
#55220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39935:
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39936:
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#55222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39937:
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#55223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39938:
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L

WARNING: line length of 113 exceeds 100 columns
#55224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39939:
+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#55225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39940:
+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39941:
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#55227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39942:
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#55228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39943:
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#55229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39944:
+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#55230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39945:
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#55231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39946:
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#55232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39947:
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#55233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39948:
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#55234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39949:
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#55235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39950:
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39951:
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39952:
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39953:
+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#55239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39954:
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#55240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39955:
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#55241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39956:
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#55242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39957:
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#55243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39958:
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#55244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39959:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#55245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39960:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#55246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39961:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#55247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39962:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#55248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39963:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#55249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39964:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39965:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#55251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39966:
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#55252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39967:
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#55253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39968:
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#55254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39969:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#55255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39970:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#55256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39971:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#55257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39972:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#55258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39973:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#55259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39974:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#55260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39975:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#55261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39976:
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#55262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39977:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#55263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39978:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#55264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39979:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#55265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39980:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#55266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39981:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#55267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39982:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#55268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39983:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#55269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39984:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#55270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39985:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#55271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39986:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#55272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39987:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#55273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39988:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#55274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39989:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#55275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39990:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#55276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39991:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#55277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39992:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#55278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39993:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#55279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39994:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#55280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39995:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#55281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39996:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#55282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39997:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#55283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39998:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#55284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:39999:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#55285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40000:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#55286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40001:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#55287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40002:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#55288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40003:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#55289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40004:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#55290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40005:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#55291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40006:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#55292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40007:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40008:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40009:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40010:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40011:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40012:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#55298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40013:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#55299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40014:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40015:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40016:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40017:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40018:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#55304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40019:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#55305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40020:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#55306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40021:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#55307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40022:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#55308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40023:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#55309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40024:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#55310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40025:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#55311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40026:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#55312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40027:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#55313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40028:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#55314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40029:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#55315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40030:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#55316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40031:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#55317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40032:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#55318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40033:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#55319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40034:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#55320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40035:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#55321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40036:
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#55322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40037:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#55323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40038:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#55324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40039:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#55325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40040:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#55326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40041:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#55327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40042:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#55328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40043:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#55329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40044:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#55330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40045:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#55331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40046:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#55332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40047:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#55333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40048:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#55334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40049:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#55335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40050:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#55336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40051:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#55337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40052:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#55338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40053:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#55339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40054:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#55340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40055:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#55341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40056:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#55342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40057:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#55343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40058:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#55344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40059:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#55345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40060:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#55346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40061:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#55347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40062:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#55348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40063:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#55349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40064:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#55350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40065:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#55351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40066:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#55352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40067:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40068:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40069:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40070:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40071:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40072:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#55358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40073:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#55359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40074:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40075:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40076:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40077:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40078:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#55364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40079:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#55365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40080:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#55366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40081:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#55367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40082:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#55368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40083:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#55369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40084:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#55370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40085:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#55371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40086:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#55372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40087:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#55373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40088:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#55374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40089:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#55375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40090:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#55376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40091:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#55377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40092:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#55378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40093:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#55379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40094:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#55380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40095:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#55381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40096:
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#55382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40097:
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#55383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40098:
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#55384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40099:
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#55385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40100:
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40101:
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40102:
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#55388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40103:
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#55389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40104:
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#55390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40105:
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#55391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40106:
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40107:
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40108:
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#55394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40109:
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#55395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40110:
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#55396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40111:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#55397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40112:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#55398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40113:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#55399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40114:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#55400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40115:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#55401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40116:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#55402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40117:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#55403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40118:
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#55404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40119:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#55405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40120:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#55406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40121:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#55407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40122:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#55408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40123:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#55409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40124:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#55410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40125:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#55411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40126:
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#55412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40127:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#55413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40128:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#55414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40129:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#55415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40130:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#55416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40131:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#55417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40132:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#55418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40133:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#55419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40134:
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#55420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40135:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#55421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40136:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#55422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40137:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40138:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40139:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40140:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#55426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40141:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#55427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40142:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#55428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40143:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8

WARNING: line length of 113 exceeds 100 columns
#55429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40144:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc

WARNING: line length of 121 exceeds 100 columns
#55430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40145:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40146:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40147:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40148:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#55434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40149:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#55435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40150:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4

WARNING: line length of 121 exceeds 100 columns
#55436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40151:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40152:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L

WARNING: line length of 120 exceeds 100 columns
#55438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40153:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#55439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40154:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4

WARNING: line length of 126 exceeds 100 columns
#55440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40155:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L

WARNING: line length of 127 exceeds 100 columns
#55441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40156:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#55442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40157:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#55443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40158:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#55444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40159:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#55445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40160:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40161:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#55447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40162:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#55448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40163:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40164:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40165:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40166:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40167:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40168:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40169:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40170:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40171:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40172:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40173:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40174:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40175:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40176:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40177:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40178:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40179:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#55465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40180:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40181:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#55467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40182:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#55468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40183:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40184:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40185:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40186:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40187:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40188:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40189:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40190:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40191:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40192:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40193:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40194:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40195:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40196:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40197:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40198:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40199:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40200:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40201:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40202:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40203:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40204:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40205:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40206:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40207:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40208:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40209:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40210:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40211:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40212:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40213:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40214:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40215:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40216:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40217:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40218:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40219:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40220:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40221:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40222:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40223:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40224:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40225:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40226:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40227:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40228:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40229:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40230:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40231:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40232:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40233:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40234:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40235:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40236:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40237:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40238:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40239:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40240:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40241:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40242:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40243:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40244:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40245:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40246:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40247:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40248:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40249:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40250:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40251:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40252:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40253:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40254:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40255:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40256:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40257:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40258:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40259:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40260:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40261:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40262:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40263:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40264:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40265:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40266:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40267:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40268:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40269:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40270:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40271:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40272:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40273:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40274:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40275:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40276:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40277:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40278:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40279:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40280:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40281:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40282:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40283:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40284:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40285:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40286:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40287:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40288:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40289:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40290:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40291:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40292:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40293:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40294:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40295:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40296:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40297:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40298:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40299:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40300:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40301:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40302:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40303:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40304:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40305:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40306:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40307:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40308:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40309:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40310:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40311:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40312:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40313:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40314:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40315:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40316:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40317:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40318:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40319:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40320:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40321:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40322:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40323:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40324:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40325:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40326:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40327:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40328:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40329:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40330:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40331:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40332:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40333:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40334:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40335:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40336:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40337:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40338:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40339:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40340:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40341:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40342:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40343:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40344:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40345:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40346:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40347:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40348:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40349:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40350:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40351:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40352:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40353:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40354:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40355:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40356:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40357:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40358:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40359:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40360:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40361:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40362:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40363:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40364:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40365:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40366:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40367:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40368:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40369:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40370:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40371:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40372:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40373:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40374:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40375:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40376:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40377:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40378:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40379:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40380:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40381:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#55667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40382:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#55668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40383:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#55669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40384:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#55670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40385:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#55671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40386:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#55672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40387:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#55673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40388:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40389:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#55675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40390:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#55676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40391:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#55677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40392:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40393:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40394:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40395:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40396:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40397:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40398:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40399:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40400:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40401:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40402:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40403:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#55689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40404:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#55690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40405:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#55691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40406:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#55692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40407:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#55693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40408:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#55694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40409:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#55695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40410:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#55696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40411:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#55697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40412:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#55698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40413:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#55699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40414:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40415:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40416:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40417:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40418:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40419:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40420:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40421:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40422:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40423:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40424:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40425:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#55711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40426:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#55712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40427:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#55713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40428:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#55714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40429:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#55715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40430:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#55716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40431:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#55717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40432:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#55718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40433:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#55719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40434:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#55720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40435:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#55721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40436:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40437:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40438:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40439:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40440:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40441:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40442:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40443:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40444:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40445:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40446:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40447:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#55733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40448:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#55734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40449:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#55735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40450:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#55736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40451:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#55737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40452:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#55738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40453:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#55739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40454:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#55740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40455:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#55741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40456:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#55742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40457:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#55743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40458:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40459:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40460:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40461:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40462:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40463:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40464:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40465:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40466:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40467:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40468:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40469:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#55755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40470:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#55756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40471:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#55757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40472:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#55758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40473:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#55759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40474:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#55760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40475:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#55761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40476:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#55762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40477:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#55763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40478:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#55764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40479:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#55765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40480:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40481:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40482:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40483:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40484:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40485:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40486:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40487:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40488:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40489:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40490:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40491:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#55777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40492:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#55778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40493:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#55779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40494:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#55780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40495:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#55781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40496:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#55782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40497:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#55783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40498:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#55784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40499:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#55785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40500:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#55786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40501:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#55787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40502:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40503:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40504:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40505:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40506:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40507:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#55793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40508:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#55794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40509:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40510:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#55796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40511:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#55797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40512:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40513:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#55799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40514:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#55800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40515:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#55801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40516:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40517:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40518:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L

WARNING: line length of 113 exceeds 100 columns
#55804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40519:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#55805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40520:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#55806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40521:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#55807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40522:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#55808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40523:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#55809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40524:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5

WARNING: line length of 113 exceeds 100 columns
#55810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40525:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8

WARNING: line length of 114 exceeds 100 columns
#55811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40526:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#55812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40527:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d

WARNING: line length of 121 exceeds 100 columns
#55813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40528:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40529:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40530:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40531:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#55817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40532:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40533:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#55819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40534:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#55820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40535:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#55821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40536:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L

WARNING: line length of 113 exceeds 100 columns
#55822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40537:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0

WARNING: line length of 118 exceeds 100 columns
#55823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40538:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4

WARNING: line length of 118 exceeds 100 columns
#55824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40539:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc

WARNING: line length of 114 exceeds 100 columns
#55825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40540:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#55826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40541:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L

WARNING: line length of 124 exceeds 100 columns
#55827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40542:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L

WARNING: line length of 124 exceeds 100 columns
#55828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40543:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L

WARNING: line length of 121 exceeds 100 columns
#55829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40544:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L

WARNING: line length of 113 exceeds 100 columns
#55830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40545:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#55831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40546:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4

WARNING: line length of 113 exceeds 100 columns
#55832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40547:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#55833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40548:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc

WARNING: line length of 117 exceeds 100 columns
#55834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40549:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#55835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40550:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40551:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#55837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40552:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40553:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L

WARNING: line length of 122 exceeds 100 columns
#55839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40554:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40555:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0

WARNING: line length of 114 exceeds 100 columns
#55841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40556:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10

WARNING: line length of 121 exceeds 100 columns
#55842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40557:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40558:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40559:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0

WARNING: line length of 114 exceeds 100 columns
#55845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40560:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#55846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40561:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40562:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40563:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#55849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40564:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#55850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40565:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8

WARNING: line length of 121 exceeds 100 columns
#55851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40566:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40567:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#55853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40568:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L

WARNING: line length of 115 exceeds 100 columns
#55854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40569:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0

WARNING: line length of 129 exceeds 100 columns
#55855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40570:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4

WARNING: line length of 121 exceeds 100 columns
#55856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40571:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L

WARNING: line length of 135 exceeds 100 columns
#55857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40572:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#55858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40573:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#55859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40574:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4

WARNING: line length of 121 exceeds 100 columns
#55860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40575:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40576:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L

WARNING: line length of 113 exceeds 100 columns
#55862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40577:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#55863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40578:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#55864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40579:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#55865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40580:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40581:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#55867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40582:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#55868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40583:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#55869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40584:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#55870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40585:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#55871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40586:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#55872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40587:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#55873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40588:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#55874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40589:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#55875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40590:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#55876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40591:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#55877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40592:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L

WARNING: line length of 121 exceeds 100 columns
#55878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40593:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#55879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40594:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L

WARNING: line length of 113 exceeds 100 columns
#55880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40595:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#55881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40596:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40597:
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#55883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40598:
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4

WARNING: line length of 121 exceeds 100 columns
#55884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40599:
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40600:
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L

WARNING: line length of 113 exceeds 100 columns
#55886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40601:
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#55887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40602:
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40603:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#55889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40604:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#55890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40605:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#55891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40606:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4

WARNING: line length of 113 exceeds 100 columns
#55892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40607:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8

WARNING: line length of 121 exceeds 100 columns
#55893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40608:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40609:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40610:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#55896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40611:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L

WARNING: line length of 121 exceeds 100 columns
#55897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40612:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L

WARNING: line length of 113 exceeds 100 columns
#55898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40613:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#55899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40614:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#55900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40615:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#55901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40616:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc

WARNING: line length of 114 exceeds 100 columns
#55902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40617:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#55903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40618:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#55904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40619:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#55905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40620:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#55906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40621:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#55907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40622:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L

WARNING: line length of 113 exceeds 100 columns
#55908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40623:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#55909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40624:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L

WARNING: line length of 113 exceeds 100 columns
#55910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40625:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#55911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40626:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#55912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40627:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#55913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40628:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#55914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40629:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#55915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40630:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#55916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40631:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#55917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40632:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#55918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40633:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#55919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40634:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#55920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40635:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#55921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40636:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#55922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40637:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#55923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40638:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19

WARNING: line length of 121 exceeds 100 columns
#55924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40639:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#55925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40640:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L

WARNING: line length of 113 exceeds 100 columns
#55926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40641:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#55927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40642:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#55928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40643:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40644:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40645:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#55931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40646:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#55932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40647:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40648:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40649:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#55935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40650:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#55936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40651:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40652:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40653:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#55939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40654:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8

WARNING: line length of 121 exceeds 100 columns
#55940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40655:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40656:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40657:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#55943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40658:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40659:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40660:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40661:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#55947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40662:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40663:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40664:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40665:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#55951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40666:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40667:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40668:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40669:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#55955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40670:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#55956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40671:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40672:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L

WARNING: line length of 113 exceeds 100 columns
#55958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40673:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#55959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40674:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#55960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40675:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#55961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40676:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc

WARNING: line length of 114 exceeds 100 columns
#55962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40677:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#55963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40678:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14

WARNING: line length of 114 exceeds 100 columns
#55964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40679:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18

WARNING: line length of 114 exceeds 100 columns
#55965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40680:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c

WARNING: line length of 121 exceeds 100 columns
#55966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40681:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L

WARNING: line length of 121 exceeds 100 columns
#55967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40682:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L

WARNING: line length of 121 exceeds 100 columns
#55968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40683:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L

WARNING: line length of 121 exceeds 100 columns
#55969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40684:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L

WARNING: line length of 121 exceeds 100 columns
#55970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40685:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L

WARNING: line length of 121 exceeds 100 columns
#55971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40686:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L

WARNING: line length of 121 exceeds 100 columns
#55972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40687:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#55973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40688:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L

WARNING: line length of 113 exceeds 100 columns
#55974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40689:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40690:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40691:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40692:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40693:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40694:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40695:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#55981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40696:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40697:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#55983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40698:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#55984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40699:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40700:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40701:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40702:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40703:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40704:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40705:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40706:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40707:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40708:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40709:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40710:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40711:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40712:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#55998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40713:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#55999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40714:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40715:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#56001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40716:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40717:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#56003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40718:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40719:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#56005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40720:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40721:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#56007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40722:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#56008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40723:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2

WARNING: line length of 113 exceeds 100 columns
#56009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40724:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#56010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40725:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#56011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40726:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5

WARNING: line length of 113 exceeds 100 columns
#56012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40727:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6

WARNING: line length of 113 exceeds 100 columns
#56013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40728:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7

WARNING: line length of 121 exceeds 100 columns
#56014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40729:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40730:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40731:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40732:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40733:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40734:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#56020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40735:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#56021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40736:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L

WARNING: line length of 113 exceeds 100 columns
#56022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40737:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#56023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40738:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2

WARNING: line length of 113 exceeds 100 columns
#56024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40739:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#56025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40740:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#56026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40741:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa

WARNING: line length of 113 exceeds 100 columns
#56027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40742:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#56028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40743:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10

WARNING: line length of 114 exceeds 100 columns
#56029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40744:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12

WARNING: line length of 114 exceeds 100 columns
#56030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40745:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#56031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40746:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18

WARNING: line length of 114 exceeds 100 columns
#56032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40747:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a

WARNING: line length of 114 exceeds 100 columns
#56033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40748:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c

WARNING: line length of 121 exceeds 100 columns
#56034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40749:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#56035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40750:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40751:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#56037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40752:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L

WARNING: line length of 121 exceeds 100 columns
#56038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40753:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40754:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#56040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40755:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L

WARNING: line length of 121 exceeds 100 columns
#56041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40756:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L

WARNING: line length of 121 exceeds 100 columns
#56042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40757:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#56043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40758:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L

WARNING: line length of 121 exceeds 100 columns
#56044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40759:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L

WARNING: line length of 121 exceeds 100 columns
#56045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40760:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#56046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40761:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#56047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40762:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#56048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40763:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#56049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40764:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#56050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40765:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8

WARNING: line length of 114 exceeds 100 columns
#56051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40766:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#56052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40767:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11

WARNING: line length of 114 exceeds 100 columns
#56053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40768:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#56054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40769:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15

WARNING: line length of 121 exceeds 100 columns
#56055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40770:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40771:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40772:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L

WARNING: line length of 121 exceeds 100 columns
#56058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40773:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#56059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40774:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#56060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40775:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#56061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40776:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L

WARNING: line length of 121 exceeds 100 columns
#56062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40777:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#56063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40778:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L

WARNING: line length of 113 exceeds 100 columns
#56064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40779:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#56065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40780:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40781:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#56067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40782:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#56068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40783:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40784:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L

WARNING: line length of 113 exceeds 100 columns
#56070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40785:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#56071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40786:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40787:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#56073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40788:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4

WARNING: line length of 113 exceeds 100 columns
#56074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40789:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8

WARNING: line length of 113 exceeds 100 columns
#56075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40790:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc

WARNING: line length of 114 exceeds 100 columns
#56076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40791:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10

WARNING: line length of 121 exceeds 100 columns
#56077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40792:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40793:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40794:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40795:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#56081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40796:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L

WARNING: line length of 115 exceeds 100 columns
#56082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40797:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#56083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40798:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L

WARNING: line length of 113 exceeds 100 columns
#56084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40799:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#56085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40800:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L

WARNING: line length of 113 exceeds 100 columns
#56086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40801:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#56087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40802:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#56088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40803:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8

WARNING: line length of 114 exceeds 100 columns
#56089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40804:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10

WARNING: line length of 114 exceeds 100 columns
#56090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40805:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14

WARNING: line length of 116 exceeds 100 columns
#56091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40806:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#56092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40807:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c

WARNING: line length of 121 exceeds 100 columns
#56093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40808:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40809:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40810:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#56096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40811:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#56097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40812:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#56098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40813:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40814:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L

WARNING: line length of 115 exceeds 100 columns
#56100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40815:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#56101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40816:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#56102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40817:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#56103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40818:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4

WARNING: line length of 113 exceeds 100 columns
#56104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40819:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#56105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40820:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#56106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40821:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f

WARNING: line length of 121 exceeds 100 columns
#56107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40822:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40823:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40824:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40825:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L

WARNING: line length of 121 exceeds 100 columns
#56111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40826:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#56112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40827:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#56113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40828:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#56114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40829:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#56115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40830:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40831:
+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#56117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40832:
+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#56118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40833:
+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40834:
+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#56120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40835:
+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#56121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40836:
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#56122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40837:
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#56123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40838:
+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40839:
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40840:
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#56126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40841:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#56127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40842:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#56128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40843:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#56129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40844:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18

WARNING: line length of 121 exceeds 100 columns
#56130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40845:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40846:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40847:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40848:
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#56134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40849:
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#56135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40850:
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2

WARNING: line length of 121 exceeds 100 columns
#56136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40851:
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40852:
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L

WARNING: line length of 113 exceeds 100 columns
#56138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40853:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#56139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40854:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#56140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40855:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd

WARNING: line length of 114 exceeds 100 columns
#56141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40856:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#56142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40857:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40858:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40859:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#56145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40860:
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40861:
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#56147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40862:
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#56148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40863:
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#56149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40864:
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#56150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40865:
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#56151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40866:
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40867:
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40868:
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40869:
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#56155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40870:
+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8

WARNING: line length of 114 exceeds 100 columns
#56156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40871:
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#56157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40872:
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19

WARNING: line length of 121 exceeds 100 columns
#56158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40873:
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40874:
+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40875:
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40876:
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L

WARNING: line length of 113 exceeds 100 columns
#56162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40877:
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#56163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40878:
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#56164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40879:
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#56165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40880:
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#56166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40881:
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#56167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40882:
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc

WARNING: line length of 121 exceeds 100 columns
#56168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40883:
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40884:
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#56170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40885:
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#56171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40886:
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L

WARNING: line length of 113 exceeds 100 columns
#56172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40887:
+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#56173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40888:
+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40889:
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#56175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40890:
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#56176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40891:
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#56177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40892:
+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#56178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40893:
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#56179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40894:
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#56180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40895:
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#56181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40896:
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#56182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40897:
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#56183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40898:
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#56184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40899:
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40900:
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40901:
+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#56187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40902:
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#56188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40903:
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#56189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40904:
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#56190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40905:
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40906:
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#56192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40907:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#56193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40908:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#56194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40909:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#56195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40910:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#56196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40911:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#56197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40912:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40913:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#56199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40914:
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#56200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40915:
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#56201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40916:
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#56202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40917:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#56203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40918:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#56204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40919:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#56205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40920:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#56206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40921:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#56207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40922:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40923:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#56209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40924:
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#56210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40925:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#56211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40926:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#56212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40927:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#56213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40928:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#56214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40929:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#56215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40930:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#56216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40931:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#56217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40932:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#56218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40933:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#56219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40934:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#56220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40935:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#56221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40936:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#56222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40937:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#56223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40938:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#56224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40939:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#56225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40940:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#56226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40941:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#56227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40942:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#56228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40943:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#56229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40944:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#56230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40945:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#56231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40946:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#56232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40947:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#56233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40948:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#56234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40949:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#56235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40950:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#56236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40951:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#56237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40952:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#56238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40953:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#56239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40954:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#56240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40955:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40956:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40957:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40958:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40959:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40960:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#56246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40961:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#56247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40962:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40963:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40964:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40965:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40966:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#56252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40967:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#56253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40968:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#56254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40969:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#56255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40970:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#56256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40971:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#56257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40972:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#56258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40973:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#56259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40974:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#56260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40975:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#56261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40976:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#56262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40977:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#56263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40978:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40979:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#56265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40980:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#56266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40981:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#56267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40982:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#56268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40983:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#56269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40984:
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#56270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40985:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#56271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40986:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#56272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40987:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#56273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40988:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#56274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40989:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#56275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40990:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#56276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40991:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#56277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40992:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#56278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40993:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#56279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40994:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#56280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40995:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#56281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40996:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#56282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40997:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#56283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40998:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#56284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:40999:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#56285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41000:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#56286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41001:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#56287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41002:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#56288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41003:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#56289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41004:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#56290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41005:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#56291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41006:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#56292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41007:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#56293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41008:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#56294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41009:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#56295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41010:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#56296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41011:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#56297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41012:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#56298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41013:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#56299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41014:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#56300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41015:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41016:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41017:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41018:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41019:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41020:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#56306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41021:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#56307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41022:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41023:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41024:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41025:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41026:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#56312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41027:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#56313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41028:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#56314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41029:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#56315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41030:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#56316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41031:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#56317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41032:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#56318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41033:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#56319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41034:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#56320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41035:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#56321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41036:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#56322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41037:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#56323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41038:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41039:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#56325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41040:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#56326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41041:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#56327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41042:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#56328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41043:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#56329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41044:
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#56330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41045:
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#56331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41046:
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#56332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41047:
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#56333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41048:
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41049:
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41050:
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#56336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41051:
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#56337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41052:
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#56338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41053:
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#56339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41054:
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41055:
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41056:
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#56342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41057:
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#56343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41058:
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#56344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41059:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#56345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41060:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#56346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41061:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#56347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41062:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#56348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41063:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#56349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41064:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41065:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#56351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41066:
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#56352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41067:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#56353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41068:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#56354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41069:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#56355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41070:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#56356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41071:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#56357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41072:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41073:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#56359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41074:
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#56360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41075:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#56361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41076:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#56362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41077:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#56363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41078:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#56364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41079:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#56365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41080:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#56366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41081:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#56367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41082:
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#56368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41083:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#56369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41084:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#56370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41085:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#56371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41086:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41087:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41088:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#56374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41089:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#56375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41090:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#56376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41091:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8

WARNING: line length of 113 exceeds 100 columns
#56377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41092:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc

WARNING: line length of 121 exceeds 100 columns
#56378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41093:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41094:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41095:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41096:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#56382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41097:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#56383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41098:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4

WARNING: line length of 121 exceeds 100 columns
#56384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41099:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41100:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L

WARNING: line length of 120 exceeds 100 columns
#56386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41101:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#56387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41102:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4

WARNING: line length of 126 exceeds 100 columns
#56388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41103:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L

WARNING: line length of 127 exceeds 100 columns
#56389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41104:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#56390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41105:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#56391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41106:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#56392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41107:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#56393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41108:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41109:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#56395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41110:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#56396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41111:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41112:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41113:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41114:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41115:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41116:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41117:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41118:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41119:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41120:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41121:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41122:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41123:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41124:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41125:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41126:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41127:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#56413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41128:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41129:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#56415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41130:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#56416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41131:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41132:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41133:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41134:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41135:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41136:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41137:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41138:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41139:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41140:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41141:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41142:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41143:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41144:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41145:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41146:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41147:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41148:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41149:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41150:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41151:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41152:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41153:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41154:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41155:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41156:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41157:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41158:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41159:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41160:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41161:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41162:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41163:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41164:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41165:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41166:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41167:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41168:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41169:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41170:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41171:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41172:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41173:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41174:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41175:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41176:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41177:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41178:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41179:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41180:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41181:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41182:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41183:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41184:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41185:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41186:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41187:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41188:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41189:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41190:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41191:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41192:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41193:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41194:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41195:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41196:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41197:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41198:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41199:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41200:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41201:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41202:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41203:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41204:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41205:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41206:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41207:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41208:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41209:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41210:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41211:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41212:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41213:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41214:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41215:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41216:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41217:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41218:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41219:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41220:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41221:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41222:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41223:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41224:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41225:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41226:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41227:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41228:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41229:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41230:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41231:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41232:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41233:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41234:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41235:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41236:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41237:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41238:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41239:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41240:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41241:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41242:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41243:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41244:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41245:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41246:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41247:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41248:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41249:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41250:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41251:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41252:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41253:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41254:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41255:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41256:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41257:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41258:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41259:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41260:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41261:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41262:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41263:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41264:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41265:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41266:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41267:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41268:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41269:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41270:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41271:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41272:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41273:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41274:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41275:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41276:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41277:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41278:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41279:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41280:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41281:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41282:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41283:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41284:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41285:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41286:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41287:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41288:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41289:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41290:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41291:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41292:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41293:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41294:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41295:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41296:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41297:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41298:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41299:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41300:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41301:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41302:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41303:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41304:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41305:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41306:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41307:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41308:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41309:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41310:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41311:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41312:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41313:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41314:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41315:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41316:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41317:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41318:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41319:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41320:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41321:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41322:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41323:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41324:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41325:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41326:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41327:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41328:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41329:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#56615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41330:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#56616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41331:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#56617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41332:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#56618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41333:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#56619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41334:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#56620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41335:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#56621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41336:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41337:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#56623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41338:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#56624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41339:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#56625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41340:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41341:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41342:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41343:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41344:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41345:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41346:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41347:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41348:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41349:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41350:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41351:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#56637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41352:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#56638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41353:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#56639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41354:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#56640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41355:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#56641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41356:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#56642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41357:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#56643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41358:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#56644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41359:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#56645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41360:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#56646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41361:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#56647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41362:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41363:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41364:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41365:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41366:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41367:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41368:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41369:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41370:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41371:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41372:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41373:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#56659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41374:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#56660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41375:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#56661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41376:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#56662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41377:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#56663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41378:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#56664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41379:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#56665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41380:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#56666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41381:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#56667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41382:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#56668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41383:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#56669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41384:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41385:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41386:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41387:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41388:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41389:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41390:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41391:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41392:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41393:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41394:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41395:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#56681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41396:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#56682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41397:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#56683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41398:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#56684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41399:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#56685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41400:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#56686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41401:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#56687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41402:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#56688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41403:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#56689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41404:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#56690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41405:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#56691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41406:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41407:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41408:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41409:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41410:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41411:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41412:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41413:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41414:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41415:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41416:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41417:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#56703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41418:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#56704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41419:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#56705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41420:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#56706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41421:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#56707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41422:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#56708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41423:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#56709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41424:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#56710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41425:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#56711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41426:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#56712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41427:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#56713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41428:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41429:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41430:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41431:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41432:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41433:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41434:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41435:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41436:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41437:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41438:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41439:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#56725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41440:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#56726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41441:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#56727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41442:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#56728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41443:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#56729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41444:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#56730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41445:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#56731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41446:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#56732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41447:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#56733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41448:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#56734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41449:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#56735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41450:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41451:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41452:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41453:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41454:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41455:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#56741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41456:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#56742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41457:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41458:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#56744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41459:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#56745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41460:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41461:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#56747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41462:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#56748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41463:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#56749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41464:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41465:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41466:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L

WARNING: line length of 113 exceeds 100 columns
#56752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41467:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#56753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41468:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#56754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41469:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#56755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41470:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#56756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41471:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#56757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41472:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5

WARNING: line length of 113 exceeds 100 columns
#56758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41473:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8

WARNING: line length of 114 exceeds 100 columns
#56759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41474:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#56760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41475:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d

WARNING: line length of 121 exceeds 100 columns
#56761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41476:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41477:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41478:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41479:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#56765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41480:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41481:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#56767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41482:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#56768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41483:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#56769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41484:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L

WARNING: line length of 113 exceeds 100 columns
#56770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41485:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0

WARNING: line length of 118 exceeds 100 columns
#56771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41486:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4

WARNING: line length of 118 exceeds 100 columns
#56772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41487:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc

WARNING: line length of 114 exceeds 100 columns
#56773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41488:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#56774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41489:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L

WARNING: line length of 124 exceeds 100 columns
#56775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41490:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L

WARNING: line length of 124 exceeds 100 columns
#56776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41491:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L

WARNING: line length of 121 exceeds 100 columns
#56777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41492:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L

WARNING: line length of 113 exceeds 100 columns
#56778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41493:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#56779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41494:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4

WARNING: line length of 113 exceeds 100 columns
#56780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41495:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#56781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41496:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc

WARNING: line length of 117 exceeds 100 columns
#56782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41497:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#56783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41498:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41499:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41500:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41501:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L

WARNING: line length of 122 exceeds 100 columns
#56787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41502:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41503:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0

WARNING: line length of 114 exceeds 100 columns
#56789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41504:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10

WARNING: line length of 121 exceeds 100 columns
#56790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41505:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41506:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41507:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0

WARNING: line length of 114 exceeds 100 columns
#56793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41508:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#56794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41509:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41510:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41511:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#56797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41512:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#56798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41513:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8

WARNING: line length of 121 exceeds 100 columns
#56799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41514:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41515:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#56801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41516:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L

WARNING: line length of 115 exceeds 100 columns
#56802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41517:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0

WARNING: line length of 129 exceeds 100 columns
#56803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41518:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4

WARNING: line length of 121 exceeds 100 columns
#56804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41519:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L

WARNING: line length of 135 exceeds 100 columns
#56805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41520:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#56806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41521:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#56807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41522:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4

WARNING: line length of 121 exceeds 100 columns
#56808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41523:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41524:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L

WARNING: line length of 113 exceeds 100 columns
#56810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41525:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#56811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41526:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#56812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41527:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#56813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41528:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41529:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#56815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41530:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#56816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41531:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#56817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41532:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41533:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#56819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41534:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#56820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41535:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#56821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41536:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#56822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41537:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#56823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41538:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#56824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41539:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#56825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41540:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L

WARNING: line length of 121 exceeds 100 columns
#56826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41541:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41542:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L

WARNING: line length of 113 exceeds 100 columns
#56828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41543:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#56829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41544:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41545:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0

WARNING: line length of 113 exceeds 100 columns
#56831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41546:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4

WARNING: line length of 113 exceeds 100 columns
#56832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41547:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8

WARNING: line length of 113 exceeds 100 columns
#56833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41548:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc

WARNING: line length of 114 exceeds 100 columns
#56834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41549:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10

WARNING: line length of 121 exceeds 100 columns
#56835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41550:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41551:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41552:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41553:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L

WARNING: line length of 121 exceeds 100 columns
#56839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41554:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L

WARNING: line length of 115 exceeds 100 columns
#56840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41555:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#56841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41556:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L

WARNING: line length of 113 exceeds 100 columns
#56842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41557:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#56843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41558:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L

WARNING: line length of 113 exceeds 100 columns
#56844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41559:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#56845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41560:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4

WARNING: line length of 113 exceeds 100 columns
#56846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41561:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8

WARNING: line length of 114 exceeds 100 columns
#56847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41562:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10

WARNING: line length of 114 exceeds 100 columns
#56848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41563:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14

WARNING: line length of 116 exceeds 100 columns
#56849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41564:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#56850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41565:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c

WARNING: line length of 121 exceeds 100 columns
#56851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41566:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41567:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41568:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#56854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41569:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#56855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41570:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L

WARNING: line length of 121 exceeds 100 columns
#56856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41571:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41572:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L

WARNING: line length of 115 exceeds 100 columns
#56858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41573:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0

WARNING: line length of 115 exceeds 100 columns
#56859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41574:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1

WARNING: line length of 115 exceeds 100 columns
#56860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41575:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#56861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41576:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4

WARNING: line length of 113 exceeds 100 columns
#56862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41577:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#56863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41578:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18

WARNING: line length of 114 exceeds 100 columns
#56864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41579:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f

WARNING: line length of 121 exceeds 100 columns
#56865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41580:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41581:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41582:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#56868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41583:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L

WARNING: line length of 121 exceeds 100 columns
#56869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41584:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#56870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41585:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#56871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41586:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#56872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41587:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#56873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41588:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41589:
+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#56875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41590:
+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#56876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41591:
+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41592:
+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#56878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41593:
+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#56879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41594:
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8

WARNING: line length of 114 exceeds 100 columns
#56880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41595:
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#56881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41596:
+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41597:
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41598:
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#56884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41599:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#56885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41600:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#56886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41601:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#56887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41602:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18

WARNING: line length of 121 exceeds 100 columns
#56888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41603:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41604:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41605:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41606:
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#56892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41607:
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1

WARNING: line length of 113 exceeds 100 columns
#56893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41608:
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2

WARNING: line length of 121 exceeds 100 columns
#56894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41609:
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#56895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41610:
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L

WARNING: line length of 113 exceeds 100 columns
#56896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41611:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#56897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41612:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#56898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41613:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd

WARNING: line length of 114 exceeds 100 columns
#56899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41614:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10

WARNING: line length of 121 exceeds 100 columns
#56900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41615:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41616:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41617:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L

WARNING: line length of 121 exceeds 100 columns
#56903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41618:
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41619:
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#56905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41620:
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#56906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41621:
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#56907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41622:
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#56908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41623:
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#56909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41624:
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41625:
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41626:
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#56912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41627:
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4

WARNING: line length of 113 exceeds 100 columns
#56913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41628:
+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8

WARNING: line length of 114 exceeds 100 columns
#56914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41629:
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18

WARNING: line length of 114 exceeds 100 columns
#56915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41630:
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19

WARNING: line length of 121 exceeds 100 columns
#56916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41631:
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41632:
+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41633:
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41634:
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L

WARNING: line length of 113 exceeds 100 columns
#56920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41635:
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#56921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41636:
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#56922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41637:
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#56923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41638:
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#56924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41639:
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#56925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41640:
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc

WARNING: line length of 121 exceeds 100 columns
#56926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41641:
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41642:
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#56928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41643:
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#56929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41644:
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L

WARNING: line length of 113 exceeds 100 columns
#56930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41645:
+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#56931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41646:
+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#56932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41647:
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#56933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41648:
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#56934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41649:
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#56935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41650:
+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#56936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41651:
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#56937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41652:
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#56938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41653:
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#56939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41654:
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#56940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41655:
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#56941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41656:
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#56942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41657:
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41658:
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#56944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41659:
+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#56945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41660:
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#56946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41661:
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#56947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41662:
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#56948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41663:
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#56949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41664:
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#56950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41665:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#56951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41666:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#56952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41667:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#56953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41668:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#56954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41669:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#56955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41670:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#56956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41671:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#56957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41672:
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#56958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41673:
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#56959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41674:
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#56960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41675:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#56961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41676:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#56962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41677:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#56963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41678:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#56964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41679:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#56965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41680:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#56966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41681:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#56967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41682:
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#56968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41683:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#56969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41684:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#56970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41685:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#56971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41686:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#56972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41687:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#56973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41688:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#56974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41689:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#56975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41690:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#56976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41691:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#56977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41692:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#56978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41693:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#56979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41694:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#56980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41695:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#56981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41696:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#56982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41697:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#56983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41698:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#56984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41699:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#56985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41700:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#56986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41701:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#56987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41702:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#56988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41703:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#56989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41704:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#56990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41705:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#56991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41706:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#56992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41707:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#56993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41708:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#56994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41709:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#56995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41710:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#56996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41711:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#56997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41712:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#56998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41713:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#56999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41714:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41715:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41716:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41717:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41718:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#57004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41719:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#57005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41720:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41721:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41722:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41723:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41724:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#57010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41725:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#57011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41726:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#57012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41727:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#57013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41728:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#57014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41729:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#57015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41730:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#57016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41731:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#57017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41732:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#57018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41733:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#57019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41734:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#57020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41735:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#57021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41736:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#57022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41737:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#57023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41738:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#57024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41739:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#57025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41740:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#57026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41741:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#57027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41742:
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#57028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41743:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#57029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41744:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#57030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41745:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#57031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41746:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#57032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41747:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#57033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41748:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#57034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41749:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#57035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41750:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#57036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41751:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#57037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41752:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#57038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41753:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#57039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41754:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#57040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41755:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#57041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41756:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#57042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41757:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#57043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41758:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#57044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41759:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#57045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41760:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#57046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41761:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#57047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41762:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#57048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41763:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#57049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41764:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#57050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41765:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#57051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41766:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#57052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41767:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#57053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41768:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#57054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41769:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#57055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41770:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#57056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41771:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#57057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41772:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#57058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41773:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41774:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41775:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41776:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41777:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41778:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#57064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41779:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#57065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41780:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41781:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41782:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41783:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41784:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#57070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41785:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#57071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41786:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#57072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41787:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#57073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41788:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#57074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41789:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#57075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41790:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#57076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41791:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#57077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41792:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#57078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41793:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#57079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41794:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#57080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41795:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#57081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41796:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#57082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41797:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#57083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41798:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#57084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41799:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#57085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41800:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#57086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41801:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#57087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41802:
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#57088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41803:
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41804:
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#57090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41805:
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#57091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41806:
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41807:
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41808:
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#57094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41809:
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#57095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41810:
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#57096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41811:
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#57097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41812:
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41813:
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41814:
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#57100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41815:
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#57101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41816:
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41817:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#57103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41818:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#57104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41819:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#57105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41820:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#57106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41821:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#57107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41822:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#57108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41823:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#57109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41824:
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#57110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41825:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#57111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41826:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#57112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41827:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#57113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41828:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#57114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41829:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#57115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41830:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#57116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41831:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#57117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41832:
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#57118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41833:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#57119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41834:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#57120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41835:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#57121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41836:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#57122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41837:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#57123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41838:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#57124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41839:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#57125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41840:
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#57126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41841:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#57127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41842:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#57128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41843:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8

WARNING: line length of 121 exceeds 100 columns
#57129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41844:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41845:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41846:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L

WARNING: line length of 113 exceeds 100 columns
#57132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41847:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0

WARNING: line length of 113 exceeds 100 columns
#57133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41848:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#57134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41849:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8

WARNING: line length of 113 exceeds 100 columns
#57135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41850:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc

WARNING: line length of 121 exceeds 100 columns
#57136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41851:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41852:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41853:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41854:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L

WARNING: line length of 113 exceeds 100 columns
#57140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41855:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#57141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41856:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4

WARNING: line length of 121 exceeds 100 columns
#57142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41857:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41858:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L

WARNING: line length of 120 exceeds 100 columns
#57144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41859:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#57145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41860:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4

WARNING: line length of 126 exceeds 100 columns
#57146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41861:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L

WARNING: line length of 127 exceeds 100 columns
#57147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41862:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#57148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41863:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#57149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41864:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#57150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41865:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8

WARNING: line length of 121 exceeds 100 columns
#57151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41866:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41867:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41868:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L

WARNING: line length of 113 exceeds 100 columns
#57154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41869:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41870:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41871:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41872:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41873:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41874:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41875:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41876:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41877:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41878:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41879:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41880:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41881:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41882:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41883:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41884:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41885:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#57171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41886:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41887:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0

WARNING: line length of 121 exceeds 100 columns
#57173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41888:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#57174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41889:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41890:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41891:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41892:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41893:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41894:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41895:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41896:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41897:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41898:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41899:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41900:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41901:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41902:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41903:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41904:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41905:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41906:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41907:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41908:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41909:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41910:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41911:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41912:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41913:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41914:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41915:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41916:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41917:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41918:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41919:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41920:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41921:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41922:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41923:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41924:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41925:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41926:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41927:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41928:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41929:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41930:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41931:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41932:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41933:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41934:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41935:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41936:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41937:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41938:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41939:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41940:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41941:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41942:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41943:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41944:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41945:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41946:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41947:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41948:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41949:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41950:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41951:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41952:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41953:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41954:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41955:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41956:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41957:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41958:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41959:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41960:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41961:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41962:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41963:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41964:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41965:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41966:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41967:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41968:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41969:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41970:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41971:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41972:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41973:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41974:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41975:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41976:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41977:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41978:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41979:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41980:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41981:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41982:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41983:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41984:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41985:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41986:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41987:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41988:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41989:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41990:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41991:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41992:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41993:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41994:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41995:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41996:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41997:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41998:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:41999:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42000:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42001:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42002:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42003:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42004:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42005:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42006:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42007:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42008:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42009:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42010:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42011:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42012:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42013:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42014:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42015:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42016:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42017:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42018:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42019:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42020:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42021:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42022:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42023:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42024:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42025:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42026:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42027:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42028:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42029:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42030:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42031:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42032:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42033:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42034:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42035:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42036:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42037:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42038:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42039:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42040:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42041:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42042:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42043:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42044:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42045:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42046:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42047:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42048:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42049:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42050:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42051:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42052:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42053:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42054:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42055:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42056:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42057:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42058:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42059:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42060:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42061:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42062:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42063:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42064:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42065:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42066:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42067:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42068:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42069:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42070:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42071:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42072:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42073:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42074:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42075:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42076:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42077:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42078:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42079:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42080:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42081:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42082:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42083:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42084:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42085:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42086:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42087:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0

WARNING: line length of 113 exceeds 100 columns
#57373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42088:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1

WARNING: line length of 113 exceeds 100 columns
#57374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42089:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2

WARNING: line length of 113 exceeds 100 columns
#57375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42090:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3

WARNING: line length of 113 exceeds 100 columns
#57376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42091:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4

WARNING: line length of 113 exceeds 100 columns
#57377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42092:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#57378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42093:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7

WARNING: line length of 113 exceeds 100 columns
#57379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42094:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42095:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9

WARNING: line length of 113 exceeds 100 columns
#57381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42096:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa

WARNING: line length of 114 exceeds 100 columns
#57382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42097:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#57383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42098:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42099:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42100:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42101:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42102:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42103:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42104:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42105:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42106:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42107:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42108:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42109:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#57395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42110:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#57396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42111:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#57397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42112:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#57398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42113:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#57399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42114:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#57400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42115:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#57401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42116:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#57402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42117:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#57403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42118:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#57404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42119:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#57405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42120:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42121:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42122:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42123:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42124:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42125:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42126:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42127:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42128:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42129:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42130:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42131:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#57417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42132:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#57418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42133:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#57419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42134:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#57420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42135:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#57421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42136:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#57422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42137:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#57423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42138:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#57424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42139:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#57425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42140:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#57426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42141:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#57427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42142:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42143:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42144:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42145:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42146:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42147:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42148:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42149:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42150:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42151:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42152:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42153:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#57439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42154:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#57440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42155:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#57441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42156:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#57442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42157:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#57443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42158:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#57444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42159:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#57445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42160:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#57446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42161:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#57447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42162:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#57448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42163:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#57449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42164:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42165:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42166:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42167:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42168:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42169:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42170:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42171:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42172:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42173:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42174:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42175:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#57461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42176:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#57462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42177:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#57463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42178:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#57464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42179:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#57465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42180:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#57466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42181:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#57467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42182:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#57468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42183:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#57469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42184:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#57470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42185:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#57471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42186:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42187:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42188:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42189:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42190:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42191:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42192:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42193:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42194:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42195:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42196:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42197:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#57483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42198:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#57484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42199:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2

WARNING: line length of 113 exceeds 100 columns
#57485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42200:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3

WARNING: line length of 113 exceeds 100 columns
#57486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42201:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4

WARNING: line length of 113 exceeds 100 columns
#57487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42202:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5

WARNING: line length of 113 exceeds 100 columns
#57488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42203:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#57489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42204:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8

WARNING: line length of 113 exceeds 100 columns
#57490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42205:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9

WARNING: line length of 113 exceeds 100 columns
#57491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42206:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa

WARNING: line length of 114 exceeds 100 columns
#57492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42207:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10

WARNING: line length of 121 exceeds 100 columns
#57493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42208:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42209:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42210:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42211:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42212:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42213:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L

WARNING: line length of 121 exceeds 100 columns
#57499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42214:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42215:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42216:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L

WARNING: line length of 121 exceeds 100 columns
#57502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42217:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#57503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42218:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42219:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#57505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42220:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4

WARNING: line length of 113 exceeds 100 columns
#57506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42221:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#57507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42222:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42223:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42224:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L

WARNING: line length of 113 exceeds 100 columns
#57510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42225:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#57511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42226:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#57512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42227:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#57513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42228:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#57514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42229:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4

WARNING: line length of 113 exceeds 100 columns
#57515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42230:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5

WARNING: line length of 113 exceeds 100 columns
#57516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42231:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8

WARNING: line length of 114 exceeds 100 columns
#57517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42232:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#57518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42233:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d

WARNING: line length of 121 exceeds 100 columns
#57519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42234:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42235:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42236:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42237:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42238:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42239:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#57525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42240:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#57526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42241:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#57527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42242:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L

WARNING: line length of 113 exceeds 100 columns
#57528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42243:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0

WARNING: line length of 118 exceeds 100 columns
#57529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42244:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4

WARNING: line length of 118 exceeds 100 columns
#57530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42245:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc

WARNING: line length of 114 exceeds 100 columns
#57531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42246:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#57532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42247:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L

WARNING: line length of 124 exceeds 100 columns
#57533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42248:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L

WARNING: line length of 124 exceeds 100 columns
#57534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42249:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L

WARNING: line length of 121 exceeds 100 columns
#57535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42250:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L

WARNING: line length of 113 exceeds 100 columns
#57536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42251:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#57537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42252:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4

WARNING: line length of 113 exceeds 100 columns
#57538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42253:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8

WARNING: line length of 113 exceeds 100 columns
#57539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42254:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc

WARNING: line length of 117 exceeds 100 columns
#57540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42255:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10

WARNING: line length of 121 exceeds 100 columns
#57541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42256:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42257:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42258:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42259:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L

WARNING: line length of 122 exceeds 100 columns
#57545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42260:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42261:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0

WARNING: line length of 114 exceeds 100 columns
#57547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42262:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10

WARNING: line length of 121 exceeds 100 columns
#57548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42263:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42264:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42265:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0

WARNING: line length of 114 exceeds 100 columns
#57551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42266:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#57552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42267:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42268:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42269:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#57555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42270:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4

WARNING: line length of 113 exceeds 100 columns
#57556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42271:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8

WARNING: line length of 121 exceeds 100 columns
#57557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42272:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42273:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42274:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L

WARNING: line length of 115 exceeds 100 columns
#57560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42275:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0

WARNING: line length of 129 exceeds 100 columns
#57561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42276:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4

WARNING: line length of 121 exceeds 100 columns
#57562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42277:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L

WARNING: line length of 135 exceeds 100 columns
#57563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42278:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#57564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42279:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#57565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42280:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4

WARNING: line length of 121 exceeds 100 columns
#57566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42281:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42282:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L

WARNING: line length of 113 exceeds 100 columns
#57568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42283:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#57569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42284:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#57570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42285:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#57571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42286:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42287:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0

WARNING: line length of 114 exceeds 100 columns
#57573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42288:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#57574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42289:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#57575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42290:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42291:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#57577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42292:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#57578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42293:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#57579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42294:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#57580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42295:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#57581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42296:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#57582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42297:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42298:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42299:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#57585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42300:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L

WARNING: line length of 113 exceeds 100 columns
#57586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42301:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#57587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42302:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#57588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42303:
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42304:
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42305:
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42306:
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42307:
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42308:
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42309:
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#57595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42310:
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42311:
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#57597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42312:
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#57598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42313:
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8

WARNING: line length of 113 exceeds 100 columns
#57599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42314:
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb

WARNING: line length of 114 exceeds 100 columns
#57600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42315:
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#57601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42316:
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#57602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42317:
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42318:
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42319:
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#57605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42320:
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42321:
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L

WARNING: line length of 121 exceeds 100 columns
#57607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42322:
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#57608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42323:
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#57609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42324:
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#57610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42325:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#57611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42326:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#57612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42327:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42328:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#57614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42329:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#57615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42330:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#57616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42331:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#57617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42332:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42333:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#57619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42334:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42335:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#57621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42336:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#57622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42337:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#57623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42338:
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L

WARNING: line length of 113 exceeds 100 columns
#57624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42339:
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42340:
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#57626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42341:
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#57627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42342:
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#57628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42343:
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42344:
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42345:
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42346:
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42347:
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42348:
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42349:
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42350:
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42351:
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42352:
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42353:
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42354:
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42355:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42356:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#57642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42357:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#57643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42358:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#57644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42359:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42360:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42361:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42362:
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L

WARNING: line length of 113 exceeds 100 columns
#57648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42363:
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#57649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42364:
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#57650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42365:
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#57651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42366:
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42367:
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42368:
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#57654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42369:
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42370:
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42371:
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42372:
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42373:
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42374:
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42375:
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#57661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42376:
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42377:
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#57663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42378:
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#57664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42379:
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8

WARNING: line length of 113 exceeds 100 columns
#57665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42380:
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb

WARNING: line length of 114 exceeds 100 columns
#57666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42381:
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#57667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42382:
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#57668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42383:
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42384:
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42385:
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#57671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42386:
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42387:
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L

WARNING: line length of 121 exceeds 100 columns
#57673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42388:
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#57674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42389:
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#57675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42390:
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#57676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42391:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#57677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42392:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#57678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42393:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42394:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#57680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42395:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#57681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42396:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#57682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42397:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#57683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42398:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42399:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#57685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42400:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42401:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#57687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42402:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#57688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42403:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#57689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42404:
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L

WARNING: line length of 113 exceeds 100 columns
#57690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42405:
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42406:
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#57692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42407:
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#57693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42408:
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#57694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42409:
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42410:
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42411:
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42412:
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42413:
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42414:
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42415:
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42416:
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42417:
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42418:
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42419:
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42420:
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42421:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42422:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#57708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42423:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#57709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42424:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#57710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42425:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42426:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42427:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42428:
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L

WARNING: line length of 113 exceeds 100 columns
#57714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42429:
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#57715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42430:
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#57716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42431:
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#57717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42432:
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42433:
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42434:
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#57720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42435:
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42436:
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42437:
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42438:
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42439:
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42440:
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42441:
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#57727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42442:
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42443:
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#57729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42444:
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#57730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42445:
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8

WARNING: line length of 113 exceeds 100 columns
#57731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42446:
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb

WARNING: line length of 114 exceeds 100 columns
#57732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42447:
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#57733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42448:
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#57734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42449:
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42450:
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42451:
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#57737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42452:
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42453:
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L

WARNING: line length of 121 exceeds 100 columns
#57739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42454:
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#57740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42455:
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#57741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42456:
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#57742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42457:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#57743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42458:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#57744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42459:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42460:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#57746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42461:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#57747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42462:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#57748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42463:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#57749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42464:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42465:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#57751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42466:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42467:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#57753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42468:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#57754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42469:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#57755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42470:
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L

WARNING: line length of 113 exceeds 100 columns
#57756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42471:
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42472:
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#57758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42473:
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#57759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42474:
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#57760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42475:
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42476:
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42477:
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42478:
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42479:
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42480:
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42481:
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42482:
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42483:
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42484:
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42485:
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42486:
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42487:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42488:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#57774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42489:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#57775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42490:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#57776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42491:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42492:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42493:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42494:
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L

WARNING: line length of 113 exceeds 100 columns
#57780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42495:
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#57781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42496:
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#57782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42497:
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#57783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42498:
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42499:
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42500:
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#57786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42501:
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42502:
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42503:
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42504:
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42505:
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42506:
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#57792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42507:
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#57793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42508:
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42509:
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#57795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42510:
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7

WARNING: line length of 113 exceeds 100 columns
#57796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42511:
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8

WARNING: line length of 113 exceeds 100 columns
#57797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42512:
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb

WARNING: line length of 114 exceeds 100 columns
#57798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42513:
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10

WARNING: line length of 114 exceeds 100 columns
#57799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42514:
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#57800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42515:
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42516:
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42517:
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#57803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42518:
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#57804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42519:
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L

WARNING: line length of 121 exceeds 100 columns
#57805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42520:
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#57806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42521:
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#57807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42522:
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#57808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42523:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#57809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42524:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#57810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42525:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#57811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42526:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5

WARNING: line length of 113 exceeds 100 columns
#57812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42527:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8

WARNING: line length of 114 exceeds 100 columns
#57813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42528:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#57814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42529:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18

WARNING: line length of 121 exceeds 100 columns
#57815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42530:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42531:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#57817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42532:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#57818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42533:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L

WARNING: line length of 121 exceeds 100 columns
#57819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42534:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#57820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42535:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L

WARNING: line length of 121 exceeds 100 columns
#57821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42536:
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L

WARNING: line length of 113 exceeds 100 columns
#57822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42537:
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42538:
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#57824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42539:
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#57825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42540:
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L

WARNING: line length of 113 exceeds 100 columns
#57826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42541:
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42542:
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42543:
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42544:
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42545:
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#57831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42546:
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42547:
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42548:
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42549:
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#57835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42550:
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42551:
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#57837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42552:
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#57838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42553:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#57839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42554:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#57840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42555:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4

WARNING: line length of 113 exceeds 100 columns
#57841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42556:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8

WARNING: line length of 121 exceeds 100 columns
#57842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42557:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42558:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42559:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L

WARNING: line length of 121 exceeds 100 columns
#57845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42560:
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L

WARNING: line length of 113 exceeds 100 columns
#57846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42561:
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#57847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42562:
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#57848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42563:
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2

WARNING: line length of 121 exceeds 100 columns
#57849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42564:
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#57850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42565:
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#57851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42566:
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L

WARNING: line length of 113 exceeds 100 columns
#57852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42567:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#57853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42568:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#57854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42569:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#57855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42570:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7

WARNING: line length of 113 exceeds 100 columns
#57856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42571:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9

WARNING: line length of 121 exceeds 100 columns
#57857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42572:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#57858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42573:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#57859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42574:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#57860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42575:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#57861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42576:
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L

WARNING: line length of 113 exceeds 100 columns
#57862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42577:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#57863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42578:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#57864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42579:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#57865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42580:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42581:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#57867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42582:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3

WARNING: line length of 113 exceeds 100 columns
#57868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42583:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#57869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42584:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7

WARNING: line length of 121 exceeds 100 columns
#57870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42585:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#57871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42586:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L

WARNING: line length of 121 exceeds 100 columns
#57872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42587:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#57873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42588:
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L

WARNING: line length of 113 exceeds 100 columns
#57874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42589:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#57875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42590:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#57876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42591:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#57877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42592:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#57878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42593:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#57879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42594:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#57880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42595:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#57881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42596:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#57882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42597:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#57883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42598:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#57884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42599:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#57885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42600:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#57886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42601:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#57887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42602:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42603:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#57889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42604:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42605:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#57891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42606:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42607:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#57893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42608:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42609:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#57895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42610:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42611:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#57897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42612:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42613:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#57899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42614:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42615:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#57901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42616:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#57902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42617:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#57903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42618:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42619:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#57905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42620:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42621:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#57907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42622:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#57908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42623:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#57909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42624:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42625:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#57911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42626:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#57912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42627:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#57913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42628:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#57914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42629:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#57915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42630:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#57916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42631:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#57917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42632:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42633:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#57919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42634:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42635:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#57921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42636:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#57922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42637:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#57923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42638:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#57924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42639:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#57925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42640:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#57926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42641:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42642:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42643:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42644:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42645:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#57931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42646:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#57932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42647:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#57933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42648:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#57934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42649:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42650:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42651:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42652:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42653:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#57939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42654:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#57940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42655:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#57941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42656:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#57942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42657:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42658:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42659:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42660:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42661:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#57947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42662:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#57948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42663:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#57949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42664:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#57950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42665:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42666:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42667:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42668:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42669:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#57955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42670:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#57956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42671:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#57957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42672:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#57958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42673:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42674:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42675:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42676:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42677:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#57963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42678:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#57964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42679:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#57965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42680:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#57966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42681:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42682:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42683:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42684:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42685:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#57971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42686:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#57972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42687:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#57973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42688:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#57974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42689:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42690:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42691:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42692:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42693:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#57979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42694:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#57980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42695:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#57981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42696:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#57982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42697:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42698:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42699:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42700:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42701:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#57987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42702:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#57988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42703:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#57989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42704:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#57990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42705:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42706:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#57992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42707:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#57993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42708:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#57994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42709:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#57995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42710:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#57996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42711:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#57997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42712:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#57998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42713:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#57999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42714:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42715:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42716:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42717:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42718:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42719:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42720:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42721:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42722:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42723:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42724:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42725:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42726:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42727:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42728:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42729:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42730:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42731:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42732:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42733:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42734:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42735:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42736:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42737:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42738:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42739:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42740:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42741:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42742:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42743:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42744:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42745:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42746:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42747:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42748:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42749:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42750:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42751:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42752:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42753:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42754:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42755:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42756:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42757:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42758:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42759:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42760:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42761:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42762:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42763:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42764:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42765:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42766:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42767:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42768:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42769:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42770:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42771:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42772:
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42773:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42774:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42775:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42776:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42777:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42778:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42779:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42780:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42781:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42782:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42783:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42784:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42785:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42786:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42787:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42788:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42789:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42790:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42791:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42792:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42793:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42794:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42795:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42796:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42797:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42798:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42799:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42800:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42801:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42802:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42803:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42804:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42805:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42806:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42807:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42808:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42809:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42810:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42811:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42812:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42813:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42814:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42815:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42816:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42817:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42818:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42819:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42820:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42821:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42822:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42823:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42824:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42825:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42826:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42827:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42828:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42829:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42830:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42831:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42832:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42833:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42834:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42835:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42836:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42837:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42838:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42839:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42840:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42841:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42842:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42843:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42844:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42845:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42846:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42847:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42848:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42849:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42850:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42851:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42852:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42853:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42854:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42855:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42856:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42857:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42858:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42859:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42860:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42861:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42862:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42863:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42864:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42865:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42866:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42867:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42868:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42869:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42870:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42871:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42872:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42873:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42874:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42875:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42876:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42877:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42878:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42879:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42880:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42881:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42882:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42883:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42884:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42885:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42886:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42887:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42888:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42889:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42890:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42891:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42892:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42893:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42894:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42895:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42896:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42897:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42898:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42899:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42900:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42901:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42902:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42903:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42904:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42905:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42906:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42907:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42908:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42909:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42910:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42911:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42912:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42913:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42914:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42915:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42916:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42917:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42918:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42919:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42920:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42921:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42922:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42923:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42924:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42925:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42926:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42927:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42928:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42929:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42930:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42931:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42932:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42933:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42934:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42935:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42936:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42937:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42938:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42939:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42940:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42941:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42942:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42943:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42944:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42945:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42946:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42947:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42948:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42949:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42950:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42951:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42952:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42953:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42954:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42955:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42956:
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42957:
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#58243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42958:
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#58244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42959:
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#58245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42960:
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7

WARNING: line length of 121 exceeds 100 columns
#58246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42961:
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#58247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42962:
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L

WARNING: line length of 113 exceeds 100 columns
#58248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42963:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42964:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42965:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42966:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42967:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42968:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42969:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42970:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42971:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42972:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42973:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42974:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42975:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42976:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42977:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42978:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42979:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42980:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42981:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42982:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42983:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42984:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42985:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42986:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42987:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42988:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42989:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42990:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42991:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42992:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42993:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42994:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42995:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42996:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42997:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42998:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:42999:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43000:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43001:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43002:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43003:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43004:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43005:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43006:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43007:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43008:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43009:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43010:
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43011:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#58297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43012:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#58298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43013:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#58299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43014:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7

WARNING: line length of 113 exceeds 100 columns
#58300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43015:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9

WARNING: line length of 121 exceeds 100 columns
#58301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43016:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#58302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43017:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#58303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43018:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#58304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43019:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#58305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43020:
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L

WARNING: line length of 113 exceeds 100 columns
#58306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43021:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#58307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43022:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#58308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43023:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#58309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43024:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43025:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#58311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43026:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3

WARNING: line length of 113 exceeds 100 columns
#58312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43027:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#58313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43028:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7

WARNING: line length of 121 exceeds 100 columns
#58314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43029:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#58315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43030:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L

WARNING: line length of 121 exceeds 100 columns
#58316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43031:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#58317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43032:
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L

WARNING: line length of 113 exceeds 100 columns
#58318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43033:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43034:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43035:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43036:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43037:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43038:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43039:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43040:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43041:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43042:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43043:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43044:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43045:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43046:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43047:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43048:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43049:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43050:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43051:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43052:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43053:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43054:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43055:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43056:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43057:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43058:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43059:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43060:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43061:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43062:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43063:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43064:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43065:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43066:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43067:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43068:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43069:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43070:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43071:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43072:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43073:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43074:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43075:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43076:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43077:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43078:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43079:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43080:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43081:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43082:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43083:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43084:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43085:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43086:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43087:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43088:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43089:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43090:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43091:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43092:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43093:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43094:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43095:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43096:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43097:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43098:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43099:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43100:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43101:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43102:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43103:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43104:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43105:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43106:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43107:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43108:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43109:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43110:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43111:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43112:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43113:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43114:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43115:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43116:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43117:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43118:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43119:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43120:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43121:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43122:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43123:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43124:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43125:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43126:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43127:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43128:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43129:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43130:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43131:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43132:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43133:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43134:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43135:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43136:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43137:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43138:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43139:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43140:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43141:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43142:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43143:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43144:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43145:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43146:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43147:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43148:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43149:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43150:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43151:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43152:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43153:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43154:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43155:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43156:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43157:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43158:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43159:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43160:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43161:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43162:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43163:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43164:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43165:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43166:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43167:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43168:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43169:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43170:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43171:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43172:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43173:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43174:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43175:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43176:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43177:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43178:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43179:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43180:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43181:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43182:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43183:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43184:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43185:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43186:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43187:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43188:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43189:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43190:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43191:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43192:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43193:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43194:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43195:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43196:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43197:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43198:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43199:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43200:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43201:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43202:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43203:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43204:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43205:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43206:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43207:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43208:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43209:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43210:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43211:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43212:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43213:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43214:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43215:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43216:
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43217:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43218:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43219:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43220:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43221:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43222:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43223:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43224:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43225:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43226:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43227:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43228:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43229:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43230:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43231:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43232:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43233:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43234:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43235:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43236:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43237:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43238:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43239:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43240:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43241:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43242:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43243:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43244:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43245:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43246:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43247:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43248:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43249:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43250:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43251:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43252:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43253:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43254:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43255:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43256:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43257:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43258:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43259:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43260:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43261:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43262:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43263:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43264:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43265:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43266:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43267:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43268:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43269:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43270:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43271:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43272:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43273:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43274:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43275:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43276:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43277:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43278:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43279:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43280:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43281:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43282:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43283:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43284:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43285:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43286:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43287:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43288:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43289:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43290:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43291:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43292:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43293:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43294:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43295:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43296:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43297:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43298:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43299:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43300:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43301:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43302:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43303:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43304:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43305:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43306:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43307:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43308:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43309:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43310:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43311:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43312:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43313:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43314:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43315:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43316:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43317:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43318:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43319:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43320:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43321:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43322:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43323:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43324:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43325:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43326:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43327:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43328:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43329:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43330:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43331:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43332:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43333:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43334:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43335:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43336:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43337:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43338:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43339:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43340:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43341:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43342:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43343:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43344:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43345:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43346:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43347:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43348:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43349:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43350:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43351:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43352:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43353:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43354:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43355:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43356:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43357:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43358:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43359:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43360:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43361:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43362:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43363:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43364:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43365:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43366:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43367:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43368:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43369:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43370:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43371:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43372:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43373:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43374:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43375:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43376:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43377:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43378:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43379:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43380:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43381:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43382:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43383:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43384:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43385:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43386:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43387:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43388:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43389:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43390:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43391:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43392:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43393:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43394:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43395:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43396:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43397:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43398:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43399:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43400:
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43401:
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#58687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43402:
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#58688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43403:
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#58689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43404:
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7

WARNING: line length of 121 exceeds 100 columns
#58690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43405:
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#58691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43406:
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L

WARNING: line length of 113 exceeds 100 columns
#58692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43407:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43408:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43409:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43410:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43411:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43412:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43413:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43414:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43415:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43416:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43417:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43418:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43419:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43420:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43421:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43422:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43423:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43424:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43425:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43426:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43427:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43428:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43429:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43430:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43431:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43432:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43433:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43434:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43435:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43436:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43437:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43438:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43439:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43440:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43441:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43442:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43443:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43444:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43445:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43446:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43447:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43448:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43449:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43450:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43451:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#58737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43452:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#58738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43453:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43454:
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43455:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#58741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43456:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#58742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43457:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#58743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43458:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7

WARNING: line length of 113 exceeds 100 columns
#58744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43459:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9

WARNING: line length of 121 exceeds 100 columns
#58745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43460:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#58746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43461:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#58747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43462:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#58748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43463:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#58749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43464:
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L

WARNING: line length of 113 exceeds 100 columns
#58750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43465:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#58751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43466:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#58752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43467:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#58753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43468:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43469:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#58755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43470:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3

WARNING: line length of 113 exceeds 100 columns
#58756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43471:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#58757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43472:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7

WARNING: line length of 121 exceeds 100 columns
#58758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43473:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#58759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43474:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L

WARNING: line length of 121 exceeds 100 columns
#58760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43475:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#58761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43476:
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L

WARNING: line length of 113 exceeds 100 columns
#58762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43477:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43478:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43479:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43480:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43481:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43482:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43483:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43484:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43485:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43486:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43487:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43488:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43489:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43490:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43491:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43492:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43493:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43494:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43495:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43496:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43497:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43498:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43499:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43500:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43501:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43502:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43503:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43504:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43505:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43506:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43507:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43508:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43509:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43510:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43511:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43512:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43513:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43514:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43515:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43516:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43517:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43518:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43519:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43520:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43521:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43522:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43523:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43524:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43525:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43526:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43527:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43528:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43529:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43530:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43531:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43532:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43533:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43534:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43535:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43536:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43537:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43538:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43539:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43540:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43541:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43542:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43543:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43544:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43545:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43546:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43547:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43548:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43549:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43550:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43551:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43552:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43553:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43554:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43555:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43556:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43557:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43558:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43559:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43560:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43561:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43562:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43563:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43564:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43565:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43566:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43567:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43568:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43569:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43570:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43571:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43572:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43573:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43574:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43575:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43576:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43577:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43578:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43579:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43580:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43581:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43582:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43583:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43584:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43585:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43586:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43587:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43588:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43589:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43590:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43591:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43592:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43593:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43594:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43595:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43596:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43597:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43598:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43599:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43600:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43601:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43602:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43603:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43604:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43605:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43606:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43607:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43608:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43609:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43610:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43611:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43612:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43613:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43614:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43615:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43616:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43617:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43618:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43619:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43620:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43621:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43622:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43623:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43624:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43625:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43626:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43627:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43628:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43629:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43630:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43631:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43632:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43633:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43634:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43635:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43636:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43637:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43638:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43639:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43640:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43641:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43642:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43643:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43644:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43645:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43646:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43647:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43648:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43649:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43650:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43651:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43652:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43653:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#58939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43654:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#58940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43655:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#58941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43656:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#58942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43657:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43658:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#58944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43659:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#58945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43660:
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#58946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43661:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43662:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43663:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43664:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43665:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43666:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43667:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43668:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43669:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#58955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43670:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#58956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43671:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#58957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43672:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#58958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43673:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43674:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43675:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43676:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43677:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#58963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43678:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43679:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43680:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43681:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43682:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43683:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#58969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43684:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43685:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43686:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43687:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43688:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43689:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43690:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43691:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43692:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43693:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43694:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43695:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43696:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43697:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#58983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43698:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#58984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43699:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#58985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43700:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#58986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43701:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#58987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43702:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#58988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43703:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43704:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43705:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43706:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43707:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#58993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43708:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#58994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43709:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#58995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43710:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#58996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43711:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#58997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43712:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#58998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43713:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#58999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43714:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43715:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43716:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43717:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43718:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43719:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43720:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43721:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43722:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43723:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43724:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43725:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43726:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43727:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43728:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43729:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43730:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43731:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43732:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43733:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43734:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43735:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43736:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43737:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43738:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43739:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43740:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43741:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43742:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43743:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43744:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43745:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43746:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43747:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43748:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43749:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43750:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43751:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43752:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43753:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43754:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43755:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43756:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43757:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43758:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43759:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43760:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43761:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43762:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43763:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43764:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43765:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43766:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43767:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43768:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43769:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43770:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43771:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43772:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43773:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43774:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43775:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43776:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43777:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43778:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43779:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43780:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43781:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43782:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43783:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43784:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43785:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43786:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43787:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43788:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43789:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43790:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43791:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43792:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43793:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43794:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43795:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43796:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43797:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43798:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43799:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43800:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43801:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43802:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43803:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43804:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43805:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43806:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43807:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43808:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43809:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43810:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43811:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43812:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43813:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43814:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43815:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43816:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43817:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43818:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43819:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43820:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43821:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43822:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43823:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43824:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43825:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43826:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43827:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43828:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43829:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43830:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43831:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43832:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43833:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43834:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43835:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43836:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43837:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43838:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43839:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43840:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43841:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43842:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43843:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43844:
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43845:
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#59131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43846:
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43847:
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#59133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43848:
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7

WARNING: line length of 121 exceeds 100 columns
#59134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43849:
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#59135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43850:
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L

WARNING: line length of 113 exceeds 100 columns
#59136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43851:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43852:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43853:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43854:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43855:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43856:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43857:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43858:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43859:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43860:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43861:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43862:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43863:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43864:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43865:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43866:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43867:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43868:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43869:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43870:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43871:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43872:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43873:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43874:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43875:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43876:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43877:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43878:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43879:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43880:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43881:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43882:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43883:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43884:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43885:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43886:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43887:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43888:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43889:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43890:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43891:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43892:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43893:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43894:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43895:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43896:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43897:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43898:
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43899:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#59185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43900:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#59186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43901:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3

WARNING: line length of 113 exceeds 100 columns
#59187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43902:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7

WARNING: line length of 113 exceeds 100 columns
#59188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43903:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9

WARNING: line length of 121 exceeds 100 columns
#59189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43904:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L

WARNING: line length of 121 exceeds 100 columns
#59190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43905:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#59191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43906:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L

WARNING: line length of 121 exceeds 100 columns
#59192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43907:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L

WARNING: line length of 121 exceeds 100 columns
#59193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43908:
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L

WARNING: line length of 113 exceeds 100 columns
#59194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43909:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#59195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43910:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#59196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43911:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0

WARNING: line length of 121 exceeds 100 columns
#59197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43912:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43913:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#59199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43914:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3

WARNING: line length of 113 exceeds 100 columns
#59200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43915:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6

WARNING: line length of 113 exceeds 100 columns
#59201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43916:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7

WARNING: line length of 121 exceeds 100 columns
#59202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43917:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L

WARNING: line length of 121 exceeds 100 columns
#59203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43918:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L

WARNING: line length of 121 exceeds 100 columns
#59204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43919:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L

WARNING: line length of 121 exceeds 100 columns
#59205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43920:
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L

WARNING: line length of 113 exceeds 100 columns
#59206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43921:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#59207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43922:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#59208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43923:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#59209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43924:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#59210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43925:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#59211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43926:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#59212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43927:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#59213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43928:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#59214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43929:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#59215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43930:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#59216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43931:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#59217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43932:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#59218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43933:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#59219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43934:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43935:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#59221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43936:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43937:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#59223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43938:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43939:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#59225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43940:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43941:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#59227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43942:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43943:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#59229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43944:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43945:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#59231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43946:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43947:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#59233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43948:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#59234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43949:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43950:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43951:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#59237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43952:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43953:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#59239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43954:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#59240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43955:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43956:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43957:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#59243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43958:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43959:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#59245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43960:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#59246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43961:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43962:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43963:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43964:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#59250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43965:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43966:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#59252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43967:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43968:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#59254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43969:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43970:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43971:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43972:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43973:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43974:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43975:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43976:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43977:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43978:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43979:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43980:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43981:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43982:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43983:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43984:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43985:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43986:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43987:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43988:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43989:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43990:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43991:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43992:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43993:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43994:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43995:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43996:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43997:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43998:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:43999:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44000:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44001:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44002:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44003:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44004:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44005:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44006:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44007:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44008:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44009:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44010:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44011:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44012:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44013:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44014:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44015:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44016:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44017:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44018:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44019:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44020:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44021:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44022:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44023:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44024:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44025:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44026:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44027:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44028:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44029:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44030:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44031:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44032:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44033:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44034:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44035:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44036:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44037:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44038:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44039:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44040:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44041:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44042:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44043:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44044:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44045:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44046:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44047:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44048:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44049:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44050:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44051:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44052:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44053:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44054:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44055:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44056:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44057:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44058:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44059:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44060:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44061:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44062:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44063:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44064:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44065:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44066:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44067:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44068:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44069:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44070:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44071:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44072:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44073:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44074:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44075:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44076:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44077:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44078:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44079:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44080:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44081:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44082:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44083:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44084:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44085:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44086:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44087:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44088:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44089:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44090:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44091:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44092:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44093:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44094:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44095:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44096:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44097:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44098:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44099:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44100:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44101:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44102:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44103:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44104:
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44105:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#59391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44106:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#59392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44107:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#59393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44108:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#59394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44109:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#59395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44110:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#59396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44111:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#59397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44112:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#59398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44113:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0

WARNING: line length of 114 exceeds 100 columns
#59399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44114:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14

WARNING: line length of 121 exceeds 100 columns
#59400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44115:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#59401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44116:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#59402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44117:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#59403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44118:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44119:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#59405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44120:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44121:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0

WARNING: line length of 121 exceeds 100 columns
#59407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44122:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44123:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#59409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44124:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44125:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#59411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44126:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44127:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0

WARNING: line length of 121 exceeds 100 columns
#59413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44128:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44129:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#59415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44130:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44131:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#59417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44132:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#59418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44133:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44134:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44135:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#59421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44136:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44137:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#59423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44138:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#59424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44139:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44140:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44141:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0

WARNING: line length of 121 exceeds 100 columns
#59427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44142:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#59428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44143:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0

WARNING: line length of 114 exceeds 100 columns
#59429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44144:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10

WARNING: line length of 121 exceeds 100 columns
#59430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44145:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44146:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44147:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44148:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#59434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44149:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44150:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#59436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44151:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44152:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#59438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44153:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44154:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44155:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44156:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44157:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44158:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44159:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44160:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44161:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44162:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44163:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44164:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44165:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44166:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44167:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44168:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44169:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44170:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44171:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44172:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44173:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44174:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44175:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44176:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44177:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44178:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44179:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44180:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44181:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44182:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44183:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44184:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44185:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0

WARNING: line length of 113 exceeds 100 columns
#59471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44186:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc

WARNING: line length of 114 exceeds 100 columns
#59472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44187:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10

WARNING: line length of 114 exceeds 100 columns
#59473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44188:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c

WARNING: line length of 121 exceeds 100 columns
#59474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44189:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44190:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44191:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44192:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44193:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44194:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44195:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44196:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44197:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44198:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44199:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44200:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44201:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44202:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44203:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44204:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44205:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44206:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44207:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44208:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44209:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44210:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44211:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44212:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44213:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44214:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44215:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44216:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44217:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44218:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44219:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44220:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44221:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44222:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44223:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44224:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44225:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44226:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44227:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44228:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44229:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44230:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44231:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44232:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44233:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44234:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44235:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44236:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44237:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44238:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44239:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44240:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44241:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44242:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44243:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44244:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44245:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44246:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44247:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44248:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44249:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44250:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44251:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44252:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44253:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44254:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44255:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44256:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44257:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44258:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44259:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44260:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44261:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44262:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44263:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44264:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44265:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44266:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44267:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44268:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44269:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44270:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44271:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44272:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44273:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44274:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44275:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44276:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44277:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44278:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44279:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44280:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44281:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#59567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44282:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc

WARNING: line length of 114 exceeds 100 columns
#59568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44283:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10

WARNING: line length of 114 exceeds 100 columns
#59569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44284:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c

WARNING: line length of 121 exceeds 100 columns
#59570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44285:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#59571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44286:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L

WARNING: line length of 121 exceeds 100 columns
#59572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44287:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#59573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44288:
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L

WARNING: line length of 113 exceeds 100 columns
#59574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44289:
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0

WARNING: line length of 121 exceeds 100 columns
#59575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44290:
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44291:
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#59577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44292:
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7

WARNING: line length of 121 exceeds 100 columns
#59578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44293:
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L

WARNING: line length of 121 exceeds 100 columns
#59579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44294:
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L

WARNING: line length of 113 exceeds 100 columns
#59580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44295:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44296:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44297:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44298:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44299:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44300:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44301:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44302:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44303:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44304:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44305:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44306:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44307:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44308:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44309:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44310:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44311:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44312:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44313:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44314:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44315:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44316:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44317:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44318:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44319:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44320:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44321:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44322:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44323:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44324:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44325:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44326:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44327:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44328:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44329:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44330:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44331:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44332:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44333:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44334:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44335:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44336:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44337:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44338:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44339:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#59625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44340:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#59626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44341:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44342:
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44343:
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#59629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44344:
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4

WARNING: line length of 121 exceeds 100 columns
#59630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44345:
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#59631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44346:
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L

WARNING: line length of 113 exceeds 100 columns
#59632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44347:
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#59633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44348:
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1

WARNING: line length of 113 exceeds 100 columns
#59634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44349:
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2

WARNING: line length of 113 exceeds 100 columns
#59635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44350:
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3

WARNING: line length of 113 exceeds 100 columns
#59636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44351:
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa

WARNING: line length of 113 exceeds 100 columns
#59637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44352:
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb

WARNING: line length of 113 exceeds 100 columns
#59638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44353:
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc

WARNING: line length of 113 exceeds 100 columns
#59639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44354:
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#59640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44355:
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14

WARNING: line length of 114 exceeds 100 columns
#59641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44356:
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15

WARNING: line length of 114 exceeds 100 columns
#59642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44357:
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16

WARNING: line length of 114 exceeds 100 columns
#59643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44358:
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17

WARNING: line length of 114 exceeds 100 columns
#59644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44359:
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#59645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44360:
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#59646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44361:
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#59647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44362:
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#59648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44363:
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#59649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44364:
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44365:
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L

WARNING: line length of 121 exceeds 100 columns
#59651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44366:
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#59652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44367:
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#59653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44368:
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#59654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44369:
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#59655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44370:
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L

WARNING: line length of 121 exceeds 100 columns
#59656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44371:
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L

WARNING: line length of 121 exceeds 100 columns
#59657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44372:
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#59658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44373:
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#59659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44374:
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#59660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44375:
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8

WARNING: line length of 113 exceeds 100 columns
#59661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44376:
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa

WARNING: line length of 113 exceeds 100 columns
#59662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44377:
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc

WARNING: line length of 114 exceeds 100 columns
#59663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44378:
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#59664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44379:
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#59665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44380:
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#59666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44381:
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#59667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44382:
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#59668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44383:
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#59669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44384:
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L

WARNING: line length of 121 exceeds 100 columns
#59670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44385:
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44386:
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L

WARNING: line length of 121 exceeds 100 columns
#59672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44387:
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L

WARNING: line length of 121 exceeds 100 columns
#59673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44388:
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#59674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44389:
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#59675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44390:
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#59676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44391:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#59677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44392:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#59678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44393:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8

WARNING: line length of 114 exceeds 100 columns
#59679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44394:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10

WARNING: line length of 121 exceeds 100 columns
#59680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44395:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#59681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44396:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#59682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44397:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L

WARNING: line length of 121 exceeds 100 columns
#59683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44398:
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44399:
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#59685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44400:
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#59686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44401:
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44402:
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44403:
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#59689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44404:
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10

WARNING: line length of 121 exceeds 100 columns
#59690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44405:
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44406:
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44407:
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#59693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44408:
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#59694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44409:
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#59695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44410:
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44411:
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0

WARNING: line length of 114 exceeds 100 columns
#59697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44412:
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#59698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44413:
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44414:
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44415:
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#59701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44416:
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10

WARNING: line length of 121 exceeds 100 columns
#59702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44417:
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44418:
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44419:
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#59705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44420:
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#59706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44421:
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#59707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44422:
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#59708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44423:
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2

WARNING: line length of 113 exceeds 100 columns
#59709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44424:
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#59710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44425:
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#59711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44426:
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#59712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44427:
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#59713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44428:
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#59714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44429:
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa

WARNING: line length of 113 exceeds 100 columns
#59715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44430:
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#59716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44431:
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#59717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44432:
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe

WARNING: line length of 121 exceeds 100 columns
#59718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44433:
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#59719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44434:
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#59720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44435:
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#59721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44436:
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L

WARNING: line length of 121 exceeds 100 columns
#59722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44437:
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#59723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44438:
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#59724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44439:
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#59725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44440:
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#59726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44441:
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44442:
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#59728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44443:
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#59729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44444:
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L

WARNING: line length of 113 exceeds 100 columns
#59730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44445:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#59731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44446:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#59732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44447:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#59733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44448:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#59734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44449:
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#59735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44450:
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#59736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44451:
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa

WARNING: line length of 113 exceeds 100 columns
#59737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44452:
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb

WARNING: line length of 114 exceeds 100 columns
#59738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44453:
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44454:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#59740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44455:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#59741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44456:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#59742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44457:
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#59743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44458:
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#59744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44459:
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#59745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44460:
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44461:
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L

WARNING: line length of 121 exceeds 100 columns
#59747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44462:
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L

WARNING: line length of 113 exceeds 100 columns
#59748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44463:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44464:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44465:
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#59751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44466:
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44467:
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44468:
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44469:
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44470:
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44471:
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44472:
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44473:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44474:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44475:
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#59761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44476:
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44477:
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44478:
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44479:
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44480:
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44481:
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44482:
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44483:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44484:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44485:
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#59771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44486:
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44487:
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44488:
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44489:
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44490:
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44491:
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44492:
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44493:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44494:
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44495:
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#59781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44496:
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44497:
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44498:
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44499:
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44500:
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44501:
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#59787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44502:
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L

WARNING: line length of 113 exceeds 100 columns
#59788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44503:
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#59789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44504:
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4

WARNING: line length of 121 exceeds 100 columns
#59790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44505:
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#59791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44506:
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L

WARNING: line length of 113 exceeds 100 columns
#59792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44507:
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44508:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#59794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44509:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#59795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44510:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#59796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44511:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9

WARNING: line length of 113 exceeds 100 columns
#59797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44512:
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa

WARNING: line length of 113 exceeds 100 columns
#59798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44513:
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#59799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44514:
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#59800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44515:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#59801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44516:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#59802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44517:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#59803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44518:
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#59804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44519:
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44520:
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L

WARNING: line length of 113 exceeds 100 columns
#59806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44521:
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#59807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44522:
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc

WARNING: line length of 114 exceeds 100 columns
#59808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44523:
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#59809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44524:
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44525:
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L

WARNING: line length of 121 exceeds 100 columns
#59811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44526:
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L

WARNING: line length of 113 exceeds 100 columns
#59812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44527:
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#59813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44528:
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc

WARNING: line length of 121 exceeds 100 columns
#59814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44529:
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44530:
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44531:
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44532:
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc

WARNING: line length of 121 exceeds 100 columns
#59818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44533:
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44534:
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44535:
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44536:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#59822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44537:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#59823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44538:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#59824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44539:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9

WARNING: line length of 113 exceeds 100 columns
#59825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44540:
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa

WARNING: line length of 113 exceeds 100 columns
#59826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44541:
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#59827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44542:
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#59828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44543:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#59829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44544:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#59830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44545:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#59831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44546:
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#59832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44547:
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44548:
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L

WARNING: line length of 113 exceeds 100 columns
#59834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44549:
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#59835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44550:
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc

WARNING: line length of 114 exceeds 100 columns
#59836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44551:
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#59837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44552:
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44553:
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L

WARNING: line length of 121 exceeds 100 columns
#59839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44554:
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L

WARNING: line length of 113 exceeds 100 columns
#59840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44555:
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#59841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44556:
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc

WARNING: line length of 121 exceeds 100 columns
#59842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44557:
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44558:
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44559:
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44560:
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc

WARNING: line length of 121 exceeds 100 columns
#59846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44561:
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44562:
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44563:
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44564:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#59850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44565:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#59851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44566:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#59852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44567:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9

WARNING: line length of 113 exceeds 100 columns
#59853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44568:
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa

WARNING: line length of 113 exceeds 100 columns
#59854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44569:
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#59855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44570:
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#59856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44571:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#59857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44572:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#59858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44573:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#59859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44574:
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#59860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44575:
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44576:
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L

WARNING: line length of 113 exceeds 100 columns
#59862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44577:
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#59863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44578:
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc

WARNING: line length of 114 exceeds 100 columns
#59864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44579:
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#59865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44580:
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44581:
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L

WARNING: line length of 121 exceeds 100 columns
#59867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44582:
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L

WARNING: line length of 113 exceeds 100 columns
#59868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44583:
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#59869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44584:
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc

WARNING: line length of 121 exceeds 100 columns
#59870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44585:
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44586:
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44587:
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44588:
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc

WARNING: line length of 121 exceeds 100 columns
#59874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44589:
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44590:
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44591:
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44592:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5

WARNING: line length of 113 exceeds 100 columns
#59878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44593:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#59879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44594:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#59880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44595:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9

WARNING: line length of 113 exceeds 100 columns
#59881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44596:
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa

WARNING: line length of 113 exceeds 100 columns
#59882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44597:
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb

WARNING: line length of 121 exceeds 100 columns
#59883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44598:
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#59884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44599:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#59885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44600:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#59886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44601:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#59887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44602:
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#59888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44603:
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L

WARNING: line length of 121 exceeds 100 columns
#59889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44604:
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L

WARNING: line length of 113 exceeds 100 columns
#59890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44605:
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#59891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44606:
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc

WARNING: line length of 114 exceeds 100 columns
#59892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44607:
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18

WARNING: line length of 121 exceeds 100 columns
#59893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44608:
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44609:
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L

WARNING: line length of 121 exceeds 100 columns
#59895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44610:
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L

WARNING: line length of 113 exceeds 100 columns
#59896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44611:
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#59897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44612:
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc

WARNING: line length of 121 exceeds 100 columns
#59898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44613:
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44614:
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44615:
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#59901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44616:
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc

WARNING: line length of 121 exceeds 100 columns
#59902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44617:
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL

WARNING: line length of 121 exceeds 100 columns
#59903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44618:
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L

WARNING: line length of 113 exceeds 100 columns
#59904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44619:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#59905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44620:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#59906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44621:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#59907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44622:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3

WARNING: line length of 121 exceeds 100 columns
#59908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44623:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#59909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44624:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#59910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44625:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#59911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44626:
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L

WARNING: line length of 113 exceeds 100 columns
#59912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44627:
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#59913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44628:
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7

WARNING: line length of 121 exceeds 100 columns
#59914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44629:
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#59915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44630:
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L

WARNING: line length of 113 exceeds 100 columns
#59916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44631:
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44632:
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44633:
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44634:
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44635:
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44636:
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44637:
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44638:
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44639:
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44640:
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44641:
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44642:
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44643:
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44644:
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44645:
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44646:
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44647:
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44648:
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44649:
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44650:
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44651:
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44652:
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44653:
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44654:
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44655:
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44656:
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44657:
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44658:
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44659:
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44660:
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44661:
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44662:
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44663:
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44664:
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44665:
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44666:
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44667:
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44668:
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44669:
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44670:
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44671:
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44672:
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44673:
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44674:
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44675:
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44676:
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44677:
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44678:
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44679:
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#59965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44680:
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7

WARNING: line length of 121 exceeds 100 columns
#59966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44681:
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#59967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44682:
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L

WARNING: line length of 113 exceeds 100 columns
#59968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44683:
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44684:
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44685:
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44686:
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44687:
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44688:
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44689:
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44690:
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44691:
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44692:
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44693:
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44694:
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44695:
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44696:
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44697:
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44698:
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44699:
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44700:
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44701:
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44702:
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44703:
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44704:
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44705:
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44706:
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44707:
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44708:
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44709:
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44710:
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#59996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44711:
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#59997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44712:
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#59998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44713:
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#59999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44714:
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44715:
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44716:
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44717:
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44718:
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44719:
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44720:
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44721:
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44722:
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44723:
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44724:
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44725:
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44726:
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44727:
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44728:
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44729:
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44730:
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44731:
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#60017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44732:
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7

WARNING: line length of 121 exceeds 100 columns
#60018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44733:
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44734:
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L

WARNING: line length of 113 exceeds 100 columns
#60020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44735:
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44736:
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44737:
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44738:
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44739:
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44740:
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44741:
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44742:
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44743:
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44744:
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44745:
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44746:
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44747:
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44748:
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44749:
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44750:
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44751:
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44752:
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44753:
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44754:
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44755:
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44756:
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44757:
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44758:
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44759:
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44760:
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44761:
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44762:
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44763:
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44764:
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44765:
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44766:
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44767:
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44768:
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44769:
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44770:
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44771:
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44772:
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44773:
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44774:
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44775:
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44776:
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44777:
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44778:
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44779:
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44780:
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44781:
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44782:
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44783:
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#60069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44784:
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7

WARNING: line length of 121 exceeds 100 columns
#60070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44785:
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44786:
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L

WARNING: line length of 113 exceeds 100 columns
#60072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44787:
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44788:
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44789:
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44790:
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44791:
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44792:
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44793:
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44794:
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44795:
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44796:
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44797:
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44798:
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44799:
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44800:
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44801:
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44802:
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44803:
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44804:
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44805:
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44806:
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44807:
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44808:
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44809:
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44810:
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44811:
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44812:
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44813:
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44814:
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44815:
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44816:
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44817:
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44818:
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44819:
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44820:
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44821:
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44822:
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44823:
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44824:
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44825:
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44826:
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44827:
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44828:
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44829:
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44830:
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44831:
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#60117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44832:
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#60118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44833:
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44834:
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44835:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#60121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44836:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#60122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44837:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#60123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44838:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#60124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44839:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#60125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44840:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#60126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44841:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#60127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44842:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#60128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44843:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#60129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44844:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#60130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44845:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#60131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44846:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#60132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44847:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#60133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44848:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#60134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44849:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#60135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44850:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44851:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#60137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44852:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#60138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44853:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44854:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#60140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44855:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#60141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44856:
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#60142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44857:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#60143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44858:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#60144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44859:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#60145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44860:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#60146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44861:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#60147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44862:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44863:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44864:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#60150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44865:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#60151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44866:
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#60152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44867:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#60153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44868:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#60154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44869:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#60155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44870:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#60156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44871:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#60157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44872:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#60158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44873:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#60159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44874:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#60160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44875:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#60161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44876:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#60162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44877:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#60163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44878:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#60164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44879:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#60165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44880:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#60166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44881:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#60167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44882:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#60168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44883:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44884:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44885:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#60171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44886:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#60172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44887:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#60173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44888:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#60174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44889:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#60175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44890:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#60176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44891:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#60177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44892:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#60178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44893:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#60179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44894:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#60180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44895:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#60181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44896:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#60182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44897:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#60183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44898:
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#60184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44899:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#60185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44900:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#60186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44901:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#60187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44902:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#60188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44903:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#60189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44904:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#60190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44905:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44906:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#60192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44907:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#60193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44908:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#60194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44909:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#60195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44910:
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44911:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#60197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44912:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#60198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44913:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#60199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44914:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#60200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44915:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44916:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44917:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#60203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44918:
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#60204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44919:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#60205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44920:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#60206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44921:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#60207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44922:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#60208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44923:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#60209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44924:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#60210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44925:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#60211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44926:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#60212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44927:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#60213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44928:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#60214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44929:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#60215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44930:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#60216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44931:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#60217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44932:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#60218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44933:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#60219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44934:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#60220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44935:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#60221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44936:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44937:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44938:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44939:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#60225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44940:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44941:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#60227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44942:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#60228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44943:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#60229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44944:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44945:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#60231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44946:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#60232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44947:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#60233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44948:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44949:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#60235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44950:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#60236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44951:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#60237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44952:
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44953:
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#60239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44954:
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44955:
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#60241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44956:
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#60242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44957:
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44958:
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#60244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44959:
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#60245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44960:
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44961:
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd

WARNING: line length of 114 exceeds 100 columns
#60247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44962:
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10

WARNING: line length of 114 exceeds 100 columns
#60248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44963:
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18

WARNING: line length of 121 exceeds 100 columns
#60249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44964:
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L

WARNING: line length of 121 exceeds 100 columns
#60250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44965:
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#60251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44966:
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L

WARNING: line length of 113 exceeds 100 columns
#60252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44967:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#60253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44968:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#60254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44969:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#60255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44970:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#60256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44971:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#60257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44972:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#60258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44973:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44974:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44975:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#60261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44976:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44977:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44978:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L

WARNING: line length of 113 exceeds 100 columns
#60264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44979:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#60265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44980:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#60266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44981:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb

WARNING: line length of 114 exceeds 100 columns
#60267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44982:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#60268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44983:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18

WARNING: line length of 121 exceeds 100 columns
#60269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44984:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#60270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44985:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L

WARNING: line length of 121 exceeds 100 columns
#60271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44986:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L

WARNING: line length of 121 exceeds 100 columns
#60272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44987:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44988:
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#60274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44989:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#60275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44990:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#60276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44991:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf

WARNING: line length of 114 exceeds 100 columns
#60277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44992:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#60278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44993:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#60279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44994:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L

WARNING: line length of 121 exceeds 100 columns
#60280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44995:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L

WARNING: line length of 121 exceeds 100 columns
#60281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44996:
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L

WARNING: line length of 113 exceeds 100 columns
#60282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44997:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#60283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44998:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1

WARNING: line length of 113 exceeds 100 columns
#60284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:44999:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2

WARNING: line length of 113 exceeds 100 columns
#60285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45000:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3

WARNING: line length of 113 exceeds 100 columns
#60286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45001:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6

WARNING: line length of 113 exceeds 100 columns
#60287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45002:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#60288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45003:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#60289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45004:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#60290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45005:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18

WARNING: line length of 114 exceeds 100 columns
#60291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45006:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c

WARNING: line length of 121 exceeds 100 columns
#60292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45007:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45008:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45009:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45010:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L

WARNING: line length of 121 exceeds 100 columns
#60296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45011:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L

WARNING: line length of 121 exceeds 100 columns
#60297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45012:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#60298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45013:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#60299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45014:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#60300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45015:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#60301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45016:
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L

WARNING: line length of 113 exceeds 100 columns
#60302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45017:
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#60303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45018:
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4

WARNING: line length of 114 exceeds 100 columns
#60304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45019:
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#60305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45020:
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#60306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45021:
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#60307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45022:
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#60308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45023:
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#60309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45024:
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45025:
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#60311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45026:
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#60312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45027:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#60313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45028:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#60314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45029:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#60315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45030:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc

WARNING: line length of 114 exceeds 100 columns
#60316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45031:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10

WARNING: line length of 121 exceeds 100 columns
#60317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45032:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45033:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45034:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45035:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#60321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45036:
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45037:
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#60323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45038:
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#60324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45039:
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#60325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45040:
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45041:
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0

WARNING: line length of 114 exceeds 100 columns
#60327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45042:
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#60328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45043:
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#60329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45044:
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#60330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45045:
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#60331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45046:
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45047:
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#60333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45048:
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45049:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#60335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45050:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#60336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45051:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#60337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45052:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc

WARNING: line length of 114 exceeds 100 columns
#60338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45053:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#60339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45054:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14

WARNING: line length of 121 exceeds 100 columns
#60340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45055:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#60341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45056:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#60342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45057:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#60343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45058:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#60344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45059:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#60345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45060:
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L

WARNING: line length of 113 exceeds 100 columns
#60346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45061:
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#60347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45062:
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8

WARNING: line length of 121 exceeds 100 columns
#60348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45063:
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45064:
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L

WARNING: line length of 113 exceeds 100 columns
#60350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45065:
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#60351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45066:
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8

WARNING: line length of 114 exceeds 100 columns
#60352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45067:
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18

WARNING: line length of 114 exceeds 100 columns
#60353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45068:
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#60354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45069:
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45070:
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45071:
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45072:
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L

WARNING: line length of 113 exceeds 100 columns
#60358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45073:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#60359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45074:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4

WARNING: line length of 113 exceeds 100 columns
#60360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45075:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb

WARNING: line length of 113 exceeds 100 columns
#60361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45076:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#60362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45077:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe

WARNING: line length of 114 exceeds 100 columns
#60363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45078:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17

WARNING: line length of 114 exceeds 100 columns
#60364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45079:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18

WARNING: line length of 114 exceeds 100 columns
#60365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45080:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#60366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45081:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e

WARNING: line length of 121 exceeds 100 columns
#60367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45082:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45083:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45084:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#60370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45085:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45086:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L

WARNING: line length of 121 exceeds 100 columns
#60372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45087:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L

WARNING: line length of 121 exceeds 100 columns
#60373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45088:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45089:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#60375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45090:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L

WARNING: line length of 113 exceeds 100 columns
#60376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45091:
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6

WARNING: line length of 113 exceeds 100 columns
#60377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45092:
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7

WARNING: line length of 121 exceeds 100 columns
#60378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45093:
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L

WARNING: line length of 121 exceeds 100 columns
#60379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45094:
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L

WARNING: line length of 113 exceeds 100 columns
#60380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45095:
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#60381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45096:
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L

WARNING: line length of 113 exceeds 100 columns
#60382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45097:
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#60383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45098:
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4

WARNING: line length of 113 exceeds 100 columns
#60384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45099:
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8

WARNING: line length of 121 exceeds 100 columns
#60385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45100:
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45101:
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#60387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45102:
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L

WARNING: line length of 113 exceeds 100 columns
#60388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45103:
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#60389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45104:
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#60390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45105:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#60391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45106:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#60392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45107:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#60393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45108:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#60394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45109:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#60395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45110:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#60396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45111:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45112:
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#60398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45113:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#60399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45114:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#60400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45115:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2

WARNING: line length of 113 exceeds 100 columns
#60401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45116:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#60402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45117:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4

WARNING: line length of 113 exceeds 100 columns
#60403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45118:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#60404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45119:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#60405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45120:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7

WARNING: line length of 113 exceeds 100 columns
#60406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45121:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#60407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45122:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9

WARNING: line length of 113 exceeds 100 columns
#60408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45123:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#60409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45124:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#60410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45125:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#60411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45126:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#60412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45127:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe

WARNING: line length of 114 exceeds 100 columns
#60413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45128:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#60414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45129:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#60415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45130:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#60416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45131:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#60417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45132:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14

WARNING: line length of 114 exceeds 100 columns
#60418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45133:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15

WARNING: line length of 114 exceeds 100 columns
#60419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45134:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16

WARNING: line length of 114 exceeds 100 columns
#60420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45135:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#60421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45136:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#60422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45137:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19

WARNING: line length of 114 exceeds 100 columns
#60423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45138:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#60424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45139:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b

WARNING: line length of 114 exceeds 100 columns
#60425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45140:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#60426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45141:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d

WARNING: line length of 114 exceeds 100 columns
#60427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45142:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e

WARNING: line length of 121 exceeds 100 columns
#60428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45143:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45144:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45145:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45146:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#60432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45147:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45148:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#60434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45149:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#60435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45150:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#60436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45151:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45152:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#60438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45153:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#60439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45154:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#60440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45155:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45156:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#60442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45157:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#60443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45158:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45159:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#60445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45160:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#60446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45161:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#60447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45162:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#60448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45163:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#60449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45164:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L

WARNING: line length of 121 exceeds 100 columns
#60450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45165:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#60451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45166:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45167:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L

WARNING: line length of 121 exceeds 100 columns
#60453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45168:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#60454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45169:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L

WARNING: line length of 121 exceeds 100 columns
#60455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45170:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#60456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45171:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#60457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45172:
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L

WARNING: line length of 113 exceeds 100 columns
#60458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45173:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#60459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45174:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#60460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45175:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#60461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45176:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#60462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45177:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#60463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45178:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5

WARNING: line length of 113 exceeds 100 columns
#60464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45179:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#60465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45180:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#60466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45181:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#60467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45182:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9

WARNING: line length of 113 exceeds 100 columns
#60468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45183:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa

WARNING: line length of 113 exceeds 100 columns
#60469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45184:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#60470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45185:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc

WARNING: line length of 113 exceeds 100 columns
#60471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45186:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd

WARNING: line length of 113 exceeds 100 columns
#60472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45187:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe

WARNING: line length of 114 exceeds 100 columns
#60473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45188:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10

WARNING: line length of 114 exceeds 100 columns
#60474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45189:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#60475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45190:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12

WARNING: line length of 114 exceeds 100 columns
#60476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45191:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#60477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45192:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#60478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45193:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15

WARNING: line length of 114 exceeds 100 columns
#60479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45194:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16

WARNING: line length of 114 exceeds 100 columns
#60480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45195:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17

WARNING: line length of 114 exceeds 100 columns
#60481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45196:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18

WARNING: line length of 114 exceeds 100 columns
#60482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45197:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19

WARNING: line length of 114 exceeds 100 columns
#60483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45198:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a

WARNING: line length of 114 exceeds 100 columns
#60484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45199:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#60485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45200:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c

WARNING: line length of 114 exceeds 100 columns
#60486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45201:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d

WARNING: line length of 114 exceeds 100 columns
#60487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45202:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e

WARNING: line length of 121 exceeds 100 columns
#60488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45203:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45204:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45205:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45206:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#60492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45207:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45208:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#60494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45209:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#60495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45210:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#60496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45211:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45212:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#60498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45213:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#60499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45214:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#60500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45215:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45216:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#60502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45217:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#60503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45218:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45219:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#60505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45220:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L

WARNING: line length of 121 exceeds 100 columns
#60506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45221:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#60507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45222:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#60508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45223:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L

WARNING: line length of 121 exceeds 100 columns
#60509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45224:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L

WARNING: line length of 121 exceeds 100 columns
#60510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45225:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L

WARNING: line length of 121 exceeds 100 columns
#60511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45226:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45227:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L

WARNING: line length of 121 exceeds 100 columns
#60513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45228:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#60514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45229:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#60515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45230:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L

WARNING: line length of 121 exceeds 100 columns
#60516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45231:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#60517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45232:
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L

WARNING: line length of 113 exceeds 100 columns
#60518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45233:
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#60519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45234:
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#60520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45235:
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#60521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45236:
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45237:
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45238:
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#60524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45239:
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#60525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45240:
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#60526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45241:
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8

WARNING: line length of 121 exceeds 100 columns
#60527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45242:
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45243:
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45244:
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#60530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45245:
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#60531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45246:
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL

WARNING: line length of 113 exceeds 100 columns
#60532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45247:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#60533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45248:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8

WARNING: line length of 114 exceeds 100 columns
#60534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45249:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10

WARNING: line length of 114 exceeds 100 columns
#60535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45250:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18

WARNING: line length of 121 exceeds 100 columns
#60536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45251:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#60537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45252:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#60538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45253:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45254:
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#60540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45255:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#60541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45256:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8

WARNING: line length of 114 exceeds 100 columns
#60542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45257:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10

WARNING: line length of 114 exceeds 100 columns
#60543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45258:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#60544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45259:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#60545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45260:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#60546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45261:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45262:
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#60548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45263:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#60549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45264:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#60550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45265:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc

WARNING: line length of 114 exceeds 100 columns
#60551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45266:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10

WARNING: line length of 121 exceeds 100 columns
#60552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45267:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#60553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45268:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#60554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45269:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45270:
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L

WARNING: line length of 113 exceeds 100 columns
#60556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45271:
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#60557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45272:
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#60558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45273:
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8

WARNING: line length of 113 exceeds 100 columns
#60559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45274:
+#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc

WARNING: line length of 113 exceeds 100 columns
#60560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45275:
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd

WARNING: line length of 114 exceeds 100 columns
#60561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45276:
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#60562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45277:
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#60563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45278:
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18

WARNING: line length of 114 exceeds 100 columns
#60564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45279:
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19

WARNING: line length of 121 exceeds 100 columns
#60565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45280:
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L

WARNING: line length of 121 exceeds 100 columns
#60566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45281:
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45282:
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45283:
+#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45284:
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#60570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45285:
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45286:
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L

WARNING: line length of 121 exceeds 100 columns
#60572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45287:
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45288:
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L

WARNING: line length of 113 exceeds 100 columns
#60574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45289:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#60575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45290:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4

WARNING: line length of 113 exceeds 100 columns
#60576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45291:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8

WARNING: line length of 113 exceeds 100 columns
#60577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45292:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#60578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45293:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45294:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45295:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L

WARNING: line length of 121 exceeds 100 columns
#60581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45296:
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L

WARNING: line length of 113 exceeds 100 columns
#60582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45297:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#60583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45298:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#60584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45299:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#60585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45300:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5

WARNING: line length of 113 exceeds 100 columns
#60586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45301:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8

WARNING: line length of 113 exceeds 100 columns
#60587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45302:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9

WARNING: line length of 113 exceeds 100 columns
#60588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45303:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc

WARNING: line length of 113 exceeds 100 columns
#60589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45304:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd

WARNING: line length of 114 exceeds 100 columns
#60590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45305:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#60591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45306:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11

WARNING: line length of 114 exceeds 100 columns
#60592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45307:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12

WARNING: line length of 114 exceeds 100 columns
#60593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45308:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13

WARNING: line length of 114 exceeds 100 columns
#60594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45309:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14

WARNING: line length of 114 exceeds 100 columns
#60595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45310:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15

WARNING: line length of 114 exceeds 100 columns
#60596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45311:
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#60597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45312:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45313:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45314:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45315:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#60601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45316:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45317:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#60603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45318:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45319:
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#60605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45320:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45321:
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#60607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45322:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#60608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45323:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#60609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45324:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L

WARNING: line length of 121 exceeds 100 columns
#60610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45325:
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L

WARNING: line length of 121 exceeds 100 columns
#60611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45326:
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#60612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45327:
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0

WARNING: line length of 121 exceeds 100 columns
#60613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45328:
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L

WARNING: line length of 113 exceeds 100 columns
#60614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45329:
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#60615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45330:
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L

WARNING: line length of 113 exceeds 100 columns
#60616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45331:
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#60617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45332:
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L

WARNING: line length of 113 exceeds 100 columns
#60618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45333:
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#60619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45334:
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L

WARNING: line length of 113 exceeds 100 columns
#60620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45335:
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#60621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45336:
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L

WARNING: line length of 113 exceeds 100 columns
#60622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45337:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#60623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45338:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#60624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45339:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc

WARNING: line length of 113 exceeds 100 columns
#60625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45340:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf

WARNING: line length of 114 exceeds 100 columns
#60626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45341:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#60627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45342:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#60628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45343:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17

WARNING: line length of 114 exceeds 100 columns
#60629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45344:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18

WARNING: line length of 114 exceeds 100 columns
#60630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45345:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#60631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45346:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a

WARNING: line length of 114 exceeds 100 columns
#60632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45347:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d

WARNING: line length of 121 exceeds 100 columns
#60633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45348:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#60634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45349:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#60635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45350:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L

WARNING: line length of 121 exceeds 100 columns
#60636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45351:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L

WARNING: line length of 121 exceeds 100 columns
#60637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45352:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45353:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#60639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45354:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L

WARNING: line length of 121 exceeds 100 columns
#60640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45355:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45356:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#60642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45357:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L

WARNING: line length of 121 exceeds 100 columns
#60643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45358:
+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#60644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45359:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#60645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45360:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#60646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45361:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3

WARNING: line length of 113 exceeds 100 columns
#60647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45362:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#60648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45363:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d

WARNING: line length of 121 exceeds 100 columns
#60649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45364:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45365:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45366:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L

WARNING: line length of 121 exceeds 100 columns
#60652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45367:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L

WARNING: line length of 121 exceeds 100 columns
#60653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45368:
+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#60654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45369:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#60655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45370:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#60656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45371:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4

WARNING: line length of 113 exceeds 100 columns
#60657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45372:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#60658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45373:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#60659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45374:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#60660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45375:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#60661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45376:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe

WARNING: line length of 114 exceeds 100 columns
#60662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45377:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#60663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45378:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12

WARNING: line length of 114 exceeds 100 columns
#60664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45379:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14

WARNING: line length of 114 exceeds 100 columns
#60665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45380:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16

WARNING: line length of 114 exceeds 100 columns
#60666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45381:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18

WARNING: line length of 114 exceeds 100 columns
#60667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45382:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#60668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45383:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#60669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45384:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e

WARNING: line length of 121 exceeds 100 columns
#60670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45385:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45386:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45387:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L

WARNING: line length of 121 exceeds 100 columns
#60673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45388:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#60674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45389:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L

WARNING: line length of 121 exceeds 100 columns
#60675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45390:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#60676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45391:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L

WARNING: line length of 121 exceeds 100 columns
#60677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45392:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#60678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45393:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L

WARNING: line length of 121 exceeds 100 columns
#60679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45394:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L

WARNING: line length of 121 exceeds 100 columns
#60680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45395:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L

WARNING: line length of 121 exceeds 100 columns
#60681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45396:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L

WARNING: line length of 121 exceeds 100 columns
#60682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45397:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L

WARNING: line length of 121 exceeds 100 columns
#60683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45398:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L

WARNING: line length of 121 exceeds 100 columns
#60684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45399:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L

WARNING: line length of 121 exceeds 100 columns
#60685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45400:
+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L

WARNING: line length of 113 exceeds 100 columns
#60686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45401:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#60687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45402:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8

WARNING: line length of 114 exceeds 100 columns
#60688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45403:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c

WARNING: line length of 114 exceeds 100 columns
#60689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45404:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d

WARNING: line length of 114 exceeds 100 columns
#60690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45405:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e

WARNING: line length of 114 exceeds 100 columns
#60691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45406:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f

WARNING: line length of 121 exceeds 100 columns
#60692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45407:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45408:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L

WARNING: line length of 121 exceeds 100 columns
#60694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45409:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L

WARNING: line length of 121 exceeds 100 columns
#60695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45410:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L

WARNING: line length of 121 exceeds 100 columns
#60696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45411:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L

WARNING: line length of 121 exceeds 100 columns
#60697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45412:
+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45413:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#60699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45414:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#60700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45415:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2

WARNING: line length of 113 exceeds 100 columns
#60701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45416:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa

WARNING: line length of 121 exceeds 100 columns
#60702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45417:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45418:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45419:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL

WARNING: line length of 121 exceeds 100 columns
#60705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45420:
+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L

WARNING: line length of 113 exceeds 100 columns
#60706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45421:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#60707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45422:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1

WARNING: line length of 113 exceeds 100 columns
#60708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45423:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2

WARNING: line length of 113 exceeds 100 columns
#60709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45424:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3

WARNING: line length of 113 exceeds 100 columns
#60710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45425:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#60711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45426:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5

WARNING: line length of 113 exceeds 100 columns
#60712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45427:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6

WARNING: line length of 113 exceeds 100 columns
#60713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45428:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7

WARNING: line length of 113 exceeds 100 columns
#60714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45429:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8

WARNING: line length of 113 exceeds 100 columns
#60715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45430:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#60716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45431:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#60717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45432:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb

WARNING: line length of 113 exceeds 100 columns
#60718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45433:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc

WARNING: line length of 113 exceeds 100 columns
#60719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45434:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd

WARNING: line length of 113 exceeds 100 columns
#60720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45435:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#60721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45436:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf

WARNING: line length of 114 exceeds 100 columns
#60722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45437:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10

WARNING: line length of 121 exceeds 100 columns
#60723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45438:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45439:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45440:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45441:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L

WARNING: line length of 121 exceeds 100 columns
#60727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45442:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#60728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45443:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#60729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45444:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L

WARNING: line length of 121 exceeds 100 columns
#60730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45445:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#60731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45446:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45447:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#60733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45448:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#60734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45449:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L

WARNING: line length of 121 exceeds 100 columns
#60735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45450:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45451:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#60737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45452:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#60738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45453:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L

WARNING: line length of 121 exceeds 100 columns
#60739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45454:
+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45455:
+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#60741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45456:
+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45457:
+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0

WARNING: line length of 114 exceeds 100 columns
#60743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45458:
+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d

WARNING: line length of 121 exceeds 100 columns
#60744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45459:
+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#60745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45460:
+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L

WARNING: line length of 113 exceeds 100 columns
#60746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45461:
+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#60747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45462:
+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45463:
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#60749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45464:
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#60750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45465:
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#60751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45466:
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#60752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45467:
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#60753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45468:
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#60754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45469:
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#60755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45470:
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#60756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45471:
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#60757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45472:
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#60758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45473:
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#60759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45474:
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#60760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45475:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#60761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45476:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#60762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45477:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#60763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45478:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3

WARNING: line length of 114 exceeds 100 columns
#60764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45479:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#60765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45480:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45481:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45482:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45483:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#60769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45484:
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#60770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45485:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#60771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45486:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#60772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45487:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8

WARNING: line length of 117 exceeds 100 columns
#60773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45488:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#60774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45489:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#60775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45490:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45491:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45492:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L

WARNING: line length of 122 exceeds 100 columns
#60778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45493:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45494:
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45495:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#60781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45496:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#60782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45497:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#60783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45498:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11

WARNING: line length of 114 exceeds 100 columns
#60784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45499:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#60785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45500:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#60786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45501:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45502:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45503:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45504:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L

WARNING: line length of 121 exceeds 100 columns
#60790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45505:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45506:
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45507:
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#60793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45508:
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#60794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45509:
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45510:
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L

WARNING: line length of 113 exceeds 100 columns
#60796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45511:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#60797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45512:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#60798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45513:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#60799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45514:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#60800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45515:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#60801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45516:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#60802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45517:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#60803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45518:
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45519:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#60805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45520:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#60806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45521:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#60807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45522:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#60808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45523:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#60809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45524:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45525:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#60811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45526:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#60812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45527:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#60813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45528:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#60814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45529:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#60815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45530:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45531:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#60817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45532:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#60818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45533:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#60819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45534:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#60820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45535:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#60821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45536:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45537:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#60823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45538:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#60824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45539:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#60825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45540:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#60826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45541:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#60827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45542:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45543:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#60829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45544:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#60830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45545:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#60831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45546:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#60832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45547:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#60833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45548:
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45549:
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#60835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45550:
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#60836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45551:
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#60837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45552:
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#60838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45553:
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#60839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45554:
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45555:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#60841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45556:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#60842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45557:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#60843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45558:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#60844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45559:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#60845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45560:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#60846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45561:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#60847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45562:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#60848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45563:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#60849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45564:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#60850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45565:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#60851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45566:
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45567:
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#60853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45568:
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8

WARNING: line length of 121 exceeds 100 columns
#60854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45569:
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45570:
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#60856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45571:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#60857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45572:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#60858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45573:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#60859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45574:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#60860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45575:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9

WARNING: line length of 113 exceeds 100 columns
#60861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45576:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#60862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45577:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#60863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45578:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18

WARNING: line length of 114 exceeds 100 columns
#60864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45579:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f

WARNING: line length of 121 exceeds 100 columns
#60865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45580:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45581:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45582:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#60868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45583:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45584:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#60870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45585:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#60871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45586:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#60872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45587:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#60873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45588:
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45589:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#60875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45590:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#60876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45591:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc

WARNING: line length of 114 exceeds 100 columns
#60877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45592:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#60878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45593:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#60879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45594:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17

WARNING: line length of 114 exceeds 100 columns
#60880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45595:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#60881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45596:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c

WARNING: line length of 114 exceeds 100 columns
#60882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45597:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d

WARNING: line length of 114 exceeds 100 columns
#60883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45598:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#60884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45599:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#60885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45600:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#60886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45601:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#60887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45602:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#60888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45603:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#60889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45604:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#60890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45605:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#60891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45606:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#60892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45607:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#60893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45608:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#60894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45609:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#60895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45610:
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45611:
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#60897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45612:
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45613:
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#60899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45614:
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#60900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45615:
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#60901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45616:
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#60902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45617:
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0

WARNING: line length of 114 exceeds 100 columns
#60903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45618:
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#60904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45619:
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#60905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45620:
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#60906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45621:
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#60907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45622:
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#60908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45623:
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#60909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45624:
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#60910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45625:
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0

WARNING: line length of 114 exceeds 100 columns
#60911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45626:
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#60912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45627:
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#60913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45628:
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#60914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45629:
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#60915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45630:
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45631:
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#60917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45632:
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45633:
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#60919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45634:
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45635:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#60921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45636:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#60922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45637:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#60923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45638:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#60924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45639:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#60925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45640:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45641:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45642:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#60928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45643:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45644:
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45645:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#60931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45646:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#60932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45647:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#60933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45648:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#60934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45649:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#60935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45650:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#60936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45651:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#60937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45652:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#60938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45653:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#60939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45654:
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#60940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45655:
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#60941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45656:
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45657:
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#60943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45658:
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45659:
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#60945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45660:
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45661:
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#60947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45662:
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45663:
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#60949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45664:
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45665:
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45666:
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45667:
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45668:
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45669:
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45670:
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45671:
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45672:
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45673:
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45674:
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45675:
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45676:
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45677:
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45678:
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45679:
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45680:
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45681:
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#60967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45682:
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45683:
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45684:
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45685:
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45686:
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45687:
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45688:
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45689:
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45690:
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45691:
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45692:
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45693:
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45694:
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45695:
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45696:
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45697:
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45698:
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45699:
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45700:
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45701:
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45702:
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45703:
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45704:
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45705:
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45706:
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45707:
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45708:
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45709:
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45710:
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#60996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45711:
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#60997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45712:
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL

WARNING: line length of 114 exceeds 100 columns
#60998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45713:
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#60999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45714:
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45715:
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#61001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45716:
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45717:
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#61003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45718:
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45719:
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#61005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45720:
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45721:
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#61007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45722:
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45723:
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#61009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45724:
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45725:
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#61011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45726:
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45727:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45728:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#61014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45729:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#61015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45730:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3

WARNING: line length of 114 exceeds 100 columns
#61016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45731:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#61017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45732:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45733:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45734:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45735:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#61021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45736:
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#61022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45737:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#61023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45738:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#61024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45739:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8

WARNING: line length of 117 exceeds 100 columns
#61025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45740:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#61026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45741:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#61027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45742:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45743:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45744:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L

WARNING: line length of 122 exceeds 100 columns
#61030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45745:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45746:
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45747:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#61033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45748:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#61034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45749:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#61035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45750:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11

WARNING: line length of 114 exceeds 100 columns
#61036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45751:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#61037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45752:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45753:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45754:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45755:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#61041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45756:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L

WARNING: line length of 121 exceeds 100 columns
#61042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45757:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#61043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45758:
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45759:
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#61045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45760:
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#61046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45761:
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45762:
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L

WARNING: line length of 113 exceeds 100 columns
#61048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45763:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#61049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45764:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#61050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45765:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#61051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45766:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#61052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45767:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#61053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45768:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#61054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45769:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#61055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45770:
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45771:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45772:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45773:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45774:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45775:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45776:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45777:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45778:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45779:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45780:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45781:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45782:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45783:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45784:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45785:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45786:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45787:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45788:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45789:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45790:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45791:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45792:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45793:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45794:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45795:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45796:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45797:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45798:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45799:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45800:
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45801:
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#61087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45802:
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#61088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45803:
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45804:
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45805:
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45806:
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45807:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#61093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45808:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#61094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45809:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#61095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45810:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#61096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45811:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#61097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45812:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45813:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45814:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45815:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#61101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45816:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#61102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45817:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45818:
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45819:
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#61105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45820:
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8

WARNING: line length of 121 exceeds 100 columns
#61106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45821:
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45822:
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#61108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45823:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#61109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45824:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#61110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45825:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#61111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45826:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#61112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45827:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9

WARNING: line length of 113 exceeds 100 columns
#61113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45828:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#61114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45829:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#61115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45830:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18

WARNING: line length of 114 exceeds 100 columns
#61116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45831:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45832:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45833:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45834:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45835:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45836:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#61122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45837:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#61123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45838:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#61124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45839:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#61125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45840:
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45841:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#61127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45842:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#61128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45843:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc

WARNING: line length of 114 exceeds 100 columns
#61129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45844:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#61130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45845:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#61131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45846:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17

WARNING: line length of 114 exceeds 100 columns
#61132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45847:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#61133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45848:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c

WARNING: line length of 114 exceeds 100 columns
#61134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45849:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d

WARNING: line length of 114 exceeds 100 columns
#61135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45850:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#61136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45851:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#61137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45852:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#61138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45853:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45854:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#61140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45855:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#61141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45856:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#61142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45857:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#61143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45858:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#61144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45859:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#61145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45860:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#61146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45861:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45862:
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45863:
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#61149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45864:
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45865:
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#61151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45866:
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#61152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45867:
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45868:
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#61154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45869:
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0

WARNING: line length of 114 exceeds 100 columns
#61155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45870:
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#61156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45871:
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45872:
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#61158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45873:
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#61159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45874:
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#61160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45875:
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#61161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45876:
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#61162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45877:
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0

WARNING: line length of 114 exceeds 100 columns
#61163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45878:
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#61164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45879:
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#61165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45880:
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45881:
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45882:
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45883:
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45884:
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45885:
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45886:
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45887:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45888:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#61174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45889:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#61175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45890:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#61176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45891:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#61177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45892:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45893:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45894:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#61180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45895:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45896:
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45897:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45898:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#61184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45899:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#61185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45900:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#61186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45901:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#61187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45902:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45903:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45904:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#61190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45905:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45906:
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45907:
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45908:
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45909:
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45910:
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45911:
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#61197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45912:
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45913:
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45914:
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45915:
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45916:
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45917:
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45918:
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45919:
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45920:
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45921:
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45922:
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45923:
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45924:
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45925:
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45926:
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45927:
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45928:
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45929:
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45930:
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45931:
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45932:
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45933:
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45934:
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45935:
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45936:
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45937:
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45938:
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45939:
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45940:
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45941:
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45942:
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45943:
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45944:
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45945:
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45946:
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45947:
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45948:
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45949:
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45950:
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45951:
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45952:
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45953:
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45954:
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45955:
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45956:
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45957:
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45958:
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45959:
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45960:
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45961:
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45962:
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45963:
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45964:
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL

WARNING: line length of 114 exceeds 100 columns
#61250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45965:
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#61251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45966:
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45967:
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#61253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45968:
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45969:
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#61255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45970:
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45971:
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#61257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45972:
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45973:
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#61259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45974:
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45975:
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#61261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45976:
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45977:
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#61263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45978:
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45979:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45980:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#61266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45981:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#61267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45982:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3

WARNING: line length of 114 exceeds 100 columns
#61268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45983:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#61269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45984:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45985:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45986:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45987:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#61273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45988:
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#61274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45989:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#61275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45990:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#61276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45991:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8

WARNING: line length of 117 exceeds 100 columns
#61277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45992:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#61278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45993:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#61279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45994:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45995:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45996:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L

WARNING: line length of 122 exceeds 100 columns
#61282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45997:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45998:
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:45999:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#61285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46000:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#61286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46001:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#61287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46002:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11

WARNING: line length of 114 exceeds 100 columns
#61288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46003:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#61289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46004:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46005:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46006:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46007:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#61293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46008:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L

WARNING: line length of 121 exceeds 100 columns
#61294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46009:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#61295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46010:
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46011:
+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#61297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46012:
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#61298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46013:
+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46014:
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L

WARNING: line length of 113 exceeds 100 columns
#61300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46015:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#61301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46016:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#61302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46017:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#61303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46018:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#61304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46019:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#61305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46020:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#61306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46021:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#61307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46022:
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46023:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46024:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46025:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46026:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46027:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46028:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46029:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46030:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46031:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46032:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46033:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46034:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46035:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46036:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46037:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46038:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46039:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46040:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46041:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46042:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46043:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46044:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46045:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46046:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46047:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46048:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46049:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46050:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46051:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46052:
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46053:
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#61339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46054:
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#61340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46055:
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46056:
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46057:
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46058:
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46059:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#61345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46060:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#61346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46061:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#61347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46062:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#61348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46063:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#61349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46064:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46065:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46066:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46067:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#61353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46068:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#61354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46069:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46070:
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46071:
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#61357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46072:
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8

WARNING: line length of 121 exceeds 100 columns
#61358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46073:
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46074:
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#61360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46075:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#61361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46076:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#61362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46077:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#61363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46078:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#61364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46079:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9

WARNING: line length of 113 exceeds 100 columns
#61365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46080:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#61366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46081:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#61367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46082:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18

WARNING: line length of 114 exceeds 100 columns
#61368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46083:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46084:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46085:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46086:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46087:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46088:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#61374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46089:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#61375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46090:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#61376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46091:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#61377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46092:
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46093:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#61379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46094:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#61380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46095:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc

WARNING: line length of 114 exceeds 100 columns
#61381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46096:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#61382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46097:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#61383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46098:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17

WARNING: line length of 114 exceeds 100 columns
#61384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46099:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#61385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46100:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c

WARNING: line length of 114 exceeds 100 columns
#61386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46101:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d

WARNING: line length of 114 exceeds 100 columns
#61387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46102:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#61388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46103:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#61389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46104:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#61390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46105:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46106:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#61392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46107:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#61393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46108:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#61394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46109:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#61395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46110:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#61396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46111:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#61397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46112:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#61398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46113:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46114:
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46115:
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#61401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46116:
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46117:
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#61403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46118:
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#61404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46119:
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46120:
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#61406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46121:
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0

WARNING: line length of 114 exceeds 100 columns
#61407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46122:
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#61408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46123:
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46124:
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#61410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46125:
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#61411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46126:
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#61412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46127:
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#61413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46128:
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#61414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46129:
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0

WARNING: line length of 114 exceeds 100 columns
#61415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46130:
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#61416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46131:
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#61417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46132:
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46133:
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46134:
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46135:
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46136:
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46137:
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46138:
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46139:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46140:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#61426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46141:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#61427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46142:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#61428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46143:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#61429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46144:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46145:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46146:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#61432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46147:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46148:
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46149:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46150:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#61436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46151:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#61437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46152:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#61438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46153:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#61439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46154:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46155:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46156:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#61442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46157:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46158:
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46159:
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46160:
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46161:
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46162:
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46163:
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#61449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46164:
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46165:
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46166:
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46167:
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46168:
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46169:
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46170:
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46171:
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46172:
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46173:
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46174:
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46175:
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46176:
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46177:
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46178:
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46179:
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46180:
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46181:
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46182:
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46183:
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46184:
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46185:
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46186:
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46187:
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46188:
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46189:
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46190:
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46191:
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46192:
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46193:
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46194:
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46195:
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46196:
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46197:
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46198:
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46199:
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46200:
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46201:
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46202:
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46203:
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46204:
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46205:
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46206:
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46207:
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46208:
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46209:
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46210:
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46211:
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46212:
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46213:
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46214:
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46215:
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46216:
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL

WARNING: line length of 114 exceeds 100 columns
#61502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46217:
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#61503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46218:
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46219:
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#61505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46220:
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46221:
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#61507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46222:
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46223:
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#61509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46224:
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46225:
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0

WARNING: line length of 121 exceeds 100 columns
#61511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46226:
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46227:
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#61513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46228:
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46229:
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0

WARNING: line length of 121 exceeds 100 columns
#61515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46230:
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46231:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46232:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#61518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46233:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2

WARNING: line length of 113 exceeds 100 columns
#61519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46234:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3

WARNING: line length of 114 exceeds 100 columns
#61520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46235:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#61521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46236:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46237:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46238:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46239:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#61525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46240:
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#61526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46241:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0

WARNING: line length of 113 exceeds 100 columns
#61527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46242:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1

WARNING: line length of 113 exceeds 100 columns
#61528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46243:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8

WARNING: line length of 117 exceeds 100 columns
#61529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46244:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10

WARNING: line length of 114 exceeds 100 columns
#61530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46245:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f

WARNING: line length of 121 exceeds 100 columns
#61531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46246:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46247:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46248:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L

WARNING: line length of 122 exceeds 100 columns
#61534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46249:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46250:
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46251:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#61537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46252:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8

WARNING: line length of 114 exceeds 100 columns
#61538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46253:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10

WARNING: line length of 114 exceeds 100 columns
#61539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46254:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11

WARNING: line length of 114 exceeds 100 columns
#61540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46255:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18

WARNING: line length of 114 exceeds 100 columns
#61541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46256:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46257:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46258:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46259:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L

WARNING: line length of 121 exceeds 100 columns
#61545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46260:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L

WARNING: line length of 121 exceeds 100 columns
#61546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46261:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L

WARNING: line length of 121 exceeds 100 columns
#61547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46262:
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46263:
+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#61549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46264:
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#61550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46265:
+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46266:
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L

WARNING: line length of 113 exceeds 100 columns
#61552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46267:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#61553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46268:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8

WARNING: line length of 114 exceeds 100 columns
#61554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46269:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10

WARNING: line length of 114 exceeds 100 columns
#61555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46270:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#61556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46271:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#61557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46272:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#61558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46273:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#61559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46274:
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46275:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46276:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46277:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46278:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46279:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46280:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46281:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46282:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46283:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46284:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46285:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46286:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46287:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46288:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46289:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46290:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46291:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46292:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46293:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46294:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46295:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46296:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46297:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46298:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46299:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46300:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10

WARNING: line length of 114 exceeds 100 columns
#61586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46301:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#61587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46302:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#61588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46303:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L

WARNING: line length of 121 exceeds 100 columns
#61589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46304:
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46305:
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#61591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46306:
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#61592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46307:
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46308:
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46309:
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46310:
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46311:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#61597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46312:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#61598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46313:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c

WARNING: line length of 114 exceeds 100 columns
#61599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46314:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d

WARNING: line length of 114 exceeds 100 columns
#61600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46315:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e

WARNING: line length of 114 exceeds 100 columns
#61601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46316:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46317:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46318:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46319:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L

WARNING: line length of 121 exceeds 100 columns
#61605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46320:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L

WARNING: line length of 121 exceeds 100 columns
#61606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46321:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46322:
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46323:
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#61609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46324:
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8

WARNING: line length of 121 exceeds 100 columns
#61610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46325:
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46326:
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L

WARNING: line length of 113 exceeds 100 columns
#61612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46327:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#61613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46328:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1

WARNING: line length of 113 exceeds 100 columns
#61614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46329:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#61615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46330:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8

WARNING: line length of 113 exceeds 100 columns
#61616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46331:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9

WARNING: line length of 113 exceeds 100 columns
#61617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46332:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa

WARNING: line length of 114 exceeds 100 columns
#61618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46333:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#61619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46334:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18

WARNING: line length of 114 exceeds 100 columns
#61620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46335:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f

WARNING: line length of 121 exceeds 100 columns
#61621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46336:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46337:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46338:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46339:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46340:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#61626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46341:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#61627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46342:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#61628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46343:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#61629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46344:
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46345:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#61631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46346:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#61632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46347:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc

WARNING: line length of 114 exceeds 100 columns
#61633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46348:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#61634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46349:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14

WARNING: line length of 114 exceeds 100 columns
#61635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46350:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17

WARNING: line length of 114 exceeds 100 columns
#61636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46351:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#61637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46352:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c

WARNING: line length of 114 exceeds 100 columns
#61638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46353:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d

WARNING: line length of 114 exceeds 100 columns
#61639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46354:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e

WARNING: line length of 114 exceeds 100 columns
#61640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46355:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#61641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46356:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#61642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46357:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46358:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#61644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46359:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L

WARNING: line length of 121 exceeds 100 columns
#61645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46360:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#61646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46361:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#61647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46362:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L

WARNING: line length of 121 exceeds 100 columns
#61648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46363:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L

WARNING: line length of 121 exceeds 100 columns
#61649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46364:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L

WARNING: line length of 121 exceeds 100 columns
#61650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46365:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46366:
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46367:
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#61653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46368:
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46369:
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0

WARNING: line length of 114 exceeds 100 columns
#61655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46370:
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#61656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46371:
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46372:
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#61658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46373:
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0

WARNING: line length of 114 exceeds 100 columns
#61659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46374:
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10

WARNING: line length of 121 exceeds 100 columns
#61660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46375:
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46376:
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L

WARNING: line length of 113 exceeds 100 columns
#61662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46377:
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0

WARNING: line length of 114 exceeds 100 columns
#61663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46378:
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18

WARNING: line length of 121 exceeds 100 columns
#61664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46379:
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL

WARNING: line length of 121 exceeds 100 columns
#61665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46380:
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#61666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46381:
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0

WARNING: line length of 114 exceeds 100 columns
#61667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46382:
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#61668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46383:
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f

WARNING: line length of 121 exceeds 100 columns
#61669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46384:
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL

WARNING: line length of 121 exceeds 100 columns
#61670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46385:
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L

WARNING: line length of 121 exceeds 100 columns
#61671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46386:
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46387:
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46388:
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46389:
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46390:
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46391:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46392:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#61678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46393:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#61679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46394:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#61680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46395:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#61681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46396:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46397:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46398:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#61684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46399:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46400:
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46401:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#61687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46402:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#61688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46403:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#61689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46404:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10

WARNING: line length of 114 exceeds 100 columns
#61690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46405:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#61691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46406:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46407:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46408:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#61694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46409:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#61695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46410:
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46411:
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46412:
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46413:
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46414:
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46415:
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0

WARNING: line length of 121 exceeds 100 columns
#61701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46416:
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46417:
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46418:
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46419:
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#61705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46420:
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46421:
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46422:
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46423:
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46424:
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46425:
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46426:
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46427:
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46428:
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46429:
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46430:
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46431:
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46432:
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46433:
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46434:
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46435:
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46436:
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46437:
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#61723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46438:
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46439:
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46440:
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46441:
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46442:
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46443:
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46444:
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46445:
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46446:
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46447:
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46448:
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46449:
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46450:
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46451:
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46452:
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46453:
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46454:
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46455:
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46456:
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46457:
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46458:
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46459:
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46460:
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46461:
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46462:
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46463:
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46464:
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46465:
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46466:
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46467:
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#61753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46468:
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL

WARNING: line length of 114 exceeds 100 columns
#61754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46469:
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#61755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46470:
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46471:
+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY__SHIFT                                              0x0

WARNING: line length of 114 exceeds 100 columns
#61757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46472:
+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD__SHIFT                                               0x14

WARNING: line length of 121 exceeds 100 columns
#61758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46473:
+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY_MASK                                                0x000FFFFFL

WARNING: line length of 121 exceeds 100 columns
#61759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46474:
+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD_MASK                                                 0xFFF00000L

WARNING: line length of 113 exceeds 100 columns
#61760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46475:
+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#61761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46476:
+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS_MASK                                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#61762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46477:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#61763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46478:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#61764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46479:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                              0x5

WARNING: line length of 114 exceeds 100 columns
#61765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46480:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#61766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46481:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR__SHIFT                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#61767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46482:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46483:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                0x00000006L

WARNING: line length of 121 exceeds 100 columns
#61769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46484:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                0x007FFFE0L

WARNING: line length of 121 exceeds 100 columns
#61770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46485:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#61771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46486:
+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR_MASK                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46487:
+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0

WARNING: line length of 117 exceeds 100 columns
#61773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46488:
+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL

WARNING: line length of 113 exceeds 100 columns
#61774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46489:
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#61775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46490:
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf

WARNING: line length of 117 exceeds 100 columns
#61776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46491:
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL

WARNING: line length of 117 exceeds 100 columns
#61777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46492:
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L

WARNING: line length of 113 exceeds 100 columns
#61778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46493:
+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#61779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46494:
+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1

WARNING: line length of 115 exceeds 100 columns
#61780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46495:
+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L

WARNING: line length of 115 exceeds 100 columns
#61781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46496:
+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L

WARNING: line length of 113 exceeds 100 columns
#61782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46497:
+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0

WARNING: line length of 115 exceeds 100 columns
#61783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46498:
+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L

WARNING: line length of 113 exceeds 100 columns
#61784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46499:
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#61785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46500:
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4

WARNING: line length of 117 exceeds 100 columns
#61786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46501:
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L

WARNING: line length of 117 exceeds 100 columns
#61787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46502:
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L

WARNING: line length of 113 exceeds 100 columns
#61788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46503:
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#61789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46504:
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7

WARNING: line length of 121 exceeds 100 columns
#61790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46505:
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#61791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46506:
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L

WARNING: line length of 113 exceeds 100 columns
#61792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46507:
+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#61793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46508:
+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46509:
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#61795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46510:
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf

WARNING: line length of 117 exceeds 100 columns
#61796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46511:
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL

WARNING: line length of 117 exceeds 100 columns
#61797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46512:
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L

WARNING: line length of 113 exceeds 100 columns
#61798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46513:
+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0

WARNING: line length of 117 exceeds 100 columns
#61799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46514:
+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL

WARNING: line length of 113 exceeds 100 columns
#61800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46515:
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#61801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46516:
+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#61802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46517:
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2

WARNING: line length of 115 exceeds 100 columns
#61803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46518:
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L

WARNING: line length of 115 exceeds 100 columns
#61804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46519:
+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L

WARNING: line length of 115 exceeds 100 columns
#61805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46520:
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L

WARNING: line length of 113 exceeds 100 columns
#61806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46521:
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#61807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46522:
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2

WARNING: line length of 115 exceeds 100 columns
#61808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46523:
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L

WARNING: line length of 115 exceeds 100 columns
#61809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46524:
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L

WARNING: line length of 113 exceeds 100 columns
#61810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46525:
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#61811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46526:
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4

WARNING: line length of 117 exceeds 100 columns
#61812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46527:
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L

WARNING: line length of 117 exceeds 100 columns
#61813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46528:
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L

WARNING: line length of 113 exceeds 100 columns
#61814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46529:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0

WARNING: line length of 114 exceeds 100 columns
#61815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46530:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c

WARNING: line length of 121 exceeds 100 columns
#61816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46531:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#61817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46532:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#61818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46533:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#61819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46534:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46535:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0

WARNING: line length of 121 exceeds 100 columns
#61821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46536:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#61822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46537:
+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0

WARNING: line length of 121 exceeds 100 columns
#61823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46538:
+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46539:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#61825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46540:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1

WARNING: line length of 121 exceeds 100 columns
#61826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46541:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46542:
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L

WARNING: line length of 113 exceeds 100 columns
#61828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46543:
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#61829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46544:
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1

WARNING: line length of 113 exceeds 100 columns
#61830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46545:
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7

WARNING: line length of 121 exceeds 100 columns
#61831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46546:
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46547:
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL

WARNING: line length of 121 exceeds 100 columns
#61833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46548:
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L

WARNING: line length of 113 exceeds 100 columns
#61834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46549:
+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0

WARNING: line length of 121 exceeds 100 columns
#61835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46550:
+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46551:
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0

WARNING: line length of 121 exceeds 100 columns
#61837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46552:
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46553:
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#61839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46554:
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46555:
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0

WARNING: line length of 121 exceeds 100 columns
#61841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46556:
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46557:
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#61843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46558:
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL

WARNING: line length of 113 exceeds 100 columns
#61845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46560:
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#61846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46561:
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT                                 0x3

WARNING: line length of 113 exceeds 100 columns
#61847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46562:
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT                                         0x8

WARNING: line length of 113 exceeds 100 columns
#61848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46563:
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT                                        0xc

WARNING: line length of 117 exceeds 100 columns
#61849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46564:
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK                                            0x0001L

WARNING: line length of 117 exceeds 100 columns
#61850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46565:
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK                                   0x00F8L

WARNING: line length of 117 exceeds 100 columns
#61851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46566:
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK                                           0x0F00L

WARNING: line length of 117 exceeds 100 columns
#61852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46567:
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK                                          0xF000L

WARNING: line length of 113 exceeds 100 columns
#61853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46568:
+#define MINOR_VERSION__MINOR_VERSION__SHIFT                                                                   0x0

WARNING: line length of 115 exceeds 100 columns
#61854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46569:
+#define MINOR_VERSION__MINOR_VERSION_MASK                                                                     0xFFL

WARNING: line length of 113 exceeds 100 columns
#61855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46570:
+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT                                                                   0x0

WARNING: line length of 115 exceeds 100 columns
#61856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46571:
+#define MAJOR_VERSION__MAJOR_VERSION_MASK                                                                     0xFFL

WARNING: line length of 113 exceeds 100 columns
#61857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46572:
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                           0x0

WARNING: line length of 117 exceeds 100 columns
#61858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46573:
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                             0xFFFFL

WARNING: line length of 113 exceeds 100 columns
#61859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46574:
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                             0x0

WARNING: line length of 117 exceeds 100 columns
#61860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46575:
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                               0xFFFFL

WARNING: line length of 113 exceeds 100 columns
#61861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46576:
+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#61862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46577:
+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT                                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#61863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46578:
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT                                             0x8

WARNING: line length of 121 exceeds 100 columns
#61864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46579:
+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46580:
+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK                                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46581:
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK                                               0x00000100L

WARNING: line length of 113 exceeds 100 columns
#61867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46582:
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT                                                             0x0

WARNING: line length of 117 exceeds 100 columns
#61868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46583:
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK                                                               0x0001L

WARNING: line length of 113 exceeds 100 columns
#61869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46584:
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT                                                       0x0

WARNING: line length of 117 exceeds 100 columns
#61870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46585:
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK                                                         0x0001L

WARNING: line length of 113 exceeds 100 columns
#61871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46586:
+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT                                                                    0x1

WARNING: line length of 121 exceeds 100 columns
#61872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46587:
+#define GLOBAL_STATUS__FLUSH_STATUS_MASK                                                                      0x00000002L

WARNING: line length of 113 exceeds 100 columns
#61873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46588:
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x0

WARNING: line length of 117 exceeds 100 columns
#61874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46589:
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFFL

WARNING: line length of 113 exceeds 100 columns
#61875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46590:
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x0

WARNING: line length of 117 exceeds 100 columns
#61876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46591:
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFFL

WARNING: line length of 113 exceeds 100 columns
#61877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46592:
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT                                                   0x0

WARNING: line length of 113 exceeds 100 columns
#61878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46593:
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#61879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46594:
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#61880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46595:
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#61881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46596:
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT                                                   0x4

WARNING: line length of 113 exceeds 100 columns
#61882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46597:
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT                                                   0x5

WARNING: line length of 113 exceeds 100 columns
#61883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46598:
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#61884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46599:
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT                                                   0x7

WARNING: line length of 113 exceeds 100 columns
#61885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46600:
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#61886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46601:
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT                                                   0x9

WARNING: line length of 113 exceeds 100 columns
#61887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46602:
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT                                                  0xa

WARNING: line length of 113 exceeds 100 columns
#61888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46603:
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT                                                  0xb

WARNING: line length of 113 exceeds 100 columns
#61889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46604:
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#61890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46605:
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT                                                  0xd

WARNING: line length of 113 exceeds 100 columns
#61891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46606:
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT                                                  0xe

WARNING: line length of 113 exceeds 100 columns
#61892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46607:
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#61893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46608:
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT                                                 0x1e

WARNING: line length of 114 exceeds 100 columns
#61894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46609:
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT                                                     0x1f

WARNING: line length of 121 exceeds 100 columns
#61895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46610:
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK                                                     0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46611:
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46612:
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK                                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46613:
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#61899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46614:
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK                                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#61900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46615:
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#61901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46616:
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#61902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46617:
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK                                                     0x00000080L

WARNING: line length of 121 exceeds 100 columns
#61903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46618:
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46619:
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK                                                     0x00000200L

WARNING: line length of 121 exceeds 100 columns
#61905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46620:
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK                                                    0x00000400L

WARNING: line length of 121 exceeds 100 columns
#61906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46621:
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK                                                    0x00000800L

WARNING: line length of 121 exceeds 100 columns
#61907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46622:
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#61908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46623:
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK                                                    0x00002000L

WARNING: line length of 121 exceeds 100 columns
#61909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46624:
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#61910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46625:
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#61911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46626:
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK                                                   0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46627:
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK                                                       0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46628:
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#61914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46629:
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#61915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46630:
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT                                                    0x2

WARNING: line length of 113 exceeds 100 columns
#61916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46631:
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#61917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46632:
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#61918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46633:
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT                                                    0x5

WARNING: line length of 113 exceeds 100 columns
#61919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46634:
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT                                                    0x6

WARNING: line length of 113 exceeds 100 columns
#61920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46635:
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT                                                    0x7

WARNING: line length of 113 exceeds 100 columns
#61921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46636:
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT                                                    0x8

WARNING: line length of 113 exceeds 100 columns
#61922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46637:
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT                                                    0x9

WARNING: line length of 113 exceeds 100 columns
#61923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46638:
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT                                                   0xa

WARNING: line length of 113 exceeds 100 columns
#61924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46639:
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT                                                   0xb

WARNING: line length of 113 exceeds 100 columns
#61925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46640:
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT                                                   0xc

WARNING: line length of 113 exceeds 100 columns
#61926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46641:
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT                                                   0xd

WARNING: line length of 113 exceeds 100 columns
#61927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46642:
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT                                                   0xe

WARNING: line length of 113 exceeds 100 columns
#61928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46643:
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT                                                   0xf

WARNING: line length of 114 exceeds 100 columns
#61929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46644:
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT                                                  0x1e

WARNING: line length of 114 exceeds 100 columns
#61930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46645:
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT                                                      0x1f

WARNING: line length of 121 exceeds 100 columns
#61931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46646:
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46647:
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46648:
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK                                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46649:
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#61935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46650:
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#61936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46651:
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK                                                      0x00000020L

WARNING: line length of 121 exceeds 100 columns
#61937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46652:
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK                                                      0x00000040L

WARNING: line length of 121 exceeds 100 columns
#61938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46653:
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK                                                      0x00000080L

WARNING: line length of 121 exceeds 100 columns
#61939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46654:
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK                                                      0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46655:
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK                                                      0x00000200L

WARNING: line length of 121 exceeds 100 columns
#61941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46656:
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK                                                     0x00000400L

WARNING: line length of 121 exceeds 100 columns
#61942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46657:
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK                                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#61943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46658:
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK                                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#61944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46659:
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK                                                     0x00002000L

WARNING: line length of 121 exceeds 100 columns
#61945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46660:
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK                                                     0x00004000L

WARNING: line length of 121 exceeds 100 columns
#61946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46661:
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK                                                     0x00008000L

WARNING: line length of 121 exceeds 100 columns
#61947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46662:
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK                                                    0x40000000L

WARNING: line length of 121 exceeds 100 columns
#61948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46663:
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK                                                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#61949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46664:
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#61950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46665:
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46666:
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#61952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46667:
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#61953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46668:
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#61954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46669:
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT                                               0x3

WARNING: line length of 113 exceeds 100 columns
#61955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46670:
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#61956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46671:
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT                                               0x5

WARNING: line length of 113 exceeds 100 columns
#61957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46672:
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT                                               0x6

WARNING: line length of 113 exceeds 100 columns
#61958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46673:
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT                                               0x7

WARNING: line length of 113 exceeds 100 columns
#61959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46674:
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#61960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46675:
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT                                               0x9

WARNING: line length of 113 exceeds 100 columns
#61961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46676:
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT                                              0xa

WARNING: line length of 113 exceeds 100 columns
#61962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46677:
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#61963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46678:
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT                                              0xc

WARNING: line length of 113 exceeds 100 columns
#61964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46679:
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT                                              0xd

WARNING: line length of 113 exceeds 100 columns
#61965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46680:
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT                                              0xe

WARNING: line length of 113 exceeds 100 columns
#61966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46681:
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT                                              0xf

WARNING: line length of 121 exceeds 100 columns
#61967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46682:
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#61968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46683:
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#61969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46684:
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#61970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46685:
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK                                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#61971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46686:
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#61972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46687:
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK                                                 0x00000020L

WARNING: line length of 121 exceeds 100 columns
#61973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46688:
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK                                                 0x00000040L

WARNING: line length of 121 exceeds 100 columns
#61974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46689:
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK                                                 0x00000080L

WARNING: line length of 121 exceeds 100 columns
#61975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46690:
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#61976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46691:
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK                                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#61977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46692:
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK                                                0x00000400L

WARNING: line length of 121 exceeds 100 columns
#61978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46693:
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#61979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46694:
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#61980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46695:
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK                                                0x00002000L

WARNING: line length of 121 exceeds 100 columns
#61981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46696:
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK                                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#61982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46697:
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK                                                0x00008000L

WARNING: line length of 113 exceeds 100 columns
#61983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46698:
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#61984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46699:
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT                                               0x7

WARNING: line length of 121 exceeds 100 columns
#61985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46700:
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#61986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46701:
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L

WARNING: line length of 113 exceeds 100 columns
#61987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46702:
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#61988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46703:
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46704:
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46705:
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#61993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46708:
+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0

WARNING: line length of 121 exceeds 100 columns
#61994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46709:
+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46730:
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#62016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46731:
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8

WARNING: line length of 121 exceeds 100 columns
#62017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46732:
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL

WARNING: line length of 121 exceeds 100 columns
#62018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46733:
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L

WARNING: line length of 114 exceeds 100 columns
#62019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46734:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE__SHIFT                                             0x12

WARNING: line length of 114 exceeds 100 columns
#62020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46735:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE__SHIFT                                             0x13

WARNING: line length of 114 exceeds 100 columns
#62021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46736:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#62022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46737:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE__SHIFT                                             0x15

WARNING: line length of 114 exceeds 100 columns
#62023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46738:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE__SHIFT                                             0x16

WARNING: line length of 114 exceeds 100 columns
#62024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46739:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#62025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46740:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#62026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46741:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#62027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46742:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1b

WARNING: line length of 114 exceeds 100 columns
#62028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46743:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#62029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46744:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE_MASK                                               0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46745:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE_MASK                                               0x00080000L

WARNING: line length of 121 exceeds 100 columns
#62031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46746:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#62032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46747:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE_MASK                                               0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46748:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE_MASK                                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#62034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46749:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#62035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46750:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#62036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46751:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#62037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46752:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE_MASK                                            0x08000000L

WARNING: line length of 121 exceeds 100 columns
#62038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46753:
+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE_MASK                                            0x10000000L

WARNING: line length of 114 exceeds 100 columns
#62039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46754:
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#62040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46755:
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x19

WARNING: line length of 114 exceeds 100 columns
#62041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46756:
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1a

WARNING: line length of 114 exceeds 100 columns
#62042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46757:
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1b

WARNING: line length of 114 exceeds 100 columns
#62043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46758:
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#62044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46759:
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE_MASK                                            0x01000000L

WARNING: line length of 121 exceeds 100 columns
#62045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46760:
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x02000000L

WARNING: line length of 121 exceeds 100 columns
#62046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46761:
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x04000000L

WARNING: line length of 121 exceeds 100 columns
#62047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46762:
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x08000000L

WARNING: line length of 121 exceeds 100 columns
#62048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46763:
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE_MASK                                            0x10000000L

WARNING: line length of 113 exceeds 100 columns
#62049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46764:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46765:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL__SHIFT                                                       0x8

WARNING: line length of 121 exceeds 100 columns
#62051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46766:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46767:
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL_MASK                                                         0x00000700L

WARNING: line length of 113 exceeds 100 columns
#62053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46768:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46769:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL__SHIFT                                                       0x8

WARNING: line length of 121 exceeds 100 columns
#62055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46770:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46771:
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL_MASK                                                         0x00000700L

WARNING: line length of 113 exceeds 100 columns
#62057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46772:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46773:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL__SHIFT                                                       0x8

WARNING: line length of 121 exceeds 100 columns
#62059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46774:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46775:
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL_MASK                                                         0x00000700L

WARNING: line length of 113 exceeds 100 columns
#62061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46776:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46777:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL__SHIFT                                                       0x8

WARNING: line length of 121 exceeds 100 columns
#62063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46778:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46779:
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL_MASK                                                         0x00000700L

WARNING: line length of 113 exceeds 100 columns
#62065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46780:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46781:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL__SHIFT                                                       0x8

WARNING: line length of 121 exceeds 100 columns
#62067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46782:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46783:
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL_MASK                                                         0x00000700L

WARNING: line length of 113 exceeds 100 columns
#62069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46784:
+#define DSCCLK_DTO_CTRL__DSCCLK0_EN__SHIFT                                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#62070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46785:
+#define DSCCLK_DTO_CTRL__DSCCLK1_EN__SHIFT                                                                    0x1

WARNING: line length of 113 exceeds 100 columns
#62071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46786:
+#define DSCCLK_DTO_CTRL__DSCCLK2_EN__SHIFT                                                                    0x2

WARNING: line length of 113 exceeds 100 columns
#62072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46787:
+#define DSCCLK_DTO_CTRL__DSCCLK3_EN__SHIFT                                                                    0x3

WARNING: line length of 113 exceeds 100 columns
#62073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46788:
+#define DSCCLK_DTO_CTRL__DSCCLK4_EN__SHIFT                                                                    0x4

WARNING: line length of 113 exceeds 100 columns
#62074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46789:
+#define DSCCLK_DTO_CTRL__DSCCLK5_EN__SHIFT                                                                    0x5

WARNING: line length of 121 exceeds 100 columns
#62075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46790:
+#define DSCCLK_DTO_CTRL__DSCCLK0_EN_MASK                                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46791:
+#define DSCCLK_DTO_CTRL__DSCCLK1_EN_MASK                                                                      0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46792:
+#define DSCCLK_DTO_CTRL__DSCCLK2_EN_MASK                                                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46793:
+#define DSCCLK_DTO_CTRL__DSCCLK3_EN_MASK                                                                      0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46794:
+#define DSCCLK_DTO_CTRL__DSCCLK4_EN_MASK                                                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46795:
+#define DSCCLK_DTO_CTRL__DSCCLK5_EN_MASK                                                                      0x00000020L

WARNING: line length of 113 exceeds 100 columns
#62081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46796:
+#define DPPCLK_CTRL__DPPCLK0_EN__SHIFT                                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#62082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46797:
+#define DPPCLK_CTRL__DPPCLK1_EN__SHIFT                                                                        0x3

WARNING: line length of 113 exceeds 100 columns
#62083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46798:
+#define DPPCLK_CTRL__DPPCLK2_EN__SHIFT                                                                        0x6

WARNING: line length of 113 exceeds 100 columns
#62084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46799:
+#define DPPCLK_CTRL__DPPCLK3_EN__SHIFT                                                                        0x9

WARNING: line length of 121 exceeds 100 columns
#62085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46800:
+#define DPPCLK_CTRL__DPPCLK0_EN_MASK                                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46801:
+#define DPPCLK_CTRL__DPPCLK1_EN_MASK                                                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46802:
+#define DPPCLK_CTRL__DPPCLK2_EN_MASK                                                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46803:
+#define DPPCLK_CTRL__DPPCLK3_EN_MASK                                                                          0x00000200L

WARNING: line length of 113 exceeds 100 columns
#62089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46804:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#62090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46805:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE__SHIFT                                             0x1

WARNING: line length of 113 exceeds 100 columns
#62091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46806:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE__SHIFT                                             0x2

WARNING: line length of 113 exceeds 100 columns
#62092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46807:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE__SHIFT                                             0x3

WARNING: line length of 113 exceeds 100 columns
#62093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46808:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#62094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46809:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE__SHIFT                                             0x9

WARNING: line length of 113 exceeds 100 columns
#62095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46810:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE__SHIFT                                             0xa

WARNING: line length of 113 exceeds 100 columns
#62096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46811:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE__SHIFT                                             0xb

WARNING: line length of 113 exceeds 100 columns
#62097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46812:
+#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                      0xf

WARNING: line length of 121 exceeds 100 columns
#62098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46813:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46814:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE_MASK                                               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46815:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46816:
+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE_MASK                                               0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46817:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46818:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE_MASK                                               0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46819:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE_MASK                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46820:
+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE_MASK                                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46821:
+#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE_MASK                                        0x00008000L

WARNING: line length of 113 exceeds 100 columns
#62107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46822:
+#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#62108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46823:
+#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON_MASK                                                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#62109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46824:
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#62110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46825:
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#62111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46826:
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46827:
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL_MASK                                                        0x00000030L

WARNING: line length of 113 exceeds 100 columns
#62113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46828:
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#62114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46829:
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#62115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46830:
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46831:
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL_MASK                                                        0x00000030L

WARNING: line length of 113 exceeds 100 columns
#62117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46832:
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#62118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46833:
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#62119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46834:
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46835:
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL_MASK                                                        0x00000030L

WARNING: line length of 113 exceeds 100 columns
#62121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46836:
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#62122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46837:
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#62123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46838:
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46839:
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL_MASK                                                        0x00000030L

WARNING: line length of 113 exceeds 100 columns
#62125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46840:
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN__SHIFT                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#62126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46841:
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL__SHIFT                                                      0x4

WARNING: line length of 121 exceeds 100 columns
#62127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46842:
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN_MASK                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46843:
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL_MASK                                                        0x00000030L

WARNING: line length of 113 exceeds 100 columns
#62130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46845:
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#62131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46846:
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL_MASK                                                      0x00000007L

WARNING: line length of 113 exceeds 100 columns
#62134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46849:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT__SHIFT                         0x6

WARNING: line length of 113 exceeds 100 columns
#62135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46850:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT__SHIFT                         0x7

WARNING: line length of 113 exceeds 100 columns
#62136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46851:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT__SHIFT                         0x8

WARNING: line length of 113 exceeds 100 columns
#62137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46852:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT__SHIFT                         0x9

WARNING: line length of 114 exceeds 100 columns
#62138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46853:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT__SHIFT                       0x10

WARNING: line length of 114 exceeds 100 columns
#62139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46854:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT__SHIFT                       0x11

WARNING: line length of 114 exceeds 100 columns
#62140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46855:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT__SHIFT                       0x12

WARNING: line length of 114 exceeds 100 columns
#62141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46856:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT__SHIFT                       0x13

WARNING: line length of 121 exceeds 100 columns
#62142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46857:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_MASK                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46858:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_MASK                           0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46859:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_MASK                           0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46860:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_MASK                           0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46861:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_MASK                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46862:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_MASK                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46863:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_MASK                         0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46864:
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_MASK                         0x00080000L

WARNING: line length of 113 exceeds 100 columns
#62150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46865:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#62151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46866:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x1

WARNING: line length of 113 exceeds 100 columns
#62152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46867:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x2

WARNING: line length of 113 exceeds 100 columns
#62153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46868:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x3

WARNING: line length of 113 exceeds 100 columns
#62154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46869:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#62155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46870:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x5

WARNING: line length of 113 exceeds 100 columns
#62156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46871:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#62157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46872:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#62158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46873:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#62159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46874:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x9

WARNING: line length of 113 exceeds 100 columns
#62160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46875:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0xa

WARNING: line length of 113 exceeds 100 columns
#62161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46876:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0xb

WARNING: line length of 121 exceeds 100 columns
#62162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46877:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46878:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46879:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46880:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46881:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46882:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46883:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46884:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46885:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46886:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46887:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46888:
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000800L

WARNING: line length of 113 exceeds 100 columns
#62174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46889:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#62175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46890:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST__SHIFT                                0x7

WARNING: line length of 113 exceeds 100 columns
#62176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46891:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST__SHIFT                                0x8

WARNING: line length of 113 exceeds 100 columns
#62177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46892:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST__SHIFT                                0x9

WARNING: line length of 114 exceeds 100 columns
#62178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46893:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#62179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46894:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x11

WARNING: line length of 114 exceeds 100 columns
#62180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46895:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#62181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46896:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x13

WARNING: line length of 121 exceeds 100 columns
#62182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46897:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46898:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46899:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46900:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46901:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46902:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46903:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46904:
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00080000L

WARNING: line length of 113 exceeds 100 columns
#62192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46907:
+#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT                                                                    0xc

WARNING: line length of 121 exceeds 100 columns
#62193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46908:
+#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK                                                                      0x00001000L

WARNING: line length of 113 exceeds 100 columns
#62194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46909:
+#define DMU_CLK_CNTL__RIOMMU_CLK_SEL__SHIFT                                                                   0x8

WARNING: line length of 113 exceeds 100 columns
#62195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46910:
+#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS__SHIFT                                                              0xc

WARNING: line length of 113 exceeds 100 columns
#62196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46911:
+#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL__SHIFT                                                           0xd

WARNING: line length of 114 exceeds 100 columns
#62197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46912:
+#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP__SHIFT                                                        0x10

WARNING: line length of 114 exceeds 100 columns
#62198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46913:
+#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP__SHIFT                                                         0x12

WARNING: line length of 114 exceeds 100 columns
#62199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46914:
+#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x14

WARNING: line length of 114 exceeds 100 columns
#62200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46915:
+#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x16

WARNING: line length of 114 exceeds 100 columns
#62201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46916:
+#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x18

WARNING: line length of 114 exceeds 100 columns
#62202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46917:
+#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP__SHIFT                                                         0x1a

WARNING: line length of 114 exceeds 100 columns
#62203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46918:
+#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS__SHIFT                                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#62204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46919:
+#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE__SHIFT                                                        0x1d

WARNING: line length of 114 exceeds 100 columns
#62205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46920:
+#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE__SHIFT                                                         0x1e

WARNING: line length of 114 exceeds 100 columns
#62206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46921:
+#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE__SHIFT                                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#62207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46922:
+#define DMU_CLK_CNTL__RIOMMU_CLK_SEL_MASK                                                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46923:
+#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS_MASK                                                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46924:
+#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL_MASK                                                             0x00006000L

WARNING: line length of 121 exceeds 100 columns
#62210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46925:
+#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP_MASK                                                          0x00030000L

WARNING: line length of 121 exceeds 100 columns
#62211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46926:
+#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP_MASK                                                           0x000C0000L

WARNING: line length of 121 exceeds 100 columns
#62212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46927:
+#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x00300000L

WARNING: line length of 121 exceeds 100 columns
#62213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46928:
+#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x00C00000L

WARNING: line length of 121 exceeds 100 columns
#62214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46929:
+#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x03000000L

WARNING: line length of 121 exceeds 100 columns
#62215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46930:
+#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP_MASK                                                           0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#62216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46931:
+#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS_MASK                                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46932:
+#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE_MASK                                                          0x20000000L

WARNING: line length of 121 exceeds 100 columns
#62218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46933:
+#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE_MASK                                                           0x40000000L

WARNING: line length of 121 exceeds 100 columns
#62219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46934:
+#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE_MASK                                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#62220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46935:
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#62221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46936:
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#62222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46937:
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46938:
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK                                                          0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#62224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46939:
+#define ZSC_CNTL__LONO_PWR_DN__SHIFT                                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#62225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46940:
+#define ZSC_CNTL__LONO_PWR_DN_MASK                                                                            0x00000100L

WARNING: line length of 113 exceeds 100 columns
#62226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46941:
+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#62227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46942:
+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY__SHIFT                                     0x4

WARNING: line length of 121 exceeds 100 columns
#62228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46943:
+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY_MASK                                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#62229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46944:
+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY_MASK                                       0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#62230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46945:
+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#62231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46946:
+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY__SHIFT                                       0x4

WARNING: line length of 121 exceeds 100 columns
#62232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46947:
+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY_MASK                                          0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#62233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46948:
+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY_MASK                                         0x00000FF0L

WARNING: line length of 113 exceeds 100 columns
#62234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46949:
+#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY__SHIFT                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#62235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46950:
+#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY_MASK                                                       0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#62238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46953:
+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#62239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46954:
+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#62240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46955:
+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46956:
+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#62242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46957:
+#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#62243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46958:
+#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#62244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46959:
+#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46960:
+#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#62246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46961:
+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#62247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46962:
+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#62248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46963:
+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46964:
+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#62250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46965:
+#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#62251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46966:
+#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#62252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46967:
+#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46968:
+#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#62254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46969:
+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#62255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46970:
+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#62256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46971:
+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46972:
+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#62258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46973:
+#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#62259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46974:
+#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#62260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46975:
+#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46976:
+#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#62262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46977:
+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#62263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46978:
+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8

WARNING: line length of 121 exceeds 100 columns
#62264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46979:
+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46980:
+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L

WARNING: line length of 114 exceeds 100 columns
#62266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46981:
+#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c

WARNING: line length of 114 exceeds 100 columns
#62267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46982:
+#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e

WARNING: line length of 121 exceeds 100 columns
#62268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46983:
+#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46984:
+#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L

WARNING: line length of 113 exceeds 100 columns
#62270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46985:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#62271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46986:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1

WARNING: line length of 113 exceeds 100 columns
#62272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46987:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#62273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46988:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3

WARNING: line length of 113 exceeds 100 columns
#62274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46989:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#62275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46990:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5

WARNING: line length of 113 exceeds 100 columns
#62276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46991:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED__SHIFT                                        0x6

WARNING: line length of 113 exceeds 100 columns
#62277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46992:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7

WARNING: line length of 121 exceeds 100 columns
#62278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46993:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46994:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46995:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46996:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46997:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46998:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:46999:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47000:
+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L

WARNING: line length of 113 exceeds 100 columns
#62286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47001:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#62287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47002:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#62288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47003:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#62289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47004:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#62290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47005:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#62291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47006:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#62292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47007:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#62293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47008:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7

WARNING: line length of 113 exceeds 100 columns
#62294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47009:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#62295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47010:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#62296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47011:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#62297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47012:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb

WARNING: line length of 113 exceeds 100 columns
#62298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47013:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#62299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47014:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#62300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47015:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe

WARNING: line length of 113 exceeds 100 columns
#62301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47016:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf

WARNING: line length of 121 exceeds 100 columns
#62302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47017:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47018:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47019:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47020:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47021:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47022:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47023:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47024:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47025:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47026:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47027:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47028:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47029:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47030:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47031:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#62317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47032:
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L

WARNING: line length of 113 exceeds 100 columns
#62318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47033:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK__SHIFT                                           0x0

WARNING: line length of 113 exceeds 100 columns
#62319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47034:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR__SHIFT                                          0x1

WARNING: line length of 113 exceeds 100 columns
#62320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47035:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK__SHIFT                                         0x2

WARNING: line length of 113 exceeds 100 columns
#62321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47036:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3

WARNING: line length of 113 exceeds 100 columns
#62322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47037:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK__SHIFT                                           0x4

WARNING: line length of 113 exceeds 100 columns
#62323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47038:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR__SHIFT                                          0x5

WARNING: line length of 113 exceeds 100 columns
#62324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47039:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK__SHIFT                                         0x6

WARNING: line length of 113 exceeds 100 columns
#62325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47040:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7

WARNING: line length of 113 exceeds 100 columns
#62326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47041:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#62327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47042:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR__SHIFT                                          0x9

WARNING: line length of 113 exceeds 100 columns
#62328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47043:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK__SHIFT                                         0xa

WARNING: line length of 113 exceeds 100 columns
#62329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47044:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb

WARNING: line length of 113 exceeds 100 columns
#62330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47045:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK__SHIFT                                           0xc

WARNING: line length of 113 exceeds 100 columns
#62331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47046:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#62332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47047:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK__SHIFT                                         0xe

WARNING: line length of 113 exceeds 100 columns
#62333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47048:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf

WARNING: line length of 121 exceeds 100 columns
#62334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47049:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK_MASK                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47050:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR_MASK                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47051:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK_MASK                                           0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47052:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47053:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK_MASK                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47054:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR_MASK                                            0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47055:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK_MASK                                           0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47056:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47057:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK_MASK                                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47058:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR_MASK                                            0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47059:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK_MASK                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47060:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47061:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK_MASK                                             0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47062:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47063:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK_MASK                                           0x00004000L

WARNING: line length of 121 exceeds 100 columns
#62349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47064:
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L

WARNING: line length of 113 exceeds 100 columns
#62350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47065:
+#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS__SHIFT                                                    0x0

WARNING: line length of 121 exceeds 100 columns
#62351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47066:
+#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS_MASK                                                      0x00000001L

WARNING: line length of 114 exceeds 100 columns
#62354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47069:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT__SHIFT                                             0x15

WARNING: line length of 114 exceeds 100 columns
#62355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47070:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT__SHIFT                                         0x16

WARNING: line length of 121 exceeds 100 columns
#62356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47071:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT_MASK                                               0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47072:
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT_MASK                                           0x00400000L

WARNING: line length of 113 exceeds 100 columns
#62358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47073:
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#62359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47074:
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L

WARNING: line length of 113 exceeds 100 columns
#62360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47075:
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47076:
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47077:
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47078:
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47079:
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47080:
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47081:
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT                                       0x0

WARNING: line length of 115 exceeds 100 columns
#62367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47082:
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK                                         0x07L

WARNING: line length of 113 exceeds 100 columns
#62368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47083:
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47084:
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47085:
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47086:
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47087:
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47088:
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47089:
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47090:
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47091:
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT                                                               0x0

WARNING: line length of 121 exceeds 100 columns
#62377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47092:
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK                                                                 0xFFFFFFFFL

WARNING: line length of 114 exceeds 100 columns
#62379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47094:
+#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS__SHIFT                                                          0x18

WARNING: line length of 121 exceeds 100 columns
#62380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47095:
+#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS_MASK                                                            0x01000000L

WARNING: line length of 113 exceeds 100 columns
#62382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47097:
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#62383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47098:
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x10

WARNING: line length of 121 exceeds 100 columns
#62384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47099:
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#62385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47100:
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0xFFFF0000L

WARNING: line length of 114 exceeds 100 columns
#62387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47102:
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT                           0x1f

WARNING: line length of 121 exceeds 100 columns
#62388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47103:
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK                             0x80000000L

WARNING: line length of 113 exceeds 100 columns
#62389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47104:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0

WARNING: line length of 114 exceeds 100 columns
#62390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47105:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18

WARNING: line length of 121 exceeds 100 columns
#62391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47106:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL

WARNING: line length of 121 exceeds 100 columns
#62392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47107:
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L

WARNING: line length of 114 exceeds 100 columns
#62393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47108:
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x11

WARNING: line length of 121 exceeds 100 columns
#62394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47109:
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK                                                       0x00020000L

WARNING: line length of 113 exceeds 100 columns
#62396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47111:
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0

WARNING: line length of 114 exceeds 100 columns
#62397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47112:
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10

WARNING: line length of 121 exceeds 100 columns
#62398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47113:
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#62399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47114:
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#62400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47115:
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0

WARNING: line length of 114 exceeds 100 columns
#62401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47116:
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#62402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47117:
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#62403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47118:
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#62405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47120:
+#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS__SHIFT                                                          0x1

WARNING: line length of 114 exceeds 100 columns
#62406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47121:
+#define AZ_CLOCK_CNTL__SCLK_GATE_DIS__SHIFT                                                                   0x10

WARNING: line length of 114 exceeds 100 columns
#62407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47122:
+#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY__SHIFT                                                              0x14

WARNING: line length of 114 exceeds 100 columns
#62408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47123:
+#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY__SHIFT                                                             0x18

WARNING: line length of 121 exceeds 100 columns
#62409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47124:
+#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS_MASK                                                            0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47125:
+#define AZ_CLOCK_CNTL__SCLK_GATE_DIS_MASK                                                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47126:
+#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY_MASK                                                                0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#62412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47127:
+#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY_MASK                                                               0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#62413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47128:
+#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#62414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47129:
+#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L

WARNING: line length of 113 exceeds 100 columns
#62432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47147:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT         0x9

WARNING: line length of 121 exceeds 100 columns
#62433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47148:
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK           0x00000200L

WARNING: line length of 117 exceeds 100 columns
#62434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47149:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0x2

WARNING: line length of 113 exceeds 100 columns
#62435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47150:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT                                          0x7

WARNING: line length of 113 exceeds 100 columns
#62436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47151:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE__SHIFT                  0xd

WARNING: line length of 113 exceeds 100 columns
#62437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47152:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP__SHIFT                           0xf

WARNING: line length of 123 exceeds 100 columns
#62438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47153:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47154:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK                                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47155:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE_MASK                    0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47156:
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP_MASK                             0x00008000L

WARNING: line length of 113 exceeds 100 columns
#62442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47157:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT                                       0x0

WARNING: line length of 113 exceeds 100 columns
#62443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47158:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#62444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47159:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT                0x8

WARNING: line length of 113 exceeds 100 columns
#62445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47160:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT               0x9

WARNING: line length of 129 exceeds 100 columns
#62446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47161:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0xa

WARNING: line length of 118 exceeds 100 columns
#62447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47162:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT  0xb

WARNING: line length of 121 exceeds 100 columns
#62448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47163:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47164:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47165:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47166:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK                 0x00000200L

WARNING: line length of 135 exceeds 100 columns
#62452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47167:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000400L

WARNING: line length of 124 exceeds 100 columns
#62453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47168:
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK  0x00000800L

WARNING: line length of 113 exceeds 100 columns
#62454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47169:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#62455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47170:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK                 0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#62456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47171:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47172:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47173:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47174:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47175:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#62461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47176:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK                 0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#62462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47177:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47178:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47179:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47180:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47181:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#62467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47182:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK                 0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#62468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47183:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47184:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47185:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47186:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47187:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT               0x0

WARNING: line length of 121 exceeds 100 columns
#62473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47188:
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK                 0x00003FFFL

WARNING: line length of 113 exceeds 100 columns
#62474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47189:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47190:
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47191:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0

WARNING: line length of 121 exceeds 100 columns
#62477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47192:
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#62478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47193:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING__SHIFT                            0x2

WARNING: line length of 121 exceeds 100 columns
#62479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47194:
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING_MASK                              0x00000004L

WARNING: line length of 114 exceeds 100 columns
#62480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47195:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#62481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47196:
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#62482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47197:
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#62483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47198:
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47199:
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5

WARNING: line length of 121 exceeds 100 columns
#62485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47200:
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47201:
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47202:
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L

WARNING: line length of 114 exceeds 100 columns
#62490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47205:
+#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW__SHIFT                                                        0x10

WARNING: line length of 121 exceeds 100 columns
#62491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47206:
+#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW_MASK                                                          0x00010000L

WARNING: line length of 113 exceeds 100 columns
#62492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47207:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT                                                 0x9

WARNING: line length of 121 exceeds 100 columns
#62493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47208:
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK                                                   0x00000200L

WARNING: line length of 113 exceeds 100 columns
#62494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47209:
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8

WARNING: line length of 121 exceeds 100 columns
#62495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47210:
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#62496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47211:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#62497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47212:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#62498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47213:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#62499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47214:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0xc

WARNING: line length of 121 exceeds 100 columns
#62500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47215:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#62501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47216:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#62502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47217:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#62503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47218:
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x0000F000L

WARNING: line length of 113 exceeds 100 columns
#62504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47219:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#62505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47220:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#62506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47221:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT                                               0x2

WARNING: line length of 113 exceeds 100 columns
#62507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47222:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT                                               0x3

WARNING: line length of 121 exceeds 100 columns
#62508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47223:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47224:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK                                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47225:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47226:
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK                                                 0x00000008L

WARNING: line length of 113 exceeds 100 columns
#62512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47227:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#62513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47228:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x4

WARNING: line length of 113 exceeds 100 columns
#62514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47229:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x8

WARNING: line length of 113 exceeds 100 columns
#62515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47230:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0xc

WARNING: line length of 121 exceeds 100 columns
#62516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47231:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#62517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47232:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#62518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47233:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#62519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47234:
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x0000F000L

WARNING: line length of 113 exceeds 100 columns
#62520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47235:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#62521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47236:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#62522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47237:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#62523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47238:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT                               0xc

WARNING: line length of 121 exceeds 100 columns
#62524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47239:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#62525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47240:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK                                 0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#62526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47241:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#62527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47242:
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK                                 0x0000F000L

WARNING: line length of 113 exceeds 100 columns
#62528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47243:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#62529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47244:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT                               0x4

WARNING: line length of 113 exceeds 100 columns
#62530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47245:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT                               0x8

WARNING: line length of 113 exceeds 100 columns
#62531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47246:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT                               0xc

WARNING: line length of 121 exceeds 100 columns
#62532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47247:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK                                 0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#62533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47248:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK                                 0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#62534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47249:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK                                 0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#62535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47250:
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK                                 0x0000F000L

WARNING: line length of 113 exceeds 100 columns
#62536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47251:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT                                   0x0

WARNING: line length of 113 exceeds 100 columns
#62537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47252:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#62538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47253:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#62539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47254:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#62540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47255:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK                                     0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#62541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47256:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK                                     0x000000F0L

WARNING: line length of 121 exceeds 100 columns
#62542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47257:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK                                     0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#62543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47258:
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK                                     0x0000F000L

WARNING: line length of 113 exceeds 100 columns
#62544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47259:
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#62545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47260:
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK                                               0x00000FFFL

WARNING: line length of 113 exceeds 100 columns
#62548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47263:
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY__SHIFT                                           0x8

WARNING: line length of 113 exceeds 100 columns
#62549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47264:
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY__SHIFT                                             0xc

WARNING: line length of 121 exceeds 100 columns
#62550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47265:
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY_MASK                                             0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#62551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47266:
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY_MASK                                               0x0000F000L

WARNING: line length of 114 exceeds 100 columns
#62553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47268:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#62554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47269:
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#62555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47270:
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#62556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47271:
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#62557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47272:
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7

WARNING: line length of 121 exceeds 100 columns
#62558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47273:
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47274:
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#62560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47275:
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L

WARNING: line length of 113 exceeds 100 columns
#62561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47276:
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47277:
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2

WARNING: line length of 121 exceeds 100 columns
#62563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47278:
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#62564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47279:
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L

WARNING: line length of 113 exceeds 100 columns
#62565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47280:
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#62566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47281:
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#62567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47282:
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#62568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47283:
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47284:
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL

WARNING: line length of 121 exceeds 100 columns
#62570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47285:
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L

WARNING: line length of 113 exceeds 100 columns
#62571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47286:
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#62572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47287:
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47288:
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#62574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47289:
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#62575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47290:
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#62576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47291:
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#62577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47292:
+#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#62578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47293:
+#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#62579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47294:
+#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK                                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47295:
+#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#62581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47296:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47297:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#62583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47298:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#62584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47299:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3

WARNING: line length of 113 exceeds 100 columns
#62585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47300:
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47301:
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#62587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47302:
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#62588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47303:
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7

WARNING: line length of 113 exceeds 100 columns
#62589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47304:
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#62590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47305:
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#62591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47306:
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#62592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47307:
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#62593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47308:
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#62594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47309:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#62595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47310:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe

WARNING: line length of 113 exceeds 100 columns
#62596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47311:
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#62597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47312:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#62598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47313:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#62599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47314:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#62600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47315:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13

WARNING: line length of 114 exceeds 100 columns
#62601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47316:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#62602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47317:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#62603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47318:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#62604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47319:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17

WARNING: line length of 114 exceeds 100 columns
#62605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47320:
+#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#62606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47321:
+#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19

WARNING: line length of 121 exceeds 100 columns
#62607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47322:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47323:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47324:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47325:
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47326:
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47327:
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47328:
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47329:
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47330:
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47331:
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47332:
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47333:
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47334:
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47335:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47336:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#62622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47337:
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#62623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47338:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47339:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47340:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47341:
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#62627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47342:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#62628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47343:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47344:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#62630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47345:
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#62631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47346:
+#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#62632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47347:
+#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L

WARNING: line length of 113 exceeds 100 columns
#62635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47350:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#62636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47351:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1

WARNING: line length of 113 exceeds 100 columns
#62637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47352:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#62638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47353:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3

WARNING: line length of 121 exceeds 100 columns
#62639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47354:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47355:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47356:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47357:
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L

WARNING: line length of 113 exceeds 100 columns
#62643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47358:
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47359:
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#62645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47360:
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#62646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47361:
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#62647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47362:
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#62648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47363:
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#62649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47364:
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#62650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47365:
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#62651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47366:
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#62652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47367:
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#62653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47368:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#62654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47369:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#62655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47370:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2

WARNING: line length of 113 exceeds 100 columns
#62656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47371:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3

WARNING: line length of 113 exceeds 100 columns
#62657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47372:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#62658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47373:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#62659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47374:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#62660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47375:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#62661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47376:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#62662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47377:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb

WARNING: line length of 113 exceeds 100 columns
#62663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47378:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc

WARNING: line length of 113 exceeds 100 columns
#62664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47379:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd

WARNING: line length of 114 exceeds 100 columns
#62665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47380:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10

WARNING: line length of 114 exceeds 100 columns
#62666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47381:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#62667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47382:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#62668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47383:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#62669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47384:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#62670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47385:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#62671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47386:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#62672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47387:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#62673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47388:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#62674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47389:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#62675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47390:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#62676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47391:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#62677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47392:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47393:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47394:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47395:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47396:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47397:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47398:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47399:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47400:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47401:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47402:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47403:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47404:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47405:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47406:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47407:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#62693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47408:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#62694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47409:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47410:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#62696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47411:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#62697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47412:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47413:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#62699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47414:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#62700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47415:
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L

WARNING: line length of 114 exceeds 100 columns
#62703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47418:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#62704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47419:
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L

WARNING: line length of 114 exceeds 100 columns
#62707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47422:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#62708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47423:
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#62709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47424:
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#62710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47425:
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#62711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47426:
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7

WARNING: line length of 121 exceeds 100 columns
#62712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47427:
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47428:
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#62714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47429:
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L

WARNING: line length of 113 exceeds 100 columns
#62715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47430:
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47431:
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2

WARNING: line length of 121 exceeds 100 columns
#62717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47432:
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#62718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47433:
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L

WARNING: line length of 113 exceeds 100 columns
#62719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47434:
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#62720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47435:
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#62721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47436:
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#62722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47437:
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47438:
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL

WARNING: line length of 121 exceeds 100 columns
#62724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47439:
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L

WARNING: line length of 113 exceeds 100 columns
#62725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47440:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47441:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#62727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47442:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#62728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47443:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3

WARNING: line length of 113 exceeds 100 columns
#62729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47444:
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47445:
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#62731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47446:
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#62732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47447:
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7

WARNING: line length of 113 exceeds 100 columns
#62733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47448:
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#62734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47449:
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#62735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47450:
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#62736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47451:
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#62737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47452:
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#62738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47453:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#62739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47454:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe

WARNING: line length of 113 exceeds 100 columns
#62740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47455:
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#62741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47456:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#62742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47457:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#62743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47458:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#62744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47459:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13

WARNING: line length of 114 exceeds 100 columns
#62745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47460:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#62746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47461:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#62747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47462:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#62748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47463:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17

WARNING: line length of 114 exceeds 100 columns
#62749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47464:
+#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#62750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47465:
+#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19

WARNING: line length of 121 exceeds 100 columns
#62751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47466:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47467:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47468:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47469:
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47470:
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47471:
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47472:
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47473:
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47474:
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47475:
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47476:
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47477:
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47478:
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47479:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47480:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#62766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47481:
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#62767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47482:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47483:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47484:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47485:
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#62771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47486:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#62772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47487:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47488:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#62774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47489:
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#62775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47490:
+#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#62776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47491:
+#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L

WARNING: line length of 113 exceeds 100 columns
#62779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47494:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#62780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47495:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1

WARNING: line length of 113 exceeds 100 columns
#62781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47496:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#62782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47497:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3

WARNING: line length of 121 exceeds 100 columns
#62783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47498:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47499:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47500:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47501:
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L

WARNING: line length of 113 exceeds 100 columns
#62787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47502:
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47503:
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#62789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47504:
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#62790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47505:
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#62791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47506:
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#62792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47507:
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#62793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47508:
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#62794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47509:
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#62795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47510:
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#62796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47511:
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#62797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47512:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#62798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47513:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#62799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47514:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2

WARNING: line length of 113 exceeds 100 columns
#62800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47515:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3

WARNING: line length of 113 exceeds 100 columns
#62801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47516:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#62802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47517:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#62803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47518:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#62804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47519:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#62805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47520:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#62806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47521:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb

WARNING: line length of 113 exceeds 100 columns
#62807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47522:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc

WARNING: line length of 113 exceeds 100 columns
#62808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47523:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd

WARNING: line length of 114 exceeds 100 columns
#62809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47524:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10

WARNING: line length of 114 exceeds 100 columns
#62810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47525:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#62811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47526:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#62812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47527:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#62813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47528:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#62814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47529:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#62815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47530:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#62816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47531:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#62817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47532:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#62818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47533:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#62819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47534:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#62820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47535:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#62821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47536:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47537:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47538:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47539:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47540:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47541:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47542:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47543:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47544:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47545:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47546:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47547:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47548:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47549:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47550:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47551:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#62837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47552:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#62838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47553:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47554:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#62840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47555:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#62841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47556:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47557:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#62843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47558:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#62844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47559:
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L

WARNING: line length of 114 exceeds 100 columns
#62847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47562:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#62848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47563:
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L

WARNING: line length of 114 exceeds 100 columns
#62851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47566:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#62852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47567:
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#62853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47568:
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#62854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47569:
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#62855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47570:
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7

WARNING: line length of 121 exceeds 100 columns
#62856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47571:
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47572:
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#62858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47573:
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L

WARNING: line length of 113 exceeds 100 columns
#62859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47574:
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47575:
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2

WARNING: line length of 121 exceeds 100 columns
#62861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47576:
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#62862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47577:
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L

WARNING: line length of 113 exceeds 100 columns
#62863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47578:
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#62864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47579:
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#62865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47580:
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#62866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47581:
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47582:
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL

WARNING: line length of 121 exceeds 100 columns
#62868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47583:
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L

WARNING: line length of 113 exceeds 100 columns
#62869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47584:
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#62870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47585:
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#62871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47586:
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#62872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47587:
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#62873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47588:
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#62874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47589:
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#62875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47590:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47591:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#62877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47592:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#62878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47593:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3

WARNING: line length of 113 exceeds 100 columns
#62879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47594:
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#62880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47595:
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#62881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47596:
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#62882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47597:
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7

WARNING: line length of 113 exceeds 100 columns
#62883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47598:
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#62884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47599:
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#62885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47600:
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#62886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47601:
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#62887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47602:
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#62888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47603:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#62889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47604:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe

WARNING: line length of 113 exceeds 100 columns
#62890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47605:
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#62891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47606:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#62892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47607:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#62893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47608:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#62894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47609:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13

WARNING: line length of 114 exceeds 100 columns
#62895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47610:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#62896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47611:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#62897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47612:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#62898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47613:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17

WARNING: line length of 114 exceeds 100 columns
#62899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47614:
+#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#62900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47615:
+#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19

WARNING: line length of 121 exceeds 100 columns
#62901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47616:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47617:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47618:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47619:
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47620:
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47621:
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47622:
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#62908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47623:
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#62909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47624:
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47625:
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47626:
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47627:
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47628:
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47629:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47630:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#62916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47631:
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#62917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47632:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47633:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47634:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47635:
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#62921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47636:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#62922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47637:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47638:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#62924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47639:
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#62925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47640:
+#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#62926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47641:
+#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L

WARNING: line length of 113 exceeds 100 columns
#62929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47644:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#62930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47645:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1

WARNING: line length of 113 exceeds 100 columns
#62931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47646:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#62932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47647:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3

WARNING: line length of 121 exceeds 100 columns
#62933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47648:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47649:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47650:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47651:
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L

WARNING: line length of 113 exceeds 100 columns
#62937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47652:
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#62938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47653:
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#62939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47654:
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#62940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47655:
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#62941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47656:
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#62942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47657:
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#62943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47658:
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#62944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47659:
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#62945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47660:
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#62946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47661:
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#62947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47662:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#62948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47663:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#62949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47664:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2

WARNING: line length of 113 exceeds 100 columns
#62950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47665:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3

WARNING: line length of 113 exceeds 100 columns
#62951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47666:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#62952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47667:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#62953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47668:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#62954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47669:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#62955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47670:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#62956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47671:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb

WARNING: line length of 113 exceeds 100 columns
#62957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47672:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc

WARNING: line length of 113 exceeds 100 columns
#62958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47673:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd

WARNING: line length of 114 exceeds 100 columns
#62959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47674:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10

WARNING: line length of 114 exceeds 100 columns
#62960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47675:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#62961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47676:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#62962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47677:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#62963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47678:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#62964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47679:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#62965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47680:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#62966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47681:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#62967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47682:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#62968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47683:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#62969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47684:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#62970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47685:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#62971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47686:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#62972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47687:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#62973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47688:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#62974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47689:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#62975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47690:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#62976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47691:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#62977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47692:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#62978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47693:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#62979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47694:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#62980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47695:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L

WARNING: line length of 121 exceeds 100 columns
#62981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47696:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#62982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47697:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#62983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47698:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#62984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47699:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#62985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47700:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#62986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47701:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#62987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47702:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#62988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47703:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#62989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47704:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#62990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47705:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#62991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47706:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#62992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47707:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#62993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47708:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#62994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47709:
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L

WARNING: line length of 114 exceeds 100 columns
#62996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47711:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#62997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47712:
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L

WARNING: line length of 114 exceeds 100 columns
#63000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47715:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#63001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47716:
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#63002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47717:
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1

WARNING: line length of 113 exceeds 100 columns
#63003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47718:
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2

WARNING: line length of 113 exceeds 100 columns
#63004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47719:
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7

WARNING: line length of 121 exceeds 100 columns
#63005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47720:
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#63006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47721:
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL

WARNING: line length of 121 exceeds 100 columns
#63007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47722:
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L

WARNING: line length of 113 exceeds 100 columns
#63008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47723:
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#63009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47724:
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2

WARNING: line length of 121 exceeds 100 columns
#63010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47725:
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L

WARNING: line length of 121 exceeds 100 columns
#63011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47726:
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L

WARNING: line length of 113 exceeds 100 columns
#63012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47727:
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#63013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47728:
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#63014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47729:
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#63015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47730:
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47731:
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL

WARNING: line length of 121 exceeds 100 columns
#63017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47732:
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L

WARNING: line length of 113 exceeds 100 columns
#63018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47733:
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0

WARNING: line length of 121 exceeds 100 columns
#63019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47734:
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#63020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47735:
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0

WARNING: line length of 114 exceeds 100 columns
#63021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47736:
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT                                 0x1f

WARNING: line length of 121 exceeds 100 columns
#63022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47737:
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0x7FFFFFFFL

WARNING: line length of 121 exceeds 100 columns
#63023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47738:
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK                                   0x80000000L

WARNING: line length of 113 exceeds 100 columns
#63024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47739:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#63025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47740:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1

WARNING: line length of 113 exceeds 100 columns
#63026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47741:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2

WARNING: line length of 113 exceeds 100 columns
#63027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47742:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3

WARNING: line length of 113 exceeds 100 columns
#63028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47743:
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#63029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47744:
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#63030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47745:
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6

WARNING: line length of 113 exceeds 100 columns
#63031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47746:
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7

WARNING: line length of 113 exceeds 100 columns
#63032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47747:
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#63033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47748:
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9

WARNING: line length of 113 exceeds 100 columns
#63034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47749:
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa

WARNING: line length of 113 exceeds 100 columns
#63035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47750:
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb

WARNING: line length of 113 exceeds 100 columns
#63036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47751:
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#63037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47752:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd

WARNING: line length of 113 exceeds 100 columns
#63038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47753:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe

WARNING: line length of 113 exceeds 100 columns
#63039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47754:
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#63040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47755:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10

WARNING: line length of 114 exceeds 100 columns
#63041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47756:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#63042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47757:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12

WARNING: line length of 114 exceeds 100 columns
#63043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47758:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13

WARNING: line length of 114 exceeds 100 columns
#63044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47759:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14

WARNING: line length of 114 exceeds 100 columns
#63045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47760:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#63046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47761:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16

WARNING: line length of 114 exceeds 100 columns
#63047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47762:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17

WARNING: line length of 114 exceeds 100 columns
#63048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47763:
+#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18

WARNING: line length of 114 exceeds 100 columns
#63049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47764:
+#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19

WARNING: line length of 121 exceeds 100 columns
#63050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47765:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47766:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#63052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47767:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L

WARNING: line length of 121 exceeds 100 columns
#63053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47768:
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#63054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47769:
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#63055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47770:
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#63056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47771:
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L

WARNING: line length of 121 exceeds 100 columns
#63057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47772:
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L

WARNING: line length of 121 exceeds 100 columns
#63058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47773:
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#63059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47774:
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L

WARNING: line length of 121 exceeds 100 columns
#63060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47775:
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#63061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47776:
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L

WARNING: line length of 121 exceeds 100 columns
#63062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47777:
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#63063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47778:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L

WARNING: line length of 121 exceeds 100 columns
#63064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47779:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#63065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47780:
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#63066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47781:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L

WARNING: line length of 121 exceeds 100 columns
#63067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47782:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#63068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47783:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L

WARNING: line length of 121 exceeds 100 columns
#63069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47784:
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#63070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47785:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L

WARNING: line length of 121 exceeds 100 columns
#63071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47786:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#63072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47787:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L

WARNING: line length of 121 exceeds 100 columns
#63073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47788:
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#63074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47789:
+#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L

WARNING: line length of 121 exceeds 100 columns
#63075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47790:
+#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L

WARNING: line length of 113 exceeds 100 columns
#63078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47793:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#63079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47794:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1

WARNING: line length of 113 exceeds 100 columns
#63080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47795:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#63081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47796:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3

WARNING: line length of 121 exceeds 100 columns
#63082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47797:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47798:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#63084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47799:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#63085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47800:
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L

WARNING: line length of 113 exceeds 100 columns
#63086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47801:
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#63087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47802:
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8

WARNING: line length of 114 exceeds 100 columns
#63088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47803:
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#63089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47804:
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#63090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47805:
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L

WARNING: line length of 121 exceeds 100 columns
#63091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47806:
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47807:
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0

WARNING: line length of 114 exceeds 100 columns
#63093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47808:
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10

WARNING: line length of 121 exceeds 100 columns
#63094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47809:
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL

WARNING: line length of 121 exceeds 100 columns
#63095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47810:
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47811:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#63097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47812:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1

WARNING: line length of 113 exceeds 100 columns
#63098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47813:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2

WARNING: line length of 113 exceeds 100 columns
#63099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47814:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3

WARNING: line length of 113 exceeds 100 columns
#63100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47815:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4

WARNING: line length of 113 exceeds 100 columns
#63101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47816:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5

WARNING: line length of 113 exceeds 100 columns
#63102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47817:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8

WARNING: line length of 113 exceeds 100 columns
#63103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47818:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9

WARNING: line length of 113 exceeds 100 columns
#63104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47819:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa

WARNING: line length of 113 exceeds 100 columns
#63105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47820:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb

WARNING: line length of 113 exceeds 100 columns
#63106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47821:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc

WARNING: line length of 113 exceeds 100 columns
#63107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47822:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd

WARNING: line length of 114 exceeds 100 columns
#63108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47823:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10

WARNING: line length of 114 exceeds 100 columns
#63109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47824:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11

WARNING: line length of 114 exceeds 100 columns
#63110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47825:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#63111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47826:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#63112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47827:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14

WARNING: line length of 114 exceeds 100 columns
#63113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47828:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15

WARNING: line length of 114 exceeds 100 columns
#63114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47829:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#63115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47830:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b

WARNING: line length of 114 exceeds 100 columns
#63116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47831:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c

WARNING: line length of 114 exceeds 100 columns
#63117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47832:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d

WARNING: line length of 114 exceeds 100 columns
#63118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47833:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e

WARNING: line length of 114 exceeds 100 columns
#63119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47834:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f

WARNING: line length of 121 exceeds 100 columns
#63120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47835:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47836:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L

WARNING: line length of 121 exceeds 100 columns
#63122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47837:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#63123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47838:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L

WARNING: line length of 121 exceeds 100 columns
#63124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47839:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L

WARNING: line length of 121 exceeds 100 columns
#63125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47840:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L

WARNING: line length of 121 exceeds 100 columns
#63126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47841:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#63127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47842:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L

WARNING: line length of 121 exceeds 100 columns
#63128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47843:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#63129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47844:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L

WARNING: line length of 121 exceeds 100 columns
#63130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47845:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L

WARNING: line length of 121 exceeds 100 columns
#63131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47846:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L

WARNING: line length of 121 exceeds 100 columns
#63132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47847:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L

WARNING: line length of 121 exceeds 100 columns
#63133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47848:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L

WARNING: line length of 121 exceeds 100 columns
#63134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47849:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#63135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47850:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#63136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47851:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L

WARNING: line length of 121 exceeds 100 columns
#63137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47852:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L

WARNING: line length of 121 exceeds 100 columns
#63138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47853:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#63139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47854:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L

WARNING: line length of 121 exceeds 100 columns
#63140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47855:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L

WARNING: line length of 121 exceeds 100 columns
#63141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47856:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L

WARNING: line length of 121 exceeds 100 columns
#63142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47857:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L

WARNING: line length of 121 exceeds 100 columns
#63143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47858:
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L

WARNING: line length of 114 exceeds 100 columns
#63146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47861:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10

WARNING: line length of 121 exceeds 100 columns
#63147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47862:
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L

WARNING: line length of 114 exceeds 100 columns
#63149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47864:
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#63150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47865:
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 114 exceeds 100 columns
#63153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47868:
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#63154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47869:
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 114 exceeds 100 columns
#63157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47872:
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#63158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47873:
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 114 exceeds 100 columns
#63161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47876:
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18

WARNING: line length of 121 exceeds 100 columns
#63162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47877:
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#63165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47880:
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#63166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47881:
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#63167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47882:
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47883:
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#63171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47886:
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#63172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47887:
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#63173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47888:
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47889:
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#63177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47892:
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#63178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47893:
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#63179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47894:
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47895:
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#63183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47898:
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#63184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47899:
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4

WARNING: line length of 121 exceeds 100 columns
#63185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47900:
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#63186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47901:
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L

WARNING: line length of 113 exceeds 100 columns
#63189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47904:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#63190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47905:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2

WARNING: line length of 121 exceeds 100 columns
#63191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47906:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#63192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47907:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#63193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47908:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47909:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47910:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47911:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47912:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47913:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47914:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#63200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47915:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#63201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47916:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#63202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47917:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#63203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47918:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47919:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47920:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#63206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47921:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#63207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47922:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47923:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#63209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47924:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#63210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47925:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#63211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47926:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#63212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47927:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L

WARNING: line length of 113 exceeds 100 columns
#63213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47928:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#63214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47929:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#63215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47930:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47931:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47932:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#63218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47933:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#63219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47934:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47935:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47936:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#63222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47937:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#63223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47938:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47939:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47940:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#63226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47941:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47942:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47943:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47944:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#63230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47945:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47946:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47947:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47948:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#63234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47949:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47950:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47951:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47952:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47953:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47954:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47955:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47956:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47957:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47958:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47959:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47960:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47961:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47962:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47963:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47964:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47965:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47966:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47967:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47968:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47969:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47970:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47971:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47972:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47973:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47974:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47975:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47976:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47977:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47978:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47979:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47980:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47981:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47982:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47983:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47984:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47985:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47986:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47987:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47988:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47989:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47990:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47991:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47992:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47993:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47994:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47995:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47996:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47997:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47998:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:47999:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48000:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48001:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48002:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48003:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48004:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48005:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48006:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48007:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48008:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48009:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48010:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48011:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48012:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48013:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48014:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48015:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48016:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48017:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48018:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48019:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48020:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48021:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48022:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48023:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48024:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48025:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48026:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48027:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48028:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48029:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48030:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48031:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48032:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48033:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48034:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48035:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48036:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48037:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48038:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48039:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48040:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48041:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48042:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48043:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48044:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48045:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48046:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48047:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48048:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48049:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48050:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48051:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48052:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48053:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48054:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48055:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48056:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48057:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48058:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48059:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48060:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48061:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48062:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48063:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48064:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48065:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48066:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48067:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48068:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48069:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48070:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48071:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48072:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48073:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48074:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48075:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48076:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48077:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48078:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48079:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48080:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48081:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48082:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48083:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48084:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48085:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48086:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48087:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48088:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#63374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48089:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#63375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48090:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48091:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48092:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#63378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48093:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#63379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48094:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48095:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48096:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#63382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48097:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#63383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48098:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48099:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48100:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#63386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48101:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48102:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48103:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48104:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#63390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48105:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48106:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48107:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48108:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#63394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48109:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48110:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48111:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#63397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48112:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48113:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48114:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48115:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48116:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48117:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48118:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48119:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48120:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48121:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48122:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48123:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48124:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48125:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48126:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48127:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48128:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48129:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48130:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48131:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48132:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48133:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48134:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48135:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48136:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48137:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48138:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48139:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48140:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48141:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48142:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48143:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48144:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#63430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48145:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#63431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48146:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#63432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48147:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#63433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48148:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48149:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48150:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48151:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48152:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48153:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48154:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48155:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48156:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48157:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48158:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48159:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48160:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48161:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48162:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48163:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48164:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48165:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48166:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48167:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48168:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48169:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48170:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48171:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48172:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48173:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48174:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48175:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48176:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48177:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48178:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48179:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48180:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48181:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48182:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48183:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48184:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48185:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48186:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48187:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48188:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48189:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48190:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48191:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48192:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48193:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48194:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48195:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48196:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48197:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48198:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48199:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48200:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48201:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48202:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48203:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48204:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48205:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48206:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48207:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48208:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48209:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48210:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48211:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48212:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48213:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48214:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48215:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48216:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48217:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48218:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48219:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48220:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48221:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48222:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48223:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48224:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48225:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48226:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48227:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48228:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48229:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48230:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48231:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48232:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48233:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48234:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48235:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48236:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48237:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48238:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48239:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48240:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#63526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48241:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#63527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48242:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#63528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48243:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#63529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48244:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48245:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48246:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48247:
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48248:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#63534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48249:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#63535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48250:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8

WARNING: line length of 121 exceeds 100 columns
#63536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48251:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#63537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48252:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#63538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48253:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L

WARNING: line length of 113 exceeds 100 columns
#63539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48254:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#63540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48255:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL

WARNING: line length of 113 exceeds 100 columns
#63541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48256:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#63542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48257:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#63543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48258:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48259:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48260:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2

WARNING: line length of 121 exceeds 100 columns
#63546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48261:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL

WARNING: line length of 113 exceeds 100 columns
#63547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48262:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#63548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48263:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#63549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48264:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#63550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48265:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10

WARNING: line length of 121 exceeds 100 columns
#63551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48266:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#63552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48267:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#63553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48268:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#63554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48269:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L

WARNING: line length of 113 exceeds 100 columns
#63555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48270:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#63556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48271:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#63557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48272:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#63558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48273:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#63559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48274:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48275:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48276:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#63562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48277:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#63563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48278:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48279:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48280:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#63566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48281:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#63567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48282:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48283:
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48284:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#63570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48285:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#63571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48286:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#63572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48287:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#63573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48288:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6

WARNING: line length of 121 exceeds 100 columns
#63574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48289:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#63575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48290:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#63576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48291:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#63577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48292:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#63578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48293:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#63579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48294:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48295:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#63581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48296:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#63582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48297:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48298:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#63584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48299:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#63585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48300:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#63586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48301:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7

WARNING: line length of 121 exceeds 100 columns
#63587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48302:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#63588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48303:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#63589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48304:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#63590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48305:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#63591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48306:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#63592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48307:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#63593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48308:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48309:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48310:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#63596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48311:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#63597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48312:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48313:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48314:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#63600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48315:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#63601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48316:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48317:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#63603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48318:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#63604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48319:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#63605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48320:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#63606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48321:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#63607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48322:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#63608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48323:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48324:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#63610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48325:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48326:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#63612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48327:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48328:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#63614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48329:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48330:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#63616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48331:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48332:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#63618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48333:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48334:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48335:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48336:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#63622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48337:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48338:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#63624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48339:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48340:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48341:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48342:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#63628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48343:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48344:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#63630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48345:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48346:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48347:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48348:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#63634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48349:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48350:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#63636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48351:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48352:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#63638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48353:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48354:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48355:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48356:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48357:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48358:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48359:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48360:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48361:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48362:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48363:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48364:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48365:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48366:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48367:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48368:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48369:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48370:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48371:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48372:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48373:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48374:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48375:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48376:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48377:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48378:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48379:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48380:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48381:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48382:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48383:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48384:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48385:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48386:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48387:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48388:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48389:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48390:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48391:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48392:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48393:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48394:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48395:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48396:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48397:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48398:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48399:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48400:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48401:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48402:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48403:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48404:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48405:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48406:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48407:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48408:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48409:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48410:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48411:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48412:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48413:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48414:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48415:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48416:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48417:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48418:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48419:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48420:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48421:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48422:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48423:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48424:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48425:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48426:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48427:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48428:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48429:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48430:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48431:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48432:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48433:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48434:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48435:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48436:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48437:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48438:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48439:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48440:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48441:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48442:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48443:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48444:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48445:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48446:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48447:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48448:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48449:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48450:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48451:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48452:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48453:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48454:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48455:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48456:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48457:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48458:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48459:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48460:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48461:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48462:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48463:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48464:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48465:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48466:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48467:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48468:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48469:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48470:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48471:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48472:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48473:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48474:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48475:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48476:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48477:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48478:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48479:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48480:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48481:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48482:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48483:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48484:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48485:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48486:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48487:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48488:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48489:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48490:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#63776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48491:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#63777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48492:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48493:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48494:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#63780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48495:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#63781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48496:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48497:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#63783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48498:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#63784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48499:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#63785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48500:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#63786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48501:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#63787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48502:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#63788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48503:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#63789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48504:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#63790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48505:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#63791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48506:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#63792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48507:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48508:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#63794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48509:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48510:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#63796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48511:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48512:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#63798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48513:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48514:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#63800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48515:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48516:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#63802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48517:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48518:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48519:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48520:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#63806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48521:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48522:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#63808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48523:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48524:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48525:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48526:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#63812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48527:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#63813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48528:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#63814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48529:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#63815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48530:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#63816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48531:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#63817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48532:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#63818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48533:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48534:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#63820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48535:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48536:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#63822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48537:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48538:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48539:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48540:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48541:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48542:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48543:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48544:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48545:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48546:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48547:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48548:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48549:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48550:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48551:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48552:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48553:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48554:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48555:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48556:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48557:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48558:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48559:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48560:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48561:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48562:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48563:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48564:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48565:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48566:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48567:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48568:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48569:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48570:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#63856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48571:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#63857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48572:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#63858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48573:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#63859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48574:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48575:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48576:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48577:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48578:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48579:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48580:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48581:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48582:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48583:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48584:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48585:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48586:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48587:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48588:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48589:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48590:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48591:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48592:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48593:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48594:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48595:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48596:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48597:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48598:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48599:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48600:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48601:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48602:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48603:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48604:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48605:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48606:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48607:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48608:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48609:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48610:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48611:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48612:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48613:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48614:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48615:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48616:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48617:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48618:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48619:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48620:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48621:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48622:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48623:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48624:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48625:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48626:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48627:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48628:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48629:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48630:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48631:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48632:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48633:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48634:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48635:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48636:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48637:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48638:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48639:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48640:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48641:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48642:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48643:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48644:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48645:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48646:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48647:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48648:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48649:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48650:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48651:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48652:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48653:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48654:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48655:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48656:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48657:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48658:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48659:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48660:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48661:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48662:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48663:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48664:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48665:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48666:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#63952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48667:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#63953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48668:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#63954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48669:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#63955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48670:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#63956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48671:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#63957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48672:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#63958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48673:
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#63959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48674:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#63960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48675:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#63961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48676:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#63962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48677:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#63963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48678:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#63964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48679:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#63965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48680:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#63966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48681:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#63967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48682:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#63968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48683:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#63969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48684:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#63970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48685:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#63971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48686:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#63972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48687:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#63973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48688:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#63974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48689:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#63975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48690:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#63976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48691:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L

WARNING: line length of 121 exceeds 100 columns
#63977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48692:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#63978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48693:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#63979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48694:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L

WARNING: line length of 121 exceeds 100 columns
#63980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48695:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L

WARNING: line length of 121 exceeds 100 columns
#63981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48696:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#63982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48697:
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L

WARNING: line length of 113 exceeds 100 columns
#63985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48700:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#63986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48701:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2

WARNING: line length of 121 exceeds 100 columns
#63987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48702:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#63988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48703:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#63989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48704:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48705:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48706:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48707:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48708:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#63994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48709:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#63995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48710:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#63996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48711:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#63997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48712:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#63998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48713:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#63999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48714:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48715:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48716:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#64002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48717:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#64003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48718:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#64004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48719:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#64005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48720:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#64006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48721:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#64007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48722:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#64008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48723:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L

WARNING: line length of 113 exceeds 100 columns
#64009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48724:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48725:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48726:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48727:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48728:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48729:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48730:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48731:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48732:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48733:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48734:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48735:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48736:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48737:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48738:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48739:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48740:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48741:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48742:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48743:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48744:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48745:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48746:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48747:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48748:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48749:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48750:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48751:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48752:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48753:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48754:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48755:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48756:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48757:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48758:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48759:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48760:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48761:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48762:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48763:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48764:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48765:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48766:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48767:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48768:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48769:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48770:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48771:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48772:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48773:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48774:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48775:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48776:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48777:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48778:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48779:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48780:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48781:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48782:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48783:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48784:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48785:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48786:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48787:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48788:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48789:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48790:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48791:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48792:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48793:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48794:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48795:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48796:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48797:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48798:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48799:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48800:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48801:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48802:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48803:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48804:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48805:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48806:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48807:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48808:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48809:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48810:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48811:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48812:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48813:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48814:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48815:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48816:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48817:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48818:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48819:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48820:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48821:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48822:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48823:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48824:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48825:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48826:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48827:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48828:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48829:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48830:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48831:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48832:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48833:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48834:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48835:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48836:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48837:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48838:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48839:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48840:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48841:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48842:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48843:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48844:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48845:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48846:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48847:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48848:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48849:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48850:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48851:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48852:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48853:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48854:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48855:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48856:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48857:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48858:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48859:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48860:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48861:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48862:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48863:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48864:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48865:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48866:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48867:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48868:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48869:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48870:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48871:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48872:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48873:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48874:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48875:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48876:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48877:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48878:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48879:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48880:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48881:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48882:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48883:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48884:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48885:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48886:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48887:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48888:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48889:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48890:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48891:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48892:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48893:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48894:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48895:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48896:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48897:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48898:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48899:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48900:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48901:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48902:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48903:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48904:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48905:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48906:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48907:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48908:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48909:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48910:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48911:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48912:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48913:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48914:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48915:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48916:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48917:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48918:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48919:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48920:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48921:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48922:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48923:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48924:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48925:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48926:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48927:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48928:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48929:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48930:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48931:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48932:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48933:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48934:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48935:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48936:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48937:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48938:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48939:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48940:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48941:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48942:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48943:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48944:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48945:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48946:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48947:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48948:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48949:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48950:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48951:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48952:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48953:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48954:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48955:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48956:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48957:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48958:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48959:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48960:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48961:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48962:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48963:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48964:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48965:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48966:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48967:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48968:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48969:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48970:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48971:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48972:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48973:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48974:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48975:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48976:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48977:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48978:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48979:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48980:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48981:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48982:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48983:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48984:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48985:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48986:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48987:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48988:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48989:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48990:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48991:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48992:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48993:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48994:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48995:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48996:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48997:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48998:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:48999:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49000:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49001:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49002:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49003:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49004:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49005:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49006:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49007:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49008:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49009:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49010:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49011:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49012:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49013:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49014:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49015:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49016:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49017:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49018:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49019:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49020:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49021:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49022:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49023:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49024:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49025:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49026:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49027:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49028:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49029:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49030:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49031:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49032:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49033:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49034:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49035:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49036:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49037:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49038:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49039:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49040:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49041:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49042:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49043:
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49044:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#64330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49045:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#64331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49046:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8

WARNING: line length of 121 exceeds 100 columns
#64332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49047:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#64333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49048:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#64334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49049:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L

WARNING: line length of 113 exceeds 100 columns
#64335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49050:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#64336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49051:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL

WARNING: line length of 113 exceeds 100 columns
#64337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49052:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#64338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49053:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#64339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49054:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49055:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49056:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2

WARNING: line length of 121 exceeds 100 columns
#64342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49057:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL

WARNING: line length of 113 exceeds 100 columns
#64343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49058:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#64344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49059:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#64345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49060:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#64346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49061:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10

WARNING: line length of 121 exceeds 100 columns
#64347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49062:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#64348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49063:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#64349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49064:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#64350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49065:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L

WARNING: line length of 113 exceeds 100 columns
#64351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49066:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#64352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49067:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#64353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49068:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#64354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49069:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#64355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49070:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49071:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49072:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#64358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49073:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#64359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49074:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49075:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49076:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#64362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49077:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#64363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49078:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49079:
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49080:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#64366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49081:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#64367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49082:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#64368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49083:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#64369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49084:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6

WARNING: line length of 121 exceeds 100 columns
#64370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49085:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#64371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49086:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#64372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49087:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#64373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49088:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#64374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49089:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#64375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49090:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#64376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49091:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#64377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49092:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#64378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49093:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49094:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#64380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49095:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#64381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49096:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#64382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49097:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7

WARNING: line length of 121 exceeds 100 columns
#64383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49098:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#64384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49099:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#64385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49100:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#64386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49101:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#64387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49102:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#64388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49103:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#64389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49104:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49105:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49106:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#64392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49107:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#64393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49108:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49109:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49110:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#64396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49111:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#64397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49112:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49113:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#64399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49114:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#64400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49115:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#64401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49116:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#64402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49117:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#64403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49118:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#64404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49119:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49120:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#64406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49121:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49122:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#64408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49123:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49124:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#64410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49125:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49126:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#64412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49127:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49128:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#64414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49129:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49130:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49131:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49132:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#64418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49133:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49134:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#64420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49135:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49136:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49137:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49138:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#64424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49139:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49140:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#64426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49141:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49142:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49143:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49144:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#64430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49145:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49146:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#64432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49147:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49148:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#64434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49149:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49150:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49151:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49152:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49153:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49154:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49155:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49156:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49157:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49158:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49159:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49160:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49161:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49162:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49163:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49164:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49165:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49166:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49167:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49168:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49169:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49170:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49171:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49172:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49173:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49174:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49175:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49176:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49177:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49178:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49179:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49180:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49181:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49182:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49183:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49184:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49185:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49186:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49187:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49188:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49189:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49190:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49191:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49192:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49193:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49194:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49195:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49196:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49197:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49198:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49199:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49200:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49201:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49202:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49203:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49204:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49205:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49206:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49207:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49208:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49209:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49210:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49211:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49212:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49213:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49214:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49215:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49216:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49217:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49218:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49219:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49220:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49221:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49222:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49223:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49224:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49225:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49226:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49227:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49228:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49229:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49230:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49231:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49232:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49233:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49234:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49235:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49236:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49237:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49238:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49239:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49240:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49241:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49242:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49243:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49244:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49245:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49246:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49247:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49248:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49249:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49250:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49251:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49252:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49253:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49254:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49255:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49256:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49257:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49258:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49259:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49260:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49261:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49262:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49263:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49264:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49265:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49266:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49267:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49268:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49269:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49270:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49271:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49272:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49273:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49274:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49275:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49276:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49277:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49278:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49279:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49280:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49281:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49282:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49283:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49284:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49285:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49286:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#64572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49287:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#64573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49288:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49289:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49290:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#64576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49291:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#64577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49292:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49293:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49294:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#64580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49295:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#64581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49296:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49297:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#64583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49298:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#64584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49299:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#64585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49300:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#64586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49301:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#64587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49302:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#64588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49303:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49304:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#64590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49305:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49306:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#64592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49307:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49308:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#64594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49309:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49310:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#64596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49311:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49312:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#64598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49313:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49314:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49315:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49316:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#64602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49317:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49318:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#64604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49319:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49320:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49321:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49322:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#64608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49323:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#64609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49324:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#64610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49325:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49326:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49327:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49328:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#64614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49329:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49330:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#64616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49331:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49332:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#64618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49333:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49334:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49335:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49336:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49337:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49338:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49339:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49340:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49341:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49342:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49343:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49344:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49345:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49346:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49347:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49348:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49349:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49350:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49351:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49352:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49353:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49354:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49355:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49356:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49357:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49358:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49359:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49360:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49361:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49362:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49363:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49364:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49365:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49366:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#64652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49367:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#64653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49368:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#64654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49369:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#64655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49370:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49371:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49372:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49373:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49374:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49375:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49376:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49377:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49378:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49379:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49380:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49381:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49382:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49383:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49384:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49385:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49386:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49387:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49388:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49389:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49390:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49391:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49392:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49393:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49394:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49395:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49396:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49397:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49398:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49399:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49400:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49401:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49402:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49403:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49404:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49405:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49406:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49407:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49408:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49409:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49410:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49411:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49412:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49413:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49414:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49415:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49416:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49417:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49418:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49419:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49420:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49421:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49422:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49423:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49424:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49425:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49426:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49427:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49428:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49429:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49430:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49431:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49432:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49433:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49434:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49435:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49436:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49437:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49438:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49439:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49440:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49441:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49442:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49443:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49444:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49445:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49446:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49447:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49448:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49449:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49450:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49451:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49452:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49453:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49454:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49455:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49456:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49457:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49458:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49459:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49460:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49461:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49462:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#64748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49463:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#64749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49464:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#64750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49465:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#64751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49466:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49467:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49468:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49469:
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49470:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#64756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49471:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#64757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49472:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#64758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49473:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#64759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49474:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#64760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49475:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#64761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49476:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#64762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49477:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#64763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49478:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#64764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49479:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#64765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49480:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#64766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49481:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#64767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49482:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#64768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49483:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#64769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49484:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#64770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49485:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#64771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49486:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#64772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49487:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L

WARNING: line length of 121 exceeds 100 columns
#64773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49488:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#64774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49489:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#64775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49490:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L

WARNING: line length of 121 exceeds 100 columns
#64776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49491:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L

WARNING: line length of 121 exceeds 100 columns
#64777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49492:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#64778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49493:
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L

WARNING: line length of 113 exceeds 100 columns
#64781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49496:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#64782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49497:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2

WARNING: line length of 121 exceeds 100 columns
#64783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49498:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#64784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49499:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#64785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49500:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#64786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49501:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49502:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#64788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49503:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49504:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#64790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49505:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#64791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49506:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#64792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49507:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#64793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49508:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#64794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49509:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#64795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49510:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49511:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#64797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49512:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#64798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49513:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#64799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49514:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#64800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49515:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#64801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49516:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#64802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49517:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#64803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49518:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#64804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49519:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L

WARNING: line length of 113 exceeds 100 columns
#64805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49520:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49521:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49522:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49523:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49524:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49525:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49526:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49527:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49528:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49529:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49530:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49531:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49532:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49533:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49534:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49535:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49536:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49537:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49538:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49539:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49540:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49541:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49542:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49543:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49544:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49545:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49546:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49547:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49548:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49549:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49550:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49551:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49552:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49553:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49554:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49555:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49556:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49557:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49558:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49559:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49560:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49561:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49562:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49563:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49564:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49565:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49566:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49567:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49568:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49569:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49570:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49571:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49572:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49573:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49574:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49575:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49576:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49577:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49578:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49579:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49580:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49581:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49582:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49583:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49584:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49585:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49586:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49587:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49588:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49589:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49590:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49591:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49592:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49593:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49594:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49595:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49596:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49597:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49598:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49599:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49600:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49601:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49602:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49603:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49604:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49605:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49606:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49607:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49608:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49609:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49610:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49611:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49612:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49613:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49614:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49615:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49616:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49617:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49618:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49619:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49620:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49621:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49622:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49623:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49624:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49625:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49626:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49627:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49628:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49629:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49630:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49631:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49632:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49633:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49634:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49635:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49636:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49637:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49638:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49639:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49640:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49641:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49642:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49643:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49644:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49645:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49646:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49647:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49648:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49649:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49650:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49651:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49652:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49653:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49654:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49655:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49656:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49657:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49658:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49659:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49660:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49661:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49662:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49663:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49664:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49665:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49666:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49667:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49668:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49669:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49670:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49671:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49672:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#64958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49673:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#64959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49674:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#64960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49675:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#64961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49676:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49677:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49678:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49679:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49680:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49681:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49682:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49683:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49684:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49685:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49686:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49687:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49688:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#64974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49689:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#64975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49690:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#64976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49691:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#64977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49692:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49693:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49694:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49695:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49696:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49697:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49698:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49699:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49700:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#64986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49701:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#64987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49702:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#64988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49703:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#64989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49704:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49705:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49706:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#64992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49707:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#64993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49708:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#64994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49709:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#64995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49710:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#64996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49711:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#64997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49712:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#64998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49713:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#64999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49714:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49715:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49716:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49717:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49718:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49719:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49720:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49721:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49722:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49723:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49724:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49725:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49726:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49727:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49728:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49729:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49730:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49731:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49732:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49733:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49734:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49735:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49736:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49737:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49738:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49739:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49740:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49741:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49742:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49743:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49744:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49745:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49746:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49747:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49748:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49749:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49750:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49751:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49752:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49753:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49754:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49755:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49756:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49757:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49758:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49759:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49760:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49761:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49762:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49763:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49764:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49765:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49766:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49767:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49768:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49769:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49770:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49771:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49772:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49773:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49774:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49775:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49776:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49777:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49778:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49779:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49780:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49781:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49782:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49783:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49784:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49785:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49786:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49787:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49788:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49789:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49790:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49791:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49792:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49793:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49794:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49795:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49796:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49797:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49798:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49799:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49800:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49801:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49802:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49803:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49804:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49805:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49806:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49807:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49808:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49809:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49810:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49811:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49812:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49813:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49814:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49815:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49816:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49817:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49818:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49819:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49820:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49821:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49822:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49823:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49824:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49825:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49826:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49827:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49828:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49829:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49830:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49831:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49832:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49833:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49834:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49835:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49836:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49837:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49838:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49839:
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49840:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#65126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49841:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#65127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49842:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8

WARNING: line length of 121 exceeds 100 columns
#65128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49843:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#65129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49844:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#65130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49845:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L

WARNING: line length of 113 exceeds 100 columns
#65131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49846:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#65132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49847:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL

WARNING: line length of 113 exceeds 100 columns
#65133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49848:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#65134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49849:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#65135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49850:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49851:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49852:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2

WARNING: line length of 121 exceeds 100 columns
#65138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49853:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL

WARNING: line length of 113 exceeds 100 columns
#65139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49854:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#65140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49855:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#65141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49856:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#65142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49857:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10

WARNING: line length of 121 exceeds 100 columns
#65143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49858:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#65144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49859:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#65145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49860:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#65146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49861:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L

WARNING: line length of 113 exceeds 100 columns
#65147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49862:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#65148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49863:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#65149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49864:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#65150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49865:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#65151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49866:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49867:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49868:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#65154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49869:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#65155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49870:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49871:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49872:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#65158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49873:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#65159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49874:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49875:
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49876:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#65162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49877:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#65163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49878:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#65164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49879:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#65165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49880:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6

WARNING: line length of 121 exceeds 100 columns
#65166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49881:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#65167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49882:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#65168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49883:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#65169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49884:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#65170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49885:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#65171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49886:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#65172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49887:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#65173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49888:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#65174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49889:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49890:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#65176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49891:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#65177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49892:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#65178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49893:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7

WARNING: line length of 121 exceeds 100 columns
#65179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49894:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#65180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49895:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#65181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49896:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#65182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49897:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#65183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49898:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49899:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49900:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49901:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49902:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49903:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49904:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49905:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49906:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49907:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49908:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49909:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#65195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49910:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49911:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#65197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49912:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49913:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#65199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49914:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49915:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49916:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#65202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49917:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49918:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#65204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49919:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49920:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#65206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49921:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49922:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#65208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49923:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49924:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#65210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49925:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49926:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49927:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49928:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#65214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49929:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49930:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#65216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49931:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49932:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49933:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49934:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#65220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49935:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49936:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#65222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49937:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49938:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49939:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49940:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#65226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49941:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49942:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#65228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49943:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49944:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#65230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49945:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49946:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49947:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49948:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49949:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49950:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49951:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49952:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49953:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49954:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49955:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49956:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49957:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49958:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49959:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49960:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49961:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49962:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49963:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49964:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49965:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49966:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49967:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49968:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49969:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49970:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49971:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49972:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49973:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49974:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49975:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49976:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49977:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49978:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49979:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49980:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49981:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49982:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49983:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49984:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49985:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49986:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49987:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49988:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49989:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49990:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49991:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49992:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49993:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49994:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49995:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49996:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49997:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49998:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:49999:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50000:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50001:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50002:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50003:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50004:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50005:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50006:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50007:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50008:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50009:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50010:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50011:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50012:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50013:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50014:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50015:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50016:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50017:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50018:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50019:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50020:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50021:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50022:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50023:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50024:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50025:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50026:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50027:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50028:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50029:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50030:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50031:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50032:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50033:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50034:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50035:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50036:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50037:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50038:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50039:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50040:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50041:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50042:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50043:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50044:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50045:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50046:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50047:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50048:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50049:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50050:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50051:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50052:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50053:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50054:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50055:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50056:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50057:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50058:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50059:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50060:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50061:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50062:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50063:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50064:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50065:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50066:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50067:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50068:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50069:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50070:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50071:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50072:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50073:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50074:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50075:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50076:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50077:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50078:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50079:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50080:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50081:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50082:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50083:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50084:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50085:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50086:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50087:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50088:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50089:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50090:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50091:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50092:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50093:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#65379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50094:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50095:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#65381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50096:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50097:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#65383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50098:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50099:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50100:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#65386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50101:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50102:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#65388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50103:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50104:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#65390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50105:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50106:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#65392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50107:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50108:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#65394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50109:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50110:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50111:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50112:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#65398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50113:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50114:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#65400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50115:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50116:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50117:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50118:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#65404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50119:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50120:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#65406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50121:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50122:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50123:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50124:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#65410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50125:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50126:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#65412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50127:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50128:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#65414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50129:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50130:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50131:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50132:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50133:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50134:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50135:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50136:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50137:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50138:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50139:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50140:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50141:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50142:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50143:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50144:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50145:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50146:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50147:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50148:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50149:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50150:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50151:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50152:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50153:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50154:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50155:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50156:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50157:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50158:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50159:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50160:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50161:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50162:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#65448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50163:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#65449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50164:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#65450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50165:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#65451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50166:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50167:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50168:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50169:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50170:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50171:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50172:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50173:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50174:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50175:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50176:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50177:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50178:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50179:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50180:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50181:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50182:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50183:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50184:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50185:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50186:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50187:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50188:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50189:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50190:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50191:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50192:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50193:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50194:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50195:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50196:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50197:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50198:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50199:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50200:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50201:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50202:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50203:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50204:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50205:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50206:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50207:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50208:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50209:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50210:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50211:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50212:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50213:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50214:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50215:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50216:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50217:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50218:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50219:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50220:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50221:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50222:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50223:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50224:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50225:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50226:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50227:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50228:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50229:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50230:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50231:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50232:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50233:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50234:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50235:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50236:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50237:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50238:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50239:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50240:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50241:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50242:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50243:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50244:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50245:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50246:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50247:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50248:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50249:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50250:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50251:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50252:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50253:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50254:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50255:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50256:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50257:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50258:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#65544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50259:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#65545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50260:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#65546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50261:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#65547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50262:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50263:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50264:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50265:
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50266:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#65552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50267:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#65553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50268:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#65554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50269:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#65555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50270:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#65556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50271:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#65557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50272:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#65558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50273:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#65559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50274:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#65560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50275:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#65561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50276:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#65562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50277:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#65563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50278:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#65564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50279:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#65565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50280:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#65566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50281:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#65567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50282:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#65568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50283:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L

WARNING: line length of 121 exceeds 100 columns
#65569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50284:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#65570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50285:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#65571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50286:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L

WARNING: line length of 121 exceeds 100 columns
#65572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50287:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L

WARNING: line length of 121 exceeds 100 columns
#65573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50288:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#65574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50289:
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L

WARNING: line length of 113 exceeds 100 columns
#65577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50292:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0

WARNING: line length of 113 exceeds 100 columns
#65578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50293:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2

WARNING: line length of 121 exceeds 100 columns
#65579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50294:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L

WARNING: line length of 121 exceeds 100 columns
#65580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50295:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL

WARNING: line length of 113 exceeds 100 columns
#65581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50296:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#65582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50297:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50298:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#65584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50299:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50300:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#65586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50301:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#65587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50302:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#65588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50303:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#65589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50304:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0

WARNING: line length of 114 exceeds 100 columns
#65590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50305:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10

WARNING: line length of 121 exceeds 100 columns
#65591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50306:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50307:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50308:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#65594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50309:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#65595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50310:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#65596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50311:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL

WARNING: line length of 113 exceeds 100 columns
#65597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50312:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0

WARNING: line length of 113 exceeds 100 columns
#65598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50313:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4

WARNING: line length of 121 exceeds 100 columns
#65599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50314:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L

WARNING: line length of 121 exceeds 100 columns
#65600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50315:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L

WARNING: line length of 113 exceeds 100 columns
#65601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50316:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#65602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50317:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#65603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50318:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50319:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50320:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#65606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50321:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#65607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50322:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50323:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50324:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#65610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50325:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#65611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50326:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50327:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50328:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#65614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50329:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50330:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50331:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#65617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50332:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#65618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50333:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50334:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50335:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#65621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50336:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#65622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50337:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50338:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50339:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#65625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50340:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50341:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50342:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50343:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50344:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50345:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50346:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50347:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50348:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50349:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50350:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50351:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50352:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50353:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50354:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50355:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50356:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50357:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50358:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50359:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50360:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50361:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50362:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50363:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50364:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50365:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50366:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50367:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50368:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50369:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50370:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50371:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50372:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50373:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50374:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50375:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50376:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50377:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50378:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50379:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50380:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50381:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50382:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50383:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50384:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50385:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50386:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50387:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50388:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50389:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50390:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50391:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50392:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50393:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50394:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50395:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50396:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50397:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50398:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50399:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50400:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50401:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50402:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50403:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50404:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50405:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50406:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50407:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50408:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50409:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50410:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50411:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50412:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50413:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50414:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50415:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50416:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50417:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50418:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50419:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50420:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50421:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50422:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50423:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50424:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50425:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50426:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50427:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50428:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50429:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50430:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50431:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50432:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50433:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50434:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50435:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50436:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50437:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50438:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50439:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50440:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50441:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50442:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50443:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50444:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50445:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50446:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50447:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50448:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50449:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50450:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50451:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50452:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50453:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50454:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50455:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50456:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50457:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50458:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50459:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50460:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50461:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50462:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50463:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50464:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50465:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50466:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50467:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50468:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50469:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50470:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50471:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50472:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50473:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50474:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50475:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50476:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#65762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50477:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#65763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50478:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50479:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50480:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#65766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50481:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#65767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50482:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50483:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50484:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0

WARNING: line length of 114 exceeds 100 columns
#65770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50485:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14

WARNING: line length of 121 exceeds 100 columns
#65771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50486:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50487:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50488:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#65774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50489:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50490:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50491:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#65777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50492:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#65778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50493:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50494:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50495:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#65781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50496:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0

WARNING: line length of 114 exceeds 100 columns
#65782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50497:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#65783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50498:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50499:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L

WARNING: line length of 113 exceeds 100 columns
#65785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50500:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50501:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50502:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50503:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50504:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50505:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50506:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50507:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50508:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50509:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50510:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50511:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50512:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50513:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50514:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50515:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50516:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50517:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50518:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50519:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50520:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50521:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50522:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50523:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50524:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50525:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50526:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50527:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50528:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50529:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50530:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50531:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50532:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0

WARNING: line length of 113 exceeds 100 columns
#65818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50533:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc

WARNING: line length of 114 exceeds 100 columns
#65819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50534:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10

WARNING: line length of 114 exceeds 100 columns
#65820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50535:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c

WARNING: line length of 121 exceeds 100 columns
#65821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50536:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50537:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50538:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50539:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50540:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50541:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50542:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50543:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50544:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50545:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50546:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50547:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50548:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50549:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50550:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50551:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50552:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50553:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50554:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50555:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50556:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50557:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50558:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50559:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50560:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50561:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50562:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50563:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50564:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50565:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50566:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50567:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50568:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50569:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50570:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50571:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50572:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50573:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50574:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50575:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50576:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50577:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50578:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50579:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50580:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50581:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50582:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50583:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50584:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50585:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50586:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50587:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50588:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50589:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50590:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50591:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50592:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50593:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50594:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50595:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50596:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50597:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50598:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50599:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50600:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50601:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50602:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50603:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50604:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50605:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50606:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50607:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50608:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50609:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50610:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50611:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50612:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50613:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50614:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50615:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50616:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50617:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50618:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50619:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50620:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50621:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50622:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50623:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50624:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50625:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50626:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50627:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50628:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0

WARNING: line length of 113 exceeds 100 columns
#65914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50629:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc

WARNING: line length of 114 exceeds 100 columns
#65915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50630:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10

WARNING: line length of 114 exceeds 100 columns
#65916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50631:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c

WARNING: line length of 121 exceeds 100 columns
#65917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50632:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#65918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50633:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L

WARNING: line length of 121 exceeds 100 columns
#65919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50634:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#65920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50635:
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L

WARNING: line length of 113 exceeds 100 columns
#65921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50636:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#65922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50637:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#65923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50638:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8

WARNING: line length of 121 exceeds 100 columns
#65924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50639:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#65925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50640:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#65926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50641:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L

WARNING: line length of 113 exceeds 100 columns
#65927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50642:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0

WARNING: line length of 121 exceeds 100 columns
#65928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50643:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL

WARNING: line length of 113 exceeds 100 columns
#65929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50644:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0

WARNING: line length of 114 exceeds 100 columns
#65930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50645:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10

WARNING: line length of 121 exceeds 100 columns
#65931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50646:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50647:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50648:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2

WARNING: line length of 121 exceeds 100 columns
#65934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50649:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL

WARNING: line length of 113 exceeds 100 columns
#65935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50650:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#65936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50651:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4

WARNING: line length of 113 exceeds 100 columns
#65937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50652:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#65938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50653:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10

WARNING: line length of 121 exceeds 100 columns
#65939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50654:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL

WARNING: line length of 121 exceeds 100 columns
#65940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50655:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#65941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50656:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L

WARNING: line length of 121 exceeds 100 columns
#65942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50657:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L

WARNING: line length of 113 exceeds 100 columns
#65943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50658:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0

WARNING: line length of 121 exceeds 100 columns
#65944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50659:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#65945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50660:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#65946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50661:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#65947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50662:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50663:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50664:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#65950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50665:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#65951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50666:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50667:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50668:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#65954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50669:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10

WARNING: line length of 121 exceeds 100 columns
#65955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50670:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#65956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50671:
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#65957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50672:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#65958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50673:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2

WARNING: line length of 113 exceeds 100 columns
#65959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50674:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3

WARNING: line length of 113 exceeds 100 columns
#65960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50675:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4

WARNING: line length of 113 exceeds 100 columns
#65961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50676:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6

WARNING: line length of 121 exceeds 100 columns
#65962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50677:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L

WARNING: line length of 121 exceeds 100 columns
#65963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50678:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L

WARNING: line length of 121 exceeds 100 columns
#65964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50679:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#65965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50680:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L

WARNING: line length of 121 exceeds 100 columns
#65966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50681:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L

WARNING: line length of 113 exceeds 100 columns
#65967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50682:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0

WARNING: line length of 121 exceeds 100 columns
#65968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50683:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL

WARNING: line length of 113 exceeds 100 columns
#65969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50684:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0

WARNING: line length of 121 exceeds 100 columns
#65970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50685:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50686:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0

WARNING: line length of 113 exceeds 100 columns
#65972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50687:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3

WARNING: line length of 113 exceeds 100 columns
#65973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50688:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#65974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50689:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7

WARNING: line length of 121 exceeds 100 columns
#65975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50690:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L

WARNING: line length of 121 exceeds 100 columns
#65976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50691:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L

WARNING: line length of 121 exceeds 100 columns
#65977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50692:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#65978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50693:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L

WARNING: line length of 113 exceeds 100 columns
#65979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50694:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50695:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50696:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50697:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50698:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50699:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50700:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50701:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#65987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50702:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#65988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50703:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#65989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50704:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#65990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50705:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#65991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50706:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50707:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#65993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50708:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50709:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#65995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50710:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#65996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50711:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50712:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#65998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50713:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#65999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50714:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#66000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50715:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50716:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#66002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50717:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50718:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#66004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50719:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50720:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#66006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50721:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#66007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50722:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#66008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50723:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#66009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50724:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#66010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50725:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50726:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#66012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50727:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#66013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50728:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#66014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50729:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#66015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50730:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#66016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50731:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50732:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#66018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50733:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#66019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50734:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#66020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50735:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#66021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50736:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#66022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50737:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#66023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50738:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#66024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50739:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#66025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50740:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#66026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50741:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#66027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50742:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50743:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50744:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50745:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50746:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50747:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50748:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50749:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50750:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50751:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50752:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50753:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50754:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50755:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50756:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50757:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50758:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50759:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50760:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50761:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50762:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50763:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50764:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50765:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50766:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50767:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50768:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50769:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50770:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50771:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50772:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50773:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50774:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50775:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50776:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50777:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50778:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50779:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50780:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50781:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50782:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50783:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50784:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50785:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50786:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50787:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50788:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50789:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50790:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50791:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50792:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50793:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50794:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50795:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50796:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50797:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50798:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50799:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50800:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50801:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50802:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50803:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50804:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50805:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50806:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50807:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50808:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50809:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50810:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50811:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50812:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50813:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50814:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50815:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50816:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50817:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50818:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50819:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50820:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50821:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50822:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50823:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50824:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50825:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50826:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50827:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50828:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50829:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50830:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50831:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50832:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50833:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50834:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50835:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50836:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50837:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50838:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50839:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50840:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50841:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50842:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50843:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50844:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50845:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50846:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50847:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50848:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50849:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50850:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50851:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50852:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50853:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50854:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50855:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50856:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50857:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50858:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50859:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50860:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50861:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50862:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50863:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50864:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50865:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50866:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50867:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50868:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50869:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50870:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50871:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50872:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50873:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50874:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50875:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50876:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50877:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50878:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#66164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50879:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#66165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50880:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#66166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50881:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#66167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50882:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#66168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50883:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#66169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50884:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#66170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50885:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L

WARNING: line length of 113 exceeds 100 columns
#66171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50886:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0

WARNING: line length of 114 exceeds 100 columns
#66172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50887:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14

WARNING: line length of 121 exceeds 100 columns
#66173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50888:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL

WARNING: line length of 121 exceeds 100 columns
#66174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50889:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L

WARNING: line length of 114 exceeds 100 columns
#66175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50890:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#66176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50891:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#66177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50892:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#66178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50893:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL

WARNING: line length of 114 exceeds 100 columns
#66179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50894:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0

WARNING: line length of 121 exceeds 100 columns
#66180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50895:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50896:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#66182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50897:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50898:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#66184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50899:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50900:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0

WARNING: line length of 121 exceeds 100 columns
#66186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50901:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50902:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#66188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50903:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50904:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#66190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50905:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#66191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50906:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#66192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50907:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#66193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50908:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#66194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50909:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50910:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#66196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50911:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#66197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50912:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#66198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50913:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#66199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50914:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0

WARNING: line length of 121 exceeds 100 columns
#66200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50915:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL

WARNING: line length of 113 exceeds 100 columns
#66201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50916:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0

WARNING: line length of 114 exceeds 100 columns
#66202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50917:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10

WARNING: line length of 121 exceeds 100 columns
#66203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50918:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#66204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50919:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#66205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50920:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#66206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50921:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#66207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50922:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#66208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50923:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#66209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50924:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#66210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50925:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL

WARNING: line length of 113 exceeds 100 columns
#66211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50926:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50927:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50928:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50929:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50930:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50931:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50932:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50933:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50934:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50935:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50936:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50937:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50938:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50939:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50940:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50941:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50942:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50943:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50944:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50945:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50946:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50947:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50948:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50949:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50950:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50951:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50952:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50953:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50954:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50955:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50956:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50957:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50958:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0

WARNING: line length of 113 exceeds 100 columns
#66244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50959:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc

WARNING: line length of 114 exceeds 100 columns
#66245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50960:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10

WARNING: line length of 114 exceeds 100 columns
#66246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50961:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c

WARNING: line length of 121 exceeds 100 columns
#66247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50962:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50963:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50964:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50965:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50966:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50967:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50968:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50969:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50970:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50971:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50972:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50973:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50974:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50975:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50976:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50977:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50978:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50979:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50980:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50981:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50982:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50983:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50984:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50985:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50986:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50987:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50988:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50989:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50990:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50991:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50992:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50993:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50994:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50995:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50996:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50997:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50998:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:50999:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51000:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51001:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51002:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51003:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51004:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51005:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51006:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51007:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51008:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51009:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51010:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51011:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51012:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51013:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51014:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51015:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51016:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51017:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51018:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51019:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51020:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51021:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51022:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51023:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51024:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51025:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51026:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51027:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51028:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51029:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51030:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51031:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51032:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51033:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51034:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51035:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51036:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51037:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51038:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51039:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51040:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51041:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51042:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51043:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51044:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51045:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51046:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51047:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51048:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51049:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51050:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51051:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51052:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51053:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51054:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0

WARNING: line length of 113 exceeds 100 columns
#66340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51055:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc

WARNING: line length of 114 exceeds 100 columns
#66341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51056:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10

WARNING: line length of 114 exceeds 100 columns
#66342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51057:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c

WARNING: line length of 121 exceeds 100 columns
#66343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51058:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#66344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51059:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L

WARNING: line length of 121 exceeds 100 columns
#66345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51060:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L

WARNING: line length of 121 exceeds 100 columns
#66346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51061:
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L

WARNING: line length of 113 exceeds 100 columns
#66347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51062:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0

WARNING: line length of 113 exceeds 100 columns
#66348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51063:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2

WARNING: line length of 113 exceeds 100 columns
#66349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51064:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#66350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51065:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8

WARNING: line length of 113 exceeds 100 columns
#66351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51066:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#66352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51067:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc

WARNING: line length of 114 exceeds 100 columns
#66353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51068:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10

WARNING: line length of 114 exceeds 100 columns
#66354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51069:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#66355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51070:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14

WARNING: line length of 114 exceeds 100 columns
#66356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51071:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#66357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51072:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a

WARNING: line length of 114 exceeds 100 columns
#66358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51073:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c

WARNING: line length of 121 exceeds 100 columns
#66359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51074:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L

WARNING: line length of 121 exceeds 100 columns
#66360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51075:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L

WARNING: line length of 121 exceeds 100 columns
#66361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51076:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L

WARNING: line length of 121 exceeds 100 columns
#66362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51077:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#66363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51078:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#66364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51079:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L

WARNING: line length of 121 exceeds 100 columns
#66365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51080:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#66366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51081:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#66367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51082:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L

WARNING: line length of 121 exceeds 100 columns
#66368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51083:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L

WARNING: line length of 121 exceeds 100 columns
#66369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51084:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#66370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51085:
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L

WARNING: line length of 114 exceeds 100 columns
#66373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51088:
+#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS__SHIFT                                                          0x18

WARNING: line length of 121 exceeds 100 columns
#66374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51089:
+#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS_MASK                                                            0x01000000L

WARNING: line length of 113 exceeds 100 columns
#66376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51091:
+#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#66377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51092:
+#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#66378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51093:
+#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#66379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51094:
+#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51095:
+#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#66381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51096:
+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#66382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51097:
+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#66383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51098:
+#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51099:
+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#66385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51100:
+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#66386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51101:
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#66387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51102:
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L

WARNING: line length of 113 exceeds 100 columns
#66388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51103:
+#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#66389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51104:
+#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51105:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1

WARNING: line length of 121 exceeds 100 columns
#66391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51106:
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L

WARNING: line length of 113 exceeds 100 columns
#66392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51107:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51108:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51109:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51110:
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51111:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51112:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51113:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51114:
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51115:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51116:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51117:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51118:
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51119:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51120:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51121:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51122:
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51123:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51124:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51125:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51126:
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51127:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51128:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51129:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51130:
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51131:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51132:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51133:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51134:
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51135:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51136:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51137:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51138:
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51139:
+#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51140:
+#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51143:
+#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#66429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51144:
+#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#66430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51145:
+#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#66431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51146:
+#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51147:
+#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#66433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51148:
+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#66434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51149:
+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#66435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51150:
+#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51151:
+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#66437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51152:
+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#66438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51153:
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#66439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51154:
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L

WARNING: line length of 113 exceeds 100 columns
#66440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51155:
+#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#66441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51156:
+#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51157:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1

WARNING: line length of 121 exceeds 100 columns
#66443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51158:
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L

WARNING: line length of 113 exceeds 100 columns
#66444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51159:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51160:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51161:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51162:
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51163:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51164:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51165:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51166:
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51167:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51168:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51169:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51170:
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51171:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51172:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51173:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51174:
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51175:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51176:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51177:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51178:
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51179:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51180:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51181:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51182:
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51183:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51184:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51185:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51186:
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51187:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51188:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51189:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51190:
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51191:
+#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51192:
+#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51195:
+#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#66481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51196:
+#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#66482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51197:
+#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#66483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51198:
+#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51199:
+#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#66485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51200:
+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#66486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51201:
+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#66487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51202:
+#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51203:
+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#66489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51204:
+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#66490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51205:
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#66491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51206:
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L

WARNING: line length of 113 exceeds 100 columns
#66492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51207:
+#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#66493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51208:
+#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51209:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1

WARNING: line length of 121 exceeds 100 columns
#66495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51210:
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L

WARNING: line length of 113 exceeds 100 columns
#66496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51211:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51212:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51213:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51214:
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51215:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51216:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51217:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51218:
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51219:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51220:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51221:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51222:
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51223:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51224:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51225:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51226:
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51227:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51228:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51229:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51230:
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51231:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51232:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51233:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51234:
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51235:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51236:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51237:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51238:
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51239:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51240:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51241:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51242:
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51243:
+#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51244:
+#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51247:
+#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#66533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51248:
+#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL

WARNING: line length of 113 exceeds 100 columns
#66534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51249:
+#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0

WARNING: line length of 121 exceeds 100 columns
#66535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51250:
+#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51251:
+#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#66537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51252:
+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#66538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51253:
+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f

WARNING: line length of 121 exceeds 100 columns
#66539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51254:
+#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51255:
+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#66541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51256:
+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#66542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51257:
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf

WARNING: line length of 121 exceeds 100 columns
#66543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51258:
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L

WARNING: line length of 113 exceeds 100 columns
#66544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51259:
+#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0

WARNING: line length of 121 exceeds 100 columns
#66545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51260:
+#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51261:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1

WARNING: line length of 121 exceeds 100 columns
#66547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51262:
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L

WARNING: line length of 113 exceeds 100 columns
#66548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51263:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51264:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51265:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51266:
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51267:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51268:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51269:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51270:
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51271:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51272:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51273:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51274:
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51275:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51276:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51277:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51278:
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51279:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51280:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51281:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51282:
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51283:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51284:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51285:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51286:
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51287:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51288:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51289:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51290:
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51291:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0

WARNING: line length of 114 exceeds 100 columns
#66577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51292:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10

WARNING: line length of 121 exceeds 100 columns
#66578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51293:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#66579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51294:
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#66580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51295:
+#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51296:
+#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51298:
+#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX__SHIFT                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#66584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51299:
+#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX_MASK                                                        0x00000007L

WARNING: line length of 113 exceeds 100 columns
#66586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51301:
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc

WARNING: line length of 121 exceeds 100 columns
#66587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51302:
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51303:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51304:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51305:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51306:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51307:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51308:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51309:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51310:
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51311:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51312:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51313:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51314:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51315:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51316:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51317:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51318:
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51319:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51320:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51321:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51322:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51323:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51324:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51325:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51326:
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51327:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51328:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51329:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51330:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51331:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51332:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51333:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51334:
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51335:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51336:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51337:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51338:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51339:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51340:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51341:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51342:
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51343:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51344:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51345:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51346:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51347:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51348:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51349:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51350:
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51351:
+#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7

WARNING: line length of 113 exceeds 100 columns
#66637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51352:
+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#66638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51353:
+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc

WARNING: line length of 121 exceeds 100 columns
#66639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51354:
+#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#66640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51355:
+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51356:
+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51357:
+#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#66643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51358:
+#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#66644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51359:
+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#66645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51360:
+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4

WARNING: line length of 121 exceeds 100 columns
#66646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51361:
+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51362:
+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L

WARNING: line length of 113 exceeds 100 columns
#66648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51363:
+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51364:
+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#66650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51365:
+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#66651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51366:
+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51367:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#66653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51368:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#66654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51369:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#66655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51370:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#66656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51371:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51372:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51373:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#66659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51374:
+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51377:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#66663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51378:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#66664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51379:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#66665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51380:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#66666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51381:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#66667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51382:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#66668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51383:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#66669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51384:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe

WARNING: line length of 121 exceeds 100 columns
#66670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51385:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#66671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51386:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51387:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51388:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#66674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51389:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51390:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#66676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51391:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#66677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51392:
+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L

WARNING: line length of 113 exceeds 100 columns
#66678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51393:
+#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51394:
+#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 114 exceeds 100 columns
#66680: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51395:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#66681: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51396:
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#66682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51397:
+#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#66683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51398:
+#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#66684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51399:
+#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#66685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51400:
+#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd

WARNING: line length of 121 exceeds 100 columns
#66686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51401:
+#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#66687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51402:
+#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51403:
+#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#66689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51404:
+#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L

WARNING: line length of 113 exceeds 100 columns
#66690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51405:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#66691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51406:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#66692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51407:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#66693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51408:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb

WARNING: line length of 113 exceeds 100 columns
#66694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51409:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd

WARNING: line length of 121 exceeds 100 columns
#66695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51410:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#66696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51411:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51412:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51413:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51414:
+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L

WARNING: line length of 113 exceeds 100 columns
#66700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51415:
+#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51416:
+#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#66706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51421:
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc

WARNING: line length of 121 exceeds 100 columns
#66707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51422:
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51423:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51424:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51425:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51426:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51427:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51428:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51429:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51430:
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51431:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51432:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51433:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51434:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51435:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51436:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51437:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51438:
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51439:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51440:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51441:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51442:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51443:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51444:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51445:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51446:
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51447:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51448:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51449:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51450:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51451:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51452:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51453:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51454:
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51455:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51456:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51457:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51458:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51459:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51460:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51461:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51462:
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51463:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51464:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51465:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51466:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51467:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51468:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51469:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51470:
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51471:
+#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7

WARNING: line length of 113 exceeds 100 columns
#66757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51472:
+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#66758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51473:
+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc

WARNING: line length of 121 exceeds 100 columns
#66759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51474:
+#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#66760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51475:
+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51476:
+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51477:
+#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#66763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51478:
+#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#66764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51479:
+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#66765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51480:
+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4

WARNING: line length of 121 exceeds 100 columns
#66766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51481:
+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51482:
+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L

WARNING: line length of 113 exceeds 100 columns
#66768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51483:
+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51484:
+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#66770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51485:
+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#66771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51486:
+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51487:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#66773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51488:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#66774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51489:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#66775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51490:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#66776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51491:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51492:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51493:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#66779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51494:
+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51497:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#66783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51498:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#66784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51499:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#66785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51500:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#66786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51501:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#66787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51502:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#66788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51503:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#66789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51504:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe

WARNING: line length of 121 exceeds 100 columns
#66790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51505:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#66791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51506:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51507:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51508:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#66794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51509:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51510:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#66796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51511:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#66797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51512:
+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L

WARNING: line length of 113 exceeds 100 columns
#66798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51513:
+#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51514:
+#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 114 exceeds 100 columns
#66800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51515:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#66801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51516:
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#66802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51517:
+#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#66803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51518:
+#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#66804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51519:
+#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#66805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51520:
+#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd

WARNING: line length of 121 exceeds 100 columns
#66806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51521:
+#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#66807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51522:
+#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51523:
+#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#66809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51524:
+#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L

WARNING: line length of 113 exceeds 100 columns
#66810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51525:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#66811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51526:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#66812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51527:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#66813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51528:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb

WARNING: line length of 113 exceeds 100 columns
#66814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51529:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd

WARNING: line length of 121 exceeds 100 columns
#66815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51530:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#66816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51531:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51532:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51533:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51534:
+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L

WARNING: line length of 113 exceeds 100 columns
#66820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51535:
+#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51536:
+#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#66824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51539:
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc

WARNING: line length of 121 exceeds 100 columns
#66825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51540:
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51541:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51542:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51543:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51544:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51545:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51546:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51547:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51548:
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51549:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51550:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51551:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51552:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51553:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51554:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51555:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51556:
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51557:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51558:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51559:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51560:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51561:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51562:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51563:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51564:
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51565:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51566:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51567:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51568:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51569:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51570:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51571:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51572:
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51573:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51574:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51575:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51576:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51577:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51578:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51579:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51580:
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51581:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51582:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51583:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51584:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51585:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51586:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51587:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51588:
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51589:
+#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7

WARNING: line length of 113 exceeds 100 columns
#66875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51590:
+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#66876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51591:
+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc

WARNING: line length of 121 exceeds 100 columns
#66877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51592:
+#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#66878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51593:
+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51594:
+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51595:
+#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#66881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51596:
+#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#66882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51597:
+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#66883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51598:
+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4

WARNING: line length of 121 exceeds 100 columns
#66884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51599:
+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51600:
+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L

WARNING: line length of 113 exceeds 100 columns
#66886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51601:
+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51602:
+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#66888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51603:
+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#66889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51604:
+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#66890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51605:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#66891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51606:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#66892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51607:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#66893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51608:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#66894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51609:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#66895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51610:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51611:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#66897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51612:
+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51615:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#66901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51616:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#66902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51617:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#66903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51618:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#66904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51619:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#66905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51620:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#66906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51621:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#66907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51622:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe

WARNING: line length of 121 exceeds 100 columns
#66908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51623:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#66909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51624:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51625:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51626:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#66912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51627:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51628:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#66914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51629:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#66915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51630:
+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L

WARNING: line length of 113 exceeds 100 columns
#66916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51631:
+#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51632:
+#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 114 exceeds 100 columns
#66918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51633:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#66919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51634:
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#66920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51635:
+#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#66921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51636:
+#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#66922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51637:
+#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#66923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51638:
+#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd

WARNING: line length of 121 exceeds 100 columns
#66924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51639:
+#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#66925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51640:
+#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51641:
+#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#66927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51642:
+#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L

WARNING: line length of 113 exceeds 100 columns
#66928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51643:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#66929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51644:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#66930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51645:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#66931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51646:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb

WARNING: line length of 113 exceeds 100 columns
#66932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51647:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd

WARNING: line length of 121 exceeds 100 columns
#66933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51648:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#66934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51649:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51650:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51651:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51652:
+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L

WARNING: line length of 113 exceeds 100 columns
#66938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51653:
+#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#66939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51654:
+#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#66944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51659:
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc

WARNING: line length of 121 exceeds 100 columns
#66945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51660:
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#66946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51661:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51662:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51663:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51664:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51665:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51666:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51667:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51668:
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51669:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51670:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51671:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51672:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51673:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51674:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51675:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51676:
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51677:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#66963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51678:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#66964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51679:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#66965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51680:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#66966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51681:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51682:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51683:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51684:
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51685:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51686:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51687:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51688:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51689:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51690:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51691:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51692:
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51693:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51694:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51695:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51696:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51697:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51698:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51699:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51700:
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51701:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#66987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51702:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#66988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51703:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#66989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51704:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#66990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51705:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#66991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51706:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#66992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51707:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#66993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51708:
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#66994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51709:
+#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7

WARNING: line length of 113 exceeds 100 columns
#66995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51710:
+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#66996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51711:
+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc

WARNING: line length of 121 exceeds 100 columns
#66997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51712:
+#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#66998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51713:
+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#66999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51714:
+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#67000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51715:
+#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#67001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51716:
+#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#67002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51717:
+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51718:
+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4

WARNING: line length of 121 exceeds 100 columns
#67004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51719:
+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51720:
+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L

WARNING: line length of 113 exceeds 100 columns
#67006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51721:
+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51722:
+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#67008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51723:
+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#67009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51724:
+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#67010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51725:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#67011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51726:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#67012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51727:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#67013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51728:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#67014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51729:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51730:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51731:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51732:
+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L

WARNING: line length of 113 exceeds 100 columns
#67020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51735:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#67021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51736:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#67022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51737:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#67023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51738:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#67024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51739:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#67025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51740:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#67026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51741:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#67027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51742:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe

WARNING: line length of 121 exceeds 100 columns
#67028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51743:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#67029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51744:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51745:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51746:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51747:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51748:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51749:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51750:
+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L

WARNING: line length of 113 exceeds 100 columns
#67036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51751:
+#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51752:
+#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 114 exceeds 100 columns
#67038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51753:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#67039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51754:
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#67040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51755:
+#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#67041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51756:
+#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#67042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51757:
+#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#67043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51758:
+#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd

WARNING: line length of 121 exceeds 100 columns
#67044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51759:
+#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51760:
+#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51761:
+#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51762:
+#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L

WARNING: line length of 113 exceeds 100 columns
#67048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51763:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#67049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51764:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#67050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51765:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#67051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51766:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb

WARNING: line length of 113 exceeds 100 columns
#67052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51767:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd

WARNING: line length of 121 exceeds 100 columns
#67053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51768:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#67054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51769:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51770:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51771:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51772:
+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L

WARNING: line length of 113 exceeds 100 columns
#67058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51773:
+#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51774:
+#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#67062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51777:
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc

WARNING: line length of 121 exceeds 100 columns
#67063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51778:
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L

WARNING: line length of 113 exceeds 100 columns
#67064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51779:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#67065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51780:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#67066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51781:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#67067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51782:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#67068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51783:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51784:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51785:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51786:
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#67072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51787:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#67073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51788:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#67074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51789:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#67075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51790:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#67076: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51791:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67077: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51792:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51793:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51794:
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#67080: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51795:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4

WARNING: line length of 113 exceeds 100 columns
#67081: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51796:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5

WARNING: line length of 114 exceeds 100 columns
#67082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51797:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14

WARNING: line length of 114 exceeds 100 columns
#67083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51798:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15

WARNING: line length of 121 exceeds 100 columns
#67084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51799:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51800:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51801:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51802:
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L

WARNING: line length of 113 exceeds 100 columns
#67088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51803:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#67089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51804:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#67090: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51805:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#67091: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51806:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#67092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51807:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51808:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67094: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51809:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51810:
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#67096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51811:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#67097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51812:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#67098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51813:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#67099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51814:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#67100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51815:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51816:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51817:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67103: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51818:
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#67104: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51819:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4

WARNING: line length of 113 exceeds 100 columns
#67105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51820:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5

WARNING: line length of 114 exceeds 100 columns
#67106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51821:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14

WARNING: line length of 114 exceeds 100 columns
#67107: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51822:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15

WARNING: line length of 121 exceeds 100 columns
#67108: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51823:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51824:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51825:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51826:
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L

WARNING: line length of 113 exceeds 100 columns
#67112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51827:
+#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7

WARNING: line length of 113 exceeds 100 columns
#67113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51828:
+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb

WARNING: line length of 113 exceeds 100 columns
#67114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51829:
+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc

WARNING: line length of 121 exceeds 100 columns
#67115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51830:
+#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L

WARNING: line length of 121 exceeds 100 columns
#67116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51831:
+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67117: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51832:
+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L

WARNING: line length of 113 exceeds 100 columns
#67118: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51833:
+#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#67119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51834:
+#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#67120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51835:
+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67121: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51836:
+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4

WARNING: line length of 121 exceeds 100 columns
#67122: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51837:
+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51838:
+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L

WARNING: line length of 113 exceeds 100 columns
#67124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51839:
+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51840:
+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#67126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51841:
+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0

WARNING: line length of 121 exceeds 100 columns
#67127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51842:
+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#67128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51843:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#67129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51844:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4

WARNING: line length of 113 exceeds 100 columns
#67130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51845:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8

WARNING: line length of 113 exceeds 100 columns
#67131: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51846:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc

WARNING: line length of 121 exceeds 100 columns
#67132: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51847:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51848:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51849:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51850:
+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L

WARNING: line length of 113 exceeds 100 columns
#67138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51853:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#67139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51854:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#67140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51855:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#67141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51856:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa

WARNING: line length of 113 exceeds 100 columns
#67142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51857:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb

WARNING: line length of 113 exceeds 100 columns
#67143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51858:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc

WARNING: line length of 113 exceeds 100 columns
#67144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51859:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd

WARNING: line length of 113 exceeds 100 columns
#67145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51860:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe

WARNING: line length of 121 exceeds 100 columns
#67146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51861:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#67147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51862:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51863:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51864:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51865:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51866:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51867:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51868:
+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L

WARNING: line length of 113 exceeds 100 columns
#67154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51869:
+#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51870:
+#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 114 exceeds 100 columns
#67156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51871:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10

WARNING: line length of 121 exceeds 100 columns
#67157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51872:
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#67158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51873:
+#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa

WARNING: line length of 113 exceeds 100 columns
#67159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51874:
+#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb

WARNING: line length of 113 exceeds 100 columns
#67160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51875:
+#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc

WARNING: line length of 113 exceeds 100 columns
#67161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51876:
+#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd

WARNING: line length of 121 exceeds 100 columns
#67162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51877:
+#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51878:
+#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51879:
+#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51880:
+#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L

WARNING: line length of 113 exceeds 100 columns
#67166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51881:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#67167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51882:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4

WARNING: line length of 113 exceeds 100 columns
#67168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51883:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5

WARNING: line length of 113 exceeds 100 columns
#67169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51884:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb

WARNING: line length of 113 exceeds 100 columns
#67170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51885:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd

WARNING: line length of 121 exceeds 100 columns
#67171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51886:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L

WARNING: line length of 121 exceeds 100 columns
#67172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51887:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51888:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51889:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51890:
+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L

WARNING: line length of 113 exceeds 100 columns
#67176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51891:
+#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51892:
+#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#67182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51897:
+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67183: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51898:
+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#67184: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51899:
+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#67185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51900:
+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#67186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51901:
+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#67187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51902:
+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L

WARNING: line length of 114 exceeds 100 columns
#67188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51903:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#67189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51904:
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51907:
+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51908:
+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#67194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51909:
+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#67195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51910:
+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#67196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51911:
+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#67197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51912:
+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L

WARNING: line length of 114 exceeds 100 columns
#67198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51913:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#67199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51914:
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51917:
+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51918:
+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#67204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51919:
+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#67205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51920:
+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#67206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51921:
+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#67207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51922:
+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L

WARNING: line length of 114 exceeds 100 columns
#67208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51923:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#67209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51924:
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51927:
+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51928:
+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#67214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51929:
+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#67215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51930:
+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#67216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51931:
+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#67217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51932:
+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L

WARNING: line length of 114 exceeds 100 columns
#67218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51933:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#67219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51934:
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51937:
+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51938:
+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#67224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51939:
+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#67225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51940:
+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#67226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51941:
+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#67227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51942:
+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L

WARNING: line length of 114 exceeds 100 columns
#67228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51943:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#67229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51944:
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51947:
+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#67233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51948:
+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#67234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51949:
+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#67235: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51950:
+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51951:
+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51952:
+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#67240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51955:
+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#67241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51956:
+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#67242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51957:
+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#67243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51958:
+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51959:
+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51960:
+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#67248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51963:
+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#67249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51964:
+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#67250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51965:
+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#67251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51966:
+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51967:
+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51968:
+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#67256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51971:
+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#67257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51972:
+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4

WARNING: line length of 113 exceeds 100 columns
#67258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51973:
+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8

WARNING: line length of 121 exceeds 100 columns
#67259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51974:
+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51975:
+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51976:
+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L

WARNING: line length of 113 exceeds 100 columns
#67263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51978:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN__SHIFT                                                          0x3

WARNING: line length of 121 exceeds 100 columns
#67264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51979:
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN_MASK                                                            0x00000008L

WARNING: line length of 113 exceeds 100 columns
#67265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51980:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN__SHIFT                                                          0x3

WARNING: line length of 121 exceeds 100 columns
#67266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51981:
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN_MASK                                                            0x00000008L

WARNING: line length of 113 exceeds 100 columns
#67267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51982:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN__SHIFT                                                          0x3

WARNING: line length of 121 exceeds 100 columns
#67268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51983:
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN_MASK                                                            0x00000008L

WARNING: line length of 113 exceeds 100 columns
#67269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51984:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN__SHIFT                                                          0x3

WARNING: line length of 121 exceeds 100 columns
#67270: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51985:
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN_MASK                                                            0x00000008L

WARNING: line length of 113 exceeds 100 columns
#67271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51986:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN__SHIFT                                                          0x3

WARNING: line length of 121 exceeds 100 columns
#67272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51987:
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN_MASK                                                            0x00000008L

WARNING: line length of 113 exceeds 100 columns
#67275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51990:
+#define DIO_DCN_STATUS__DCN_ACTIVE__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#67276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51991:
+#define DIO_DCN_STATUS__DCN_ACTIVE_MASK                                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#67277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51992:
+#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL__SHIFT                                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#67278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51993:
+#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS__SHIFT                                                               0x9

WARNING: line length of 113 exceeds 100 columns
#67279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51994:
+#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS__SHIFT                                                               0xa

WARNING: line length of 113 exceeds 100 columns
#67280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51995:
+#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS__SHIFT                                                                0xb

WARNING: line length of 113 exceeds 100 columns
#67281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51996:
+#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS__SHIFT                                                                0xc

WARNING: line length of 113 exceeds 100 columns
#67282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51997:
+#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS__SHIFT                                                                0xd

WARNING: line length of 113 exceeds 100 columns
#67283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51998:
+#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS__SHIFT                                                             0xe

WARNING: line length of 113 exceeds 100 columns
#67284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:51999:
+#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS__SHIFT                                                             0xf

WARNING: line length of 114 exceeds 100 columns
#67285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52000:
+#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS__SHIFT                                                                0x10

WARNING: line length of 114 exceeds 100 columns
#67286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52001:
+#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS__SHIFT                                                                0x11

WARNING: line length of 114 exceeds 100 columns
#67287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52002:
+#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS__SHIFT                                                                 0x14

WARNING: line length of 121 exceeds 100 columns
#67288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52003:
+#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL_MASK                                                                   0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#67289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52004:
+#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS_MASK                                                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52005:
+#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS_MASK                                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52006:
+#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS_MASK                                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52007:
+#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS_MASK                                                                  0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52008:
+#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS_MASK                                                                  0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52009:
+#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS_MASK                                                               0x00004000L

WARNING: line length of 121 exceeds 100 columns
#67295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52010:
+#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS_MASK                                                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52011:
+#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS_MASK                                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#67297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52012:
+#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS_MASK                                                                  0x00020000L

WARNING: line length of 121 exceeds 100 columns
#67298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52013:
+#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS_MASK                                                                   0x00100000L

WARNING: line length of 113 exceeds 100 columns
#67299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52014:
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT                                             0x0

WARNING: line length of 113 exceeds 100 columns
#67300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52015:
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT                                            0x1

WARNING: line length of 121 exceeds 100 columns
#67301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52016:
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK                                               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52017:
+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK                                              0xFFFFFFFEL

WARNING: line length of 113 exceeds 100 columns
#67303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52018:
+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#67304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52019:
+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK                                                 0x00000001L

WARNING: line length of 113 exceeds 100 columns
#67305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52020:
+#define DIO_STATUS__DIO_EN__SHIFT                                                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52021:
+#define DIO_STATUS__DIO_EN_MASK                                                                               0x00000001L

WARNING: line length of 113 exceeds 100 columns
#67309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52024:
+#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52025:
+#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L

WARNING: line length of 113 exceeds 100 columns
#67311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52026:
+#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52027:
+#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L

WARNING: line length of 113 exceeds 100 columns
#67313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52028:
+#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52029:
+#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L

WARNING: line length of 113 exceeds 100 columns
#67315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52030:
+#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52031:
+#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L

WARNING: line length of 113 exceeds 100 columns
#67317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52032:
+#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0

WARNING: line length of 121 exceeds 100 columns
#67318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52033:
+#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L

WARNING: line length of 114 exceeds 100 columns
#67323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52038:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#67324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52039:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#67325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52040:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e

WARNING: line length of 114 exceeds 100 columns
#67326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52041:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#67327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52042:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52043:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#67329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52044:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#67330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52045:
+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L

WARNING: line length of 114 exceeds 100 columns
#67331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52046:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#67332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52047:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#67333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52048:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e

WARNING: line length of 114 exceeds 100 columns
#67334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52049:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#67335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52050:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52051:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#67337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52052:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#67338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52053:
+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L

WARNING: line length of 114 exceeds 100 columns
#67339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52054:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#67340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52055:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#67341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52056:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e

WARNING: line length of 114 exceeds 100 columns
#67342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52057:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#67343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52058:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52059:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#67345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52060:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#67346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52061:
+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L

WARNING: line length of 114 exceeds 100 columns
#67347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52062:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#67348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52063:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#67349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52064:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e

WARNING: line length of 114 exceeds 100 columns
#67350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52065:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#67351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52066:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52067:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#67353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52068:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#67354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52069:
+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L

WARNING: line length of 114 exceeds 100 columns
#67355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52070:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c

WARNING: line length of 114 exceeds 100 columns
#67356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52071:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d

WARNING: line length of 114 exceeds 100 columns
#67357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52072:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e

WARNING: line length of 114 exceeds 100 columns
#67358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52073:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f

WARNING: line length of 121 exceeds 100 columns
#67359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52074:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52075:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L

WARNING: line length of 121 exceeds 100 columns
#67361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52076:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L

WARNING: line length of 121 exceeds 100 columns
#67362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52077:
+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52078:
+#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT                                                         0x2

WARNING: line length of 121 exceeds 100 columns
#67364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52079:
+#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK                                                           0x00000004L

WARNING: line length of 114 exceeds 100 columns
#67365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52080:
+#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT                                                               0x14

WARNING: line length of 121 exceeds 100 columns
#67366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52081:
+#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK                                                                 0x00100000L

WARNING: line length of 113 exceeds 100 columns
#67369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52084:
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT                                              0x4

WARNING: line length of 121 exceeds 100 columns
#67370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52085:
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK                                                0x00000010L

WARNING: line length of 113 exceeds 100 columns
#67371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52086:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#67372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52087:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#67373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52088:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#67374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52089:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT                                                 0x3

WARNING: line length of 113 exceeds 100 columns
#67375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52090:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#67376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52091:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#67377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52092:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#67378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52093:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT                                                0x8

WARNING: line length of 113 exceeds 100 columns
#67379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52094:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT                                              0x9

WARNING: line length of 113 exceeds 100 columns
#67380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52095:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT                                               0xa

WARNING: line length of 113 exceeds 100 columns
#67381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52096:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT                                               0xb

WARNING: line length of 121 exceeds 100 columns
#67382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52097:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52098:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52099:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52100:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK                                                   0x00000008L

WARNING: line length of 121 exceeds 100 columns
#67386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52101:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52102:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52103:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#67389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52104:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52105:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK                                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52106:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52107:
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK                                                 0x00000800L

WARNING: line length of 113 exceeds 100 columns
#67393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52108:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#67394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52109:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#67395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52110:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT                                                 0x2

WARNING: line length of 113 exceeds 100 columns
#67396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52111:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT                                                 0x3

WARNING: line length of 113 exceeds 100 columns
#67397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52112:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT                                                 0x4

WARNING: line length of 113 exceeds 100 columns
#67398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52113:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#67399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52114:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT                                                 0x6

WARNING: line length of 113 exceeds 100 columns
#67400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52115:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT                                                0x8

WARNING: line length of 113 exceeds 100 columns
#67401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52116:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT                                              0x9

WARNING: line length of 113 exceeds 100 columns
#67402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52117:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT                                               0xa

WARNING: line length of 113 exceeds 100 columns
#67403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52118:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT                                               0xb

WARNING: line length of 121 exceeds 100 columns
#67404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52119:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52120:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52121:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK                                                   0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52122:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK                                                   0x00000008L

WARNING: line length of 121 exceeds 100 columns
#67408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52123:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK                                                   0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52124:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52125:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK                                                   0x00000040L

WARNING: line length of 121 exceeds 100 columns
#67411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52126:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52127:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK                                                0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52128:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK                                                 0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52129:
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK                                                 0x00000800L

WARNING: line length of 113 exceeds 100 columns
#67415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52130:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#67416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52131:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#67417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52132:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#67418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52133:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT                                              0x3

WARNING: line length of 113 exceeds 100 columns
#67419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52134:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT                                              0x4

WARNING: line length of 113 exceeds 100 columns
#67420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52135:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT                                              0x5

WARNING: line length of 113 exceeds 100 columns
#67421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52136:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT                                              0x6

WARNING: line length of 113 exceeds 100 columns
#67422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52137:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT                                             0x8

WARNING: line length of 113 exceeds 100 columns
#67423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52138:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT                                           0x9

WARNING: line length of 113 exceeds 100 columns
#67424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52139:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT                                            0xa

WARNING: line length of 113 exceeds 100 columns
#67425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52140:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT                                            0xb

WARNING: line length of 113 exceeds 100 columns
#67426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52141:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT                                                  0xc

WARNING: line length of 113 exceeds 100 columns
#67427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52142:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT                                                  0xd

WARNING: line length of 113 exceeds 100 columns
#67428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52143:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT                                                  0xe

WARNING: line length of 113 exceeds 100 columns
#67429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52144:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT                                                  0xf

WARNING: line length of 114 exceeds 100 columns
#67430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52145:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#67431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52146:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT                                                  0x11

WARNING: line length of 121 exceeds 100 columns
#67432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52147:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52148:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52149:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52150:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK                                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#67436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52151:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK                                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52152:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK                                                0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52153:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK                                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#67439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52154:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52155:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK                                             0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52156:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK                                              0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52157:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK                                              0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52158:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK                                                    0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52159:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK                                                    0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52160:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#67446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52161:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK                                                    0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52162:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK                                                    0x00010000L

WARNING: line length of 121 exceeds 100 columns
#67448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52163:
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK                                                    0x00020000L

WARNING: line length of 113 exceeds 100 columns
#67451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52166:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#67452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52167:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#67453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52168:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                             0x2

WARNING: line length of 114 exceeds 100 columns
#67454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52169:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#67455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52170:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#67456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52171:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                  0x15

WARNING: line length of 114 exceeds 100 columns
#67457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52172:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                   0x16

WARNING: line length of 121 exceeds 100 columns
#67458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52173:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52174:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52175:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52176:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#67462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52177:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52178:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                    0x00200000L

WARNING: line length of 121 exceeds 100 columns
#67464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52179:
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                     0x00400000L

WARNING: line length of 113 exceeds 100 columns
#67467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52182:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#67468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52183:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                            0x1

WARNING: line length of 113 exceeds 100 columns
#67469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52184:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                             0x2

WARNING: line length of 114 exceeds 100 columns
#67470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52185:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                0x10

WARNING: line length of 114 exceeds 100 columns
#67471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52186:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#67472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52187:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                  0x15

WARNING: line length of 114 exceeds 100 columns
#67473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52188:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                   0x16

WARNING: line length of 121 exceeds 100 columns
#67474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52189:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52190:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52191:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52192:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                  0x00010000L

WARNING: line length of 121 exceeds 100 columns
#67478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52193:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52194:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                    0x00200000L

WARNING: line length of 121 exceeds 100 columns
#67480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52195:
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                     0x00400000L

WARNING: line length of 113 exceeds 100 columns
#67483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52198:
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#67484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52199:
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL

WARNING: line length of 114 exceeds 100 columns
#67485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52200:
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#67486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52201:
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#67487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52202:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc

WARNING: line length of 114 exceeds 100 columns
#67488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52203:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c

WARNING: line length of 121 exceeds 100 columns
#67489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52204:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52205:
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#67493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52208:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#67494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52209:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#67495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52210:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52211:
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L

WARNING: line length of 113 exceeds 100 columns
#67498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52213:
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52214:
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4

WARNING: line length of 121 exceeds 100 columns
#67500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52215:
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52216:
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L

WARNING: line length of 113 exceeds 100 columns
#67503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52218:
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#67504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52219:
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL

WARNING: line length of 114 exceeds 100 columns
#67505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52220:
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#67506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52221:
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#67507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52222:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc

WARNING: line length of 114 exceeds 100 columns
#67508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52223:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c

WARNING: line length of 121 exceeds 100 columns
#67509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52224:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52225:
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#67513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52228:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#67514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52229:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#67515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52230:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52231:
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L

WARNING: line length of 113 exceeds 100 columns
#67517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52232:
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52233:
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4

WARNING: line length of 121 exceeds 100 columns
#67519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52234:
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52235:
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L

WARNING: line length of 113 exceeds 100 columns
#67523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52238:
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#67524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52239:
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL

WARNING: line length of 114 exceeds 100 columns
#67525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52240:
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#67526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52241:
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#67527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52242:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc

WARNING: line length of 114 exceeds 100 columns
#67528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52243:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c

WARNING: line length of 121 exceeds 100 columns
#67529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52244:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52245:
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#67533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52248:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#67534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52249:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#67535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52250:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52251:
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L

WARNING: line length of 113 exceeds 100 columns
#67537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52252:
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52253:
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4

WARNING: line length of 121 exceeds 100 columns
#67539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52254:
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52255:
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L

WARNING: line length of 113 exceeds 100 columns
#67543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52258:
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#67544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52259:
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL

WARNING: line length of 114 exceeds 100 columns
#67545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52260:
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18

WARNING: line length of 121 exceeds 100 columns
#67546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52261:
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L

WARNING: line length of 113 exceeds 100 columns
#67547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52262:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc

WARNING: line length of 114 exceeds 100 columns
#67548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52263:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c

WARNING: line length of 121 exceeds 100 columns
#67549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52264:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52265:
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L

WARNING: line length of 113 exceeds 100 columns
#67552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52267:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc

WARNING: line length of 114 exceeds 100 columns
#67553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52268:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#67554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52269:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52270:
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L

WARNING: line length of 113 exceeds 100 columns
#67556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52271:
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52272:
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4

WARNING: line length of 121 exceeds 100 columns
#67558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52273:
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67559: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52274:
+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L

WARNING: line length of 113 exceeds 100 columns
#67562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52277:
+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT                                                    0x0

WARNING: line length of 113 exceeds 100 columns
#67563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52278:
+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT                                                0x4

WARNING: line length of 121 exceeds 100 columns
#67564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52279:
+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK                                                      0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52280:
+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK                                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#67566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52281:
+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#67567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52282:
+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT                                     0x1

WARNING: line length of 121 exceeds 100 columns
#67568: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52283:
+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67569: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52284:
+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK                                       0x00000002L

WARNING: line length of 113 exceeds 100 columns
#67572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52287:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT                                                      0x0

WARNING: line length of 113 exceeds 100 columns
#67573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52288:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#67574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52289:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT                                               0x2

WARNING: line length of 114 exceeds 100 columns
#67575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52290:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT                                          0x10

WARNING: line length of 114 exceeds 100 columns
#67576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52291:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT                                          0x14

WARNING: line length of 114 exceeds 100 columns
#67577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52292:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT                                          0x18

WARNING: line length of 114 exceeds 100 columns
#67578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52293:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT                                          0x1c

WARNING: line length of 121 exceeds 100 columns
#67579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52294:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK                                                        0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52295:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK                                                   0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52296:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK                                                 0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52297:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK                                            0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#67583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52298:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK                                            0x00F00000L

WARNING: line length of 121 exceeds 100 columns
#67584: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52299:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK                                            0x0F000000L

WARNING: line length of 121 exceeds 100 columns
#67585: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52300:
+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK                                            0xF0000000L

WARNING: line length of 113 exceeds 100 columns
#67586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52301:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#67587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52302:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT                                               0xc

WARNING: line length of 114 exceeds 100 columns
#67588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52303:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT                                                  0x18

WARNING: line length of 114 exceeds 100 columns
#67589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52304:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT                                            0x19

WARNING: line length of 114 exceeds 100 columns
#67590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52305:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT                                            0x1a

WARNING: line length of 114 exceeds 100 columns
#67591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52306:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT                                         0x1c

WARNING: line length of 114 exceeds 100 columns
#67592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52307:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT                                           0x1d

WARNING: line length of 114 exceeds 100 columns
#67593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52308:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT                                   0x1e

WARNING: line length of 121 exceeds 100 columns
#67594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52309:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK                                                 0x000001FFL

WARNING: line length of 121 exceeds 100 columns
#67595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52310:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK                                                 0x001FF000L

WARNING: line length of 121 exceeds 100 columns
#67596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52311:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK                                                    0x01000000L

WARNING: line length of 121 exceeds 100 columns
#67597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52312:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK                                              0x02000000L

WARNING: line length of 121 exceeds 100 columns
#67598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52313:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK                                              0x0C000000L

WARNING: line length of 121 exceeds 100 columns
#67599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52314:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK                                           0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67600: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52315:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK                                             0x20000000L

WARNING: line length of 121 exceeds 100 columns
#67601: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52316:
+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK                                     0x40000000L

WARNING: line length of 113 exceeds 100 columns
#67602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52317:
+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT                             0x0

WARNING: line length of 114 exceeds 100 columns
#67603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52318:
+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT                       0x1f

WARNING: line length of 121 exceeds 100 columns
#67604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52319:
+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK                               0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#67605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52320:
+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52321:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#67607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52322:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#67608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52323:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#67609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52324:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                             0x8

WARNING: line length of 121 exceeds 100 columns
#67610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52325:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52326:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK                                                 0x00000006L

WARNING: line length of 121 exceeds 100 columns
#67612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52327:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK                                                 0x00000030L

WARNING: line length of 121 exceeds 100 columns
#67613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52328:
+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                               0x00000300L

WARNING: line length of 113 exceeds 100 columns
#67616: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52331:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#67617: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52332:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                                0x4

WARNING: line length of 113 exceeds 100 columns
#67618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52333:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                                 0x8

WARNING: line length of 113 exceeds 100 columns
#67619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52334:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT                          0xc

WARNING: line length of 121 exceeds 100 columns
#67620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52335:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52336:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52337:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52338:
+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK                            0x00001000L

WARNING: line length of 113 exceeds 100 columns
#67624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52339:
+#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT                        0x0

WARNING: line length of 121 exceeds 100 columns
#67625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52340:
+#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK                          0x00000007L

WARNING: line length of 113 exceeds 100 columns
#67626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52341:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT                          0x0

WARNING: line length of 113 exceeds 100 columns
#67627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52342:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT                           0x4

WARNING: line length of 113 exceeds 100 columns
#67628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52343:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT                  0x8

WARNING: line length of 113 exceeds 100 columns
#67629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52344:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT                0xc

WARNING: line length of 114 exceeds 100 columns
#67630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52345:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT                        0x10

WARNING: line length of 114 exceeds 100 columns
#67631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52346:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT                      0x14

WARNING: line length of 114 exceeds 100 columns
#67632: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52347:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT             0x18

WARNING: line length of 114 exceeds 100 columns
#67633: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52348:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT                           0x1c

WARNING: line length of 121 exceeds 100 columns
#67634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52349:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK                            0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52350:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                             0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52351:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK                    0x00000300L

WARNING: line length of 121 exceeds 100 columns
#67637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52352:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK                  0x00003000L

WARNING: line length of 121 exceeds 100 columns
#67638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52353:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK                          0x00030000L

WARNING: line length of 121 exceeds 100 columns
#67639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52354:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK                        0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52355:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#67641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52356:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                             0x30000000L

WARNING: line length of 113 exceeds 100 columns
#67642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52357:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT             0x0

WARNING: line length of 113 exceeds 100 columns
#67643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52358:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT             0x1

WARNING: line length of 113 exceeds 100 columns
#67644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52359:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT             0x2

WARNING: line length of 113 exceeds 100 columns
#67645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52360:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT                 0x4

WARNING: line length of 113 exceeds 100 columns
#67646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52361:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT                   0xc

WARNING: line length of 114 exceeds 100 columns
#67647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52362:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#67648: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52363:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT               0x18

WARNING: line length of 114 exceeds 100 columns
#67649: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52364:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT                      0x1f

WARNING: line length of 121 exceeds 100 columns
#67650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52365:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK               0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52366:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK               0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52367:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK               0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52368:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK                   0x000003F0L

WARNING: line length of 121 exceeds 100 columns
#67654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52369:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK                     0x0000F000L

WARNING: line length of 121 exceeds 100 columns
#67655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52370:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK                     0x001F0000L

WARNING: line length of 121 exceeds 100 columns
#67656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52371:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK                 0x3F000000L

WARNING: line length of 121 exceeds 100 columns
#67657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52372:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK                        0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52373:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT                0x0

WARNING: line length of 113 exceeds 100 columns
#67659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52374:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT                  0x5

WARNING: line length of 113 exceeds 100 columns
#67660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52375:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT                      0x8

WARNING: line length of 113 exceeds 100 columns
#67661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52376:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT                      0xc

WARNING: line length of 121 exceeds 100 columns
#67662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52377:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK                  0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#67663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52378:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK                    0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67664: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52379:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK                        0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67665: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52380:
+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK                        0x00001000L

WARNING: line length of 113 exceeds 100 columns
#67668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52383:
+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52384:
+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8

WARNING: line length of 114 exceeds 100 columns
#67670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52385:
+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10

WARNING: line length of 121 exceeds 100 columns
#67671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52386:
+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L

WARNING: line length of 121 exceeds 100 columns
#67672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52387:
+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#67673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52388:
+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L

WARNING: line length of 114 exceeds 100 columns
#67674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52389:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f

WARNING: line length of 121 exceeds 100 columns
#67675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52390:
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52399:
+#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT                                                            0x0

WARNING: line length of 113 exceeds 100 columns
#67685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52400:
+#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT                                                                0x4

WARNING: line length of 113 exceeds 100 columns
#67686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52401:
+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT                                                           0x8

WARNING: line length of 121 exceeds 100 columns
#67687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52402:
+#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK                                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52403:
+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK                                                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52404:
+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK                                                             0x00000100L

WARNING: line length of 113 exceeds 100 columns
#67690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52405:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#67691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52406:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                0x8

WARNING: line length of 114 exceeds 100 columns
#67692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52407:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT                                                  0x10

WARNING: line length of 114 exceeds 100 columns
#67693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52408:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT                                                        0x18

WARNING: line length of 121 exceeds 100 columns
#67694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52409:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52410:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK                                                  0x00000300L

WARNING: line length of 121 exceeds 100 columns
#67696: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52411:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK                                                    0x00030000L

WARNING: line length of 121 exceeds 100 columns
#67697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52412:
+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK                                                          0x03000000L

WARNING: line length of 113 exceeds 100 columns
#67698: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52413:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#67699: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52414:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT                                          0x8

WARNING: line length of 113 exceeds 100 columns
#67700: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52415:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT                                        0xc

WARNING: line length of 114 exceeds 100 columns
#67701: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52416:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT                                     0x10

WARNING: line length of 121 exceeds 100 columns
#67702: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52417:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK                                            0x0000001FL

WARNING: line length of 121 exceeds 100 columns
#67703: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52418:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#67704: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52419:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK                                          0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67705: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52420:
+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK                                       0x00010000L

WARNING: line length of 113 exceeds 100 columns
#67706: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52421:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67707: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52422:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#67708: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52423:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#67709: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52424:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                0x8

WARNING: line length of 113 exceeds 100 columns
#67710: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52425:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                             0xc

WARNING: line length of 114 exceeds 100 columns
#67711: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52426:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                            0x10

WARNING: line length of 114 exceeds 100 columns
#67712: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52427:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                        0x1f

WARNING: line length of 121 exceeds 100 columns
#67713: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52428:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67714: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52429:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67715: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52430:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                  0x00000030L

WARNING: line length of 121 exceeds 100 columns
#67716: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52431:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                  0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67717: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52432:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67718: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52433:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                              0x00070000L

WARNING: line length of 121 exceeds 100 columns
#67719: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52434:
+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                          0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67720: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52435:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT                                                  0x0

WARNING: line length of 113 exceeds 100 columns
#67721: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52436:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT                                                  0x1

WARNING: line length of 113 exceeds 100 columns
#67722: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52437:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT                                                0x4

WARNING: line length of 113 exceeds 100 columns
#67723: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52438:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT                                                0x5

WARNING: line length of 113 exceeds 100 columns
#67724: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52439:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT                                      0x6

WARNING: line length of 113 exceeds 100 columns
#67725: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52440:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT                                                 0x8

WARNING: line length of 113 exceeds 100 columns
#67726: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52441:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT                                       0x9

WARNING: line length of 113 exceeds 100 columns
#67727: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52442:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT                                          0xc

WARNING: line length of 113 exceeds 100 columns
#67728: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52443:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT                                          0xd

WARNING: line length of 113 exceeds 100 columns
#67729: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52444:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT                                0xe

WARNING: line length of 114 exceeds 100 columns
#67730: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52445:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                          0x10

WARNING: line length of 121 exceeds 100 columns
#67731: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52446:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK                                                    0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67732: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52447:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK                                                    0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67733: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52448:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK                                                  0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67734: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52449:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK                                                  0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67735: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52450:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK                                        0x00000040L

WARNING: line length of 121 exceeds 100 columns
#67736: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52451:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK                                                   0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67737: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52452:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67738: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52453:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK                                            0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67739: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52454:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK                                            0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67740: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52455:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK                                  0x00004000L

WARNING: line length of 121 exceeds 100 columns
#67741: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52456:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                            0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#67742: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52457:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT                                                0x0

WARNING: line length of 114 exceeds 100 columns
#67743: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52458:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT                                                 0x10

WARNING: line length of 121 exceeds 100 columns
#67744: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52459:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK                                                  0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67745: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52460:
+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK                                                   0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#67746: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52461:
+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67747: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52462:
+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT                                                    0x2

WARNING: line length of 113 exceeds 100 columns
#67748: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52463:
+#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT                                                     0x4

WARNING: line length of 121 exceeds 100 columns
#67749: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52464:
+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67750: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52465:
+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK                                                      0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67751: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52466:
+#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK                                                       0x00000010L

WARNING: line length of 113 exceeds 100 columns
#67752: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52467:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#67753: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52468:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#67754: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52469:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#67755: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52470:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#67756: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52471:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#67757: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52472:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#67758: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52473:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT                                     0x6

WARNING: line length of 113 exceeds 100 columns
#67759: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52474:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#67760: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52475:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                        0x8

WARNING: line length of 113 exceeds 100 columns
#67761: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52476:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                        0x9

WARNING: line length of 113 exceeds 100 columns
#67762: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52477:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT                                     0xa

WARNING: line length of 113 exceeds 100 columns
#67763: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52478:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                              0xb

WARNING: line length of 113 exceeds 100 columns
#67764: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52479:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                        0xc

WARNING: line length of 113 exceeds 100 columns
#67765: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52480:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                        0xd

WARNING: line length of 113 exceeds 100 columns
#67766: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52481:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT                                     0xe

WARNING: line length of 113 exceeds 100 columns
#67767: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52482:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                              0xf

WARNING: line length of 114 exceeds 100 columns
#67768: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52483:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                        0x10

WARNING: line length of 114 exceeds 100 columns
#67769: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52484:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                        0x11

WARNING: line length of 114 exceeds 100 columns
#67770: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52485:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT                                     0x12

WARNING: line length of 114 exceeds 100 columns
#67771: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52486:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                              0x13

WARNING: line length of 114 exceeds 100 columns
#67772: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52487:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                        0x14

WARNING: line length of 114 exceeds 100 columns
#67773: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52488:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                        0x15

WARNING: line length of 114 exceeds 100 columns
#67774: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52489:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT                                     0x16

WARNING: line length of 114 exceeds 100 columns
#67775: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52490:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                              0x17

WARNING: line length of 114 exceeds 100 columns
#67776: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52491:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                        0x18

WARNING: line length of 114 exceeds 100 columns
#67777: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52492:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                        0x19

WARNING: line length of 114 exceeds 100 columns
#67778: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52493:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT                                     0x1a

WARNING: line length of 114 exceeds 100 columns
#67779: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52494:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                              0x1b

WARNING: line length of 114 exceeds 100 columns
#67780: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52495:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                        0x1c

WARNING: line length of 114 exceeds 100 columns
#67781: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52496:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                        0x1d

WARNING: line length of 114 exceeds 100 columns
#67782: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52497:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT                                     0x1e

WARNING: line length of 114 exceeds 100 columns
#67783: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52498:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                              0x1f

WARNING: line length of 121 exceeds 100 columns
#67784: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52499:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67785: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52500:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67786: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52501:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67787: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52502:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#67788: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52503:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67789: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52504:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67790: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52505:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#67791: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52506:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#67792: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52507:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                          0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67793: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52508:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                          0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67794: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52509:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK                                       0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67795: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52510:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67796: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52511:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                          0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67797: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52512:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                          0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67798: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52513:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK                                       0x00004000L

WARNING: line length of 121 exceeds 100 columns
#67799: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52514:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67800: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52515:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                          0x00010000L

WARNING: line length of 121 exceeds 100 columns
#67801: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52516:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                          0x00020000L

WARNING: line length of 121 exceeds 100 columns
#67802: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52517:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK                                       0x00040000L

WARNING: line length of 121 exceeds 100 columns
#67803: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52518:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                0x00080000L

WARNING: line length of 121 exceeds 100 columns
#67804: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52519:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                          0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67805: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52520:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                          0x00200000L

WARNING: line length of 121 exceeds 100 columns
#67806: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52521:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK                                       0x00400000L

WARNING: line length of 121 exceeds 100 columns
#67807: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52522:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                0x00800000L

WARNING: line length of 121 exceeds 100 columns
#67808: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52523:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                          0x01000000L

WARNING: line length of 121 exceeds 100 columns
#67809: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52524:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                          0x02000000L

WARNING: line length of 121 exceeds 100 columns
#67810: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52525:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK                                       0x04000000L

WARNING: line length of 121 exceeds 100 columns
#67811: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52526:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                0x08000000L

WARNING: line length of 121 exceeds 100 columns
#67812: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52527:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                          0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67813: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52528:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                          0x20000000L

WARNING: line length of 121 exceeds 100 columns
#67814: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52529:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK                                       0x40000000L

WARNING: line length of 121 exceeds 100 columns
#67815: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52530:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67816: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52531:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#67817: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52532:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT                                        0x1

WARNING: line length of 113 exceeds 100 columns
#67818: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52533:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT                                     0x2

WARNING: line length of 113 exceeds 100 columns
#67819: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52534:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                              0x3

WARNING: line length of 113 exceeds 100 columns
#67820: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52535:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT                                        0x4

WARNING: line length of 113 exceeds 100 columns
#67821: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52536:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT                                        0x5

WARNING: line length of 113 exceeds 100 columns
#67822: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52537:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT                                     0x6

WARNING: line length of 113 exceeds 100 columns
#67823: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52538:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                              0x7

WARNING: line length of 113 exceeds 100 columns
#67824: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52539:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT                                       0x8

WARNING: line length of 113 exceeds 100 columns
#67825: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52540:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT                                       0x9

WARNING: line length of 113 exceeds 100 columns
#67826: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52541:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT                                    0xa

WARNING: line length of 113 exceeds 100 columns
#67827: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52542:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                             0xb

WARNING: line length of 113 exceeds 100 columns
#67828: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52543:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT                                       0xc

WARNING: line length of 113 exceeds 100 columns
#67829: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52544:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT                                       0xd

WARNING: line length of 113 exceeds 100 columns
#67830: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52545:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT                                    0xe

WARNING: line length of 113 exceeds 100 columns
#67831: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52546:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                             0xf

WARNING: line length of 114 exceeds 100 columns
#67832: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52547:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT                                       0x10

WARNING: line length of 114 exceeds 100 columns
#67833: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52548:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT                                       0x11

WARNING: line length of 114 exceeds 100 columns
#67834: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52549:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT                                    0x12

WARNING: line length of 114 exceeds 100 columns
#67835: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52550:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                             0x13

WARNING: line length of 114 exceeds 100 columns
#67836: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52551:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT                                       0x14

WARNING: line length of 114 exceeds 100 columns
#67837: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52552:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT                                       0x15

WARNING: line length of 114 exceeds 100 columns
#67838: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52553:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT                                    0x16

WARNING: line length of 114 exceeds 100 columns
#67839: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52554:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                             0x17

WARNING: line length of 114 exceeds 100 columns
#67840: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52555:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT                                       0x18

WARNING: line length of 114 exceeds 100 columns
#67841: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52556:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT                                       0x19

WARNING: line length of 114 exceeds 100 columns
#67842: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52557:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT                                    0x1a

WARNING: line length of 114 exceeds 100 columns
#67843: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52558:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                             0x1b

WARNING: line length of 121 exceeds 100 columns
#67844: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52559:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67845: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52560:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK                                          0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67846: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52561:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67847: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52562:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK                                0x00000008L

WARNING: line length of 121 exceeds 100 columns
#67848: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52563:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK                                          0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67849: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52564:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK                                          0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67850: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52565:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK                                       0x00000040L

WARNING: line length of 121 exceeds 100 columns
#67851: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52566:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK                                0x00000080L

WARNING: line length of 121 exceeds 100 columns
#67852: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52567:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK                                         0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67853: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52568:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK                                         0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67854: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52569:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK                                      0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67855: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52570:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK                               0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67856: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52571:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK                                         0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67857: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52572:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK                                         0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67858: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52573:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK                                      0x00004000L

WARNING: line length of 121 exceeds 100 columns
#67859: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52574:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK                               0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67860: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52575:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK                                         0x00010000L

WARNING: line length of 121 exceeds 100 columns
#67861: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52576:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK                                         0x00020000L

WARNING: line length of 121 exceeds 100 columns
#67862: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52577:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK                                      0x00040000L

WARNING: line length of 121 exceeds 100 columns
#67863: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52578:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK                               0x00080000L

WARNING: line length of 121 exceeds 100 columns
#67864: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52579:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK                                         0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67865: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52580:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK                                         0x00200000L

WARNING: line length of 121 exceeds 100 columns
#67866: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52581:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK                                      0x00400000L

WARNING: line length of 121 exceeds 100 columns
#67867: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52582:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK                               0x00800000L

WARNING: line length of 121 exceeds 100 columns
#67868: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52583:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK                                         0x01000000L

WARNING: line length of 121 exceeds 100 columns
#67869: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52584:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK                                         0x02000000L

WARNING: line length of 121 exceeds 100 columns
#67870: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52585:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK                                      0x04000000L

WARNING: line length of 121 exceeds 100 columns
#67871: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52586:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK                               0x08000000L

WARNING: line length of 113 exceeds 100 columns
#67872: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52587:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#67873: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52588:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                      0x1

WARNING: line length of 113 exceeds 100 columns
#67874: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52589:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                              0x2

WARNING: line length of 113 exceeds 100 columns
#67875: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52590:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                      0x3

WARNING: line length of 113 exceeds 100 columns
#67876: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52591:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#67877: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52592:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                      0x5

WARNING: line length of 113 exceeds 100 columns
#67878: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52593:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                              0x6

WARNING: line length of 113 exceeds 100 columns
#67879: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52594:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                      0x7

WARNING: line length of 113 exceeds 100 columns
#67880: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52595:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                              0x8

WARNING: line length of 113 exceeds 100 columns
#67881: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52596:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                      0x9

WARNING: line length of 113 exceeds 100 columns
#67882: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52597:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                              0xa

WARNING: line length of 113 exceeds 100 columns
#67883: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52598:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                      0xb

WARNING: line length of 113 exceeds 100 columns
#67884: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52599:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                              0xc

WARNING: line length of 113 exceeds 100 columns
#67885: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52600:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                      0xd

WARNING: line length of 113 exceeds 100 columns
#67886: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52601:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                              0xe

WARNING: line length of 113 exceeds 100 columns
#67887: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52602:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                      0xf

WARNING: line length of 114 exceeds 100 columns
#67888: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52603:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                              0x10

WARNING: line length of 114 exceeds 100 columns
#67889: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52604:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                      0x11

WARNING: line length of 114 exceeds 100 columns
#67890: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52605:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                              0x12

WARNING: line length of 114 exceeds 100 columns
#67891: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52606:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                      0x13

WARNING: line length of 114 exceeds 100 columns
#67892: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52607:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                             0x14

WARNING: line length of 114 exceeds 100 columns
#67893: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52608:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                     0x15

WARNING: line length of 114 exceeds 100 columns
#67894: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52609:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                             0x16

WARNING: line length of 114 exceeds 100 columns
#67895: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52610:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                     0x17

WARNING: line length of 114 exceeds 100 columns
#67896: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52611:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                             0x18

WARNING: line length of 114 exceeds 100 columns
#67897: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52612:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                     0x19

WARNING: line length of 114 exceeds 100 columns
#67898: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52613:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                             0x1a

WARNING: line length of 114 exceeds 100 columns
#67899: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52614:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                     0x1b

WARNING: line length of 114 exceeds 100 columns
#67900: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52615:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                             0x1c

WARNING: line length of 114 exceeds 100 columns
#67901: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52616:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                     0x1d

WARNING: line length of 121 exceeds 100 columns
#67902: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52617:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67903: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52618:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                        0x00000002L

WARNING: line length of 121 exceeds 100 columns
#67904: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52619:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#67905: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52620:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                        0x00000008L

WARNING: line length of 121 exceeds 100 columns
#67906: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52621:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#67907: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52622:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                        0x00000020L

WARNING: line length of 121 exceeds 100 columns
#67908: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52623:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#67909: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52624:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                        0x00000080L

WARNING: line length of 121 exceeds 100 columns
#67910: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52625:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                0x00000100L

WARNING: line length of 121 exceeds 100 columns
#67911: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52626:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                        0x00000200L

WARNING: line length of 121 exceeds 100 columns
#67912: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52627:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                0x00000400L

WARNING: line length of 121 exceeds 100 columns
#67913: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52628:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                        0x00000800L

WARNING: line length of 121 exceeds 100 columns
#67914: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52629:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67915: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52630:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                        0x00002000L

WARNING: line length of 121 exceeds 100 columns
#67916: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52631:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                0x00004000L

WARNING: line length of 121 exceeds 100 columns
#67917: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52632:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                        0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67918: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52633:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                0x00010000L

WARNING: line length of 121 exceeds 100 columns
#67919: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52634:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                        0x00020000L

WARNING: line length of 121 exceeds 100 columns
#67920: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52635:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                0x00040000L

WARNING: line length of 121 exceeds 100 columns
#67921: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52636:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                        0x00080000L

WARNING: line length of 121 exceeds 100 columns
#67922: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52637:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                               0x00100000L

WARNING: line length of 121 exceeds 100 columns
#67923: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52638:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                       0x00200000L

WARNING: line length of 121 exceeds 100 columns
#67924: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52639:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                               0x00400000L

WARNING: line length of 121 exceeds 100 columns
#67925: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52640:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                       0x00800000L

WARNING: line length of 121 exceeds 100 columns
#67926: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52641:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                               0x01000000L

WARNING: line length of 121 exceeds 100 columns
#67927: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52642:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                       0x02000000L

WARNING: line length of 121 exceeds 100 columns
#67928: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52643:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                               0x04000000L

WARNING: line length of 121 exceeds 100 columns
#67929: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52644:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                       0x08000000L

WARNING: line length of 121 exceeds 100 columns
#67930: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52645:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                               0x10000000L

WARNING: line length of 121 exceeds 100 columns
#67931: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52646:
+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                       0x20000000L

WARNING: line length of 113 exceeds 100 columns
#67932: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52647:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67933: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52648:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#67934: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52649:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#67935: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52650:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#67936: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52651:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67937: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52652:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67938: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52653:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK                                           0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#67939: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52654:
+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67940: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52655:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67941: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52656:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#67942: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52657:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#67943: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52658:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#67944: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52659:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67945: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52660:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67946: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52661:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK                                           0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#67947: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52662:
+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67948: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52663:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67949: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52664:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#67950: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52665:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#67951: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52666:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#67952: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52667:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67953: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52668:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67954: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52669:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK                                           0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#67955: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52670:
+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67956: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52671:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67957: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52672:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#67958: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52673:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#67959: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52674:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#67960: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52675:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67961: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52676:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67962: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52677:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK                                           0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#67963: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52678:
+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67964: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52679:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67965: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52680:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT                                          0xf

WARNING: line length of 114 exceeds 100 columns
#67966: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52681:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT                                         0x10

WARNING: line length of 114 exceeds 100 columns
#67967: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52682:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT                                          0x1f

WARNING: line length of 121 exceeds 100 columns
#67968: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52683:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67969: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52684:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK                                            0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67970: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52685:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK                                           0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#67971: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52686:
+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK                                            0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67972: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52687:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#67973: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52688:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT                                       0xf

WARNING: line length of 114 exceeds 100 columns
#67974: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52689:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#67975: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52690:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#67976: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52691:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67977: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52692:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67978: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52693:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK                                        0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#67979: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52694:
+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67980: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52695:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT                                      0x0

WARNING: line length of 113 exceeds 100 columns
#67981: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52696:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT                                       0xf

WARNING: line length of 114 exceeds 100 columns
#67982: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52697:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT                                      0x10

WARNING: line length of 114 exceeds 100 columns
#67983: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52698:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT                                       0x1f

WARNING: line length of 121 exceeds 100 columns
#67984: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52699:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67985: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52700:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK                                         0x00008000L

WARNING: line length of 121 exceeds 100 columns
#67986: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52701:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK                                        0x7FFF0000L

WARNING: line length of 121 exceeds 100 columns
#67987: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52702:
+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK                                         0x80000000L

WARNING: line length of 113 exceeds 100 columns
#67988: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52703:
+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT                                         0x0

WARNING: line length of 113 exceeds 100 columns
#67989: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52704:
+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT                                          0xf

WARNING: line length of 121 exceeds 100 columns
#67990: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52705:
+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK                                           0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#67991: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52706:
+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK                                            0x00008000L

WARNING: line length of 113 exceeds 100 columns
#67992: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52707:
+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                        0x0

WARNING: line length of 113 exceeds 100 columns
#67993: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52708:
+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                        0xc

WARNING: line length of 113 exceeds 100 columns
#67994: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52709:
+#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                     0xf

WARNING: line length of 121 exceeds 100 columns
#67995: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52710:
+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#67996: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52711:
+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                          0x00001000L

WARNING: line length of 121 exceeds 100 columns
#67997: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52712:
+#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                       0x00008000L

WARNING: line length of 113 exceeds 100 columns
#67998: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52713:
+#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#67999: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52714:
+#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68000: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52715:
+#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#68001: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52716:
+#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK                                                              0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#68002: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52717:
+#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68003: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52718:
+#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68004: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52719:
+#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#68005: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52720:
+#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK                                                              0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#68006: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52721:
+#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68007: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52722:
+#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68008: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52723:
+#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                            0x0

WARNING: line length of 121 exceeds 100 columns
#68009: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52724:
+#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK                                                              0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#68010: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52725:
+#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                         0xc

WARNING: line length of 121 exceeds 100 columns
#68011: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52726:
+#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                           0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68012: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52727:
+#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                           0x0

WARNING: line length of 121 exceeds 100 columns
#68013: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52728:
+#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK                                                             0x000FFFFFL

WARNING: line length of 113 exceeds 100 columns
#68014: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52729:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT                              0x0

WARNING: line length of 113 exceeds 100 columns
#68015: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52730:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT                               0x1

WARNING: line length of 113 exceeds 100 columns
#68016: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52731:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT                              0x4

WARNING: line length of 113 exceeds 100 columns
#68017: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52732:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT                           0x8

WARNING: line length of 114 exceeds 100 columns
#68018: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52733:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT                            0x18

WARNING: line length of 121 exceeds 100 columns
#68019: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52734:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68020: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52735:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK                                 0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68021: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52736:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK                                0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68022: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52737:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK                             0x0000FF00L

WARNING: line length of 121 exceeds 100 columns
#68023: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52738:
+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK                              0x1F000000L

WARNING: line length of 113 exceeds 100 columns
#68024: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52739:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT                                                 0x0

WARNING: line length of 113 exceeds 100 columns
#68025: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52740:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT                                               0x1

WARNING: line length of 113 exceeds 100 columns
#68026: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52741:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT                                               0x4

WARNING: line length of 113 exceeds 100 columns
#68027: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52742:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                             0x8

WARNING: line length of 121 exceeds 100 columns
#68028: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52743:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK                                                   0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68029: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52744:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK                                                 0x00000006L

WARNING: line length of 121 exceeds 100 columns
#68030: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52745:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK                                                 0x00000030L

WARNING: line length of 121 exceeds 100 columns
#68031: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52746:
+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                               0x00000300L

WARNING: line length of 113 exceeds 100 columns
#68032: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52747:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#68033: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52748:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                       0x4

WARNING: line length of 113 exceeds 100 columns
#68034: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52749:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                               0x8

WARNING: line length of 114 exceeds 100 columns
#68035: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52750:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                 0x10

WARNING: line length of 121 exceeds 100 columns
#68036: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52751:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68037: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52752:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                         0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68038: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52753:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#68039: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52754:
+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                   0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#68040: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52755:
+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT                                                      0x0

WARNING: line length of 114 exceeds 100 columns
#68041: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52756:
+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT                                                       0x10

WARNING: line length of 121 exceeds 100 columns
#68042: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52757:
+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK                                                        0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#68043: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52758:
+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK                                                         0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#68044: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52759:
+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT                                                    0x0

WARNING: line length of 114 exceeds 100 columns
#68045: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52760:
+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT                                                     0x10

WARNING: line length of 121 exceeds 100 columns
#68046: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52761:
+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK                                                      0x00007FFFL

WARNING: line length of 121 exceeds 100 columns
#68047: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52762:
+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK                                                       0x7FFF0000L

WARNING: line length of 113 exceeds 100 columns
#68048: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52763:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT                                                              0x0

WARNING: line length of 113 exceeds 100 columns
#68049: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52764:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT                                                         0x1

WARNING: line length of 113 exceeds 100 columns
#68050: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52765:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT                                                            0x8

WARNING: line length of 113 exceeds 100 columns
#68051: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52766:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT                                                         0xa

WARNING: line length of 114 exceeds 100 columns
#68052: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52767:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT                                                    0x10

WARNING: line length of 114 exceeds 100 columns
#68053: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52768:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT                                                  0x11

WARNING: line length of 121 exceeds 100 columns
#68054: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52769:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK                                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68055: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52770:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK                                                           0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68056: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52771:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK                                                              0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68057: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52772:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK                                                           0x00000C00L

WARNING: line length of 121 exceeds 100 columns
#68058: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52773:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK                                                      0x00010000L

WARNING: line length of 121 exceeds 100 columns
#68059: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52774:
+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK                                                    0x00060000L

WARNING: line length of 113 exceeds 100 columns
#68060: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52775:
+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT                                                         0x0

WARNING: line length of 114 exceeds 100 columns
#68061: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52776:
+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT                                                         0x10

WARNING: line length of 121 exceeds 100 columns
#68062: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52777:
+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK                                                           0x0000FFFFL

WARNING: line length of 121 exceeds 100 columns
#68063: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52778:
+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK                                                           0xFFFF0000L

WARNING: line length of 113 exceeds 100 columns
#68064: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52779:
+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68065: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52780:
+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT                                          0x4

WARNING: line length of 121 exceeds 100 columns
#68066: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52781:
+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68067: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52782:
+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK                                            0x00000010L

WARNING: line length of 113 exceeds 100 columns
#68068: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52783:
+#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT                                                             0x0

WARNING: line length of 113 exceeds 100 columns
#68069: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52784:
+#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT                                                       0x8

WARNING: line length of 121 exceeds 100 columns
#68070: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52785:
+#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK                                                               0x00000003L

WARNING: line length of 121 exceeds 100 columns
#68071: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52786:
+#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK                                                         0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68072: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52787:
+#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT                                                0x0

WARNING: line length of 121 exceeds 100 columns
#68073: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52788:
+#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK                                                  0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68074: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52789:
+#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#68075: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52790:
+#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK                                                           0x0000FFFFL

WARNING: line length of 114 exceeds 100 columns
#68078: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52793:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10

WARNING: line length of 121 exceeds 100 columns
#68079: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52794:
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#68082: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52797:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#68083: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52798:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68084: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52799:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#68085: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52800:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#68086: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52801:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#68087: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52802:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4

WARNING: line length of 121 exceeds 100 columns
#68088: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52803:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68089: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52804:
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#68092: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52807:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10

WARNING: line length of 121 exceeds 100 columns
#68093: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52808:
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#68095: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52810:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#68096: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52811:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68097: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52812:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#68098: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52813:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#68099: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52814:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#68100: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52815:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4

WARNING: line length of 121 exceeds 100 columns
#68101: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52816:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68102: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52817:
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#68105: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52820:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10

WARNING: line length of 121 exceeds 100 columns
#68106: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52821:
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#68109: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52824:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#68110: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52825:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68111: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52826:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#68112: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52827:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#68113: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52828:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#68114: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52829:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4

WARNING: line length of 121 exceeds 100 columns
#68115: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52830:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68116: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52831:
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L

WARNING: line length of 114 exceeds 100 columns
#68119: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52834:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10

WARNING: line length of 121 exceeds 100 columns
#68120: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52835:
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L

WARNING: line length of 113 exceeds 100 columns
#68123: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52838:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8

WARNING: line length of 121 exceeds 100 columns
#68124: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52839:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68125: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52840:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0

WARNING: line length of 121 exceeds 100 columns
#68126: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52841:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#68127: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52842:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0

WARNING: line length of 113 exceeds 100 columns
#68128: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52843:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4

WARNING: line length of 121 exceeds 100 columns
#68129: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52844:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68130: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52845:
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L

WARNING: line length of 113 exceeds 100 columns
#68133: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52848:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#68134: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52849:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L

WARNING: line length of 113 exceeds 100 columns
#68135: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52850:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT                                        0x8

WARNING: line length of 121 exceeds 100 columns
#68136: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52851:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68137: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52852:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68138: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52853:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68139: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52854:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68140: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52855:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68141: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52856:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68142: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52857:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68143: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52858:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68144: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52859:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68145: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52860:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68146: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52861:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68147: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52862:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68148: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52863:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68149: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52864:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68150: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52865:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68151: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52866:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68152: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52867:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68153: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52868:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68154: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52869:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68155: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52870:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68156: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52871:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68157: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52872:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68158: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52873:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68159: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52874:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68160: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52875:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68161: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52876:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68162: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52877:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68163: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52878:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68164: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52879:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68165: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52880:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68166: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52881:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68167: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52882:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68168: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52883:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68169: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52884:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8

WARNING: line length of 121 exceeds 100 columns
#68170: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52885:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68171: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52886:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#68172: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52887:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#68173: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52888:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#68174: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52889:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68175: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52890:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#68176: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52891:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#68177: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52892:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2

WARNING: line length of 113 exceeds 100 columns
#68178: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52893:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3

WARNING: line length of 121 exceeds 100 columns
#68179: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52894:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68180: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52895:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68181: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52896:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68182: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52897:
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L

WARNING: line length of 113 exceeds 100 columns
#68185: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52900:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc

WARNING: line length of 121 exceeds 100 columns
#68186: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52901:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L

WARNING: line length of 113 exceeds 100 columns
#68187: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52902:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT                                        0x8

WARNING: line length of 121 exceeds 100 columns
#68188: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52903:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68189: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52904:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68190: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52905:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68191: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52906:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68192: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52907:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68193: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52908:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68194: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52909:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68195: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52910:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68196: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52911:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68197: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52912:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68198: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52913:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68199: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52914:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68200: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52915:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68201: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52916:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4

WARNING: line length of 113 exceeds 100 columns
#68202: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52917:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5

WARNING: line length of 121 exceeds 100 columns
#68203: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52918:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68204: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52919:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68205: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52920:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68206: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52921:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68207: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52922:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68208: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52923:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68209: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52924:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68210: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52925:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68211: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52926:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68212: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52927:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68213: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52928:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68214: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52929:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68215: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52930:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68216: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52931:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68217: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52932:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4

WARNING: line length of 113 exceeds 100 columns
#68218: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52933:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT                               0x5

WARNING: line length of 121 exceeds 100 columns
#68219: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52934:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68220: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52935:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L

WARNING: line length of 113 exceeds 100 columns
#68221: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52936:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8

WARNING: line length of 121 exceeds 100 columns
#68222: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52937:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L

WARNING: line length of 113 exceeds 100 columns
#68223: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52938:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0

WARNING: line length of 121 exceeds 100 columns
#68224: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52939:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL

WARNING: line length of 113 exceeds 100 columns
#68225: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52940:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0

WARNING: line length of 121 exceeds 100 columns
#68226: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52941:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68227: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52942:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0

WARNING: line length of 113 exceeds 100 columns
#68228: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52943:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1

WARNING: line length of 113 exceeds 100 columns
#68229: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52944:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2

WARNING: line length of 113 exceeds 100 columns
#68230: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52945:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3

WARNING: line length of 121 exceeds 100 columns
#68231: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52946:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68232: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52947:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68233: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52948:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68234: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52949:
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L

WARNING: line length of 113 exceeds 100 columns
#68236: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52951:
+#define DLPC_ENABLE__DLPC_EN__SHIFT                                                                           0x0

WARNING: line length of 113 exceeds 100 columns
#68237: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52952:
+#define DLPC_ENABLE__PWRUP_TRIGGER_EN__SHIFT                                                                  0x4

WARNING: line length of 113 exceeds 100 columns
#68238: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52953:
+#define DLPC_ENABLE__PWRUP_TRIGGER_CLR__SHIFT                                                                 0x5

WARNING: line length of 113 exceeds 100 columns
#68239: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52954:
+#define DLPC_ENABLE__PWRUP_TRIGGER_STATUS__SHIFT                                                              0x6

WARNING: line length of 113 exceeds 100 columns
#68240: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52955:
+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_EN__SHIFT                                                             0x8

WARNING: line length of 113 exceeds 100 columns
#68241: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52956:
+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_CLR__SHIFT                                                            0x9

WARNING: line length of 113 exceeds 100 columns
#68242: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52957:
+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_STATUS__SHIFT                                                         0xa

WARNING: line length of 113 exceeds 100 columns
#68243: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52958:
+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_EN__SHIFT                                                     0xc

WARNING: line length of 113 exceeds 100 columns
#68244: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52959:
+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_CLR__SHIFT                                                    0xd

WARNING: line length of 113 exceeds 100 columns
#68245: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52960:
+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_STATUS__SHIFT                                                 0xe

WARNING: line length of 121 exceeds 100 columns
#68246: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52961:
+#define DLPC_ENABLE__DLPC_EN_MASK                                                                             0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68247: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52962:
+#define DLPC_ENABLE__PWRUP_TRIGGER_EN_MASK                                                                    0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68248: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52963:
+#define DLPC_ENABLE__PWRUP_TRIGGER_CLR_MASK                                                                   0x00000020L

WARNING: line length of 121 exceeds 100 columns
#68249: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52964:
+#define DLPC_ENABLE__PWRUP_TRIGGER_STATUS_MASK                                                                0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68250: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52965:
+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_EN_MASK                                                               0x00000100L

WARNING: line length of 121 exceeds 100 columns
#68251: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52966:
+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_CLR_MASK                                                              0x00000200L

WARNING: line length of 121 exceeds 100 columns
#68252: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52967:
+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_STATUS_MASK                                                           0x00000400L

WARNING: line length of 121 exceeds 100 columns
#68253: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52968:
+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_EN_MASK                                                       0x00001000L

WARNING: line length of 121 exceeds 100 columns
#68254: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52969:
+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_CLR_MASK                                                      0x00002000L

WARNING: line length of 121 exceeds 100 columns
#68255: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52970:
+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_STATUS_MASK                                                   0x00004000L

WARNING: line length of 113 exceeds 100 columns
#68256: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52971:
+#define DLPC_CURRENT_COUNT__VALUE__SHIFT                                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#68257: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52972:
+#define DLPC_CURRENT_COUNT__VALUE_MASK                                                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68258: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52973:
+#define DLPC_OPTC_SNAPSHOT__VALUE__SHIFT                                                                      0x0

WARNING: line length of 121 exceeds 100 columns
#68259: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52974:
+#define DLPC_OPTC_SNAPSHOT__VALUE_MASK                                                                        0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68260: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52975:
+#define DLPC_PWRUP__VALUE__SHIFT                                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#68261: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52976:
+#define DLPC_PWRUP__VALUE_MASK                                                                                0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68262: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52977:
+#define DLPC_OTG_RESYNC__VALUE__SHIFT                                                                         0x0

WARNING: line length of 121 exceeds 100 columns
#68263: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52978:
+#define DLPC_OTG_RESYNC__VALUE_MASK                                                                           0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68264: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52979:
+#define DLPC_DCN_ZSC_LONO_PWRUP__VALUE__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#68265: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52980:
+#define DLPC_DCN_ZSC_LONO_PWRUP__VALUE_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68266: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52981:
+#define DLPC_SPARE__SPARE__SHIFT                                                                              0x0

WARNING: line length of 121 exceeds 100 columns
#68267: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52982:
+#define DLPC_SPARE__SPARE_MASK                                                                                0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68268: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52983:
+#define DLPC_COUNTER_INIT_VALUE__DLPC_COUNTER_INIT_VALUE__SHIFT                                               0x0

WARNING: line length of 121 exceeds 100 columns
#68269: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52984:
+#define DLPC_COUNTER_INIT_VALUE__DLPC_COUNTER_INIT_VALUE_MASK                                                 0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68271: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52986:
+#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS__SHIFT                                                       0x0

WARNING: line length of 113 exceeds 100 columns
#68272: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52987:
+#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS__SHIFT                                                     0x2

WARNING: line length of 113 exceeds 100 columns
#68273: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52988:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS__SHIFT                                                  0x8

WARNING: line length of 113 exceeds 100 columns
#68274: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52989:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS__SHIFT                                                0xb

WARNING: line length of 113 exceeds 100 columns
#68275: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52990:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS__SHIFT                                             0xc

WARNING: line length of 113 exceeds 100 columns
#68276: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52991:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS__SHIFT                                            0xd

WARNING: line length of 113 exceeds 100 columns
#68277: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52992:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS__SHIFT                                                  0xe

WARNING: line length of 114 exceeds 100 columns
#68278: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52993:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL__SHIFT                                                       0x18

WARNING: line length of 121 exceeds 100 columns
#68279: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52994:
+#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS_MASK                                                         0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68280: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52995:
+#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS_MASK                                                       0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68281: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52996:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS_MASK                                                    0x00000100L

WARNING: line length of 121 exceeds 100 columns
#68282: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52997:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS_MASK                                                  0x00000800L

WARNING: line length of 121 exceeds 100 columns
#68283: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52998:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS_MASK                                               0x00001000L

WARNING: line length of 121 exceeds 100 columns
#68284: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:52999:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS_MASK                                              0x00002000L

WARNING: line length of 121 exceeds 100 columns
#68285: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53000:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS_MASK                                                    0x00004000L

WARNING: line length of 121 exceeds 100 columns
#68286: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53001:
+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL_MASK                                                         0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68287: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53002:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#68288: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53003:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#68289: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53004:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#68290: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53005:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9

WARNING: line length of 113 exceeds 100 columns
#68291: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53006:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON__SHIFT                                                 0xa

WARNING: line length of 114 exceeds 100 columns
#68292: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53007:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#68293: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53008:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12

WARNING: line length of 121 exceeds 100 columns
#68294: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53009:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68295: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53010:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68296: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53011:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68297: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53012:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#68298: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53013:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#68299: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53014:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#68300: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53015:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L

WARNING: line length of 113 exceeds 100 columns
#68301: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53016:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#68302: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53017:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#68303: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53018:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#68304: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53019:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#68305: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53020:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#68306: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53021:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE__SHIFT                                                 0x9

WARNING: line length of 121 exceeds 100 columns
#68307: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53022:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68308: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53023:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68309: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53024:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68310: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53025:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#68311: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53026:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#68312: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53027:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE_MASK                                                   0x00000200L

WARNING: line length of 113 exceeds 100 columns
#68313: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53028:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#68314: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53029:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#68315: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53030:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#68316: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53031:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9

WARNING: line length of 113 exceeds 100 columns
#68317: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53032:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON__SHIFT                                                 0xa

WARNING: line length of 114 exceeds 100 columns
#68318: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53033:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#68319: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53034:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12

WARNING: line length of 121 exceeds 100 columns
#68320: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53035:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68321: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53036:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68322: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53037:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68323: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53038:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#68324: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53039:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#68325: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53040:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#68326: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53041:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L

WARNING: line length of 113 exceeds 100 columns
#68327: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53042:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#68328: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53043:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#68329: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53044:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#68330: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53045:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#68331: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53046:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#68332: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53047:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE__SHIFT                                                 0x9

WARNING: line length of 121 exceeds 100 columns
#68333: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53048:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68334: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53049:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68335: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53050:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68336: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53051:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#68337: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53052:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#68338: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53053:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE_MASK                                                   0x00000200L

WARNING: line length of 113 exceeds 100 columns
#68339: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53054:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#68340: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53055:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#68341: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53056:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#68342: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53057:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9

WARNING: line length of 113 exceeds 100 columns
#68343: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53058:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON__SHIFT                                                 0xa

WARNING: line length of 114 exceeds 100 columns
#68344: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53059:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#68345: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53060:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12

WARNING: line length of 121 exceeds 100 columns
#68346: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53061:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68347: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53062:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68348: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53063:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68349: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53064:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#68350: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53065:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#68351: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53066:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#68352: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53067:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L

WARNING: line length of 113 exceeds 100 columns
#68353: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53068:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#68354: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53069:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#68355: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53070:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#68356: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53071:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#68357: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53072:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#68358: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53073:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE__SHIFT                                                 0x9

WARNING: line length of 121 exceeds 100 columns
#68359: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53074:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68360: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53075:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68361: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53076:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68362: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53077:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#68363: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53078:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#68364: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53079:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE_MASK                                                   0x00000200L

WARNING: line length of 113 exceeds 100 columns
#68365: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53080:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC__SHIFT                                                         0x0

WARNING: line length of 113 exceeds 100 columns
#68366: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53081:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN__SHIFT                                                       0x1

WARNING: line length of 113 exceeds 100 columns
#68367: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53082:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN__SHIFT                                                      0x2

WARNING: line length of 113 exceeds 100 columns
#68368: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53083:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9

WARNING: line length of 113 exceeds 100 columns
#68369: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53084:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON__SHIFT                                                 0xa

WARNING: line length of 114 exceeds 100 columns
#68370: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53085:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11

WARNING: line length of 114 exceeds 100 columns
#68371: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53086:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12

WARNING: line length of 121 exceeds 100 columns
#68372: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53087:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC_MASK                                                           0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68373: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53088:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN_MASK                                                         0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68374: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53089:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN_MASK                                                        0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68375: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53090:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L

WARNING: line length of 121 exceeds 100 columns
#68376: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53091:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L

WARNING: line length of 121 exceeds 100 columns
#68377: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53092:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L

WARNING: line length of 121 exceeds 100 columns
#68378: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53093:
+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L

WARNING: line length of 113 exceeds 100 columns
#68379: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53094:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST__SHIFT                                                     0x0

WARNING: line length of 113 exceeds 100 columns
#68380: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53095:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST__SHIFT                                                   0x1

WARNING: line length of 113 exceeds 100 columns
#68381: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53096:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST__SHIFT                                                  0x2

WARNING: line length of 113 exceeds 100 columns
#68382: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53097:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST__SHIFT                                                   0x3

WARNING: line length of 113 exceeds 100 columns
#68383: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53098:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE__SHIFT                                               0x8

WARNING: line length of 113 exceeds 100 columns
#68384: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53099:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE__SHIFT                                                 0x9

WARNING: line length of 121 exceeds 100 columns
#68385: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53100:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST_MASK                                                       0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68386: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53101:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST_MASK                                                     0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68387: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53102:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST_MASK                                                    0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68388: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53103:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST_MASK                                                     0x00000008L

WARNING: line length of 121 exceeds 100 columns
#68389: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53104:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE_MASK                                                 0x00000100L

WARNING: line length of 121 exceeds 100 columns
#68390: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53105:
+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE_MASK                                                   0x00000200L

WARNING: line length of 113 exceeds 100 columns
#68391: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53106:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#68392: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53107:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#68393: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53108:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#68394: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53109:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#68395: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53110:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19

WARNING: line length of 114 exceeds 100 columns
#68396: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53111:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#68397: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53112:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#68398: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53113:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#68399: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53114:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#68400: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53115:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#68401: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53116:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#68402: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53117:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L

WARNING: line length of 113 exceeds 100 columns
#68403: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53118:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#68404: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53119:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#68405: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53120:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#68406: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53121:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#68407: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53122:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19

WARNING: line length of 114 exceeds 100 columns
#68408: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53123:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#68409: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53124:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#68410: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53125:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#68411: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53126:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#68412: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53127:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#68413: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53128:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#68414: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53129:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L

WARNING: line length of 113 exceeds 100 columns
#68415: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53130:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#68416: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53131:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#68417: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53132:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#68418: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53133:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#68419: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53134:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19

WARNING: line length of 114 exceeds 100 columns
#68420: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53135:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#68421: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53136:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#68422: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53137:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#68423: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53138:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#68424: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53139:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#68425: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53140:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#68426: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53141:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L

WARNING: line length of 113 exceeds 100 columns
#68427: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53142:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0

WARNING: line length of 113 exceeds 100 columns
#68428: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53143:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8

WARNING: line length of 114 exceeds 100 columns
#68429: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53144:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT__SHIFT                                              0x10

WARNING: line length of 114 exceeds 100 columns
#68430: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53145:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18

WARNING: line length of 114 exceeds 100 columns
#68431: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53146:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19

WARNING: line length of 114 exceeds 100 columns
#68432: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53147:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a

WARNING: line length of 121 exceeds 100 columns
#68433: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53148:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL

WARNING: line length of 121 exceeds 100 columns
#68434: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53149:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L

WARNING: line length of 121 exceeds 100 columns
#68435: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53150:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L

WARNING: line length of 121 exceeds 100 columns
#68436: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53151:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L

WARNING: line length of 121 exceeds 100 columns
#68437: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53152:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L

WARNING: line length of 121 exceeds 100 columns
#68438: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53153:
+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L

WARNING: line length of 113 exceeds 100 columns
#68439: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53154:
+#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#68440: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53155:
+#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT_MASK                                          0x0000003FL

WARNING: line length of 113 exceeds 100 columns
#68441: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53156:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS__SHIFT                                                0x0

WARNING: line length of 113 exceeds 100 columns
#68442: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53157:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS__SHIFT                                                0x3

WARNING: line length of 113 exceeds 100 columns
#68443: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53158:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS__SHIFT                                                0x6

WARNING: line length of 113 exceeds 100 columns
#68444: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53159:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS__SHIFT                                                0x9

WARNING: line length of 114 exceeds 100 columns
#68445: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53160:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS__SHIFT                                             0x1f

WARNING: line length of 121 exceeds 100 columns
#68446: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53161:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS_MASK                                                  0x00000007L

WARNING: line length of 121 exceeds 100 columns
#68447: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53162:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS_MASK                                                  0x00000038L

WARNING: line length of 121 exceeds 100 columns
#68448: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53163:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS_MASK                                                  0x000001C0L

WARNING: line length of 121 exceeds 100 columns
#68449: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53164:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS_MASK                                                  0x00000E00L

WARNING: line length of 121 exceeds 100 columns
#68450: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53165:
+#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS_MASK                                               0x80000000L

WARNING: line length of 113 exceeds 100 columns
#68451: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53166:
+#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN__SHIFT                                                        0x0

WARNING: line length of 114 exceeds 100 columns
#68452: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53167:
+#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK__SHIFT                                                0x18

WARNING: line length of 121 exceeds 100 columns
#68453: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53168:
+#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN_MASK                                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68454: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53169:
+#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK_MASK                                                  0x01000000L

WARNING: line length of 113 exceeds 100 columns
#68455: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53170:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS__SHIFT                                        0x0

WARNING: line length of 113 exceeds 100 columns
#68456: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53171:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR__SHIFT                                              0x2

WARNING: line length of 114 exceeds 100 columns
#68457: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53172:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP__SHIFT                                                0x14

WARNING: line length of 114 exceeds 100 columns
#68458: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53173:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS__SHIFT                                         0x18

WARNING: line length of 121 exceeds 100 columns
#68459: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53174:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS_MASK                                          0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68460: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53175:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR_MASK                                                0x000FFFFCL

WARNING: line length of 121 exceeds 100 columns
#68461: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53176:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP_MASK                                                  0x00100000L

WARNING: line length of 121 exceeds 100 columns
#68462: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53177:
+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS_MASK                                           0x01000000L

WARNING: line length of 113 exceeds 100 columns
#68463: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53178:
+#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK__SHIFT                                            0x0

WARNING: line length of 113 exceeds 100 columns
#68464: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53179:
+#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK__SHIFT                                             0x1

WARNING: line length of 121 exceeds 100 columns
#68465: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53180:
+#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK_MASK                                              0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68466: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53181:
+#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK_MASK                                               0x00000002L

WARNING: line length of 113 exceeds 100 columns
#68467: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53182:
+#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV__SHIFT                                        0x0

WARNING: line length of 121 exceeds 100 columns
#68468: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53183:
+#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV_MASK                                          0x0000007FL

WARNING: line length of 113 exceeds 100 columns
#68469: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53184:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS__SHIFT                                              0x0

WARNING: line length of 113 exceeds 100 columns
#68470: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53185:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS__SHIFT                                              0x1

WARNING: line length of 113 exceeds 100 columns
#68471: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53186:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS__SHIFT                                              0x2

WARNING: line length of 113 exceeds 100 columns
#68472: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53187:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS__SHIFT                                              0x3

WARNING: line length of 121 exceeds 100 columns
#68473: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53188:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS_MASK                                                0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68474: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53189:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS_MASK                                                0x00000002L

WARNING: line length of 121 exceeds 100 columns
#68475: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53190:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS_MASK                                                0x00000004L

WARNING: line length of 121 exceeds 100 columns
#68476: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53191:
+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS_MASK                                                0x00000008L

WARNING: line length of 113 exceeds 100 columns
#68477: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53192:
+#define DPIA_GLUE_CTRL__DPIA_IO_EN__SHIFT                                                                     0x0

WARNING: line length of 121 exceeds 100 columns
#68478: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53193:
+#define DPIA_GLUE_CTRL__DPIA_IO_EN_MASK                                                                       0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68479: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53194:
+#define DPIA_PERF_COUNT_CONTROL0__ENABLE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68480: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53195:
+#define DPIA_PERF_COUNT_CONTROL0__MODE__SHIFT                                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#68481: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53196:
+#define DPIA_PERF_COUNT_CONTROL0__STATUS__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#68482: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53197:
+#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#68483: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53198:
+#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#68484: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53199:
+#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68485: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53200:
+#define DPIA_PERF_COUNT_CONTROL0__ENABLE_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68486: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53201:
+#define DPIA_PERF_COUNT_CONTROL0__MODE_MASK                                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#68487: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53202:
+#define DPIA_PERF_COUNT_CONTROL0__STATUS_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68488: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53203:
+#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT_MASK                                                            0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#68489: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53204:
+#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68490: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53205:
+#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68491: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53206:
+#define DPIA_PERF_COUNT_CONTROL1__ENABLE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68492: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53207:
+#define DPIA_PERF_COUNT_CONTROL1__MODE__SHIFT                                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#68493: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53208:
+#define DPIA_PERF_COUNT_CONTROL1__STATUS__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#68494: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53209:
+#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#68495: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53210:
+#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#68496: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53211:
+#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68497: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53212:
+#define DPIA_PERF_COUNT_CONTROL1__ENABLE_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68498: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53213:
+#define DPIA_PERF_COUNT_CONTROL1__MODE_MASK                                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#68499: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53214:
+#define DPIA_PERF_COUNT_CONTROL1__STATUS_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68500: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53215:
+#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT_MASK                                                            0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#68501: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53216:
+#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68502: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53217:
+#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68503: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53218:
+#define DPIA_PERF_COUNT_CONTROL2__ENABLE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68504: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53219:
+#define DPIA_PERF_COUNT_CONTROL2__MODE__SHIFT                                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#68505: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53220:
+#define DPIA_PERF_COUNT_CONTROL2__STATUS__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#68506: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53221:
+#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#68507: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53222:
+#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#68508: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53223:
+#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68509: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53224:
+#define DPIA_PERF_COUNT_CONTROL2__ENABLE_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68510: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53225:
+#define DPIA_PERF_COUNT_CONTROL2__MODE_MASK                                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#68511: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53226:
+#define DPIA_PERF_COUNT_CONTROL2__STATUS_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68512: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53227:
+#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT_MASK                                                            0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#68513: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53228:
+#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68514: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53229:
+#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68515: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53230:
+#define DPIA_PERF_COUNT_CONTROL3__ENABLE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68516: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53231:
+#define DPIA_PERF_COUNT_CONTROL3__MODE__SHIFT                                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#68517: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53232:
+#define DPIA_PERF_COUNT_CONTROL3__STATUS__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#68518: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53233:
+#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#68519: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53234:
+#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#68520: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53235:
+#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68521: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53236:
+#define DPIA_PERF_COUNT_CONTROL3__ENABLE_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68522: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53237:
+#define DPIA_PERF_COUNT_CONTROL3__MODE_MASK                                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#68523: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53238:
+#define DPIA_PERF_COUNT_CONTROL3__STATUS_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68524: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53239:
+#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT_MASK                                                            0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#68525: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53240:
+#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68526: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53241:
+#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68527: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53242:
+#define DPIA_PERF_COUNT_CONTROL4__ENABLE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68528: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53243:
+#define DPIA_PERF_COUNT_CONTROL4__MODE__SHIFT                                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#68529: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53244:
+#define DPIA_PERF_COUNT_CONTROL4__STATUS__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#68530: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53245:
+#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#68531: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53246:
+#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#68532: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53247:
+#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68533: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53248:
+#define DPIA_PERF_COUNT_CONTROL4__ENABLE_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68534: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53249:
+#define DPIA_PERF_COUNT_CONTROL4__MODE_MASK                                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#68535: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53250:
+#define DPIA_PERF_COUNT_CONTROL4__STATUS_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68536: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53251:
+#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT_MASK                                                            0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#68537: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53252:
+#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68538: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53253:
+#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68539: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53254:
+#define DPIA_PERF_COUNT_CONTROL5__ENABLE__SHIFT                                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68540: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53255:
+#define DPIA_PERF_COUNT_CONTROL5__MODE__SHIFT                                                                 0x1

WARNING: line length of 113 exceeds 100 columns
#68541: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53256:
+#define DPIA_PERF_COUNT_CONTROL5__STATUS__SHIFT                                                               0x4

WARNING: line length of 113 exceeds 100 columns
#68542: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53257:
+#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT__SHIFT                                                          0x5

WARNING: line length of 113 exceeds 100 columns
#68543: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53258:
+#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT__SHIFT                                                          0x8

WARNING: line length of 113 exceeds 100 columns
#68544: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53259:
+#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT__SHIFT                                                          0xc

WARNING: line length of 121 exceeds 100 columns
#68545: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53260:
+#define DPIA_PERF_COUNT_CONTROL5__ENABLE_MASK                                                                 0x00000001L

WARNING: line length of 121 exceeds 100 columns
#68546: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53261:
+#define DPIA_PERF_COUNT_CONTROL5__MODE_MASK                                                                   0x0000000EL

WARNING: line length of 121 exceeds 100 columns
#68547: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53262:
+#define DPIA_PERF_COUNT_CONTROL5__STATUS_MASK                                                                 0x00000010L

WARNING: line length of 121 exceeds 100 columns
#68548: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53263:
+#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT_MASK                                                            0x000000E0L

WARNING: line length of 121 exceeds 100 columns
#68549: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53264:
+#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT_MASK                                                            0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68550: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53265:
+#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT_MASK                                                            0xFFFFF000L

WARNING: line length of 113 exceeds 100 columns
#68551: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53266:
+#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT__SHIFT                                                          0x0

WARNING: line length of 113 exceeds 100 columns
#68552: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53267:
+#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT__SHIFT                                                             0x4

WARNING: line length of 121 exceeds 100 columns
#68553: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53268:
+#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT_MASK                                                            0x00000007L

WARNING: line length of 121 exceeds 100 columns
#68554: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53269:
+#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT_MASK                                                               0x00000070L

WARNING: line length of 113 exceeds 100 columns
#68555: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53270:
+#define DPIA_PERF_COUNT_DATA_LO__VALUE__SHIFT                                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#68556: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53271:
+#define DPIA_PERF_COUNT_DATA_LO__VALUE_MASK                                                                   0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68557: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53272:
+#define DPIA_MU_SPARE__DPIA_MU_SPARE__SHIFT                                                                   0x0

WARNING: line length of 121 exceeds 100 columns
#68558: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53273:
+#define DPIA_MU_SPARE__DPIA_MU_SPARE_MASK                                                                     0xFFFFFFFFL

WARNING: line length of 113 exceeds 100 columns
#68560: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53275:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX__SHIFT                                               0x0

WARNING: line length of 113 exceeds 100 columns
#68561: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53276:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI__SHIFT                                             0x6

WARNING: line length of 113 exceeds 100 columns
#68562: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53277:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE__SHIFT                                       0x7

WARNING: line length of 121 exceeds 100 columns
#68563: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53278:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX_MASK                                                 0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68564: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53279:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI_MASK                                               0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68565: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53280:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE_MASK                                         0x00000080L

WARNING: line length of 113 exceeds 100 columns
#68566: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53281:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA__SHIFT                                                 0x0

WARNING: line length of 121 exceeds 100 columns
#68567: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53282:
+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA_MASK                                                   0x000000FFL

WARNING: line length of 113 exceeds 100 columns
#68570: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53285:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68571: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53286:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68572: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53287:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68573: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53288:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68574: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53289:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68575: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53290:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68576: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53291:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68577: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53292:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68578: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53293:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68579: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53294:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68580: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53295:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68581: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53296:
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68582: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53297:
+#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68583: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53298:
+#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68586: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53301:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68587: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53302:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68588: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53303:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68589: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53304:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68590: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53305:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68591: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53306:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68592: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53307:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68593: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53308:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68594: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53309:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68595: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53310:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68596: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53311:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68597: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53312:
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68598: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53313:
+#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68599: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53314:
+#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68602: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53317:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68603: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53318:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68604: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53319:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68605: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53320:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68606: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53321:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68607: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53322:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68608: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53323:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68609: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53324:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68610: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53325:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68611: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53326:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68612: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53327:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68613: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53328:
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68614: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53329:
+#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68615: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53330:
+#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68618: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53333:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68619: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53334:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68620: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53335:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68621: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53336:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68622: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53337:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68623: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53338:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68624: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53339:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68625: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53340:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68626: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53341:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68627: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53342:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68628: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53343:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68629: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53344:
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68630: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53345:
+#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68631: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53346:
+#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68634: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53349:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68635: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53350:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68636: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53351:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68637: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53352:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68638: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53353:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68639: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53354:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68640: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53355:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68641: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53356:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68642: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53357:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68643: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53358:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68644: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53359:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68645: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53360:
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68646: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53361:
+#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68647: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53362:
+#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68650: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53365:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68651: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53366:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68652: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53367:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68653: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53368:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68654: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53369:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68655: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53370:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68656: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53371:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68657: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53372:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68658: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53373:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68659: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53374:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68660: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53375:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68661: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53376:
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68662: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53377:
+#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68663: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53378:
+#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68666: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53381:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68667: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53382:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68668: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53383:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68669: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53384:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68670: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53385:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68671: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53386:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68672: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53387:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68673: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53388:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68674: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53389:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68675: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53390:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68676: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53391:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68677: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53392:
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68678: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53393:
+#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68679: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53394:
+#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: line length of 113 exceeds 100 columns
#68682: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53397:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0

WARNING: line length of 113 exceeds 100 columns
#68683: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53398:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6

WARNING: line length of 113 exceeds 100 columns
#68684: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53399:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7

WARNING: line length of 113 exceeds 100 columns
#68685: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53400:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8

WARNING: line length of 114 exceeds 100 columns
#68686: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53401:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10

WARNING: line length of 114 exceeds 100 columns
#68687: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53402:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18

WARNING: line length of 121 exceeds 100 columns
#68688: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53403:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL

WARNING: line length of 121 exceeds 100 columns
#68689: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53404:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L

WARNING: line length of 121 exceeds 100 columns
#68690: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53405:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L

WARNING: line length of 121 exceeds 100 columns
#68691: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53406:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L

WARNING: line length of 121 exceeds 100 columns
#68692: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53407:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L

WARNING: line length of 121 exceeds 100 columns
#68693: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53408:
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L

WARNING: line length of 113 exceeds 100 columns
#68694: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53409:
+#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0

WARNING: line length of 121 exceeds 100 columns
#68695: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53410:
+#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L

WARNING: adding a line without newline at end of file
#68697: drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h:53412:
+#endif

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